BR112013006329A2 - controlador de memória de múltiplas portas com portas associadas às classes de tráfego - Google Patents
controlador de memória de múltiplas portas com portas associadas às classes de tráfegoInfo
- Publication number
- BR112013006329A2 BR112013006329A2 BR112013006329A BR112013006329A BR112013006329A2 BR 112013006329 A2 BR112013006329 A2 BR 112013006329A2 BR 112013006329 A BR112013006329 A BR 112013006329A BR 112013006329 A BR112013006329 A BR 112013006329A BR 112013006329 A2 BR112013006329 A2 BR 112013006329A2
- Authority
- BR
- Brazil
- Prior art keywords
- memory controller
- different
- qos
- traffic
- operations
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
- G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
- G06F13/1642—Handling requests for interconnection or transfer for access to memory bus based on arbitration with request queuing
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
- G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
- G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
- G06F13/161—Handling requests for interconnection or transfer for access to memory bus based on arbitration with latency improvement
- G06F13/1626—Handling requests for interconnection or transfer for access to memory bus based on arbitration with latency improvement by reordering requests
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
- G06F13/1668—Details of memory controller
- G06F13/1689—Synchronisation and timing concerns
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Memory System (AREA)
- Data Exchanges In Wide-Area Networks (AREA)
- Logic Circuits (AREA)
- Transceivers (AREA)
- Transmitters (AREA)
- Dram (AREA)
- Memory System Of A Hierarchy Structure (AREA)
- Multi Processors (AREA)
Abstract
controlador de memória de múltiplas portas com portas associadas às classes de tráfego. a presente invenção refere-se a um controlador de memória inclui múltiplas portas. cada porta pode ser dedicada a um tipo diferente de tráfego. em uma modalidade, os parâmetros de qualidade de serviço (qos) podem ser definidos para tipos de tráfego, e diferentes tipos de tráfego, e diferentes tipos de tráfego podem ter diferentes definições de parâmetro de qos. o controlador de memória pode ser configurado para operações programadas recebidas em diferentes portas com base nos parâmetros de qos. em um modalidade, o controlador de memória pode suportar a atualização dos parâmetros de qos quando operações subsequentes são recebidas e possuem parâmetros de qos mais altos, através de solicitação de banda lateral, e/ou através do envelhecimento das operações. em uma modalidade, o controlador de memória é configurado para reduzir a ênfase nos parâmetros de qos e aumentar a ênfase na otimização de largura de banda de memória à medida que as operações fluem através da tubulação de controlador de memória.
Applications Claiming Priority (9)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US12/883,888 US8510521B2 (en) | 2010-09-16 | 2010-09-16 | Reordering in the memory controller |
US12/883,878 | 2010-09-16 | ||
US12/883,848 | 2010-09-16 | ||
US12/883,888 | 2010-09-16 | ||
US12/883,878 US8631213B2 (en) | 2010-09-16 | 2010-09-16 | Dynamic QoS upgrading |
US12/883,864 US8314807B2 (en) | 2010-09-16 | 2010-09-16 | Memory controller with QoS-aware scheduling |
US12/883/864 | 2010-09-16 | ||
US12/883,848 US20120072677A1 (en) | 2010-09-16 | 2010-09-16 | Multi-Ported Memory Controller with Ports Associated with Traffic Classes |
PCT/US2011/049940 WO2012036905A1 (en) | 2010-09-16 | 2011-08-31 | Multi-ported memory controller with ports associated with traffic classes |
Publications (2)
Publication Number | Publication Date |
---|---|
BR112013006329A2 true BR112013006329A2 (pt) | 2016-06-21 |
BR112013006329B1 BR112013006329B1 (pt) | 2020-12-01 |
Family
ID=44908227
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
BR112013006329-7A BR112013006329B1 (pt) | 2010-09-16 | 2011-08-31 | controlador de memória compreendendo uma pluralidade de portas, circuito integrado e método |
Country Status (13)
Country | Link |
---|---|
EP (1) | EP2431884B1 (pt) |
JP (1) | JP5610636B2 (pt) |
KR (1) | KR101270848B1 (pt) |
CN (1) | CN102402490B (pt) |
AU (1) | AU2011302452B2 (pt) |
BR (1) | BR112013006329B1 (pt) |
GB (1) | GB2483763B (pt) |
HK (2) | HK1168159A1 (pt) |
MX (1) | MX2013002773A (pt) |
NL (1) | NL2007411C2 (pt) |
RU (1) | RU2556443C2 (pt) |
TW (1) | TWI465903B (pt) |
WO (1) | WO2012036905A1 (pt) |
Families Citing this family (18)
Publication number | Priority date | Publication date | Assignee | Title |
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US9881657B2 (en) | 2012-05-08 | 2018-01-30 | Marvell World Trade Ltd. | Computer system and method of memory management |
CN102681946B (zh) * | 2012-05-11 | 2015-03-11 | 龙芯中科技术有限公司 | 内存访问方法和装置 |
EP2973571B1 (en) | 2013-03-15 | 2020-04-22 | Intel Corporation | A memory system |
CN104156328B (zh) * | 2013-05-15 | 2019-02-05 | 中兴通讯股份有限公司 | 一种识别操作系统类型的方法及usb设备 |
KR102114453B1 (ko) * | 2013-07-19 | 2020-06-05 | 삼성전자주식회사 | 모바일 장치 및 그것의 제어 방법 |
WO2015067295A1 (en) | 2013-11-05 | 2015-05-14 | Huawei Technologies Co., Ltd. | Method and arrangement for controlling requests to a shared electronic resource |
US9563369B2 (en) | 2014-04-14 | 2017-02-07 | Microsoft Technology Licensing, Llc | Fine-grained bandwidth provisioning in a memory controller |
US10163508B2 (en) | 2016-02-26 | 2018-12-25 | Intel Corporation | Supporting multiple memory types in a memory slot |
US10222853B2 (en) | 2016-03-03 | 2019-03-05 | Qualcomm Incorporated | Power saving techniques for memory systems by consolidating data in data lanes of a memory bus |
US11221971B2 (en) | 2016-04-08 | 2022-01-11 | Qualcomm Incorporated | QoS-class based servicing of requests for a shared resource |
US10037150B2 (en) | 2016-07-15 | 2018-07-31 | Advanced Micro Devices, Inc. | Memory controller with virtual controller mode |
EP3270295A1 (en) * | 2016-07-15 | 2018-01-17 | Advanced Micro Devices, Inc. | Memory controller with virtual controller mode |
TWI587145B (zh) * | 2016-12-08 | 2017-06-11 | 群聯電子股份有限公司 | 通道切換裝置、記憶體儲存裝置及通道切換方法 |
US11709624B2 (en) * | 2018-02-15 | 2023-07-25 | Xilinx, Inc. | System-on-chip having multiple circuits and memory controller in separate and independent power domains |
US11237893B2 (en) * | 2019-06-26 | 2022-02-01 | Western Digital Technologies, Inc. | Use of error correction-based metric for identifying poorly performing data storage devices |
US20240004551A1 (en) * | 2020-10-26 | 2024-01-04 | Google Llc | Modulating Credit Allocations in Memory Subsystems |
CN112597080B (zh) * | 2020-12-29 | 2022-10-21 | 联芸科技(杭州)股份有限公司 | 读请求控制装置及方法以及存储器控制器 |
CN115329016B (zh) * | 2022-10-14 | 2023-04-25 | 深圳迅策科技有限公司 | 一种金融资产交易数据处理方法、系统及可读介质 |
Family Cites Families (19)
Publication number | Priority date | Publication date | Assignee | Title |
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IL116708A (en) * | 1996-01-08 | 2000-12-06 | Smart Link Ltd | Real-time task manager for a personal computer |
US6859438B2 (en) * | 1998-02-03 | 2005-02-22 | Extreme Networks, Inc. | Policy based quality of service |
US6101613A (en) * | 1998-07-06 | 2000-08-08 | Intel Corporation | Architecture providing isochronous access to memory in a system |
US6651128B1 (en) * | 2000-02-10 | 2003-11-18 | Advanced Micro Devices, Inc. | Systems and methods for arbitrating between asynchronous and isochronous data for access to data transport resources |
TW513635B (en) * | 2000-11-24 | 2002-12-11 | Ibm | Method and structure for variable-length frame support in a shared memory switch |
US7606744B1 (en) * | 2001-02-16 | 2009-10-20 | Financial Systems Technology (Intellectual Property) Pty. Ltd. | System and method for real-time pricing with volume discounting |
US7054968B2 (en) * | 2003-09-16 | 2006-05-30 | Denali Software, Inc. | Method and apparatus for multi-port memory controller |
US20050138251A1 (en) * | 2003-12-18 | 2005-06-23 | Fanning Blaise B. | Arbitration of asynchronous and isochronous requests |
US7500045B2 (en) * | 2005-03-23 | 2009-03-03 | Qualcomm Incorporated | Minimizing memory barriers when enforcing strongly-ordered requests in a weakly-ordered processing system |
US20080244135A1 (en) * | 2005-05-04 | 2008-10-02 | Nxp B.V. | Memory Controller and Method For Controlling Access to a Memory, as Well as System Comprising a Memory Controller |
KR100784385B1 (ko) * | 2005-08-10 | 2007-12-11 | 삼성전자주식회사 | 공유 자원에 대한 접근 요청을 중재하는 시스템 및 방법 |
WO2007071889A1 (en) * | 2005-12-22 | 2007-06-28 | Arm Limited | Arbitration method reordering transactions to ensure quality of service specified by each transaction |
CN100581172C (zh) * | 2006-04-19 | 2010-01-13 | 杭州华三通信技术有限公司 | 一种对目的磁盘进行访问的方法和扩展磁盘容量的系统 |
US20080077720A1 (en) * | 2006-09-27 | 2008-03-27 | Blaise Fanning | Isochronous memory access with variable channel priorities and timers |
CN101026556B (zh) * | 2007-01-10 | 2010-04-21 | 华为技术有限公司 | 一种支持服务质量的仲裁方法及装置 |
US9292436B2 (en) * | 2007-06-25 | 2016-03-22 | Sonics, Inc. | Various methods and apparatus to support transactions whose data address sequence within that transaction crosses an interleaved channel address boundary |
US7908440B2 (en) * | 2007-08-09 | 2011-03-15 | Intel Corporation | Simultaneous personal sensing and data storage |
US8209439B2 (en) * | 2008-08-25 | 2012-06-26 | Sandisk Il Ltd. | Managing multiple concurrent operations with various priority levels in a local storage device |
CN101419579B (zh) * | 2008-12-10 | 2011-11-16 | 中国科学院计算技术研究所 | 一种在动态随机存储器上提供服务质量的装置和方法 |
-
2011
- 2011-08-31 RU RU2013117127/08A patent/RU2556443C2/ru not_active IP Right Cessation
- 2011-08-31 AU AU2011302452A patent/AU2011302452B2/en not_active Ceased
- 2011-08-31 BR BR112013006329-7A patent/BR112013006329B1/pt active IP Right Grant
- 2011-08-31 WO PCT/US2011/049940 patent/WO2012036905A1/en active Application Filing
- 2011-08-31 MX MX2013002773A patent/MX2013002773A/es active IP Right Grant
- 2011-09-06 EP EP11180199.9A patent/EP2431884B1/en active Active
- 2011-09-08 GB GB1115481.2A patent/GB2483763B/en not_active Expired - Fee Related
- 2011-09-09 TW TW100132698A patent/TWI465903B/zh active
- 2011-09-14 NL NL2007411A patent/NL2007411C2/en not_active IP Right Cessation
- 2011-09-15 JP JP2011221349A patent/JP5610636B2/ja active Active
- 2011-09-16 CN CN201110274403.1A patent/CN102402490B/zh active Active
- 2011-09-16 KR KR1020110093570A patent/KR101270848B1/ko not_active IP Right Cessation
-
2012
- 2012-09-04 HK HK12108647.6A patent/HK1168159A1/xx unknown
- 2012-09-21 HK HK12109346.8A patent/HK1168672A1/xx not_active IP Right Cessation
Also Published As
Publication number | Publication date |
---|---|
BR112013006329B1 (pt) | 2020-12-01 |
GB2483763A (en) | 2012-03-21 |
EP2431884A1 (en) | 2012-03-21 |
KR101270848B1 (ko) | 2013-06-05 |
EP2431884B1 (en) | 2015-03-11 |
GB2483763B (en) | 2013-01-09 |
TW201216056A (en) | 2012-04-16 |
NL2007411A (en) | 2012-03-19 |
NL2007411C2 (en) | 2012-05-09 |
RU2013117127A (ru) | 2014-10-27 |
AU2011302452B2 (en) | 2014-09-04 |
JP2012074042A (ja) | 2012-04-12 |
MX2013002773A (es) | 2013-04-05 |
RU2556443C2 (ru) | 2015-07-10 |
CN102402490B (zh) | 2015-12-02 |
AU2011302452A1 (en) | 2013-03-28 |
HK1168159A1 (en) | 2012-12-21 |
GB201115481D0 (en) | 2011-10-26 |
CN102402490A (zh) | 2012-04-04 |
WO2012036905A1 (en) | 2012-03-22 |
JP5610636B2 (ja) | 2014-10-22 |
HK1168672A1 (en) | 2013-01-04 |
TWI465903B (zh) | 2014-12-21 |
KR20120029366A (ko) | 2012-03-26 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
B06F | Objections, documents and/or translations needed after an examination request according [chapter 6.6 patent gazette] | ||
B06U | Preliminary requirement: requests with searches performed by other patent offices: procedure suspended [chapter 6.21 patent gazette] | ||
B09A | Decision: intention to grant [chapter 9.1 patent gazette] | ||
B16A | Patent or certificate of addition of invention granted [chapter 16.1 patent gazette] |
Free format text: PRAZO DE VALIDADE: 20 (VINTE) ANOS CONTADOS A PARTIR DE 31/08/2011, OBSERVADAS AS CONDICOES LEGAIS. |