AU9689898A - High-performance architecture for disk array controller - Google Patents

High-performance architecture for disk array controller

Info

Publication number
AU9689898A
AU9689898A AU96898/98A AU9689898A AU9689898A AU 9689898 A AU9689898 A AU 9689898A AU 96898/98 A AU96898/98 A AU 96898/98A AU 9689898 A AU9689898 A AU 9689898A AU 9689898 A AU9689898 A AU 9689898A
Authority
AU
Australia
Prior art keywords
disk array
array controller
performance architecture
architecture
performance
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
AU96898/98A
Inventor
Mitchell A. Altman
John Peter Herz
James A. Mcdonald
William Edward Smith
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
3ware Inc
Original Assignee
3ware Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US09/034,247 external-priority patent/US6134630A/en
Priority claimed from US09/034,812 external-priority patent/US6098114A/en
Priority claimed from US09/034,248 external-priority patent/US6138176A/en
Application filed by 3ware Inc filed Critical 3ware Inc
Publication of AU9689898A publication Critical patent/AU9689898A/en
Abandoned legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
    • G06F3/061—Improving I/O performance
    • G06F3/0613—Improving I/O performance in relation to throughput
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/10—Program control for peripheral devices
    • G06F13/12—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor
    • G06F13/124—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor where hardware is a sequential transfer control unit, e.g. microprocessor, peripheral processor or state-machine
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0655—Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
    • G06F3/0658—Controller construction arrangements
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
    • G06F3/0671—In-line storage system
    • G06F3/0683—Plurality of storage devices
    • G06F3/0689—Disk arrays, e.g. RAID, JBOD

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Human Computer Interaction (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
AU96898/98A 1997-11-14 1998-10-08 High-performance architecture for disk array controller Abandoned AU9689898A (en)

Applications Claiming Priority (9)

Application Number Priority Date Filing Date Title
US6584897P 1997-11-14 1997-11-14
US60065848 1997-11-14
US09/034,247 US6134630A (en) 1997-11-14 1998-03-04 High-performance bus architecture for disk array system
US09/034,812 US6098114A (en) 1997-11-14 1998-03-04 Disk array system for processing and tracking the completion of I/O requests
US09/034,248 US6138176A (en) 1997-11-14 1998-03-04 Disk array controller with automated processor which routes I/O data according to addresses and commands received from disk drive controllers
US09034247 1998-03-04
US09034812 1998-03-04
US09034248 1998-03-04
PCT/US1998/021203 WO1999026150A1 (en) 1997-11-14 1998-10-08 High-performance architecture for disk array controller

Publications (1)

Publication Number Publication Date
AU9689898A true AU9689898A (en) 1999-06-07

Family

ID=27488201

Family Applications (1)

Application Number Title Priority Date Filing Date
AU96898/98A Abandoned AU9689898A (en) 1997-11-14 1998-10-08 High-performance architecture for disk array controller

Country Status (4)

Country Link
EP (1) EP1031091A4 (en)
JP (1) JP2001523860A (en)
AU (1) AU9689898A (en)
WO (1) WO1999026150A1 (en)

Families Citing this family (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4392877B2 (en) * 1998-09-18 2010-01-06 株式会社日立製作所 Disk array controller
US6389494B1 (en) 1998-12-30 2002-05-14 Emc Corporation System for interfacing a data storage system to a host utilizing a plurality of busses for carrying end-user data and a separate bus for carrying interface state data
US7117275B1 (en) 1999-01-04 2006-10-03 Emc Corporation Data storage system having separate data transfer section and message network
US7007194B1 (en) 2000-06-29 2006-02-28 Emc Corporation Data storage system having point-to-point configuration
US6584513B1 (en) 2000-03-31 2003-06-24 Emc Corporation Direct memory access (DMA) transmitter
US6993621B1 (en) 2000-03-31 2006-01-31 Emc Corporation Data storage system having separate data transfer section and message network with plural directors on a common printed circuit board and redundant switching networks
US7003601B1 (en) * 2000-03-31 2006-02-21 Emc Corporation Data storage system having separate data transfer section and message network with plural directions on a common printed circuit board
US7010575B1 (en) 2000-03-31 2006-03-07 Emc Corporation Data storage system having separate data transfer section and message network having bus arbitration
US6651130B1 (en) 2000-04-28 2003-11-18 Emc Corporation Data storage system having separate data transfer section and message network with bus arbitration
US6779071B1 (en) 2000-04-28 2004-08-17 Emc Corporation Data storage system having separate data transfer section and message network with status register
US6496900B1 (en) * 2000-09-12 2002-12-17 3Ware, Inc. Disk array system, controller, and method for verifying command data written to disk drives
US6732201B2 (en) * 2001-12-17 2004-05-04 Lsi Logic Corporation Hardware speed selection behind a disk array controller
US20030212859A1 (en) * 2002-05-08 2003-11-13 Ellis Robert W. Arrayed data storage architecture with simultaneous command of multiple storage media
US20030217211A1 (en) * 2002-05-14 2003-11-20 Rust Robert A. Controller communications over an always-on controller interconnect
US6904498B2 (en) 2002-10-08 2005-06-07 Netcell Corp. Raid controller disk write mask
US20050015655A1 (en) * 2003-06-30 2005-01-20 Clayton Michele M. Intermediate station
ES2223283B1 (en) * 2003-07-18 2006-04-16 Angel Iglesias, S.A. COMMUNICATIONS SYSTEM, FOR CONTROLLING PROGRAMMABLE PERIPHERALS.
TW200912728A (en) * 2007-09-13 2009-03-16 Thomson Licensing System and method for splitting data and data control information
US8639877B2 (en) 2009-06-30 2014-01-28 International Business Machines Corporation Wear leveling of solid state disks distributed in a plurality of redundant array of independent disk ranks
US8234520B2 (en) 2009-09-16 2012-07-31 International Business Machines Corporation Wear leveling of solid state disks based on usage information of data and parity received from a raid controller

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2270791B (en) * 1992-09-21 1996-07-17 Grass Valley Group Disk-based digital video recorder
JP3258117B2 (en) * 1993-03-08 2002-02-18 株式会社日立製作所 Storage subsystem
JPH07134635A (en) * 1993-11-10 1995-05-23 Nec Eng Ltd Disk array device
US5671349A (en) * 1994-12-06 1997-09-23 Hitachi Computer Products America, Inc. Apparatus and method for providing data redundancy and reconstruction for redundant arrays of disk drives

Also Published As

Publication number Publication date
JP2001523860A (en) 2001-11-27
EP1031091A1 (en) 2000-08-30
WO1999026150A1 (en) 1999-05-27
EP1031091A4 (en) 2002-11-06

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Legal Events

Date Code Title Description
MK6 Application lapsed section 142(2)(f)/reg. 8.3(3) - pct applic. not entering national phase