AU640551B2 - Optical subscriber access unit - Google Patents

Description

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P/00/011 2816/91 Regutatlon 3.2

AUSTRALIA

Patents Act. 1990) S S

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ORIGINAL

COMPLETE SPECIFICATION ISTANDARD

PATENT

Inventionl Titl: "OPTICAL SUI3SCRIRFR ACCESS UNIT" The following statemenclt is a Full dlescription of this invcntion, incIluding thc best method of performing it knownl to uls:- 2 This invention relates to an optical subscriber access unit for connecting subscriber terminals using asynchronous time-division multiplexing to a telecommunication network. Asynchronous timc-division multiplexing enables all kinds of information to be transmitted in a single lirm comprising packets of bits of fixed length called cells and including a virtual circuit label identifying a call and a virtual circuit group label identifying where applicable a communication circuit group.

It is known to connect subscriber terminals to a telecommunication network using a subscriber access unit conmprising n control unit, a plurality of concentrators, :and a switching network connected to the conccntrators and to a local central office.

The concentrators are provided with subsc ibir access circuits connected to the subscriber terminals. The switching nctwork is usually some distance from the local central office. The concentrators may be in ice immediate vicinity of the switching network or remotely located.

An all electronic digital subscriber access unit is known, for connecting sub- 15 scriber terminals using various transmission techniques, including asynchronous time-division multiplexing, to a telecommunication network. The switching network .is connected to a digital local central office and to the control unit by means of asynchronous multiplex links.

SThe cells may contain call data or mninlenance caLa or signalling data. When 20 a subscriber is not sending data his subscriher terminal sends empty cells to the concentrator. Reciprocally, if a concentrator has no data to send on a communication channel set up to a subscriber terminal the concentrator sends it empty cells instead.

In this known type subscriber access unil each concentrator comprises subscriber access circuits and two stages of concentration.

Each subscriber access circuit provides functions including: optical-electronic conversion :nd vice versa for each subscriber terminal connected to the concentrator by an optical fibre line; delineation of the cells received from the subscriber terminal, by which is meant the identification of the start of each cell; descrambling of the data field of each cell received from a subscriber terminal; scrambling of the data field of each cell sent by the concentrator to a subscriber terminal; calculation of the error detection wnord relating to the header of each cell sent from the concentrator to a subscriber ctrmintil or received from a subscriber terminal; re-synchronisation of the cells sent by subscriber terminal to a local clock of the subscriber access unit; a policing function which monitors the output bit rates of the subscriber terminals; extracting signalling cells from the cells sent by a subscriber terminal and injecting signalling cells into the cells sent by Ihc concentrator to a subscriber terminal; conversion of the virtual circuit and virtual circuit group labels included in each cell sent by a subscriber terminal: calculation of the routing label for rouling each cell in the switching network 10 and insertion of this label in front of the cell header; elimination of empty cells sent by ai subscriber terminal; and insertion of empty cells into the cells sent from the concentrator to the subscriber terminals.

S The first stage of concentration comprises an asynchronous time-division 15 switching matrix controlled by a microprocessor. The second stage of concentration S comprises another asynchronous time-division switching matrix or a time-division multiplexer/demultiplexer controlled by a microprocessor.

The design of this subscriber access unit is optimised for use of electronic com- Si ponents but is not optimised for use of optical components. These have the advan- 20 tage of a higher speed and enable spectral multiplexing. Retaining the design of known type subscriber access units would result in under use of the performance capabilities of optical technology.

An object of the invention is to propose an optical subscriber access unit whose design is not merely deduced from that of known electronic subscriber access unit but which is optimised for the use of oplic;l components.

The invention comprises an oplica;l subscriber access unit for connecting to a telecommunication nctwork subscriber terminals sending and receiving data in the form of fixed length cells by asynchronous limec-division multiplexing, comprising: a switching network connected to a local ccnt-ral office; a control unit connected to the switching network; a plurality of concentrators connccled to the switching network; and subscriber access circuits respectively connected to the subscriber terminals and to the concentrators; said network, said control uni. said codcntrators and said line terminals comprising: 4 means for translating a virtual circuit Inbel or virtual circuit group label included in each cell sent or received by the subscriber access unit and adding to it a routing label for routing said cell in said subscriber access unit; means for synchronising each cell sent by a subscriber terminal with a local clock; and means for implementing a policing function; wherein the means for translating a virtual circuit label or virtual circuit group label for each cell sent or received by the subscriber access unit and adding a routing label to it are located in the switching network and arc the same for processing the cells sent or received to or from all subscriber terminals connected to at least one concentrator.

Preferably, the mcans for implementing the policing function are located in the switching network and the same policing means are used to process cells received from all the subscriber terminals connected to at least one concentrator.

15 This subscriber access unit makes it possible to reduce the number of virtual circuit or virtual circuit group label translator devices, routing label inserter devices and policing devices as these are common to a large number of subscriber terminals, for example 256 terminals. The cost of a subscriber access unit in accordance with the invention is therefore reduced com pared to that which it would have if it were of 20 the same design as a known type subscriber access unit.

In order that the invention will be better understood, embodiments thereof will now be described in relation t tothe drawings, in which: Figure 1 shows a block diagram of one embodiment of an optical subscriber access unit in accordance with the invention.

Figure 2 shows a block diagram of one embodiment of a subscriber access circuit Swhich is part of the embodiment shown in Figure I.

SFigure 3 shows a block diagram of one embodiment of a concentrator circuit Swhich is part of th xame xampc shownn Figure 1.

Figure 4 shows a block diagram of one example of a switching network which is part of the example shown in Figure I.

Figure 5 shows a block diagram of one embodiment of a stage included in each concentrator which effects a first level of concentration by non-synchronous statistical Sspectral and time-division multiplexing.

1 Figure 6 shows a block diagram of one cmbodiment of a stage included in each concentrator which re-synchronises the cells to a local clock of the subscriber access unit.

Figures 7 and 8 show block diagrams of two embodiments of a stage included in each concentrator which changes the bit rate of cells sent by a the subscriber access circuit to the switching network.

Figure 9 shows a block diagram of one embodiment of a stage included in each concentrator which effects a second stage of concentration by periodic time-division multiplexing.

Figure 10 shows a block diagram of one embodiment of a switching matrix of the switching network of the cmbodimcnt shown in Figure 1.

S. Figure 11 shows a more detailed block diagram of this switching matrix.

Figure 12 shows a block diagram of one embodiment of a time-division Sdemuitiplexer stage included in each concentrator which effects a first level of decon- 15 centration of thecells sent from this concentrator to a subscriber terminal.

S i Figures 13 and 14 show block diagrams of two embodiments of a bit rate con- Sverter stage included in each concentrator to process cells transmitted from the Sconcentrator to a subscriber terminal.

Figure 15 shows ablock diagramn ol'one embodiment of a stage included in each S: .20 concentrator which effects a second degree of dcconcentration by spectral demultiplexing of cells sent by this concentrar tor o a subscriber terminal.

9 Figures 16 and 17 show block diagrnms of one embodiment of first and second multiplexer/demuipeplexers featuring bit rale conversion used to connect a remote concentrator to the switching network.

Figure 18 shows a block diagram of one embodiment of the multiplex part of the first rmultiplcxcr/demtultiplexcr with hit rate conversion.

Figure 19 shows a block diagrami of one embodiment of the demultiplex part.

Figure 20 shows a block diagram of one embodiment of the bit rate converter part.

S o0 Referring to the drawings, Figure I shows the block diagram of one embodiment of an optical subscriber access unit in accordance with the invention. It comprises: terminals LAI through LA256 and LFI through LF256 respectively connected to subscriber terminals sending and receiving data in the form of fixed length cells by means of asynchronous time-division'multiplexing; S- subscriber access circuits I and 6. for example; 6 concentrators such as the concentrntors 2 and 7; -a switching network 5 comprising 128 two-way ports; a control unit 8; multiplexer/demultiplexcrs 9 for example; and input-output terminals such as the terminal 10 connected to a local central office which is part of the main telecommunication network by asynchronous timedivision multiplexes.

Each subscriber is connected to a subscriber access circuit such as the circuit I by a bi-directional monomode optical 'ibrc offering a bit rate of 622 Mb/s, for ex- S ample. Each access circuit is connected to an input terminal on a concentrator by an optical fibre offering the same bit rate. The concentrator 2 is connected to 256 subscriber access circuits by 256 lines LBI through LB256, for example.

i Ther re are two categories of concentrator, depending on their distance from the switching network 5. Remote concentrators such as the concentrator 2 are connected 15 to the switching network 5 by a multiplexer/demultiplexer 3, two optical fibres MDI and MD2 and a multiplexer/demultiplexer 4. The multiplexer/demul plexer 3 is near Sthe concentrator 2 and is connected to it by four bi-directional multiplexes MCI through MC4. The multiplexer/demultiplexer 4 is near the switching network 5 and is connected to it by four bi-directional multiplexes MTI through MT4. The multi- S 20 plexes MCI through MC4 and MTI through MT4 offer a bit rate of 2.67 Gb/S and a load of 0.4 Erlang. The lines MDI, MD2 offer a bit rate of 2.5 Gb/s and a load of 0.8 Erlang, representing the standardised specification of optical fibre transport **networks using asynchronous time-division multiplexing.

The multiplexes of the switching network 5 offer a bit rate of 2.6 Gb/s with a maximal load of 0.4 Erlang. This bit rate his been adopted because it enables the very high speed of optical technology to be exploited and the reduced load of 0.4 Erlang makes it possible to reduce the size of the buffers used in the switching network 5, the reduction in the size of these buffers being very significant if the load is reduced from 0.8 to 0.4 Erlang. However, the transmission systems connecting the remote concentrators to the switching network 5 must have a maximal load compatible with the optimal efficiency of a link, which represents a load of 0.8 Erlang.

To exploit the speed of optical technology in the first stages of the subscriber access unit, cells arriving from terminals are multiplcxcd at 2.6 Gb/s. This bit rate is the same for all the concentrators so that till can have the same structure irrespective of their distance from the local central office. Transmission between a remote 1r .f 7 concentrator such as the concentrator 2 and the switching network 5 is therefore handled by a multiplexer/dccmultiplexer 3 which multiplexes cells from a subscriber terminal in the ratio 2 to I and a multiplexcr/demultiplexer 4 which clemultiplexes the same cells in a ratio I to 2. The multiplexcr/dcmultiplexers 3 and 4 naturally effect the converse functions for cells from the switching network and to a subscriber terminal. The multiplexer/demultiplexer 3 also changes the bit rate from 2.6 Gb/s to and the multiplexer/demultiplexer 4 effects the converse change in the bit rate to match the input-output bit rate of the multiplexer/dmultiplexers 3 and 4 to the standardised bit rate of the lines MDI and MD2.

Concentrators near the switching network 5 such as the concentrator 7 are each connected directly to the network by four bi-directional multiplexes each offering a bit rate of 2.6 Gb/s and a load of 0.4 Erlang. In this example the switching network 5 has 28 two-way ports for 128 multiplexes MTI through MTI28 at the bit rate of 2.6 Gb/s and a load equal to 0.4 Erlang. It can connect 16 concentrators and there- 15 fore 4 096 subscriber terminals. The 16 concentrators use 64 ports of the switching network 5. Two other ports are connected to the control unit 8 by two multiplexes and 62 other ports are connected to 31 utiplxrmultiplexr/dmultiplexers providing a link to the local central office. Of thcsc, only the multiplexer/demultiplexer 9 is shown by way of example.

20 The multiplexer/demultiplexcr 9 applies time-divlsion multiplexing to the cells supplied by the switching network 5 and laddressed to the main telecommunication network, converting the bit rate from 2.6 Gbis to 2.5 Gb/s because it modifies the cell headers by eliminating the routing label thnt was needed as far as the output of the switching network 5 but not beyond this point. It modifics the load of the multiplexes outgoing from the switching network 5 by increasing it from 0.4 Erlang to 0.8 Erlang so that is more compatible with the optimal efficiency of transmission lines to the main telecommunciation network. It carries out the opposite conversion for cells incoming from the.main telecommunciation network. It raises the bit reate from 2.5 to 2.6 Gb/s by leaving 24 bit periods free before each cell for the subsequent insertion of a routing label.

In most of the means shown in Figure I the functions are implemented by optical circuits but are controlled by electronic circuits, especially the control unit 8, the technology of optical memories being as vel insufficiently developed for it to be feasible to substitute optical circuits for all the cOntrol electronic circuits.

Figure 2 shows the block diagram of a subscriber access circuit such as the circuit 1 for example. It comprises two scrics of three stages connected in parallel to process the cells from a subscriber terminal and the cells to this subscriber terminal.

Cells from a subscriber terminal entering via the two-way line LAI are first processed by a cell delineator stage 21 which identilies the start of each cell. The cells are then processed by a stage 22 which de-scrambles the data contained in each cell. It is then processed by a stage 23 which extracts the empty cells sent by the subscriber terminal when there is no data to send. Finally, these cells are sent over the bi-directional line

LBI.

Cells addressed to the subscriber terminal arrive over the bi-directional line LBI and are processed by an empty cell inscrtor stage 26 so that each time interval re- 7 presenting a cell is occupied by the transmission of a cell to the subscriber terminal, even if there are no data cells to be sent. The cells, empty or otherwise, are then S. processed by a data scrambler stage 25. All the cells to be sent to the subscriber terminal are then processed by a stage 24 which calculates an error detection word relating to the header of each cell. Finally, the cells arc sent over the line LA1.

Scrambling, de-scrambling and error detection word calculation conform to CCITT Recommendation 1432 and are implemented by optical circuits derived directly from Sconventional electronic circuits in which optical components having the same respective functions are substituted for the electronic components. Their implementation will therefore be obvious to the man skilled in the art.

Figure 3 shows the block diagram ofl a concc itrator such as the concentrator 2.

It comprises two series of stages in parallel respectively processing cells from and cells to the subscriber access circuits. The cells from 256 subscriber accss circuits arriving over the 256 lines LBI through LB256 arc first processed by a stage 31 comprising 16 modules 31.1 through 31.16 in parallel. Each of these 16 modules has 16 inputs connected to 16 of the lines LBI through LB256. Take the module 31.1, for example.

For 16 lines LBI through LB16 it effects concentration by means of non-synchronous statistical spectral and time-division multiplexing. The module 31.1 supplies on a single optical fibre 32.1 at a bit rate of 622 Mb/s cells encoded by 16 different wavelengths (colours).

These cells are then processed by a slige 33 which re-synchronises them to a local clock of the subscriber access unit. The.stagc 33 comprises 16 modules 33.1 through 33.16 in parallel. Each of these 16 m.odules has an input connected to a respective output of a module 31.1 through 31.16. For example, the module 33.1 resynchronises cells supplied by the module 31.1 over the optical fibre 32.1. From the output of the module 33.1 an optical fibre 34.1 conveys the re-synchronised cells to a spectral multiplexing and bit rate converter stage 35. The stage 35 has 16 inputs connected to the respective outputs of 16 modules 33.1 through 33.16 by 16 optical fibres 34.1 through 34.16. At each input it receives cells that can take 16 colours at a bit rate of 622 Mb/s and it restores at a single output cells of 16 colours at 2.6 Gb/s.

An optical fibre 36 conveys these cells to a periodic time-division multiplexing stage 37 to divide the cells between four multiplexes MCI through MC4 at a bit rate of 2.6 Gb/s and with a load of 0.4 Erlang.

The cells are spectrally multiplexed in the stage 31 to divide by 16 the number of modules of the re-synchronisation stage 33. The cells reconstituted by the stage 33 are spectrally re-multiplexed by the stage 35 to impart 16 different colours to the S. respective 16 cells received on the 16 inputs of the stage 35. Because of this spectral re-multiplexing it is possible to use a single moduile in stage 35 to process cells from 5 16 modules of the stage 33 representing 256 subscriber terminals.

On the other hand, this spectral multiplexing cannot be retained in the switching network 6. This is why there is provided a stage 37 which substitutes foi spectral multiplexing of 16 colours on the optical fibre 36 periodic time-division multiplexing on four optical fibres. The cells sent on these four fibres representing the multiplexes MCI, MC4 can be any colour; these colours are no longer indicative of spectral multiplexing.

Cells from the switching network 5 and addressed to 256 subscriber terminals are supplied to a stage 40 by the multiplexes MCI through MC4. The order of these cells has been changed by the switching network 5 so that they can be time-division multiplexed by simple periodic timc-division demultiplexing. The stage 40 effects a first degree of deconcentration by means of periodic time-division &dg. and carries out spectral multiplexing to simplify the stages on its output side.

The cells arriving from the switching network 5 can be any colour. The stage groups them onto a single fibre 41 assigning them-16 different colours. The bit rate of 2.6 Gb/s is retained and as a result each packet of 16 different colour cells is followed by a gap whose duration is equal to three cell periods.

A stage 42 then changes the bit rate from 2.6 Gb/s to 657 Mb/s and applies a first degree of spectral demultiplexing. 16 optical fibres 43.1 through 43.16 convey to a stage 44 the cells supplied by the stage 42 and which are spectrally multiplexed using 16 different colours at 657 Mb/s. The stage 44 comprises 16 modules 44.1 through 44.16 in parallel. Each module effects a second stage of deconccntration by a second stage of spectral demultiplexing. Each module supplies cells to 16 lines chosen from the 256 lines LBI through LB256. It adjusts the bit rate to 622 Mb/s by eliminating the 24 routing label bits associated with each cell, which are of no further utility beyond this stage 44.

It is seen that each re-synchronisation module 33.1, 33.16 is on the output side of a spectral and time-division multiplexer module 31.1, 31.16, which provides a first level of concentration representing 16 subscriber terminals. Consequently, a subscriber access unit in accordance with the invention requires 16 times fewer resynchronisation modules 33.1 thrcough 33.16 than a known type subscriber access unit.

Because spectral multiplexing is used the bit rate converter state 35 is common to 256 subscriber terminals. Consequently, a subscriber access unit in accordance with the invention requires 256 times fewer bit rate converter devices than a known 15 type subscriber access unit.

Thanks to the spectral multiplexing carried out by the stage 40 on the input side of the bit rate converter stage 42, the latter is common to 256 subscriber terminals.

On the other hand, it would have to be duplicated 16 times if there were no spectral multiplexing.

By virtue of the spectral multiplexing function which remains up to stage 44, the bit rate conversion function is implemented in each module 44.1 through 44.16 for 16 subscriber terminals.

Figure 4 shows the block diagram of one embodiment of the switching network 5. It comprises 16 identical devices 50.1 through 50.16 each having eight inputoutputs respectively connected to eight of Ihe multiplexes MTI through MT128 to verify the cell headers, translate the virtual circuity or virtual circuit group label of each cell, insert a routing label in front of the header of each cell, calculate a new error detection word and fulfil the policing function which monitors the bit rate on each call, in other words corresponding to each virtual circuit or virtual circuit group.

It further comprises 24 16x16 switching matrices which are identical and of which 16 (51.1 through 51.16) are used in an 8x8 bi-directional access configuration to constitute simultaneously first and third switching stages and eight matrices 53.1 through 53.8 are used folded to offer 16 input-outputs and constitute a second switching stage.

II

Each device 50.1 through 50.16 further comprises eight input-outputs connected respectively to eight input-outputs of one of the 16 matrices 51.1 through 51.16. The input-outputs ESI through ESS represcnt the rows of the matrix. Each of the matrices is associated respectively with an electronic control device 52.1 through 52.16 comprising a microprocessor. Also, the matrices 51.1 through 51.6 each have eight input-outputs ES'I through ES'8 in corresponding relationship to the columns of the matrices and which are connected to eight input-outputs of the matrices 53.1 through 53.8 in the following manner: the ith input-output of the matrix 53.j is connected to the jth input-output relating to a column of the matrix 51,i i varies between I and 8 and i varies between I and 16). Each of the matrices 53.1 through 53.8 is associated with a respective control device 54.1 through 54.8 analogous to the control devices 0. S 1. 52.1 through 52.16.

Each cell comprises a header of five bytes followed by 48 data bytes when it .enters the switching network 5. The header includes a label identifying the virtual circuit of a subscriber, a label identifying any virtual circuit group connecting a plurality of virtual circuits and an error detection word relating to the header. The routing in each switching stage, in particular in the matrices of the switching network 5, is effected by means of a routing label which is joined to the header of each cell.

In the subscriber access unit in accordance with the invention the routing label is inserted at the switching network 5 when a cell enters the network 5 by means of the devices 50.1 through 50.16.

in this typical embodiment the switching matrices of the network 5 have 16 outputs. Determiinig the routing at each stage of the call requires four bits. The maximum number of switching stages to be passed through is five, and consequently the routing label must comprise at least 20 bits. There is therefore provision for adding a routing label on three bytes (24 bits) to the header of each cell. This produces cells comprising a larger number of bits and therefore imposes a bit rate change from 2.5 Gb/s to 2.6 Gb/s. The routing labels are deleted and the initial bit rate of 2.5 Gb/s is re-selected in the multiplexcr/demultiplexers etc.) which constitute a transmission interface to a local central office of the main telecommunication network.

Note that the concentrators 2 and 7 offer a bit rate of 2.6 Gb/s even though they do not implement the routing label insertion function. They space out the cells by making provision for subsequent insertion of'routing labels by means of the devices 50.1 through 50.16.

Ij 12 These devices 50.1 through 50. i6 group togcther the functions relating to access to the switching network 5: verification of the header of each cell, translation of the label of the virtual circuit or virtual circuit group, insertion of a routing label before the pre-existing header, '.lculation of a new error detection word applying to all of the new header and the policing function. These functions are located at the entry to the switching network 5 and not in each subscriber access circuit, as was the case with the prior art. They are common to four multiplex MCI through MC4 which represents 256 terminal subscribers in this embodiment. Consequently, reducing their number makes it possible to reduce the overall cost of the optical subscriber access unit.

It is possible to shift these functions to the input of the switching network because asynchronous time-division multiplex switching is a statistical multiplexing process. In particular, the subscriber terminal call concentration function is for statistical multiplexing of cells from lightly loaded subscriber multiplexes to multiplexes that have a higher load. As concentration is a simple function of statistical multiplexing, it is possible to shift as far as the entry of the switching network 5 the devices implementing the functions mentioned above. However, this arrangement requires the provision of different virtual circuit labels for all of the 256 subscriber terminals connected to each concentrator. The CCITT provides 16 bits for each virtual circuit label in the cell header so that for the virtual circuit label field there is no problem of assigning different labels to calls reprcscnting 256 subscriber terminals connected oo to the same concentrator.

A virtual circuit label is assigned to each call by the control unit 8. This label designates the virtual circuit as assigned to that call on a multiplex in orer to route the call either to the local central office of Ihe subscriber access unit or to a multiplex to another subscriber terminal connected to the same subscriber access unit through the same concentrator or a different concentrator.

A routing label is assigned to each cell of a call by the control unit 8 for routing this cell across the switching network 5 or across a concentrator 2, 7, etc. In this latter case the routing label comprises not only information for crossing the switching stages o< the switching network 5 but also routing information for crossing the concentrator to which the destination subscriber terminal is connected. To route a call from the switching network 5 to a subscriber terminal requires switching and not only the multiplexing in concentrator stage 44 for cells from the switching network B 13 addressed to a subscriber terminal. This will emerge later during the detailed description of the concentrator 2.

The switching network 5 not only routes each cell to a multiplex connected to the concentrator to which the cell is addressed but also sorts the cells outgoing on each multiplex so that the stage 40 of a concentrator can time-division demultiplex them by means of simple periodic time-division demultiplexing. Twelve bits of the routing label are used to route each cell in the three stages of the network 5 and two other bits are used to identify the order of the cells in a group of four cells on a multiplex.

The routing bits are read in the control devices 52.1 through 52.16 and 54.1 through 54.8 associated with the matrices 51.1 through 51.16 and 53.1 through 53.8.

These control devices route and delay the cells in the ,:atrix queues according to the routing bits. The two bits used to identify the order are assigned to the cells in such a way as to identify the order in which the cells must leave the switching S 15 network Figure 5 shows the more detailed block diagram of one embodiment of the module 31.1 from the stage 31 of the concentrator 2 which effects a first concentration of the cells from the subscriber terminals by means of non-synchronous statistical spectral and time-division multiplexing. This module 31.1 comprises a first part consisting of 16 encoders Cl through C16 each used to encode a cell using a S•different wavelength chosen from 16 wavelengths, a second part comprising a buffer 76 for writing and reading 16 cells encoded using the 16 previously mentioned wavelengths and an electronic control device 70 including a local clock.

An input of each encodcr Cl through CI6 is connected to a respective line LBI through LBI6. An output of each encoder is connected to an input of the buffer 76.

The buffer 76 comprises: an electrically controlled filter 59; a combiner 60 having 16 inputs constituting the inputs of the buffer 76; two three-port couplers 61 and 63; an optical amplifier 62; a two-input combiner 64; two electrically controlled optical gates 65 and 69; two periodic filters 66 and 67; and an optical delay line 68 introducing a'time-delay equal to the duration of a cell at 622 Mb/s.

14 An output of the comb'ner 60 is connected to a first port of a coupler 61. A second port of the coupler 61 is connected to an input of the optical amplifier 62.

An output of the latter is connected to a iirsl port of the coupler 63. A second port of the latter constitutes the output of the buffer 76 and is connected to an input of the filter 59. The output of the filter 59 constitutes the output of the memory 76 and of the module 31.1.

A third port of the coupler 63 is connected to a first end of the delay line 68.

A second end of the delay line 68 is connected to two filters 66, 67 in parallel. Each of these two filters covers a band of wavelengths comprising eight of the wavelengths used to encode the cells. These filters can therefore eliminate these 16 wavelengths, in groups of eight. The filter 66 is connected to the optical gate 65. TheI. 'lter 67 is connected to the gate 69. The outputs of the gates 65 and 69 are connected to the i inputs of the combiner 64. An output of the latter is connected to the third port of ;.the coupler 61.

The electronic control device 70 has \two outputs connected to respective control inputs of the gates 65 and 69, an output connected to a common control input of each of the encoders Ci through C16, an output connected to the module 33.1 and an input receiving cell detection signals supplied by an output common to the 16 encoders Cl through C16.

Each encoder, for example the encoder Cl, comprises: a cell detector device 71 comprising an optical part (not shown) through which passes the optical signal conveying the cells and an electronic part (not shown) capable of recognising the start of a cell; a delay line 72 deaying the optical signal from the device 71 to give the electronic part of the device 71 and the device 70 time to carry out their calculations; a wavelength converter 73 having an input recciving an optical signal supplied by an output of the dclny line 72, an electrical control input and an output constituting the output of the encoder and supplying an optical signal to the combiner an electronic AND gate 74; and an electronic control circuit 75 which supplies the control signal for the wavelength converter 73.

The AND gate 74 has a first input which constitutes the control input of the encoder and receives a control signal supplied by the device 70 to determine the wavelength of the signal leaving the encoder,'a second input connected to an output of the cell detector device 72 which supplies a signal to enable this gate and an output connected to an input of the electronic control circuit 75. The electronic part of the device 71 has an output which supplies a cell detection signal at the common output of the encoders connected to the input of the control device When the device 71 detects a cell the control device 70 chooses the wavelength with which the cell will be encoded and sends a message to the common input of the encoders Cl through C16. This message is sent in the coder which has received the cell, the AND gate 74 being enabled in this encoder by the cell detector device 71 and the "ounterpart gates being disabled in the other encoders. The cell encoded in this wt y one colour is stored in the buffer 76.

The device 70 measures the phase difference between the start of each cell and the local clock. It determines the value R of the time-delay to be applied to each cell in order to re-synchronise it with the local clock and then sends this value to the module 33.1 immediately before sending it the relevant.cell.

The buffer 76 operates as follows: it comprises a loop that can store up to 16 S 15 cells of 16 different colours. The amplifier 62 regenerates an optical signal each time that it has completed one cycle in the btffer 76. The time-delay introduced by the delay line 76 represents one cell. Reading one cell of the 16 cells stored in the buffer is carried out by filtering in the filter 59 so as to read only one cell at a time. The buffer 76 is erased one half at a time, by erasing eight cells encoded on eight wavelengths while eight other cells are being written on eight other wavelengths. The op- "tical gates 65 and 69 are alternatively opened and closed by the device 70 to carry out this "half and half" writing and erasing.

At this stage the cells from 16 subscriber terminals are concentrated onto the single optical fibre 32.1 by spectral multiplexing on 16 wa~clengths but they are not synchronised to the local clock.

Figure 6 shows the more detailed block diagram of the module 33.1 from the stage 33 of the concentrator 2 for synchronising cells relative to the local clock. This module 33.1 processes the cells one by one. It comprises: a variable delay line 80 that is adapted to introduce a time-delay between 0 and Tb where Tb is the bit period; two three-port electrically controlled couplers 81 and 85 adapted to route a signal supplied to an input to a chosen one of two outputs; nine fixed delay lines 86, 87. 88.introducing time-delays equal to 2'Tb, 256.Tb, where p varies from 0 thro6gh 8; 16 eight four-port couplers 82, 83, 84 adapted to be controlled electrically to route a signal supplied to either of two inputs to a chosen one of two outputs; and a control device 79 connected to the control device 70 of the module 31.1 to receive the value R of the time-delay to be applied to each cell.

The fibre 32.1 is connected to an input of the delay line 80. An output of the line 80 is connected to an input of the couplr 81 The coupler 81 sends the cells from the delay line 80 either to a First input of the coupler 82 via the delay line 86 or directly to a second input of the couplcr 82. The latter sends the cells either to its first output or to its second output. When the cells reach the coupler 83 it sends them either to the first input of the coupler 84 via the delay line 87 or directly to the second input of the coupler 84. The cells are sent in this way stage by stage to the coupler 85 which has only three ports, a first input connected to the output of the delay line 88, a second input connected directly to another coupler on its upstream side and an output constituting the output of the stage 33 connected to the optical fibre 34.1. The 15 variable delay line 80 and the couplcrs 81 through 85 have control inputs connected to respective outputs of the control device 79.

Each cell comprises 424 bits at this stage. It is necessary to be able to delay all the bits of a cell by an amount variable betwen 0 and 424.Tb. As the number 424 is between the numbers 256 and 512, the stage 33 comprises nine fixed delay lines of value Tb, 2,Tb, 4.Tb, 8.Tb, 16.Tb, 32.Tb. 64.Tb, 128.Tb, 256.Tb enabling all timedelay values between Tb and 512.Tb to bc obtained by the series combination of some delay lines and short-circuiting the remainder by means of the couplers 82, 83, 84 electrically controlled by the device 79. The variable delay line 80 provides more refined synchronisation. The cells outgoing on the fibre 34.1 are therefore synchronised to the local clock cell period.

Figure 7 shows the block diagram ol a first embodiment 35 a of the spectral multiplexing and bit rate converter stage 35 which operates cell by cell to increase the bit rate from 622 Mb/s to 2.6 Gb/s. At this stage each cell comprises 448 bits because the bit rate conversion also adds a space for 24 routing bits that will be added later to the header of each cell. The stage 35 processes 16 cells simultaneously because the 16 modules of stage 33 supply it simultancously with 16 cells encoded by 16 colours which are not necessarily different. For this reason its first function is to apply spectral multiplexing on 16 different colours., This embodiment comprises: 17 -16 wavelength converters 89.1 through 89.16 having 16 inputs respectively connected to the 16 fibres 34.1 through 34.16 to assign 16 different colours to the 16 cells supplied by the modules 33.1 through 33.16; a combiner 90 with 16 inputs respectively connected to the 16 outputs of the converters 89.1 through 89.16; an optical arplifier 91; a first set of 424 delay lines 95. 96. 97 each introducing a time-delay equal to the bit period Tb at 622 Mb/s; a second set of 424 delay lines 105, 106, 107 each introducing a time-delay equal to the bit period T'b at 2.6 Gb/s; 424 three-port couplers 92, 93, 94 interleaved between the delay lines of the first syt; 424 optical ports 100, 101, 102, 103; a delay line 112 introducing a time-delay equal to 24.T'b representing the S 15 space left for 24 routing bits; and a control device 1ll controlling in parallel all the optical gates 100, 103.

The output of the combiner 90 is connected to the input of the amplifier 91.

The output of the latter is connected to the first set of delay lines through the coupler 92. A first output of each of the couplers 92 through 94 is connected to a respective input of the gates 100, 102. The output of the delay line 97 is connected to an 'input of the gate 103. An output of each of the gates 101, 102 is respectively connected to an input of one of the couplers 108, 109. An output of the gate 100 is connected to an input of the delay line 105.

The set of delay lines 95 through 97 constitutes a first shift register with parallel outputs. The second set of delay lines 105 through 107 constitutes a second shift register having parallel inputs. The gates 100, 103 enable the content of the first register to be transferred to the second register. In the first register the bits of the cell are separated by time intervals Tb relating to the bit rate of 622 Mb/s. When a complete cell is present in the first register its bits are transferred simultaneously into th: second register. The bits of this cell arc separated in the second register by a time interval T'b relating to the bit rate of 2.6 Gb/s. The delay line 112 lengthens each cell by 24 empty bits for the later insertion of 24 routing bits, producing a total of 448 bits per cell. The cell then becomes a 2.6 Gb/s cell and is supplied to the output fibre 34 by the output of the coupler 110. The ccll, supplied by this output are in the form of packets of 16 synchronous cells of 16 different colours. Two consecutive packets are separated by a time interval approximately equal to three times the duration of a packet as the bit rate has been multiplied by approximately four.

Figure 8 shows the block diagram of a second embodiment 35 b of the spectral multiplexing and bit rate conversion stage. This embodiment operates on blocks of 16 bits instead of on cells on 424 bits plus 24 empty bits, which significantly reduces the number of components needed to implement this bit rate converter stage. Each cell of 448 bits is divided into 28 blocks of 16 bits, the 28th block being empty and the 27th block containing only eight wanted bits. The stage 35 b comprises a part 118 which carries out spectral multiplexing, a part 120 which carries out the bit rate conversion on blocks of 16 bits and a part 121 which concatenates the blocks of 16 bits after the bit rate conversion. The stagr 15 b processes 16 blocks of 16 different colours simultaneously, executing spectral multiplexing on 16 different colours deno nted for example, FI F12, F 3, F14, F21, F44. The part 120 outputs each cell in the form ofa string of 28 blocks of bits at 2.6 Gb/s with gaps whose approximate duration is three times the duration of one block, because the bit rate has been multiplied by approximately four.

SThe part 121 concatenates these blocks and outputs packets of 16 synchronous cells separated by gaps witha aapproximate duration of three times the duration of a cell at 2.6 Gbis.

The part 118 comprises: 16 wavelength converters 89'.1 through 89'.16 having 16 inputs respectively connected to the 16 fibres 34.1 through 34.16 to assign 16 different colours to the 16 cells supplied by the modules 33.1 through 33.16; and a combiner 90' having 16 inputs respectively connected to the 16 outputs of the converters 89'. 1 through 89'.16 and an output connected to the part 120 by a single optical fibre 119.

The part 120 comprises: an optical amplifier 91'; a set of 16 delay lineS 95', 96', 97' each introducing a time-delay equal to one bit period Tb at 622 Mb/s; 16 three-port couplers 92', 93', 94'; a second set o delay lines 105', 106'. 107' each introducing a time-delay equal to one bit period T'b at 2.6 Gb/s; 1- 6 three-input couplers 108', 109', 110'; 16 optical gates 100', 101', 102', 103'; and a control device 11 controlling in parallel all the optical gates 100' through 'i (103' with a period equal to the.duration of 16 bits at 622 Mb/s.

The design of this part 120 is similar to the design of the stage 35 a described previously but comprises many fewer components and the transfer from the first register to the second register is 28 times faster. On the other hand, the blocks of 16 bits supplied at the output of the part 120 arc separated by gaps in which there is no bit with the result that each cell is no longer a continuous stream of 424 bits.

The function of the part 121 is to re-establish the continuity of the bits in each cell by concatenating the blocks of 16 bits. The part 121 comprises: a splitter 122; S- 28 optical gates 123, 124, 126; a control device 127 electrically controlling the optical gates 123 through 126 independently of each other; 28 fixed delay lines 127, 128, 129, 130 introducing respective time-delays equal to 0, D, 2.D, 3.DF, 25.D, 26.D where D is the difference between the durations of a block of 16 bits at 622 Mb/s and at 2.6 Gb/s; a combiner 131 whose output constitutes the output of the part 121 and of the stage a control device 132; and a delay line 133 introducing a time-delay equal to 24.T'b.

The splitter 122 has 28 outputs respectively connected to 28 inputs of the combiner 131 by 28 gates 123 through 126 in series with one of the delay lines 127 through 130.

SFor each cell the first block must be delayed by 27.D, the second by 26.D, and so on. The control device 132 controls the gates 123 through 126 in succession to pass the first block into the delay line 130, the second block into the delay line 129, and so on. The 28th block is passed directly by the gate 126 to the combiner 131. At the output of the combiner 131 each cell is again in the form of a continuous stream of 424 bits. Each cell has a different one of 16 colours and is at a bit rate of 2.6 Gb/s.

Spectral multiplexing using 16 colours provides for very efficient use of the stages 33 and 35 but is not suitable for switching in the switching network 5. The function of the stage 37 is to time-division multiplex these cells onto four optical fibres to constitute four 2.6 Gb/s multiplexes that are not spectrally multiplexed.

Figure 9 shows the block diagram of ond embodiment of the stage 37. It receives from the fibre 34 16 synchronous cells multiplexed by 216 different colours denoted Fll, F12, F13, F14, F21, F41, F42, F43. F44. Each packet of 16 cells is followed by a gap whose approximate duration is equal to three cell periods at 2.6 Gb/s.

This embodiment comprises: a splitter 140; a periodic filter 141 passing the colours F I, F21, F31, F41; a periodic filter 142 passing the colours F12, F22, F32, F42; a periodic filter 143 passing the colours F13, F23, F33, F43; a periodic filter 144 passing the colours F14, F24, F34, F44; four delay lines 154 through 157 inlroducing time-delays equal to 0, Tc, 2.Tc, 3.Tc where Tc is the cell period at 2.6 Gbis; a combiner 148; a splitter 149; a bandpass filter 150 passing the colours F14, F13, F12, Fl1; a bandpass filter 151 passing the colours F24, F23, F22, F21; 15 a bandpass filter 152 passing the colours F34, F33, F32, F31; and a bandpass filter 153 passing the colours F44, F43, F42, F41.

The splitter 140 has four outputs respectively connected to four inputs of the combiner 148 by four channels respectively comprising the filter 141, the filter 142 in series with the delay line 155, the filter 143 in series with the delay line 156 and the filter 144 in series with the delay line 157. The output of the combiner 148 is connected to the input of the splitter 149. The splitter 149 has four outputs respectively connected to four outputs of the stage 37 by the respective filters 150 through 153 to provide the multiplexes MCI, MC4.

The four channels which connect the splitter 140 to the combiner 148 shifts the 25 cells to form four packets of four synchronous cells. The first channel passes on with no time-delay the cells having the colours FI I, F21, F31, F41. The second channel passes on with a time-delay equal to the cell period the cells having the colours F12, F22, F32, F42. The third channel passes on with a time-delay equal to two cell periods the cells having the colours F13, F23, F33, F43. The fourth channel passes on with a time-delay equal to three cell periods the cells having the colours F14, F24, F34, F44.

The cells having the colours Fl I, F12. F13, F14 having been made successive and contiguous in time, it remains to route them onto a separate multiplex from the cells representing the other 12 colours. The function of the splitter 149 is to split the 16 colour cells to the four filters 150 through 153 which divde them between four 21 physically separate multiplexes MCI, MC4 on four optical fibres. The filter 150 passes the four consecutive cells having the colours F14, F13, F12, Fl I. At the same time, the filter 151 passes the four consecutive cells having the colours F24, F23, F22, F21. At the same time, the filter 152 At the same time, the filter 152 passes the four consecutive cells having the colours F34, F33, F32, F31. At the same time, the filter 153 passes the four consecutive cells having the colours F44, F43, F42, F41.

At the output of the stage 37 the cells retain their various colours but no longer constitute a spectral multiplex. Each cell can be distinguished by the time slot and the multiplex conveying it.

Figure 10 shows the block diagram of one part of the switching network comprising the device 50.1, the matrix 51.1 and the control device 52.1 associated with the matrix. The matrix 51.1 comprises eight input-outputs ESI, ES8 which are c-nnected to the device 50.1 and eight input-outputs ES'I, ES'8 which are respectively connected to the matrices 53.1, comprises a matrix 180 having 16 inputs for the 5 matrix rows and 16 outputs for the matrix columns. Each input-output ESI, ES8 of the matrix 51.1 is therefore made up of a separate input and output respectively connected to one of the 16 inputs c c 16 of the matrix 180 and to one of the 16 outputs s 1, s 16 of the matrix 180.

The matrix 51.1'further comprises 16 threec-port couplers and 16 delay lines en- 20 abling four routing bits to be sampled in e;ch :cll and supplied to the control device 52.1. For example, the input-output ESI is connected to the input c 1 of the matrix 180 by a coupler 166 in series with a delay line 167 which introduces a time-delay equal to the processing time required for the device 52.1 to interpret the routing bits.

The input-output ES1 is also onnected directly to the output s I of the matrix 180.

25 One port of the coupler 166 is connected to ;n input of the control device 52.1 whose block diagram will be described later.

The device 50.1 comprises eight pairs of 3-port couplers such as the couplers 160, 161, eight pairs of delay lines such as the delay lines 162, 163 and eight pairs of 3-port couplers with an electrical control input such as the couplers 164, 165. Each bi-directional multiplex MTI, MT8 is carried in the device 50.1 by two unidirectional channels with the result that the components of this device are duplicated.

The device 50.1 further comprises: a microprocessor 170; an input-output interface 171; 22 a translation memory 172 a signalling memory 173; a policing memory 175; and a bus 174 interconnecting all the above components.

The cells arriving from subscriber terminals via a concentrator pass in succession through the coupler 160, the delay line 162 and the coupler 164. The coupler 160 is a passive coupler whose third port is connected to an input of the interface 171 to send to the latter the five header bytes of each cell. The delay line 162 introduces a time-delay equal to the time required for the microprocessor 170 to process this header.

The microprocessor 170 checks this header by recalculating the error detection word and comparing it with that cntained in the header, translates the virtual circuit Slabel or virtual circuit group label by consulting the memory 172 which supplies a new label value, adds a routing label to the existing header, calculates a new error 15 detection word to allow for the new virtual circuit or virtual circuit group label and implements the conventional policing function. The coupler 164 is an active coupler for inserting a new header into the cell preceded by three routing label bytes. To this e'.i the coupler 164 has a third port connected to an optical output of the interface 171 and an electrical control input connected to an output of the interface 171 supi 20 plying an electrical enabling signal.

9 The coupler 164 is also used to send signalling or maintenance cells instead of empty cells. The signalling memory 173 stores signalling cells incoming from or out- 9 *going to the switching network 5, for example signalling cells to or from a control system of the telecommunication network to which the subscriber access unit is con- 25 nected.

l Figure 11 shows a more detailed block diagram of the switching matrix 180 and the associated control device 52.1. The device 52.1 comprises a microprocessor 200, an input-output interface 201, a routing memory 202, a pointer memory 203, a signalling memory 205 and a bus 204 intcrconnecting all these components.

The switching matrix 180 comprises 16 wavelength converters 183, 184, a buffer 181 and a space switching device 182. The converters 183, 184 have 16 inputs respectively connected to the 16 inputs c I, c 16 of the matrix 180, 16 outputs respectively connected to the 16 inputs of' the buffer 181 and 16 electrical control inputs respectively connected to outputs of t.i interface 201 of the control device 52.1.

The device 182 executes space switching to transfer each cell reccived on one of the 16 inputs e e 16 of the matrix 180 to one of the 16 outputs s 1, s 16 of the matrix 180.

SThe function of the buffer 181 is to delay the cells before they are transferred into the device 182 as a means of resolving contention problems, that is to say conflict between two cells arriving simultaneously and addressed to the same output of the matrix 180. It must be possible to delay in 16 FIFO type queues cells addressed to any of the 16 outputs s s 16. In the switching matrix 180 the cells can be assigned 16 different colours by the converters 183 through 184 and the cell colour provides a means of distinguishing between 16 queues respectively associated with the S16 outputs, while storing the cells in a set of delay lines common to all these outputs.

The 16 queues are managed by the microprocessor 200 using pointers stored in the pointer memory 203.

neThe value of each pointer is between 0 and k 1 where k is the number of delay 15 lines in the buffer 181. In this example k 16. The next cell to store in a given S queue will be written into the delay line'of rank q I if the pointer of this queue is 0.0 equal to q and if q, is less than k I. If q k I the queue is full and this cell will be lost because it cannot be written into the bufrer 181.

The converters 183, 184 are elec rically controlled by the microprocessor 200 via the interface 201 on the basis of fiour bils which the device 52.1 extracts from the routing label indicating the number of the output to which the cell is addressed. The colour assigned to the cell represents this output of the matrix 180.

The routing memory 202 stores: control parameters of the converter 183, 184 to assign a colour to each cell J* 25 according to the output to which it is ;nddrc~,sed and an indicator for each cell showing whether the latter is part of a point-to-point connection or a point-to-multonnection o ino-ulpon nnection, in which latter case the routing memory 202 supplies parameters for tuning a plurality of filters at the output of the device 182.

The buffer 181 comprises 16 splitters 185, 186, 272 optical gates P272, 16 combiners 187, 188 and 16 delay lines 189, 190 introducing delays respectively equal to 0, Tc, 2.Tc, 3.Tc, 15.Tc where Tc is the cell period. These delay lines can delay any cell byn an amount betwcii) and 15.Tc independently of the cell colour. The splitters 185, 186 each have ;fn input constituting a respective one of 24 the 16 inputs of the buffer 181 and 17 outputs respectively connected to one of the 272 optical gates PI, P272.

Of the 17 outputs of each splitter, 16 are connected by these gates to a respective input of one of the 16 combiners 187, 188 and the seventeenth output is connected by a gate to one input of the input-output interface 201 of the control device 52.1.

This input of the interface 201 is provided with an optical-electronic converter device (not shown) and enables the microprocessor 200 to receive the content of the signalling cells. Each input of each of the combiners 187, 188 is therefore connected by one of the gates PI, P272 to:an output of one of the splitters 185, 186. Thus any cell arriving at any one of the 16 inputs of the matrix 180 can be passed through any one of the 16 combiners, 187, 188 by opening one of the gates PI, P272 which are controlled independently of each other by the microprocesso 200 via the interface 201.

Each combiner 188 has an output connected to one of the delay lines 15. 189, 190. The control device 52.1 therlefore decides to delay by an amount between 0 and 15.Tc each of the cells arriving on one of the 16 inputs of the matrix 180 according to pointers contained in the memory 203 enabling the flow of cells addressed to each of the 16 outputs to be monitored and the time-delay assigned to each cell to be determined. The buffer 181 bchaves like 16 FIFO queues for the 16 outputs of the memory 180.

The number of cells that can hb scored in each queue is set by the number k of delay lines 189, 190. In this example this number is 16. The article "Buffer Sizing in an ATM Switch for both ATM and STM traffics", International Journal of Digital and Analog Cabled Systems, vol 2, 247-252 (1989) shows that an output buffer hav- 25 ing a capacity of 16 cells for each output makes it possible to achieve a cell loss rate equal to 10 1 o It is possible to obtain a given loss figure by choosing the number k of delay lines 189, 190.

In this embodiment the matrices 51.1 through 51.16 of the switching network also change the order of the cells addressed to a concentrator, the order required being indicated by two routing bits. To achieve a given order at the output of the matrix, the cells must be read in this order inside the buffer 181. The queue of each output multiplex is managed by the microprocessor 200 like four independent "subqueues" respectively adapted to store the cells ranked 1, 2, 3, 4.

Consider the queuing of four cells whiclh are to be sent in the order Cl, C2, C3, C4 to a given output of the matrix 181 although they arrive at the inputs of thU ma- 4, 4 trix 181 in the order C2, Cl, C4, C3, for example. The cell C2 is written into the second sub-queue, the cel l C is written into the first sub-queue, the cell C4 is written into the fourth sub-queue and the cell C3 is written into the third sub-queue. The write sub-queue is chosen from the four pending sub-queues for a given multiplex by the two routing bits indicating the rank of each cell. The read sub-queue is chosen periodically: first, then second, then third, then fourth, etc.

The space switching device 182 comprises: a combiner 191 having 16 inputs respectively connected to the 16 outputs of the buffer 181 and formed by the. outputs of the 16 delay lines 189, 190; an optical amplifier amplifying the optical signal supplied by an output of the combiner 191; a splitter 193 having one input connected to the amplifier 192 and 16 outputs; and 16 filters 194, 195 each having an input connected to a respective output of the splitter 193, an electrical control input connected to an output of the interface 201 and selecting one of 16 colours and an output constituting one of the 16 outputs -s 1, s 16 of the switching matrix 180.

The combiner 191, the amplifier 192 and the splitter 193 enable all of the cells leaving the buffer 181 to be applied to the 16 filters 194, control signal supplied to it S 20 by the control device 52.1 for each cell period. They are usually controlled in such a S* way that each filters a different colour to route a cell from a point to a uniquely dei fined other point. In some cases, for example to broadcast a message simultaneously to multiple addressees, these filters can be commanded to filter the same colour in a Splurality of filters representing a plurality of addressees of the same cell.

25 Figure 12 shows the block diagram of the spectral multiplex and time-division demultiplex stage 40 of the concentrator 2. It receives on the four multiplexes MCI, MC4 cells with any colour at a bit rate of 2.6 Gb/s. It outputs on a single optical fibre 41 packets of 16 synchronous cells by spectral multiplexing using 16 different colours at 2.6 Gb/s. Two consecutive packets of 16 cells are separated by a gap whose duration is equal to three cell periods. This stage comprises: four wavelength converters 245 through 248 having four inputs respectively connected to the four multiplexes MCI, MC4; a combiner 249 having four inputs respectively connected to four outputs of the converters 245 through 248; j

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26 a splitter 250 having an input connected to the output of the combiner 249 and four outputs; four electrically controlled optical gates 251 through 254; a set of four delay lines 255 through 257 introducing respective time-delays equal to 0, Tc, 2.Tc, 3.Tc where Tc is the cell period at 2.6 Gb/s; a combiner 262 having four inputs a an an output constituting the output of the stage 40 connected to the fibre 41; and a control device 263 controlling each of the gates 251 through 254 independently and controlling each of the converters 245 through 248 independently.

Each output of the splitter 250 is respectively connected to an input of the combiner 262 by a gate 251, 254 and a delay line 255, 258.

Consider time-division demultiplcxing: S- a packet of four consecutive cells Cl, C2, C3, C4 arriving on multiplex MCI; a packet of four consecutive cells C5. C6, C7, C8 arriving on multiplex MC2; 15 a packet of four consecutive cells C9, CIO, C i, C12 arriving on multiplex MC3; and a packet of four consecutive cells C13, C14, C15, Cl6 arriving on multiplex MC4; these four packets arriving simultaneously.

The four cells from each packet are coloured in succession by one of the converters 245 through 248 so that 16 different colours are assigned to the cells Cl through C16. The colours arc assigned pr-ciodically at intervals of four cell periods.

The four cells of each packet arc time-delayed by respective amounts equa! to 0, Tc, 2.Tc, 3.Tc in order to make them synchronous with each other. To this end 25 each gate 251 and 252 is opened in turn lor the duration of a cell and periodically with a period equal to four cell periods Tc. Thus the cells C4, C8, C12, C16, for example, are sent similtaneously by the gate 254 and arc delayed simultaneously by the delay line 258 which introduces a time-delay equal to 3.Tc. They reach the combiner 262 at the same time as the cells Cl5, C5, 9, C3, for example which are transmitted simultaneously by the gate 251 and which are transmitted with a null time-delay by the line 255.

Figure 13 shows the block diagram of a first embodiment 42 a of the bit rate converter stage 42 of the concentrator 2. This embodiment operates cell by cell in an analogous manner to the stage 35a shown in'Figure 7 and previously described. It processes 16 cells simultaneously, receiving simultaneously 16 synchronous cells spectrally multiplexed using 16 different colours.

Each cell comprises 424 bits plus 24 routing label bits, or 448 bits in all, at this level of the concentrator 2. The bit rate is therefore 657 Mb/s.

The stage 42 a comprises: a first series of 448 delay lines 233, 234 each introducing a time-delay T'b equal to the bit period at 2.6 Gb/s; a first series of 448 three-port couplers 230, 231, 232 interleaved into the first series of delay lines on the input side of each of these lines, respectively; a second series of 448 delay lines 239. 240 each introducing a time-delay equal to Tb', the bit period at 657 Mb/s; a second series of 448 three-port couplers 241, 242, 243 interleaved into the second series of delay lines at the output of each of these lines; 448 electrically controlled optical gates 235, 236, 237; 15 a control device 244 having an output controlling simultaneously all the optical gates 235, 236, 237, 238; a splitter 210 with 16 outputs; and 16 filters 211, 212 respectively tuned to the 16 cell colours having 16 inputs respectively connected to the 16 outputs of the splitter 210 and 16 outputs constitut- S 20 ing the 16 outputs of the stage 42 a connccted to the fibres 43.1, 43.16.

SThe optical gate 235 connects a third port of the coupler 230 to the input of the display line 239. The optical gate 236 connects a third port of the coupler 231 to the third port of the coupler 241 at the output of the delay line 239, etc. The optical gate 237 connects a third port of the coupler 232 to the third port of the coupler 242 at the 25 input of the delay line 240. The optical gate 238 connects the output of the last delay line 234 of the first series of delay lines to the third port of the coupler 243 at the output of the last delay line 240 of the second series of delay lines. One port of the coupler 230 constitutes the input of the stage 42a and is connected to the optical fibre 41. A port of the coupler 243 is connected to an input of the splitter 280.

The two series of delay lines are used like two shift registers. When a complete cell is stored in the first series of delay lines 233, 234 the control device 244 simultaneously commands all the optical gates 235, 238 to transfer 448 bits simultaneously into the second series of delay lines. The bits arrive at the first series of delay lines 230 through 234 at 2.6 Gb/s and leave the second series of delay lines 239 throgh 240 at 657 Mb/s as they are separated by a time-delay equal to Tb'. The splitter 210 and the filters 211, 212 spectrally dlmultiplex each packet of 16 cells onto 16 output optical fibres 43.1 through 43.16.

Figure 14 shows the block diagram of a second cmbodiment 42 b of the bit rate converter stage 42 in the concentrator 2. This second embodiment is an optimised variant of the first embodiment 42 a. The two series of 448 delay lines are replaced by two series of 16 delay lines to apply bit rate conversion in blocks of 16 bits rather than cell by cell, with a view to simplifying the implementation. However, the cells must be divided into 28 blocks of 16 bits first. The stage 42 b therefore comprises a first part 220 dividing each cell into 28 blocks of 16 bits, a second part 221 carrying out the bit rate conversion block by block and a third part 222 comprising a splitter 280' and 16 filter 281', 282' for spectrally demultiplexing each packet of 16 cells onto 6 output optical fibres 43.1 through 43.16.

The first part 220 comprises: a splitter 270 having an input connected to the optical fibre 41 supplying cells at 2.6 Gb/s and having 28 outputs; a combiner 280 having an output constituting the output of the first part 220 which is connected to an input of the second part 221 and 28 inputs; 28 electrically controlled optical gales 271, 272, 273, 274; S- 27 delay lines 275, 276, 277. 278 introducing time-delays respectively equal 20 to 27.D, 26.D, D, 0 where D is the difference between the duration of a block of 16 bits at 657 Mb/s and its original duration at 2.6 Gb/s; and a control device 279 having outputs respectively connected to control inputs of the optical gates 271, 274.

27 outputs of the splitter 270 are respectively connected to one of the 28 inputs S 25 of the combiner 280 by a channel comprising an optical gate in series with a delay Sline.

The control device 279 successively opens the gates 271, 274 to pass successively the 28 blocks of 16 bits constituting each cell. A first block is passed without any time-delay by the gate 274 and the direct connection. A second block is passed 31; by the gate 273 to be stored and delayed in the delay line 277 introducing a timedelay representing a block of 16 bits. A third block is passed by a gate (not shown) into a delay line (not shown) introducing a time-delay representing two blocks of 16 bits, and so on. The 28th block is passed by the gate 271 to be stored in the delay line 275 for a duration representing 27 blocks of 16 bits. The first part 220 therefore passes blocks of 16 bits to the second part 221 and spaces them by a time-delay re- I

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29 presenting the duration of 16 bits at 657 Mb/s, so that each block can be processed in the part 221 because the time available is equal to the duration of a block of 16 bits at 657 Mb/s.

The design of the part 221 is similar to that of the first embodiment 42 a described previously and shown in Figure 14 except that the number of delay lines of the first series 223', 234', the number of couplers 230', 232' interleaved into the first series of delay lines, the number of optical gates 238', the number of delay lines of the second series 240', and the number of couplers 241', 243' interleaved into the second series of delay lines is equal to 16 instead of 448 in each case. Consequently this bit rate converter stage 42 b is much easier to implement than that of the stage 42 a previously described.

The splitter 210' and the converters 211', 212' have the same functions as the components with the same reference numbers in the embodiment 42 a.

Figure 15 shows the block diagram of one embodiment of a module 44.1 of the stage 44 which provides a second stage of dcconcentration by spectral demultiplexing and bit rate adjustment. It comprises: a three-port coupler 289; a bit rate adjuster device 295 which eliminates the three routing label bytes and changes the bit rate from 657 Mb/s to 622 Mb/s to re-establish the continuity of the bits following elimination of the routing header; a wavelength converter 296 having an electrically controlled input; a 16 output splitter 297: 16 filters 298, 299 respectively passing 16 fixed wavelengths and having outputs which constitute the 16 outputs of Ihe module 293 connected to the lines LB1, S 25 LB16; and a routing label extractor device 288.

The coupler 289 has three ports: a first port constitutes the input of the module 44.1, a second port is connected to an input of the bit rate adjuster device 295 and a third port is connected to an input of the routing label extractor device 288. This is a conventional design and its function is to control the wavelength converter 296 by supplying to it an electrical signal which selects a colour so as to impart to a cell a colour representing the content of its routing label. The output of the device 295 is connected to the input of the wavelength converter 296. The output of the latter is connected to the input of the splitter 297. The 16 outputs of the splitter 297 are respectively connected to the inputs of the 16 filters 298 299. The filter representing the wavelength of a cell passes that cell to subscriber terminal.

The bit rate adjuster device 295 will not be described in detail. Its design is similar to that of the part 120 of the stage 35b described previously and shown in Figure 8. The man skilled in the art will know how to adapt this design to effect a change of bit rate from 657 Mb/s to 622 Mb/s.

Figure 16 shows the block diagram of one embodiment of the multiplexer/demultiplcxer/bit rate converter 3. It comprises: four bit rate converter devices DI through D4 receiving the cells from the concentrator 2 via the multiplexes MCI through MC4 at 2.6 Gb/s and outputting these cells at 2.5 Gb/s; a statistical multiplexer 350 receiving the cells output by the devices Dl through D4 on four inputs and outputting on two outputs time-division multiplex cells such that the load of each multiplex is modified from 0.4 to 0.8 Erlang, these cells being then conveyed by the multiplexes MDI and MD2 to the multiplexer/demultiplexer 4; a demultiplexer 351 receiving on two inputs cells supplied via the multiplexes MDI and MD2 at 2.5 Gb/s and having a: maximal load of 0.8 Erlang and outputting demultiplexed cells on four outputs, each multiplex having a load of only 0.4 Erlang; S 20 and four bitrate converter devices D5 though D8 receiving the cells demultiplexed by the demultiplexer 351 at 2.5 Ob/s and outputting them to the multiplexers MCI through MC4 at 2.6 Gb/s.

Figure 17 shows the block diagram ,of one embodiment of the 25 multiplexer/dcmultiplexcr/bit rate convertcr 4. It comprises: a demultiplexer 352 receiving cells supplied by the two multiplexes MDI, MD2 at 2.5 Gb/s and having a maximal load of 0.8 Erlang and outputting on four outputs demultiplexed cells at a bit rate of 2.5 Gb/s and having a maximal load of 2.4 Erlangs; four bit rate converter devices D9 through D12 respectively connected to the four outputs of the demultiplexer 352 to receive demultiplexed cells at 2.5 Gb/s to change their bit rate to 2.6 Gb/s and to supply them to the multiplexes MTI through MT4; four bit rate converter devices D13 I.hrough D16 respectively receiving cells supplied by the four multiplexes MTI through MT4 at 2.6 Gb/s and having a maximal load of 0.4 Erlang and restoring them at 2.5 Gb/s; and a statistical multiplexer 353 receiving on four input cells reconstituted by the devices D13 through DI6 and timc-division multiplexing them to output them via two ou.tputs to the two multiplexes MDI and MD2 at 2.5 Gb/s with a maximal load of 0.8 Erlang.

Figure 18 shows the block diagram of one embodiment of the multiplexer 350.

It comprises: four wavelength converters 300 through 303 each having a first input receiving cells respectively supplied by the four bit rate converter devices Dl through D4; a combiner 304 having four inputs respectively connected to four outputs of the converters 300 through 303; a buffer 305 having a first input connected to the output of the combiner 304; 15 a splitter 306 having an input connected to the output of the buffer 305 and three outputs one of which is connected to a second input of the bu. 305; two electrically controlled filters 307 and 308 having inputs respectively connected to two outputs of the splitter 306 and two outputs respectively connected to the two multiplexes MDI, MD2; and an electronic control device 309 having outputs respectively connected to control inputs of the converters 301, 303. a control input of the buffer 305 and control inputs of the filters 307 and 308, *The design of the buffer 305 is similar to that previously described for the stage 31 of the concentrator 2 and shown in Figure 5. It comprises: S 25 a three-port coupler 310 a first port of which constitutes the first input of the buffer 305; an optical amplifier 311 having an input connected to a second port of the coupler 310 and an output constituting the output of the buffer 305; a combiner 12 having an output connected to the third port of the coupler 310; two electrically controlled optical gates 313 and 314 whose outputs are respectively connected to two inputs of the combiner 312 and which have control inputs connected to outputs of the electronic control device 309; two periodic filters 315 and 316 having outputs respectively connected to inputs of the gates 313 and 314; and 32 a delay line 317 introducing tinmc-delay representing the duration of a cell comprising 424 bits at 2.5 Gb/s whose output is connected to a common input of the filters 315 and 316 and whose input constitutes a second input of the buffer 305 and which is connected to an output of the splitter 306.

The components 310 through 317 constitute a loop which can store up to 16 cells coded by 16 different colours assigned by means of the converters 300, 303. The electronic control device 309 knows at all times the number and the colours of the cells stored in the buffer 305. A particular cell is read by tuning one of the filters 307, 308 to the colour of that cell. The device 309 then commands the erasing of that cell in the buffer 305 by means of an erasing system comprising the components 312 through 316. The filter 3!5 erases cight of the 16 possible colours and the filter 316 erases the other eight colours. The device 309 selects the filter 315 or the filter 316 by opening one of the two optical gates 313, 314. When both optical gates are open none of the colours is eliminated and 16 cells of 16 different colours can therefore S. 15 circulate in the loop in which they are regenerated by the amplifier 311. An alternative implementation of the erasing system comprises two electrically controlled filters instead of the fixed filters 315, 316 and the gates 313, 314.

The statistical multiplexer 353 of the multiplexer/demultiplexer/bit rate converter 4 may be implemented in the same way as the multiplexer 350 described above.

20 Figure 19 shows the block diagram of one embodiment of the demultiplexer 351.

It comprises: two wavelength converters 330. 331 having inputs respectively connected to iii. the two multiplexes MDI, MD2; a combiner 332 having two inputs respectively connected to the outputs of the converters 330, 331; 'i 1- a buffer 333 identical to the buffer 305 previously described having a first input connected to an output of the combiner 332; a splitter 334 having an input connected to an output of the buffer 333 and five outputs one of which is connected to a second in-put of the buffer 333; four electrically controlled filters 335 through 338 each having an input connected to a respective output of the splitter 334 and an output connected to the respective input of one of the bit rate converter circuits D5 through D8; and -an electronic control device 339 having outputs connected to respective control inputs of the wavelength converters 330, 33 1 the buffer 333 and the filters 335 through 338.

The cells supplied by the multiplexes MDI and MD2 with a maximal load of 0.8 Erlang are assigned a colour chosen From 16 colours by means of the wavelength converters 330 and 331 in order to store up to 16 different colour cells in the buffer 333. The control device 339 knows at all times the numbers and the colours of the cells stored in the buffer 333. It commands reading of the stored cells in order to send them in succession to the bit rate converter devices D5 through D8 by commanding the filters 335 through 338 to pass a selected cell to one of the outputs of the demultiplexer 351. When eight cells have been read in the buffer 333 the control device 339 commands the erasing system to crase the cells of these eight colours from the buffer 333.

Figure 20 shows the block diagram of a bit rate converter circuit, for example the circuit D5. It comprises: a splitter 360 having an input connected to the output of the demultiplexer 351 to receive cells at 2.5 Gb/s and n outputs where n is the number of bits in a cell, S 15 which is equal to 424 in the case of the circuit (n 1) delay lines 361, 362, 363 introducing time-delays respectively equa; to (n l).Tbl, (n 2).Tbl, TbI each having an input connected to a respective output of the splitter 360, Tbl being the bit period before the bit rate is changed, that is say the bit period at 2.6 Gb/s for the circuit Cl; S 20 n electrically controlled optical gates 364, 365, 366 each having an input connected to the respective output of one of the delay lines 361, 362, 363 and a gate 367 having an input connected directly to an output of the splitter 360; n delay lines 368, 369, 370 respectively introducing time-delays equal to Tb2, (n 2).Tb2, (n l).Tb2 each having n input connected to a respective output 25 of the gates 365, 366, 367 where Th2 is the bit period for the new bit rate which is 2.5 Gb/s for the circuit DI; n additional delay lines 371, 372, 373, 374 each introducing a time-delay equal to m.Tb2 where m is the number of routing label bits which is 24 in this subscriber access unit; a combiner 375 having an input connected directly to the output of the gate 364, n 1 inputs connected to the respective outputs of the additional delay lines 371, 372, 373, 374 and an output constituting the output of the circuit D5 which is connected to the multiplex MCI and supplies it with cells at a new bit rate of 2.6 Gb/s; and -an electronic control device 376 having an output connected to control inputs of the gates 364, 365, 366, 367.

The n outputs of the splitter 360 are therefore all connected to an input of one of the gates 364, 365, 366, 367 by n delay lines whose time-delays run from 0 through(n l).Tbl in steps of Tbl. Consequently, n bits of the same cell arrive at the input of these gates simultaneously. The control device 376 then opens all the gates 364 through 367 simultaneously to transfer these n bits into the other series of delay lines representing the bit duration Tb2 at Ihe second bit rate. The output of the gate 364 is connected directly to the input of the additional delay line 371. The outputs of all the other gates 365, 366, 367 are connected to the respective inputs of the additional delay lines 372, 373, 374 by a set of delay lines 368, 369, 370 whose time-delays run from 0 through (n I).Tb2 in steps of Tb2.

Consequently, bits output simultaneously by the delay lines 361, 363 arrive with an increasing offset at the input of the additional delays lines 371, 372, 373, 15 374. They are then spread out at intervals equal to the new bit period Tb2. The additional delay lines delay them uniformly by m.Tb2 to leave a gap between two successive cells for subsequent insertion of m routing label bits, m being equal to 24 in this example. At the output of the combiner 375 the various bits of the same cell arrive serially with a bit period Tb2 appropriate to the required bit rate which is 2.6 Gb/s.

The bit rate converter circuits D6, D7, D8 are naturally of the same design as the circuit D5 described above. The bit rate converter circuits DI, D2, D3, D4 which change the bit rate from 2.6 Gb/s to 2,5 Gh/s are of similar design with Tbl replaced by Tb2 for the delay lines 361, 362 33 nd Tb2 replaced by Tbl for the delay 25 lines 368, 369, 370. On the other havnd, Ih le additional delay lines 371, 372, 373, 374 are not requrired as there is no routing label to be inserted for the multiplexes MDI, MD2. The bit rate converter circuits D9 through D12 of the multiplexer/demultiplexer 4 are identical to the circuit D5 described previously, the additonlal delay lines being retained with the same additional time-delay m.Tb2. The bit rate converter circuits D9 through D12 are similar to the circuit D5 previously described except that the additional delay lines 371, 372, 373, 374 are eliminated and the values Tbl and Tb2 are interchanged.

The multiplexer/demultiplexers 9, etc. connecting the network 5 to a local central office are similar to the multiplexer/demultiplexers 3 ano 4 described above.

The scope of the invention is not limi(cd to the cmbodiments described above.

Numerous variants will be obvious to the man skilled in the art. In particular, it is possible to reorder the cells addressed to subscriber terminal by means of a dedicated state on the input side of the stage 40 in cach concentrator interpreting two routing bits to change the order of the cells and comprising a buffer with a capacity of at least four cells for each multiplex connecting a concentrator to the switching network.

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215 20 *C S 2

Claims (8)

1. An optical subscriber access unit for connecting to a telecommunication net- work subscriber terminals sending and receiving data in the form of fixed length cells by asynchronous time-division multiplexing, comprising: a switching network connected to -i local central office; a control unit connected to the switching network; a plurality of concentrators connected to the switching network; and subscriber access circuits respectively connected to the subscriber terminals and to the concentrators; said network, said control unit, said concentrators and said line terminals comprising: means for translating a virtual circuit label or virtual circuit group label included in each cell sent or received by the subscriber access unit and adding to it a u routing label for routing said cell in said subscriber access unit; S. 15 means for synchronising each cell sent by a subscriber terminal with a local clock; and means for implementing a policing function; wherein the means for translating a virtual circuit label or virtual circuit group 20 label for each cell sent or received by the subscriber access unit and adding a routing 20 label to it are located in the switching network and are the same for processing the cells sent or received to or from all subscriber terminals connected to at least one concentrator.

2. An optical subscriber access unit as claimed in claim 1, wherein said means for i implementing the policing function arc located in the switching network and the same 25 policing means are used to process cells received from all the subscriber terminals connected to at least one concentrator.

3. An optical subscriber access unit as claimed in claim wherein said synchronisation means are located in each concentrator and each concentrator further comprises means for spectrally multiplcxing cells received from subscriber terminals O 30 located on the input side of said synchronisation means.

4. An optical subscriber access unit as claimed in claim I, wherein each Sconcentrator further comprises: means for multiplying the bit rale of the spectrally multiplexed and synchronised cells; and means for time-division multiplexing without spectral multiplexing the cells output by said bit rate multiplier means.

An optical subscriber access unit as claimed in claim 1, wherein for sending cells to subscriber terminals each concentrator comprises means for spectrally de- multiplexing cells.

6. An optical subscriber access unit as claimed in claim 5, wherein for sending cells to subscriber terminals each concentrator further comprises: means for time-division demultiplexing cells supplied by said switching net- work addressed to subscriber terminals and then spectrally multiplexing them; and means for dividing the bit rate of the cells supplied by said time-division demultiplexing arnd spectral multiplexing means, said divider means being located on the input side of said spectral demultiplexing means.

7. An optical subscriber access unit as claimed in claim 6, wherein said means for time-division dernultiplexing and spectral multiplexing cells supplied by said switch- 15 ing network addressed to subscriber terminals operate periodically and said switching network further comprises means for chianging the order of the time-division multi- plexed cells according to a routing label before they are supplied to a concentrator.

8. An optical subscriber access unit substantially as herein described with refer- ence to Figures 1 -20 of the accompanying drawings. DATED THIS TWENTYTHIRD DAY OF JANUARY 1992 ALCATEL N.V. -25 'i *e ABSTRACT An optical subscriber access unit for connecting to a telecommunication network subscriber terminals sending and receiving data in the form of fixed length cells by asynchronous time-division multiplexing cornpriscs a switching network connected to a ocal central office. A control unit and a plurality of concentrators 7) are connected to the switching network. Subscriber access circuits 6) are connected to the subscriber terminals and to the concentrators. The design of the subscriber access unit is optimised for better use of optical components. Each concentrator (2, S7) comprises a system for spectrally multiplexing cells received from subscriber ter- Sminals and, on the output side of the hatter, a system for synchronising the multi- plexed cells to a local clock. The switching network comprises a system for translating a virtual circuit label or virtual circuit group label included in each cell sent or received by the subscriber access unit and adding to it a routing label for routing said: ell in said subscriber access unit and a system for implementing a po- licing function. The subscriber access unit has applications in asynchronous time- Sdivision multiplex telecommunication networks. Figure 1. 0 0' 0•