AU624658B2 - A communication adaptor - Google Patents

Description

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ORIGINAL

COMMIONWEALTH OF AUSTRALIA PATENT'S ACT 1952-1969 00.

0 a0 0 00.0 00 COMPLETWE SPECIFICATION FOR 'THE INVENTION ENTITLED "A COMMUNICATION ADAPTOR" The following statement is a full description of' this invention, including the best method of' performing it known to us:- This invention relates to a communication adaptor including a conversion device able to convert first signals received from a first communication device connected to said conversion device and transmitting said first zignal1 according to first electrical and functional interface characteristics into second signals to be sent to a second communication device also connected to said conversion device and able to receive said second signals according to second electrical and functional interface characteristics.

Such an adaptor is already known, e.g. from the article entitle& "Subsets, Terminals, and Teminal adaptors for the public ISDN" by D. Adolphs et al, published in "Electrical Communication" Volume 61, No. 1, 1987, pages 72 to 80. Therein, the communication adaptor is built on an interface printed circuit board and two of such boards may be inserted in a so-called "terminal adaptor". Each of these two communication adaptors is able to operate according to one rate adaptation scheme, i.e. to convert first signals with first 0° interface characteristics into second signals with second interface characteristics. One of these known communiration adaptors is for instaice able to convert the interface characteristics X.21 class 4 or 2.4 kilobit/second data rate of a user station ixito 64 kilobit/second B-channel signals of an Integrated Services Digital Network (ISDN) interface, whilst another communication adaptor i.s able to convert the interface characteristics X.21 class 30 or 64 kilobit/second data rate of another user station into the same 64 kilobit/second B-channel signals of this ISDN interface. Both these conversions correspond to the rate adaptation scheme based on the International Consultative Committee for Telegraphy and Telephony (CC2IT) Recommendation 0 0 0 0 0 A drawback of this known communication adaptor is that it can only perform one rate adaptation scheme and that the interface board onto which it is built has thus to be replaced each time the user station or at least the interface characteristics of the signals thereof are modified. Furthermore, the described solution of including two communication adaptors in a same ter- :4 I minal adaptor box necessarily increases the power dissipation and the volume occupied by this adaptor.

This is avoided by the solution described in the article entitled "The Universal. ISDN Terminal adaptor" by P.E. Weston published as "Conference Record" of "GLOBECOM '86: IEEE Global Telecommunications Conference. Communications Broadening Technology Horizons.", Ref. (Cat. No. 86CH2298-9), Houston, TX, USA, 1-4 Dec. 1986 (New York, USA: IEEE 1986), pages 1434 to 1438, Vol.3. Therein, the conversion device is integrated in a Very Large Scale Integration (VLSI) device or electronic chip and may be programmed in accordance with parameters which define said first electrical and functional interface characteristics amongst a plurality of different possible first electrical and functional interface characteristics.

However, this last known conversion device is only able to handle one type of said second electrical and functional interface characteristics.

~n object of the present invention is to provide a communication adaptor 0 0 of the last mentioned known type but which is even more universal, i.e. a sin- 0 0 o gle communication adaptor which is able to convert first signals with first 00 of. interface characteristics into second signals with second interface characteristics, these being selected out of at least two sets of first or of second electrical and functional interface characteristics.

According to the invention, this object is achieved by including in said 00 0 conversation device, connected between said first and said second communir cation devices, the cascade connection of first progranmable converter rimeans to which the first mentioned parameters are applied and second programmable converter means which are able to be programned in accordance with second pa- 0 Srameters which define said second electrical and functional interface characteristics amongst a plurality of different possible second electrical and functional interface characteristics.

In this way, by a suitable choice of the first and the second parameters the same communication adaptor may operate according to different rate adaptai 1;i tion schemes, i.e. the first and/or the second communication devices connected thereat may be changed whilst only the programmation of the first and/or the second programmable converter means of the communication adaptor has then respectively to be modified and t'ie communication adaptor itself has not to be changed.

Preferably, the second electrical and functional interface characteristics at least consist in transmitting said second signals as standard information channels of a Time Division Multiplex (TDM) link.

Preferably, the first and second parameters are stored into said first and second programmable converter means respectively under the control of processor means.

Preferably, the communication adaptor further includes a second conversion device of the same type as the first mentioned conversion device, operating independently thereof and connected in the opposite direction between said second and first communication devices.

In this way, the above universal communication adaptor operates in a o o So fully bidirectional way.

0 0 0oo0 Preferably, the second converter means is interconnectable with an input of said third converter means and that said communication adaptor includes internal test means able to generate a random test signal having one of said oo0 first electrical and functional interface characteristics, said test means being also able to transmit said test signal to an input of said first converter 0. o means and to compare said test signal with a return signal received in re- So sponse at the output of said fourth converter means, said test signal being successively transmitted through said first, second, third and fourth converter means via said interconnection.

In this way, a self test of at least the communication adaptor may be easily performed at any moment and without requiring external test devices.

Preferably the communication adaptor is integrated in an electronic chip.

p: The integration of a multi-standard communication adaptor in a single electronic chip reduces substantially the volume occupied thereby. irbreover, the use of, eg., the known CMOS technology allows such an integration since the power dissipated is limited to acceptable values.

The above mentioned and other objects and features of the invention will become more apparent and the invention itself will be best understood by referring to the following description of an embodiment taken in conjunction with the accompany.ng drawings wherein Figure 1 shows a block diagram of a communication adaptor MSRA according to the invention; Figure 2 shows a telecommunication system using two communication adaptors MSRA of Figure 1; and Figure 3 shows other applications of the communication adaptors MSRA of Figure 1 in a telecommunication system.

The communication adaptor MSRA shown in Figure 1 is a bidirectional Multi-Standard Rate adaptor for digital telecommunication systems. It is a 3-port device connected to the outside world via: a terminal port TP including a data input terminal TXD, a data output ter- 0 o a o a minal RXD, signalling input terminals generally indicated by TXS, signalling oO o0 output terminals generally indicated by RXS. a transmitter clock input termi- 00 o nal TCI, a transmitter clock output terminal TCO and a receiver clock output terminal RCO; .o o a 64 kilobit/second network port NP including a transmit terminal TX, a reo o ceive terminal RX, a clock terminal CL and a frame terminal FR; and a microprocessor port PP including a microprocessor data bus terminal PD a and control terminals generaly indicated by UT.

It is also provided with two clock reference terminals CRI and CRO across 0 which an external crystal XTAL may be connected to control an internal S oscillator as will be described later.

It mainly comprises three basic sections: a transmit path circuit TXP which couples the data input terminal TXD to the transmit terminal TX; a receive path circuit RXP which couples the receive terminal RS to the data output terminal RSC; and a control section CRTP which is connected to the clock terminals TCI, TCO, RCO, CRI, CRO, CL, the frame terminal FR and the signalling terminals TXS and

RXS.

The transmit path circuit TXP includes, between the terminals TXD and TX, the series connection of a first Universal Synchronous/Asynchronous Receive/Transmit (USART) device TXUS, a transmit buffer TXFI and a transmit framer TXFR. TXUS, TXFI and TXFR are interconnected by unidirectional internal busses and, as will be described later, TXUS and TXFR are programmable in order to be able to operate according to various electrical and functional interface characteristics of the signals handled thereby.

The receive path circuit RXP, analogous to TXP, includes, between the terminals RX and RXD the series connection of a receive fr_ Imr RXFR, a receive 0 .o buffer RXFI and a second Universal Synchronous/Asynchronous :ceive/Transmit S (USART) device RXUS. RXFR, RXFI and RXUS are interconnected by internal 0 0 unidirectional busses and, as for TXFR and TXUS, RSFR and RXUS are also pro- 0, 0 29 grarmable.

On the one hand, the transmit path circuit TXP of the communication adaptor MSRA is able to convert data signals transmitted from a user station, such as TEM or TES shown in Figure 2 and connected to the data input terminal TXD of the terminal port TP, via a low speed link, such as LSM or LSS respectively of Figure 2, into information signals which are loaded in information channels transmitted to a network which is for instance an Integrated Services I t 4 Digital Network (ISDN), such as DSN shown in Figure 2 and connected to the transmit terminal TX of the network port NP, via a high speed link, such as IISM and HSS of Figure 2.

I

On the other hand, the receive path circuit RXP of the MSRA is able to perform the inverse operation, i.e. to convert information signals contained in information channels received from the network DSN to the receive terminal RX of the network port NP via a high speed link HSM or P3S, into data signals transmitted to the user station TEM or TES respectively via the data output terminal RXD of the terminal port TP and the corresponding low speed link LSM or LSS.

The low speed side of the communication adaptor MSRA, including the USARTs TXUS and RXUS, is able to handle different signals to be sent (RXUS) to or received (TXUS) from the user station having for instance as main electrical and functional interface characteristics: a bitrate ranging from 75 bit/second up to 64 kilobit/second up to 64 kilobit/second synchronous or up to 19.2 kilobit/second asynchronous; and a format corresponding to a 7 bit or an 8 bit synchronous or asynchronous (with start and stop bits) communication protocol or the HDLC (High level Data Link Control) protocol.

The high speed side of the MSRA, including the framers TXFR and RXFR, is o able to handle, i.e. to generate (TXFR) or to analyse (RXFR), different inforo o mation channels having for instance as main electrical and functional inter- 0 o020 face characteristics a bitrate of 64 kilobit/second and of which the format 0000 corresponds for instance to the rate adaptation scheme: ECMA 102 recommended by the European Computer Manufacturers Association (ECMA) or its equivalent CCIT2 X.30/X.31 recommended by the International o o Consultative Committee for Telegraphy and Telephony (CCITT); DMI (Digital Multiplex Interface) modes 0 to 3; or S- other byte synchronous based data communication protocols or rate adaptation schemes.

0 o' o As will be described below, the high speed link is able to transmit a 0 carrier signal having a frequency of, eg., 64, 256 or 2,000 kilohertz and the 64 kilobit/second information channels are transmitted thereon as part of a frame of a Time Division Multiplex (TDM) signal. The types of TDM signal, i.e. with 1, 4 or 32 information channels per frame, used to transmit these information channels between the MSRA and the network may also form part of the electrical and functional interface characteristics thereof.

The control section CRTP includes a transmit handshake control circuit TXHA, a receive handshake control circuit RXHA, a bus adaptor BUSA, a clock synchronization device and Baudrate generator BAUDA, a microprocessor interface circuit UPIF and an internal mode register or parameter storage circuit INMR of which the functions are described below.

Signalling from the user station to the network occurs via the series connection of the low speed link, the signalling input terminals TXS of the terminal port TP, the transmit handshake control circuit TXHA of the control section CRTP, an unidirectional internal bus linking TXHA and the transmit buffer TXFI, this latter buffer TXFI and the transmit framer TXFR both of the transmit path circuit TXP and via the internal bus linking them, the transmit terminal TX of the network port NP and the high speed link.

In the other direction, signalling is received from the network and transmitted to the user station via the series connection of the high speed link, the receive terminal RX of the network port NP, the receive framer RXFR and the receive buffer RXFI both of the receive path circuit RXP and via the internal bus linking them, another unidirectional internal bus linking RXFI and the receive handshake control circuit RXHA of the control section CRTP, this latter circuit RXHA, the signalling output terminals RXS of the terminal port TP and the low speed link.

It is to be noted that the USARTs TXUS and RXUS only handle data whilst the buffers TXFI and RXFI and the framers TXFR and RXPR handle both data and signalling.

The bus adaptor BUSA of the control section CRTP is connected to both the clock terminal CL and to the frame terminal FR of the network port NP and receives therethrough respective clock and frame signals from the network connected thereat. These clock and frame signals control the operation of BUSA which is further connected to the framers TXFR and RXFR via respective internal busses. More in detail, the bus adaptor BUSA control the moment at which the 64 kilobit/second channel information or any sub-channel of 32, 16 or 8 kilobit/second or super-channel of 128 kilobit/second may be loaded onto or unloaded from the high speed link by the transmit TXFR or by the receive RXPR framers respectively. The bus adaptor BUSA is programmable and is able to handle a TDM carrier signal as mentioned above and which has for instance a frame frequency of: 64 kilohertz according to standards currently used in codec interfaces; 256 kilohertz compatible with interfaces currently available from Mitel; or 2 Megahertz compatible with V* interfaces currently available from Alcatel.

Each frame of the TDM signal is subdivided into either 1 (codec), 4 (Mitel) or 32 (Alcatel) channels of 64 kilobit/second and only one channel out of each frame of this TDM signal is handled by the MSRA.

Up to 256 multi-standard rate adaptors MSRAs may be connected to a same high-speed link or TDM highway without r quiring any additional hardware o therein and under the control of a single host microprocessor (not shown) con- 0 0 nected to the microprocessor port PP of each of these MSRAs.

As will also be described later, when two MSRAs MSRAM-and MSRAS are interconnected through a network DSN such as shown in Figure 2, the clock syn- S o" chronization device and Baudrate generator BAUDAM of the control section CRTP Sof one of these MSRAs, say MSRAM, generates Synchronous Clock Adjust information SCA which is sent to the clock synchronization device and Baudrate generator BAUDAS of the remote MSRA, say MSRAS, which analyses this received information SCA.

S" To this end, the clock synchronizablon device and Baudrate generator 0 S BAUDA is connected to both th-. transmit framer TXPR of the transmit path circuit TXP and to the receive framefr RXPR of the receive path circuit RXP via internal links. The clock synchronization device and Baudrate generator BAUDA is connected to both the transmit framer TXFR of the transmit path circuit TXP and to the receive framer RXFR of the receive path circuit RXP via internal links. The clock synchronization device and Baudrate generator BAUDA is further connected to the transmitter clock input terminal TCI, the transmitter clock output terminal TOO and the receiver clock output terminal RCO of the terminal port TP through which it may send (TCI, TCO)/receive (RCO) clock signals to/from the user station connected to this terminal port TP. These clock signals are used on the low speed link and control the transmission of the data signals flowing through the data terminals TXD and RXD of the terminal port TP. BAUDA is also connected to the above mentioned clock reference terminals CRI and CRO.

The MSRA further interfaces with a host microprocessor (not shown) via a microprocessor bus connected to the microprocessor port PP. This host microprocessor may be of a suitable commercially available type, eg. 8088 of Intel, 6502 of Motorola or any compatible thereto the type being selected by o means of straps (not shown) with its data transmitted/received via the microprocessor data bus terminal PD and its control signals vta the microprocessor control terminals UT of the microprocessor port PP. The control 0 Q terminals UT are connected to the microprocessor interface circuit UPIF of the control section CRTP which, by means of interrupts, controls the operation of other constituent parts of the MSRA to which UPIF is connected via a network 'of internal busses shown in Figure 1. The microprocessor data bus terminal PD is also connected to this internal network of busses. As will be indicated below the microprocessor port PP is mainly used to transmit parameters from the host microprocessor to the parameter storage circuit INMR, data between this host microprocessor and the buffers TXPI and RXPI and signalling between this host microprocessor and the handshake control circuits TXHA and RXHA.

The parameter storage circuit INMR of the control section CRTP of the MSRA stores the above parameters received from the host microprocessor under f i i r control of the microprocessor interface circuit UPIF. These parameters define the electrical and functional interface characteristics of both the user station and the network, i.e. on the rate adaptation scheme to be performed by the MSRA. More in detail, they control the operations of the programmable framers TXFR and RXPR, of the programmable USARTs TXUS and RXUS, of the clock synchronization device and Baudrate generator BAUDA, and of the programmable bus adaptor BUSA to which they are transmitted via an internal network of control lines (not shown) linking these elements to the paramjieter storage circuit INMR. In a preferred embodiment, the parameter storage circuit INMR is distributed over the elements which then only store corresponding parameters so that this circuit INMR does not exist as such.

The parameters indicate to the framers TXFR and RXFR which rate adaptation scheme (ECMA 102, DMI 0, DMI 1, DMI 2, is used; o o to the USARTs TXUS and RXUS which conmunication protocol (synchronous, o asynchronous, HDLC, is used; S to the clock synchronization device and Baudrate generator BAUDA which 0* 0 0 bitrate (19.2 to 64 kilobit/second) is used by the user sbation; and to the bus adaptor BUSA which kind of TDM highway (codec, Mitel, Alcatel, is used.

In this way, when for instance the user of the multi-standard rate adaptor MSRA changes the configuration (characteristics) of his telecommuni- Scation system (user station, network, protocol, the same MSRA may still be used in the new configuration. The user only has to change, via his host microprocessor, the parameters stored in the parameter storage means, and the S constituent parts (TXFR, RXFER, BUSA, TXUS, RXUS) of the MSRA will operate according to this new configuration indicated thereto by these parameters.

Data and signalling flows are possible in both directions between the terminal port TP and the network port NP via TX)FR/RXFR, TXFI/RXPI and TXUS/RXUS, between the terminal port TP and the microprocessor port PP via 11 UE TXUS/RXUS, and data flow only between the microprocessor port PP and the network port NP via TXFR/RXFR and TXFI/RXFI. It is also possible to send information simultaneously from the terminal port TP to both the network port NP and the microprocessor port PP as well as from the network port NP to both the terminal port mP and the microprocessor port PP.

The bufi'er TXi/RXFI is able to request for transmitting/receiving data to/from tli. "ost microprocessor. In that case, they operate with a certain hysteresis. More in detail, the capacity of a buffer TXPI/RXFI is of 16 bytes and for instance TXFI will only request for transmitting data from the host microprocessor when it is almost empty, I when its content is less than or equal to 4 bytes, and this request is stopped when it is full, i.e. when it contains 16 bytes. In this way, the occupancy (load) of the host microprocessor is reduced.

In case the rate adaptation scheme used requires more data storage than that available in the buffers TXFI and RXPI, data may be temporarily transferred via the microprocessor data bus terminal PD to an external RAM memory S (not shaEvo) under control of the host microprocessor.

S mmaarising, the transmit buffer TXPI of the communication adaptor MSRA receives data signals from the USAT TXUS and signalling or control signals from the transmit handshake control circuit TXHA. This transmit buffer TXFI latches all these received signals and transmits them to the transmit framer o TXFR at a suitable moment.

The transmit framer TXFR then arranges these signals and those received from the clock synchronization device and Baudrate generator BAUDA according to a predetermined 64 kilobit/second information channel format corresponding a a o to the required rate adaptation scheme.

a Under the control of the bus adaptor BUSA the transmit framer TXFR "writes" this information channel into the high speed link via the transmit terminal TX. This writing occurs at a suitable moment which is for instance L_ function of the channel number allocated to this adaptor MSRA when a multichannel TDM transmission is realised.

In the other direction the receive framer RXFR under the control of the bus adaptor BUSA, an information channel in each incoming frame of the TDM signal arriving at the receive terminal RX of the MSRA. The information contained in this channel is extracted therefrom by RXFR which transmits it either to the receive buffer RXFI (data and signalling) or to the clock synchronization device and Baudrate generator BAUDA (clock synchronous adjust information SCA). RXFI then distributes the data signals to the USART RXUS and the signalling to the receive handshake control circuit RRXA.

Due to the MSRA being bidirectional, it can readily perform a self test using a built-in raadom signal generator able to send a test data signal to an input of the USART TXUS and to receive in return a test data signal from an output of the USART RXUS. Indeed, one merely has to establish a temporary Sinternal test connection between an output of TXFR and an input of RXFR to complete the necessary loop.

S0'"a By comparing the sent and the returned test signals, one can detect malfunctions of the MSRA. Moreover, the test loop may even be extended through the high speed link to a remote device connected thereto instead of a direct connection between TXFR and RXFR.

The operation of the corrmmunication adaptor MSRA and more particulally of S the clock synchronization device ,and Baudrate generator BAUDA thereof is deiscribed more ii detail hereafter by means of an example illustrated by Figure 2 which shows an application of MSRA in a communication system. In this example, two communication adaptors MSRAM and MSRAS are used to allow the communication between a user station TE and a remote user station TES via a comon digital switching network DSN of the ISDN type. The user station TEM is connected to MSRAM via its low speed link LSM and the remote user station TES is connected to the remote MSRAS via the low speed link LSS of the latter. The 1 i switching network DSN is connected to both MSRAM and MSRAS via the high speed links HSM and HSS thereof respectively.

The user station TEM is provided with a local clock generator which supplies a clock signal CLKM, eg. of 19.2 kilohertz, on the part of the low speed transmission link LSM connected to the transmitter clock input terminal TCI of MSRAM. Because of its local clock generator, the user station TEM may be considered as being the master user station for the signals transmitted therefrom to the user station TES, whilst the latter TES, which is not provided with any local clock generator, is the slave user station for these signals. As will be described below, a clock signal CLKS identical to the clock signal DLEM will be applied on the part of the low speed link LSS connected to the receiver clock output terminal RCO of the remote MSRAS.

This concerns only the signals transmitted from the user station TEM to oo, the user station TES. For the signals transmitted in the other direction, ie.

from the user station TES to the user station TEM, the clock signal on the low speed links LSM and LSS connected to MSRAM and to MSRAS respectively must not necessarily be generated in the same way. Indeed, TES may then for instance be the master user station whilst TEM is the slave user station, or other systems (given later) to generate this clock signal may be used.

To simplify the following description, only the signals transmitted from the master user station TEM to the slave user station TES are considered here- S after.

0 o 0o cc 00 D I S; The clock synchronization device and Baudrate generator BAUDAM of the o communication adaptor MSRAM receives the local clock signal CLM from the master user station TEM via the transmitter clock input terminal TCI of MSRAM and S receives a master clock signal CLKN, eg. of 4 Megahertz, from the switching network DSN via the clock terminal CLM of MSRAM to which part of the high speed link HSM is connected. BAUDAM then derives an exact 19.2 kilohertz reference clock signal from the received master clock signal CLKN and checks the accuracy of the local clock signal CL~M by comparing it with this reference i- r- :1.r 'i -lipi clock signal. Any deviation of the frequency of CLKM from the exact 19.2 kilohertz reference clock signal is detected by BAUDAM which then generates a corresponding Synchronous Clock Adjust information SCA. This information SCA is transmitted via the transmit terminal TX of MSRAM and the high speed link HSM to tne switching network DSN. From there, the information SCA is transmitted further to the clock synchronization device and Baudrate generator BAUDAS of the remote MSRAS via the high speed link HSS and the receive terminal RX of MSRAS. On the other hand, BAUDAS also receives the master clock signal CLKN from the switching network DSN via the high speed link HSS and the clock terminal CLS of MSRAS. By combining SCA and CLKN, BAUDAS generates a clock signal CLKS which is identical to the above clock signal CLKM. The clock signal CLKS is supplied to the slave user station TES via the receive clock output terminal RCO of MSRAS and the low speed link LSS. In this way, a same clock signal CLKM CLKS is used on both the low speed links LSM and LSS of the master user station TEM and of the slave user station TES respectively.

o n ?o When, for instance, the clock signal CLKM is faster than the reference c lock signal of 19.2 kilohertz, the rate of data bits transmitted from the Qo" master user station TEM to the slave user station TES is also larger than the one which normally appears on the low speed links of LSM and LSS. To avoid loss of data in the MSRAM and thus also at the slave user station TES due to o• this too fast clock signal CLKM (and thus also CLKS), the channel format used on the high speed links HSM and HSS is such that it carries, additionally to o the normal number of data bits, eg. 48, an extra data bit which will hb trans- 5 mitted from MSRAM to MSRAS. From MSRAS, these 4b 1 bits of data are transmitted to the slave user station TES according to the clock signal CLKS. On S the low speed link LSS, the rate of data bits is increased owing to this extra Out data bit so that no data is lost during the transmission from TEM to TES.

In the above example, the communication system operates in a so-called "network independent clock mode". However, when neither the user station TEM nor the remote user station TES is provided with a local internal clock gener- 1 Nji ator, the clock signal on the low speed links LSM and LSS is directly derived from the master clock signal CLKN supplied by DSN to both MSRAM and MSRAS and the comnunication system operates in a so-called "network dependent clock mode".

When the master clock signal CLKN has a frequency which is too low, eg.

less than 4 Megahertz, to allow the operation of the communication system in either the network clock dependent or independent mode, another master clock signal may be produced by an internal oscillator connected to the external crystal XTAL mentioned above via the two clock reference terminals CRI Fnd CRO. The frequency, eg. of 8.192 kilohertz, of the crystal XTAL need not be very accurate since the internal oscillator forms part of a Digital Phase Locked Loop DPLL (not shown) which is controlled by an accurate frame signal of 8 kilohertz provided by the network at the frame terminal FR of MSRA.

000) oooa In another application, the multi-standard rate adaptor MSRA may be used 0 0, o0 to connect a Digital Data Set (DDS) or a Digital Feature Set (DFS) to an S- 00 O o interface bus of an Integrated Services Digital Network ISDN. As shown in 0 Fig re 3, such a digital sat or terminal equipment TE is connected to the 0oo0 switching network DSN of the ISDN via the series connection of a terminal adaptor TA including the MSRA in series with an S-interface line circuit SIFC, the S-interface bus S, a network termination NT, a U-interface line Ul of the S ISDN arid a line termination LT1 of DSN. It is to be noted that a host microprocessor MPU1 controlling MSRA is also included in the terminal adaptor TA.

t The same Figure 3 shows also an application wherein two multi-standard 0 rate adaptors MSRA1 and MSRA2 form part of a U-interface model UM. MSRA1 and oooo MSRA2 have their high speed links connected in parallel to a single chip Uo" interface line U2 of the ISDN. The low speed links of MSRA1 and MSRA 23 are connected to data terminals DTI and DT2 via low speed interface circuits INTF1 and INTF2 respectively. The latter INTF1 and INTF2 are also included in the modem UM which further includes a host microprocessor MPU2 connected to both MSRA1 and MSRA2 and to a keyboard/display terminal DSPL. The latter terminal 16 DSPL allows to control the host microprocessor MPU2 and thus also MSRA1 and MSRA2. Such a modem UM allows Time Division Multiplexing (TDM) of 16 data terminals onto one full duplex 2-wires 144 kilobit/second link.

Still another application (not shown) of the adaptor MSRA is to interface existing analog networks or model equipments of analog telephone networks with the 64 kilobit/second B-channel of an ISDN network.

A commercial embodiment of the described MSRA has been realised as a 54-pin electronic chip built on a 68-pin package, with a die size of 54 square millimeter and comprising about 38,000 transistors. It was realised in a 2 micron CMOS technology and a supp.' 1 v-oltage of 5 Volts is applied thereto.

Remote feeding of the MSF'I is possible since its power consumption is of only milliWatt.

While the principles of the invention have been described above in con- 00 o,0 nection with specific apparatus, it is to be clearly understood that this de- 0 01 S0, scription is made only by way of example and not as a limitation on The scope 00 0 o a of the invention.

a 0 0 00o o o000 0 00 0 C, 0 00 u

Claims (22)

1. A communication adaptor including a conversion device able to convert first signals received from a first communication device at a user station connected to said conversion device and converting said first signals according to first electrical and functional interface characteristics relating to signal bit rate into second signals to be sent to a second communication device at a switching station also connected to said conversion device and able to receive said second signals according to second elec- trical and functions interface characteristics, relating to signal bit rate, wherein said conversion device includes a cascade connection of first programmable converter means, buffer means and second programmable converter means between said first and said second communication devices, the first mentioned parameters being applied to said first programmable converter means, said buffer means being able to store said first signals during their transmission from said first to said second converter means, and said second programmnable converter means being able to be programmed 0. 15 in accordance with second parameters which define said second electrical and func- tional interface characteristics amongst a plurality of different possible second elec- trical and functional interface characteristics.

2. A communication adaptor as claimed in claim 1, wherein said signals transmit- ted between said first and said second communication devices are successively loaded 20 into and unloaded from a memory associated with processor means via said buffer means so as to unload these buffer means.

3. A communication adaptor as claimed in claim 2, wherein said signals are only Stransmitted from said buffer means into said memory when a predetermined maxi- mum amount of signals is stored in said buffer means, and in that said signals are 5 only transmitted from said memory back to said buffer means when a predetermined minimum amount of signals is stored in said buffer means so as to reduce the opera- Stion load of said processor means.

4. A communication adaptor as claimed in claim 1, wherein second electrical and functional interface characteristics at least consist in transmitting said second signals as standard information channels of a Time Division Multiplex link. A communication adaptor as claimed in claim 4, wherein said standard infor- mation channels have a bitrate of 64 kilobit/second.

6. A communication adaptor as claimed in claim 4, wherein said second electrical and functional interface characteristics at least consist in transmitting said second 19 signals as information channels which have a bitrate which is a multiple of that of said standard information channels.

7. A communication adaptor as claimed in claim 6, wherein said first signals are received from said first communication device according to a first clock signal having a first clock frequency, whilst said information channels of said second signals are transmitted on said Time Division Multiplex link which operates at a second clock frequency equal to or higher than said first clock frequency, and in that said com- munication adaptor includes control means wherein a bus adaptor controlled by said second clock frequency indicates to said second converter means the moment at which said information channels may be sent to said second communication device.

8. A communication adaptor as claimed in claim 7, wherein said bus adaptor is programmable and operates under control of third parameters which define said moment.

9. A communication adaptor as claimed in claim 8, wherein said third parameters 0 0 15 are stored into said programmable bus adaptor under the control of processor means.

10. A communication adaptor as claimed in claim 1, 8 or 9, wherein all said pa- rameters are stored into parameter storage means included in said communication adaptor and controlled by said processor means.

11. A plurality of communication adaptors as claimed in claim 8, wherein said 0 20 adaptors are connected in parallel to a same Time Division Multiplex link, each of said communication adaptors being programmed to handle a distinct one of said in- formation channels transmitted on said link, a oto S" 12. A communication adaptor as claimed in claim 7, wherein said communication adaptor includes clock synchronization means able to generate said first clock signal by means of a digital phase locked loop controlled by said second clock frequency. OC"" 13. A communication adaptor as claimed in claim 12, wherein said clock synchroni- zation means are able to detect any deviation of said first clock frequency with respect to a reference first clock frequency derived from said second clock frequency by said clock synchronization means, and to transmit said detected deviation to a remote communication adaptor via said second converter means.

14. A communication adaptor as claimed in claim 13, wherein said first converter means are constituted by a Universal Synchronous and Asynchronous Receive and Transmit device. f r I r_ r l- A communication adaptor as claimed in claim 14, wherein said first and second parameters are stored into said first and second programmable converter means re- spectively under the control of processor means.

16. A communication adaptor as claimed in claim 15, wherein said communication adaptor further includes a second conversion device of the same type as the first mentioned conversion device, operating independently thereof and connected in the opposite direction between said second and first communication devices.

17. A communication adaptor as claimed in claim 16, wherein said second conver- sion device includes third and fourth programmable converter means of the same type as said second and first programmable converter means respectively.

18. A communication adaptor as claimed in claim 17, wherein said clock synchroni- zation means are also able to receive said detected deviation from another communi- oo0o00 o' cation adaptor via said third converter means and to generate a second clock signal o 5 at a third clock frequency corresponding to the frequency according to which said o 15 first signals are transmitted to said first communication device and which is based on '"oo a reference third clock frequency derived from said second clock frequency by said clock synchronization means and which includes said received deviation.

19. A communication adaptor as claimed in claim 18, wherein said reference first and reference third clock frequencies are identical, anc' in that said first and third 20 clock frequencies are also identical. o 9

20. A communication adaptor as claimed in claim 17, wherein an output of said second converter means is interconnectable with an input of said third converter 00 *1 0 a means and that said communication adaptor includes internal test means able to generate a random test signal having one of said first electrical and functional inter- S25 face characteristics, said test means being also able to transmit said test signal to an I S°°i input ofsaid first converter means and to compare said test signal with a return signal S received in response at the output of said fourth converter means, said test signal being successively transmitted through said first, second, third and fourth converter means via said interconnection.

21. A communication adaptor as claimed in claim 20, wherein when said output of said second converter means is not interconnected with said input of said third con- verter means, said test signal is also transmitted through at least said second com- munication device. 2" A communication adaptor as claimed in claim 16, wherein said control means R are common to said first and second conversion devices. I .49~ Si., 21

23. A communication adaptor as claimed in claim 16, wherein said clock synchroni- zation means are common to said first and second conversion devices.

24. A communication adaptor as claimed in any one of claims 1 to 23, wherein said communication adaptor is integrated in an electronic chip.

25. A communication adaptor as claimed in claim 24, wherein said processor means of claims 3, 4, 10, 11 or 16 are external to said electronic chip and connected to said communication adaptor integrated therein via a microprocessor port.

26. A communication adaptor as claimed in claim 25, wherein, after being pro- grammed, said communication adaptor is able to transmit all said signals between said first and said second communication devices without control of said processor means.

27. A communication adaptor as claimed in claim 25, wherein said clock synchroni- zation means of claim 13 operates independently of said processor means. 28 A communication adaptor as herein described with reference to the accompany- 15 ing drawings. a 00 0o00 0 0o 00 o 0 a a o 4o 0 a 0K O 0 DATED THIS SEVENTEENTH DAY OF MARCH 1992 ALCATEL N.V. 04 0 ou 0 0 *4a i i: i: 6