AU623121B2 - Process for addressing processing units - Google Patents

Description

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PIT? I W DATE 22/09/89 6 PIT 1 WEAOJP DATE 19/10/89 APPLN. I D 31876 89 PCT NUMBER PCT/DE89/00117 INTERN.JIONALE ZUSAMME'NARBEIT AUF DEM GEBIET DES PATENTWESENS (PCT) (51) Internationale Patentklassifikation 4 (11) Internationale Veriffentlichungsquummer: WO 89/ 08359 H144B 17/02 Al (43) Internationales Veriiffentlichungsdatum: 8. September 1989 (08.09.89) (21) Internaiionales Aktenzeichen: PCT/DE89/001 17 (72) Erfinder;und Erfinder/Anmelder (nurffir US) HERRMANN, Karl (22) Internationales Anmeldedatum: [DE/DE]; Narzissenweg 13, D-8501 Eckental (DE).

28. Februar 1989 (28.02.89) HECHT, Wilfried [DE/DE]; Stem menreuterweg D-8570 Pegnitz STEINER, Erhard [AT/DE]; (31) Prioritatsaktenzeichen: P 38 06 948.2 Flurstrage 1, D-8031I Eichenau NARJES, Ferdinand [DE/DE]; T6lzerstralle 41, D-8000 Milnchen (32) PrioritAtsdatum: 3. Miirz 1988 (03.03.88) WEIMERT, GOnter [DE/DE]; Geisenbrunner- (33)Prioit~tland DE stralle 64, D-8000 Minchen 71 (DE).

(74) Anwalt: MEHL, Ernst; Postfach 22 13 17, D-8000 (71) Anmelder (nurftr PHILIPS PATENTVERWAL- Mfinchen (DE).

TUNG GMBH [DE/DE]; Wendenstralle 35, D-2000 Hamburg 1 (81) Bestimmungsstaaten: AT (europdisches Patent), AU, BE (europliisches Patent), CH (europdisches Patent), (71) Anmelder (far allk Bestirnmungsstaaten ausser DE DE (europdisches Patent), FR (europ~.isches Patent), N.V. PHILIPS GLOETLAMPENFABRIEKEN [NL/ GB (europiiisches Patent), IT (europdisches Patent), NLQ; Groenewoudseweg 1, NL-5621 BA Eindhoven JP, LU (europiiisches Patent), NL (europaisches Patent), SE (europiiischts Patent), US.

(71) Anmnelder (fir alle Bestirnmungsstaaten ausser US): SIE- Veroffentlicht M ENS AKTI ENGESELLSCHAFT [DE/DE]; Wit- Mit ihternationalem Recherchenbericht.

telsbacherplatz 2, D-8000 Miinehen 2 (DE).

(54) Title: PROCESS FOR ADDRESSING PROCESSING UNITS (54) Bezeichnung: VERFAHREN ZUM ADRESSIEREN VON PROZESSOREINHEITEN (57) Abstract In a process for addressing processing units of a monitoring and/or control device, in which a calling unit and processing units provided with addresses exchange information, the processing units are automatically addressed by means of addressing telegrams so that each address contained in an address telegram is incremented. The process is advantageously used in devices for in-process monitoring of devices in communication engineering.

(57) Zusamnmernfassung Bei einemn Verfahren zur Adressierung von Prozessoreinheiten einer Einrichtung zur clberwachung und/oder Steuerung, b ei der eine Aufrufeinheit und mit Adressen versehene Prozessoreinheiten Informationen austauschen, werden die Prozessoreinheiten mit Hilfe von Adressiertelegrammen dadurch' selbsttatig adressiert, dag eine im Adressiertelegramm enthaltene Adresse jeweils inkrementiert wird. Das Verfabren ldBt sich vorteilhaft in Vorrichtungen zur In-Betrieb- Oberwachung von Einrichtungen der Nachrichtenflbertragungstechnik verwenden.

The invention relates to a method of addressing processor units as specified in the precharacterizing part of patent Claim 1.

Such methods are known from German Application 28 23 925 Laid Open for Public Inspection. In the known methods, the addresses are set with the aid of encoding switches or are defined by a peculiar wiring of the rack.

A method of in-service monitoring of a signal communication system in which useful signals are transmitted via an electro-optical transmission circuit and telemetry signals are transmitted via an auxiliary channel is already known from Ewald Braun and Erhard Steiner: "Uberwachung und zusatzliche Dienste der DigitalUbertragungssysteme fur Lichtwellenleiter" [Monitoring and Additional Services of Digital Transmission Systems for Lightguides], telcom report 10 (1987) Special "Multiplex- und Leitungseinrichtungen" [Multiplex and Line Systems], pages 109 through 114.

The known method makes use of address-free telemetry messages so that there is no need for addressing the processor units provided in line terminal units and intermediate regenerators of a transmission circuit.

However, the method cannot be employed directly in signal transmission systems which have a star or tree structure. When in a signal transmission network with star or tree structure, in the message transmission circuit of the associated telemetry system there are provided processor units which are called in a cyclic sequence in address-controlled fashion by a locati,ig unit, one can provide a structure corresponding to the useful signal network also for the message transmission network of the telemetry system.

But there arises the problem that each of the processor units must be set to a specific address, and this must be done not only when the telemetry system is put into operation but also whenever the signal transmission system is subjected to a modification necessitating new addressing of the processor units.

This problem is also encountered, for example, when branched systems for distributing electrical energy or the like are to be monitored with the aid of remote-control means.

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2 Therefore, the goal of the invention is to create a method and circuitry for carrying out the method, which make it possible to automatically address the processor units. More specifically, it should be possible to automatically address instruments comprising processor units for in-service monitoring of communication circuits, preferably digital signal transmission channels.

In particular, a method of in-service monitoring with the polling method, which offers the possibility of central monitoring of digital signal transmission networks with linear structure, branched structure and/or star structure, is to offer the additional advantages of self-addressing of the entire net so that an expensive error-prone manual presetting of addresses is not necessary.

In accordance with the present invention there is disclosed a method for addressing processor units of a means for monitoring and/or 15 controlling a communication transmission equipment, whereby at least one monitoring unit and processor units, the processor units having respective addresses, exchange information with one another during normal operation via a telegram transmission network such that answer back telegrams containing polling telegrams and monitoring data of the S• 20 communication transmission equipment are transmitted to the processor units, said method comprising the steps of: providing processor units at respective operating locations of devices in the communication transmission equipment; providing at least one on-line monitoring channel in the communication transmission equipment, the on-line monitoring channel covering a plurality of transmission sections of the telegram e transmission network; providing in each address of the processor units a first sub-address for the respective transmission section and a second sub-address for the ordering number of the respective processor unit in the respective transmission section; a processor unit connected to one of two ends of the respective transmission section and serving as an addressing unit in an addressing mode outputting an addressing telegram that contains the first sub-address of the respective transmission section; and S 1443 IA 1443o n 2A the processor units of the respective transmission section forwarding a new addressing telegram after an incrementation of the second sub-address contained in the addressing telegram; and each processor unit of the transmission section respectively storing one of the respective address of the received addressing telegrams and the ;i respective address pf the transmitted addressing telegram as its own address.

The invention will be explained in detail with reference to the "i embodiments shown in the figures.

There show Figure 1, a digital signal base line segment; Figure 2, a line net composed of three digital signal base line segments; Figure 3, a star net comprising a plurality of parallel lines; i :4:3 ii -s !i *o 3 Figure 4, a branched star net; Figure 5, a message transmission net with a cascade circuit; Figure 6, a message transmission net with a plurality of cascade circuits; Figure 7, a block diagram of a versatile processor unit; Figure 8, a block diagram of a processor unit with a bus terminal; and Figure 10, a distributed net with a distribution index for the selfaddressing of processor units.

Line terminal units, intermediate regenerators, and lightguides are the basic elements of the digital signal transmission circuit illustrated in Figure 1; the functioning and the transmission features of these elements are controlled with the aid of instruments of a system for in-service monitoring, comprising the locating module 7, the personal computer 8, and the in-service monitoring processor units 6, subsequently termed processor units.

One can do without the locating module, provided that the processor units 6 are designed so that they can be connected as a master or a slave.

Then one of the processor units 6 must be connected as the master and must take on the tasks of the locating module and the other processor units must be connected as slaves.

The smallest unit of a digital signal transmission circuit is a digital signal base line segment, termed line segment 4 in what follows.

In the transmission system of Figure 1, the line segment is composed of two terminal sets 1 and one or a plurality of intermediate regenerators 2 which can be incorporated in the circuit, if necessary.

Each of the terminal sets 1 and each of the intermediate regenerators 2 comprises a processor unit 6 each of which receives the monitoring data via an internal bus from the main system to be monitored.

Depending upon the requirements, the locating region can consist of the following structures: a line which, according to Figure 1 or Figure 2, is built up of one or a plurality of line segments connected in a chain configuration; according to Figure 3, of a net with a plurality of parallel lines; according to Figure 4, a star net provided with branch points.

4 -4- Each of the processor units 6 is controlled by a microprocessor and is configured as shown in Figures 7 through 9. It [the processor unitj has a terminal K2 in the terminal unit 1 and two terminals Kl and K2 in the intermediate regenerator 2, one terminal for each of the two directions, for engaging and disengaging an auxiliary channel superimposed on the useful signal. In addition, a terminal K3 or K3a can be provided for a network node or two terminals K3, K4 or K3a, K4a can be provided for a cascade circuit.

Depending upon the application, terminal K3a or terminals K3a, K4a with two unidirectional interfaces or terminal K3 or terminals K3, K4 with one bidirectional interface are employed.

The data of the processor units 6 are outputted within each line segment 4 through terminals Kl, K2 and transmitted in an auxiliary channel which is preferably superimposed on the useful signal.

Within a line, data of the processor units 6 are inputted and outputted from terminal unit 1 to terminal unit 1 via the four-wire terminals Kl, K2 into the auxiliary channel and, if necessary, transmitted via terminals K3 or K3a from one line segment 4a to the next line segment 4b.

In the arrangement shown in Figure 2, the line segments 4a 4c are connected in a chain configuration. In one of the two end stations of the chain configuration, the locating module 7 is connected to the processor unit 6 of the terminal unit 1. A personal computer 8 is connected to this locating module 7. Additional personal computers 8 are directly connected with the processor unit of the first line terminal unit 1 and with two of the intermediate regenerators 2n.

Within the line segments 4a 4c, useful signals are transmitted from line terminal unit 1 to line terminal unit 1. Within each of the line segments 4a 4c, the data of the processor units 6 are transmitted via an auxiliary channel and between each of line segments 4a 4c, the data of the processor units 6 are transmitted via an ISM bus (in-service monitoring bus) 9 having the interface RS 485 (terminal K3 of processor unit 6).

1 r i All the processor units 6 have an additional terminal 90, specifically with the interface RS 232 C, to which a personal computer 8 can be j connected. Use has been made of this possibility in one line terminal unit and in two intermediate regenerators.

U Figure 3 shows two of a plurality of lines ending at net node N V (branch point).

At network node point N, the processor units of the line terminal units 1 and the locating module 7 are interconnected through the ISM bus 9 S(terminal K3 of processor unit 6).

In Figure 4, points A through G are interconnected via a branched star network. Between point A and B there are provided a line segment 4AB without an intermediate regenerator; between points B and C, two line segments 4BCl, 4BC2, each with an intermediate regenerator 2; between points B and D, a line segment 4BD; and between points D and F and D and G, a line segment 4DF and 4DG, respectively. Moreover, point E is connected via a line segment 4E with the intermediate regenerator 2 of line segment 4BC2.

At each of points A and C, a personal computer 8 is connected to the processor unit of line terminal set 1. Personal computer 8 can be i optionally connected to the ISM bus 9 with the interface RS 485 and with an additional terminal of the processor unit having the interface RS 232 4 C. In addition to the line terminal units 1 of the line segments terminating at the particular point, to ISM bus 9 at point D there is

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connected the locating module 7 which is provided with a system for polling control. For the purpose of connecting signal collecting means, locating module 7 has an additional terminal 70 through which the monitoring data of the star network can be recalled by locating module 7 via the signal collecting means.

The data of processor unit 6 are transmitted at a branch point between line terminal units 1 via terminals K3 or K4 and a network node point.

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6 In the nets as per Figures 1 to 4, a device for process control, specifically a locating module 7 and/or a personal computer 8, is connected to one of the net nodes or one of the processor units. The locating module 7 or the personal computer 8 calls the various processor units 6 in succession by call messages to their addresses, receive their monitoring data by reply message, and evaluate the same.

In the method described below for in-service monitoring, the l.cating messages are transmitted in asynchronous fashion with a standard log according to IEX TC 57. Other logs, CCITT X25 (HDLC format), can be used to transmit the messages. In the master function, the locating module interrogates the processor units of the entire net.

The addressing of the units has a hierarchical structure. There is provided one byte for the addressing of line segments and one byte for the addressing of units, formed by line terminal units and intermediate regenerators within a line segment. The first octet of the address field comprises the address of the line segment, the second octect, the address of the unit, the address of the line terminal unit or the intermediate regenerator.

Subsequently all the addresses are stated in decimal form and encoded in binary form in the message.

The line terminal unit close to the locating module in a line segment is given the function of a so-called addressing line terminal unit.

It is the task of the addressing line terminal unit to initiate the self-addressing procedure within the associated line segment. The addressing line terminal unit is requested to start the self-addressing procedure by the emission of a start-addressing message either from the locating module upon putting the entire net into operation, a unit (a line terminal unit or an intermediate regenerator), e.g., after replacing a unit and the concurrent loss of the respective address, or from a personal computer connected to a unit within the line segment.

7 -7- The start-addressing message fills the two address bytes with the address 255 which, according to IEC TC 57, has the meaning of a broadcast to everybody. The command proper is contained in a so-called organization byte.

Reacting to the start-addressing message, the addressing line terminal units enter into a mode which causes intermediate storage of all the messages arriving from the interface with other digital signal base line segments. In normal operation, the messages are transmitted in transparent mode in the in-service monitoring channel. The various units i are listeningin in parallel and are switched on when their own messages i are transmitted.

In the ensuing development of the procedure, a distinction need be i made between pure line nets and star or branch nets. Line nets are shown in Figures 1 and 2. Star nets are shown in Figures 3 and 4.

First the procedure for a line net is to be described. In this case, automatic self-addressing is possible without any manual address setting.

As has been mentioned before, the addressing line terminal units switch to the storage mode of operation after having received the startaddressing message. The ensuing activities of the addressing line terminal units depend upon the origin of the start-addressing message. If the start-addressing message has been emitted by the locating module, the addressing line terminal units wait for the arrival of so-called addressing messages. In a second step, after emission of the start-addressing message, the locating module emits an address message with the following structure: address fields: line segment 255 (broadcast to everybody) line terminal unit/intermediate regenerator 255 (broadcast to everybody) organization byte: recognition of address message data byte Dl: 1 (current address of the line segment) data byte D2: 1 (current address of the line terminal unit/intermediate regenerator).

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L A 8 Reacting to this address message, all the line terminal units or intermediate regenerators input the contents of D1 into their address memory for the line segment and the contents of D2 into the address memory for the line terminal units or intermediate regenerators. Furthermore, each of the line terminal units or intermediate regenerators increments the contents of D2 and emits a new address message with the new D2 contents. This second address message is received by all line terminal units or intermediate regenerators except for the first line terminal unit. They take over the contents of D1 as their line segment address and the contents of D2 as their address of the unit, subsequently increment D2, and emit a new address message with the new contents of D2. This is sent to all line terminal units or intermediate regenerators except for the first line terminal unit and the first intermediate regenerator.

The above-described cycle continues in accordance with the table of Figure 10 until the distal line terminal unit of the first segment has been reached. In this line terminal unit, the contents of Dl, the address of the line segment, is incremented and the contents of D2, i.e., the address of the line terminal unit or of the intermediate regenerator, is reset to 1.

The proximal line terminal unit, the addressing line terminal unit of the second segment, now accepts 2 as the line segment address and 1 as the address of the line terminal unit or of the intermediate regenerator.

The cycle is continued until the distal line terminal unit of the last segment has been reached.

After an exchange of units, the new units at the beginning do not have any valid addresses. In this case, one must carry out a selfaddressing procedure which may be restricted to the respective line segment.

When put into operation, the replaced instrument emits a startaddressing message. The addressing line terminal unit associated with the

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9 line segment recognizes from the direction of the arriving message (from the line, in the case considered) that a self-addressing procedure is to be initiated.

It emits an address message containing a code in the organization byte indicating that new addressing is to take place only within the digital signal base line segment. The address of the respective line segment is known to the addressing line terminal unit and appears in byte Dl of this address message. Starting from the addressing line terminal unit, the address of the unit is incremented in accordance with the previously described procedure until the distal line terminal unit has been reached. The addressing line terminal unit of the ensuing line segment recognizes from the contents of the organization byte that this address message must not be passed on.

When in a replacement of instruments, one does without the addressing related to the line segment and, in such a case, effects a new addressing of the entire (line) net, the address messages need not be entered into intermediate storage in the addressing line terminal units.

In the case of a star-branch structure, parallel branching of the monitoring net requires presetting the addresses of the digital signal base line segments in the addressing line terminal units, with the aid of switches, encoding pins, soldered shunts or by inputting via a personal computer.

After reception of a start-addressing message, the addressing line terminal units emit address messages irrespective of the origin of the start-addressing message; as in the linear structure, the address messages contain 255 in the two address fields. The respective line segment address appears in byte DI of the data field. Byte D2 again contains the serially numbered addresses for line terminal units or intermediate regenerators. Following the procedure which was described earlier for the case of the linear structure, the units of a line segment are addressed with the fixed line segment address and the serially numbered address of the line terminal units or intermediate regenerators.

10 In this mode of operation, the addressing line terminal units do not pass on the address messages arriving via the interface ISM bus 9.

It is a prerequisite for the proper functioning of the selfaddressing procedure that the address messages are inputted only in the forward direction of a circuit, starting from the addressing line terminal unit.

In what follows, the addressing procedure of a digital signal base line segment after replacement of a line terminal unit or an intermediate regenerator is described.

After exchanging a line terminal unit or an intermediate regenerator and after pulling out a processor module, only all the processor units of a single line segment are conveniently provided with new addresses because of the concurrent loss of addresses. The address assignment within a line segment is initiated after plugging a processor unit into the module of the line segment to be given new addresses and after automatic release by the locating module or the personal computer in a time slot after an interrogation cycle.

The inserted processor module emits a control message via terminals KI through K4 to all processor units in the region of locating. The control message is a long message with the address 255 (all line segments) in the address field, with the address 255 (all processor units) in the address extension, and with the command "transition to monitoring operation" in the organization byte of the data field.

All processor units in normal operation pass on a control message to the ensuing processor units without intermediate storage. In addition, they monitor the address field and the address extension of the message and, after assessing the organization byte, switch to monitoring operation.

Now the processor unit emits a start-addressing message to all processor units of its line segment. The start-addressing message is a long message with the address 255 (all digital signal base line segments) in the address field, with the address 255 Dez. (all the processor units) -0"TI" i L 1 -r; i 11 in the address extension, and with the command "initiate proper addressing line terminal unit for addressing digital signal base line segment" in the organization byte of the data field.

An addressing line terminal unit for addressing a line segment executes the command "initiate proper addressing line terminal unit for addressing line segment" only if it receives this command in a message via terminal K1 or terminal K2. If this command is received in a message via terminal K3 or terminal K4, this message is rejected.

Having received the start-addressing message, the addressing line terminal units for the addressing of a line segment generate an address message with 255 in the address field, 255 in the address extension, the number of the line segment in the third byte of the data field (proper line segment address), and 001 in the fourth byte of the data field (proper processor unit address). After that, this message is sent to the ensuing processor units.

The ensuing processor units in the intermediate regenerators and in the receiving line terminal units at the end of each line segment receive the address message through one of'terminals KI, K2. They [the processor units] directly take over the third data byte of the address message as proper line segment address, increment the fourth data byte by one, and thereafter take it over as the proper processor unit address. Subsequently, the contents of the proper address memory are inputted into the third and the fourth data byte of a new address message and the same is transmitted via terminals K2 of the intermediate generator or K3 of the line terminal unit to the processor module in the same or in the next line segment.

The processor modules in the addressing line terminal units for addressing a line segment receive the address messages of a neighbouring line segment via terminal K3. They reject these messages and do not pass them on.

It is a prerequisite the orderly functioning of the p, edure that the address messages are passed on only to the nexi processor unit but are not sent back.

6h.- 1, 12 In the case of manual addressing of the addressing line terminal units 1, the addresses are set as follows in the locating region.

The addresses of the processor unit are composed of two bytes: an address byte for the number of the line segment in which the processor unit is incorporated; an address byte for the number of the processor unit 6 within this line segment. In a call message with the transmission log according to, say, IEC TC57, the address field is given the number of the line segment 4 and the first data byte (extension of the address) in the data field is given the number of the processor unit 6 to be called within this line segment.

In order to put the devices of the communication link into operation, one of the two line terminal units I at the beginning or the end of each line is given the function of an addressing line terminal unit for the addressing phase. This function, and a freely selectable line segment address, are assigned to the addressing line terminal unit 1 either with the aid of a coding switch or DIP-FIX switch in processor unit 6, through coding pins in the rack, through the edgeboard connector of the module, or through a proper PC connection.

In order to obtain an assignment, in ascending order, of the number of the line segment 4 and the number of the processor unit in the automatic addressing of a locating segment to the processor units as addresses in a unique fashion, considered from the locating module or the personal computer that line terminal unit of each line, which is closer to the locating module or the personal computer, is conveniently designated the addressing line terminal unit.

The processor unit can be switched to two modes for transmitting the messages.

1. Normal mode: All messages arriving at the interfaces are directly transmitted to the following units of the communication link and their contents are checked in parallel by the microprocessor.

2. Storage mode: All the messages arriving at the interfaces are first checked for their contents by the microprocessor before they are passed on to the next units of the communication link.

13 The addressing procedure is as follows when a communication link with manual addressing of the addressing line terminal units is put into operation: After installation of the communication link, the automatic address assignment for all processor units of a locating region is started either at the locating module, by means of a key, or at a personal computer 8 through its keyboard. The locating module 7 or the personal computer 8 transmit a start-addressing message to all processor units of the locating region.

All the -processor units work in the normal mode. The startaddressing message is a long message with the address 255 (all line segments 4) in the address field, with the address 255 (all processor units) in the address extension, and with the commands "transition to storage mode" and "start addressing of addressing line terminal units" in the organization byte of the data field.

All processor units 6 transmit the start-addressing message to the ensuing processor units 6 without intermediate storage. In addition, they [the processor units] control the address field and the address extension of the message and, having checked the organization byte, switch to the storage mode.

Having received the start-addressing message, the addressing line terminal units generate an addressing message with 255 in the address field, 255 in the address extension, the number of the line segment 4 in the third byte of the data field (proper line segment address, termed L address irn what follows), and 001 in the fourth byte of the data field (proper processor address, termed P address in what follows). After that, these messages are sent to the subsequent processor unit.

The subsequent processor units in the intermediate regenerators and in the receiving line terminal units at the end of each line segment 4 receive the addressing message via one of their terminals Kl, K2. They [the processor units] take over the thid data byte of the address message as the proper L address, increment the fourth data byte by one, and 1' I ~1 14 thereafter take it over as the proper P address. After that, the contents of the proper address memory are inserted into the third and fourth data bytes of a new address message and the same is passed on to the processor unit in the following line segment 4 via terminals K1 or K2 in the case of an intermediate regenerator or via terminal K3 in the case of a line terminal unit.

The processor units of the emitting line terminal units receive the address messages via terminal K3 (beginning of a line segment). They increase the third data byte by one (proper L address), transcribe the fourth data byte with 001 (proper P address), and intr'Juce it into the address memory. After that, the contents of the proper address memory is inserted in the third and fourth data byte of a new address message and the same is passed on to the next processor unit.

The processor units of the addressing line terminal units receive the address messages of a neighbouring line segment 4 via terminal K3.

They reject these messages and do not pass them on.

It is a prerequisite for the proper functioning of the procedure that the address messages are passed on only to the next procssor unit 6 but are not sent back.

After replacement of a line terminal unit or an intermediate regenerator, the addressing procedure with manual addressing of the addressing line terminal units is as follows: After exchanging an addressing line terminal unit, the equipment receives its L address either with the aid of coding switch or DIP-FIX switch in the processor unit, through coding pins in the rack, through the edgeboard connector of the module, or through a proper PC connection.

After exchanging a receiving line terminal unit or an intermediate regenerator and after pulling out a processor unit associated with this equipment from the rack, only all the processor units of a line are conveniently provided with new addresses because of the concurrent loss of addresses. The address assignment within a line is initiated after plugging a processor unit into the module of the line to be given new addresses and after automatic release by the locating module or the personal computer in a time slot after a call cycle.

Within this time slot, the inserted processor module emits a controlling message via terminals Kl, K2, and K3 to all processor units and to the locating module or the personal computer in the region of locating. The control message is a long message with the address 255 (all line segments 4) in the address field, with the address 255 (all processor units) in the address extension, and with the command "transition to storage operation" in the organization byte of the data field.

All processor units in normal operation pass on a control message to the ensuing processor units without intermediate storage. In addition, they monitor the address field and the address extension of the message and, after assessing the organization byte, switch to storage operation.

Having received the control message, the locating module/the personal computer enable a time slot which suffices for the addressing operation.

Now the processor unit emits a start-addressing message to the processor units of its line segment. The start-addressing message is a long message with the address 255 (all line segments 4) in the address field, with the address 255 (all processor units) in the address extension, and with the command "start addressing of proper addressing line terminal unit" in the organization byte of the data field.

An addressing line terminal unit executes the command "start addressing of proper addressing line terminal unit" only if this command is obtained in a message via terminals Kl, K2. If this command is obtained in a message via terminal K3, this message is rejected.

Having received the start-addressing message, the addressing line terminal units generate an address message with 255 in the address field, 255 in the address extension, the number of the line segment in the third byte of the data field (proper L address), and 001 in the fourth byte of the data field (proper P address). After that, they send this message to the subsequent processor unit.

16- The subsequent processor units in the intermediate regenerators and in the receiving line terminal units at the end of each line segment receive the address message through one of terminals Kl, K2. They take over the third data byte of the address message directly as the proper L address, increment the fourth data byte by one, and thereafter take it over as the proper P address. After that, the contents of the proper address memory are inserted in the third and fourth data bytes of a new address message and the same is passed on via terminals Kl, K2 in the case of the intermediate regenerator or terminal K3 in the case of the line terminal unit to the processor module in the next line segment 4.

The processor units in the emitting line terminal units receive the address messages via the terminal K3 (beginning of a line segment 4).

They increement the third data byte by one (proper L address), transcribe the fourth data byte with 001 (proper P address), and introduce them into the address memory. After that, the contents of the proper address memory are inserted into the third and fourth data bytes of a new address message and the same is passed on to the next processor unit.

The processor units in the addressing line terminal units receive the address messages of a neighbouring line segment 4 via terminal K3.

They reject these messages and do not pass them on.

It is a prerequisite for the proper functioning of the procedure that the address messages are passed on only to the next processor unit but are not sent back.

In the procedure described so far, the address of an addressing line terminal unit must be set at a branch point or a net node by means of codling pins or by inputting into a personal computer at that point. When in place of a net node with parallel connection one uses a cascade circuit for the branching units, automatic setting of the L address is possible.

Figure 7 shows the block diagram of a processor module with two terminals K3 and K4 or K3a and K4a for the cascade connection of a branch point. Bidirectional busses must be connected to the two terminals K3 and K4 and/or four-wire busses must be connected to terminals K3a and Kea.

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n A -17- Figures 5 and 6 show examples of cascade connections making use of the terminals K3 and K4. Figure 5 shows a net with parallel lines and Figure 6, a net with a tree structure.

The first unit of each branch point becomes an addressing line terminal unit with proper L address in the addressing operation. Each processor unit of a line segment 4 has the same L address and a proper P address.

The following procedure is provided for the addressing: Inputting the net structure through personal computer 8 into locating module 7. An interactive procedure is used to input via the screen of the personal computer the net structure, the number of net nodes, the number of branches with one addressing line terminal unit at each net node, and the number of processor units in each line segment 4.

After establishing the communication link, the automatic address assignment for all processor units of a locating region is initiated either on the locating module by a key or on a personal computer by its keyboard. All processor units are in normal operation.

The locating module or the personal computer sends a control message to all processor units of the locating region. The control message is a long message with the address 255 (all line segments 4) in the address field, with the address 255 (all processor units) in the address extension, and with the command "transition to storage operation" in the organization byte of the data field.

All processor units pass the control message on to the subsequent processor units without intermediate storage. In addition, they control the address field and the address extension of the message and, after 4 checking the organization byte, switch to the storage mode.

The locating module or the personal computer now sends a startaddressing message to the first emitting line terminal unit via terminal K3 of the first net node. The start-addressing message is a long message with 255 in the address field, 255 in the address extension, the number of the line segment in the third byte of the data field (assigned L address), -18- 001 in the fourth data byte of the data field (P address), and the command "start addressing of addressing line terminal unit" in the organization byte of the data field. Through this message this line terminal unit becomes an addressing line terminal unit. The addressing line terminal unit takes over the third data byte and the fourth data byte into its address memory and emits the start-addressing message with a third data byte incremented by one via terminal K4 to the next emitting line terminal unit via terminal K2 of the net node, etc.

Having received the start-addressing message, the addressing line terminal units- at the first net node generate an address message with 255 in the address field, 255 in the address extension, the number of the line segment in third byte of the data field (proper L address), and 001 in the fourth byte of the data field (proper P address). Then they send this message via terminal K1, K2 to the subsequent processor unit.

The subsequent processor units in the intermediate regenerators and in the receiving line terminal units at the end of each line segment 4 receive the address messages via one of terminals Kl, K2. They [the subsequent processor units] take over the third data byte of the address message as the L address, increment the fourth data byte by one, and then take it over as the proper P address.

The receiving line terminal unit does not pass on any address messages via its terminals Kl, K2.

The locating module or the personal computer calls in succession the addressed receiving line terminal units by their address, which units are connected through terminal K4 with an ensuing line segment 4, and causes them to emit a start-addressing message with the previously determined L address to their first emitting line terminal unit.

The emitting line terminal units and the processor units in the line segments of the next net node are addressed in analogy to the addressing of the first net node.

It is a prerequisite for the correct functioning of the procedure that the address messages are passed on only to the next processor unit but are not sent back.

If -19- After the replacement of a line terminal unit or en intermediate regenerator with automatic addressing of addressing line terminal units, the addressing procedure of a line segment 4 is as follows: After replacement of an addressing line terminal unit, the L addresses are re-addressed. The address assignment is initiated after plugging in the new module and after automatic release by the locating module or the personal computer in a time slot after a call cycle.

In this time slot, the processor module of the new module emits an inquiry message to the locating module or the personal computer.

The inquiry message is a long message with the address 255 (all line segments) in the address field, with the address 255 (all processor units) in the address extension, and with the command "re-addressing of the line segments" in the organization byte of the data field.

After reception of this message by the locating module or the personal computer, the re-addressing operation of the line segment is started.

The locating module or the personal computer sends a control message to all processor units of the locating region. The control message is a long message with the address 255 (all line segments) in the address field, with the address 255 (all processor units) in the address extension, and with the command "transition to the storage mode" in the organization byte of the data field.

All the processor units pass on the control message to the subsequent processor units without intermediate storage. In addition, they check the address field and the address extension of the message and, after checking the organization byte, switch to the storage mode.

The locating module or the personal computer now sends a startaddressing message to the first emitting line terminal unit (terminal K3) of the first net node. The start-addressing message is a long message with 255 in the address field, 255 in the address extension, the number of the line segment in the third byte of the data field (assigned L address), 001 in the fourth data byte of the data field (P address), and the command 20 "start addressing of addressing line terminal unit" in the organization byte of the data field. With this message, this line terminal unit becomes an addressing line terminal unit.

The addressing line terminal unit inputs the third data byte and the fourth data byte into the address memory and emits via terminal K4 the start-addressing message with the contents of the third data byte incremented by one to the next addressing line terminal unit (terminal K3) of the net node, etc.

After exchanging a receiving line termi'nal unit or an intermediate regenerator or after pulling the processor module associated with these instruments out of the rack, it is convenient to re-address only all the processor units of a line segment because of the address loss suffered.

The address assignment within a line segment is initiated after plugging a processor unit into the rack of the line segment which is to be re-addressed and after automatic enabling by the locating module or the personal computer within a time slot after a call cycle.

The processor module inserted into the rack emits in this time slot a control message via terminals Kl, K2, K3, and K4 to all processor units and to the locating module or the personal computer in the locating range. The control message is a long message with the address 255 (all line segments) in the address field, with the address 255 (all processor units) in the address extension, and with the command "transition to the storage mode" in the organization byte of the data field.

All processor units in normal operation pass a control message to the subsequent processor units without intermediate storage. In addition, they check the address field and the address extension of the message and, after evaluation of the organization byte, switch to the storage mode.

Having received the control message, the locating module or the personal computer enable a time slot which suffices for the addressing operation.

Now the processor unit sends a start-addressing message to the processor units of its line segment.

212 21 The start-addressing message is is a long message with the address 255 (all line segments) in the address field, with the address 255 (all processor units) in the address extension, and with the command "start addressing the proper addressing line terminal unit" in the organization S byte of the data field.

An addressing line terminal unit executes the command "start addressing the proper addressing line terminal unit" only if this command is obtained in a message through terminals Kl, K2. If this command is obtained in a message via terminals K3, K4, this message is rejected.

After reception of the start-addressing message, the addressing line terminal units generate an address message with 255 in the address field, 255 in the address extension, the number of the line segment in the third byte of the data field (proper L address), and 001 in the fourth byte of the data field (proper P address). After that, this message is sent to the ensuing processor units.

The ensuing processor units in the intermediate regenerators and in the receiving line terminal units at the end of each line segment receive the address message through one of terminals Kl, K2. They [the processor units] directly take over the third data byte of the address message as the proper L address, increment the fourth data byte by one, and thereafter take it over as the proper P address. After that, the contents of the proper address memory are inserted into the third and the fourth data byte of a new address message and the same is sent on via terminals Kl, K2 to the processor module in the next intermediate regenerator. The addressing procedure is completed, when the receiving line terminal unit of this line segment has been addressed. The address message is passed on only within the line segment 4 via terminals Kl, K2.

It is a prerequisite for the orderly functioning of the procedure that the address messages are passed on only to the next processor unit but are not sent back.

In the cases described, in addition to the automatic generation of addresses, a manual, local address inputting via a personal computer connected to the processor unit is possible.

22 -22- Figures 7 through 9 show three types of processor units in principle. The processor unit shown in Figure 7 has the advantage of combining the three types in it.

The processor unit shown in Figure 7 has two four-wire terminals Ki, K2 and the two bidirectional bus terminals K3, K4 for transmitting messages. It [the processor unit] therefore can be used in a line terminal unit 1 as well as in an intermediate regenerator 2.

The four-wire terminal Kl has an input El and an output Al for connecting a first four-wire data channel, terminal K2 has an input E2 and an output A2 for connecting a second four-wire data channel, terminal K3a has an input E3 and an output A3 for connecting a third four-wire data channel, and terminal K4a has an input E4 and an output A4 for connecting a fourth four-wire data channel.

Between the four-wire terminal pair E3, A3 and the bus terminal K3, between terminals K3a and K3, for connecting a first bidirectional bus, there is located the emitter-receiver module 10. The control input of this emitter-receiver module 10, through which driver D serving as the emitter can be activated, is connected to the output of OR gate Between the four-wire terminal pair E4, A4 and the bus terminal K4, between terminals K4a and K4, for connecting a second bidirectional bus, there is located the emitter-receiver module 40 composed of the driver D and the receiver R. The control input of this emitter-receiver module 40, through which driver D can be activated, is connected to the output of OR gate 45. Receiver R is continually activated.

Each of the four outputs Al, A2, A3, A4 can be optionally connected via a commutator 13, 19, 32 or 37 controlled by microprocessor 35 to the output of an OR gate 11, 17, 41, 39, to a pulling or pull-up resistor 12, 18, 42 or 38, or to the output of a parallel-serial converter 26. This parallel-serial converter 26 is with its parallel input connected with port PO of the microprocessor Microprocessor 35 controls commutator 13 via the two-wire control line St4, commutator 19 via the two-wire control line Stl, commutator 43 via the two-wire control line St8, and commutator 37 via the two-wire control line St7.

It 23 The outputs of OR gates 11, 17, 41, 39 are connected via commutators 13, 19, 32, 37 to one of outputs Al, A2, A3, A4, respectively. Their inputs are accordingly connected with the inputs of the three other fourwire terminal pairs.

Switch 16 is inserted in the line connecting input E3 and the inputs of the OR gates 17, 41, 39. The control line of switch 16 is connected with the output of the OR gate Switch 46 is inserted in the line connecting input E4 and the inputs of the OR gates 11, 17, 39. The control line of switch 46 is connected with the output of the OR gate The output of OR gate 11 is connected to an input of OR gate 15 via the device 14a for edge recognition and the timer circuit 14b connected in series therewith. The other input of OR gate 15 is connected to control line St3 from microprocessor 35. The control input of devices 14a, 14b is connected to the control line St5 from microprocessor The output of OR gate 41 is connected to an input of OR gate 45 via the device 44a for edge recognition and the timer circuit 44b connected in series therewith. The other input of OR gate 45 is connected to control line StlO from microprocessor 35. The control input of devices 44a, 44b is connected to the control line St9 from microprocessor Each of the inputs El, E2, E3, E4 is connected with an input of a serial-parallel converter 24, 25, 27, 28, respectively. The outputs of the serial-parallel converters 24, 25, 27, 28 are connected with the microprocessor 35 via the 8-bit parallel bus 31. Signal collector 20 is likewise connected to bus 31, namely through an interface module 21 with serial-parallel converter 22 and with the parallel-serial converter 23.

The serial-parallel converters 22, 24, 25, 27, 28 and the parallelserial converters 23, 26 are contained in UART circuit components and, if necessary, interrupt the program of microprocessor 35 via the interrupt circuit component 30 connected with the interrupt input Int O. They are connected through bus 31 to port PO of the microprocessor 35 and selected by the microprocessor 35 through a chip-select circuit component 29.

4 r' -24 24 Furthermore, encoding switch 51 is connected to port PO of microprocessor 35 via switch 50 with the aid of which the processor unit can be set to an address and the function of an addressing LE.

Furthermore, connected to microprocessor 35 are: RAM 32 which serves Ias a data memory; EPROM 33 which serves as a program memory; EEPROM 34 which serves as a nonvolatile data memory; and circuit component 36 for i intrinsic checking.

In normal operation, the data transmission is as follows: The messages from input El, E2 or E4 are passed on directly to output A2 via OR gate 17 and commutator 19. Data from input E3 in addition pass through Sswitch 16, whereas data from input E4 in addition pass through switch 46.

iData which arrive at input E2, E3 or E4 pass to output Al via OR gate i 39 and commutator 37. Data from input E3 pass additionally through switch i 16, data from input E4 pass additionally through switch 46.

Data which arrive at input El, E2 or E4 pass via OR gate 11 and commutator 13 to driver D of the emitter-receiver module 10 and from the same to bus terminal K3. For this purpose, commutator 13 must be in the normal position illustrated and driver D must be activated. Driver D is activated when device 14a recognizes a rising edge and OR gate 15 receives from microprocessor 35 a corresponding control potential via device 14a, 14b and/or control line St3.

When in normal operation data are passed through OR gate 11 to bus terminal K3, these data are inputted also into device 14a for edge recognition.

When device 14a for edge recognition recognizes the rising edge of the first byte of a message, timer circuit 14b is started. This timer circuit generates an output pulse which is independent of the bit sequence arriving at the input of device 14a for edge recognition. The output pulse passes through OR gate 15 to emitter-receiver module 10 and immediately switches on driver D. Data arriving at one of the inputs El, E2 or E4 are therefore immediately transferred to bus terminal K3 as a consequence of the recognition of an ascending edge. The data emitted from bus terminal K3 are received by receiver R but are blocked in switch 16 which was opened by OR gate Data which arrive at input El, E2 or E3 pass via OR gate 41 and commutator 43 to driver D of the emitter-receiver module 40 and from the same to bus terminal K4. For this purpose, commutator 43 must be in the normal position illustrated and driver D must be activated. Driver D is activated when OR gate 45 receives from microprocessor 35 a corresponding control potential via device 44a, 44b and/or control line StlO.

i When in normal operation data are passed through OR gate 41 to bus terminal K4, these data are also inputted in device 44a for edge recogj i nition. When device 44a for edge recognition recognizes the rising edge i of the first bit of a message, timer circuit 44b is started. This timer circuit supplies an output pulse which is independent of the bit sequence Sarriving at the input of device 44a for edge recognition. The output pulse passes through OR gate 45 to emitter-receiver module 40 and immediately i switches on driver D. Data arriving at one of the inputs El, E2 or E3 of processor unit 6 are therefore immediately transferred to terminal K4 as a consequence of the recognition of an ascending edge. The data emitted from bus terminal K4 are received by receiver R but are blocked in switch 46 which was opened by OR gate All data arriving at inputs El, E2, E3, E4 are transmitted to microprocessor 35 for processing. Data arriving at input El pass through serial-parallel converter 25, data from input El through serial-parallel converter 25, data from input E2 through serial-parallel converter 27, data from input E3 through serial-parallel converter 24, and data from input E4 through serial-parallel converter 28 to microprocessor The serial-parallel converters 24, 25, 27, 28 accept the data byte by byte and then each of them sends an interrupt pulse via interrupt circuit component 30 to microprocessor 35 when a byte has been completely read in, this [byte] satisfies the start, stop, and parity conditions, and can be taken over via bus 31 at port PO by microprocessor 26 When microprocessor 35 establishes that the data from inputs El, E2 or E4 satisfy predetermined requirements, it activates control line St3.

In this way, after the time span predetermined by timer circuit 14b as elapsed, microprocessor 35 activates through OR gate 15 the driver D in the interface module or emitter-receiver module When microprocessor 35 establishes that the data from inputs El, E2 or E3 satisfy predetermined requirements, it activates control line StlO.

In this way, after the time span predetermined by timer circuit 44b has elapsed, microprocessor 35 activates through OR gate 45 the driver D in the interface module In normal operation, data must be transmitted only over one of inputs El, E2, E3, E4 at a time, otherwise the data are superimposed in OR gates 11, 17, 41, 39, and, hence, are altered.

The processor unit can be caused to switch into the storage mode by a command "transition into the storage mode" in the control message of the personal computer 8.

The control message with the command "transition into the storage mode" passes through all the processor units in normal operation. In parallel therewith, microprocessor 35 of each processor unit processes the control message and, following its evaluation, passes into the storage mode.

When microprocessor 35, while evaluating a message, notes that predetermined requirements are not satisfied, the respective processor unit is made to switch into the storage mode.

In the storage mode, the data arriving at inputs El, E2, E3, E4 are inputted via serial-parallel converters 24, 25, 27, 28 into the microprocessor for processing. Depending upon the type of the message, after the evaluation microprocessor 35 in accordance with the procedure activates one to three of control lines Stl, St4, St7, St8. Thus, the data processed in microprocessor 35 and supplied by parallel-serial converter 26 are fed via one to three of the commutators 13, 19, 43, 47 to one to three of outputs Kl, K2, K3, and K4, namely to those outputs of the terminals at which the message was not received.

7 P I 27 Each of inputs El, E2, E3, E4 is connected with proper serialparallel converter 24, 25, 27, 28. With the aid of the interrupt pulses, microprocessor 35 recognizes the input through which data are being inputted.

Control lines Stl, St4, St7, St8 are activated by the microprocessor so that those of outputs Al, A2, A3, A4, which are not involved in the transmission, are set to high potential through commutators 13, 19, 43, 47 and with the aid of pull-up resistors 12, 18, 42, 48.

In normal operation, the start-addressing messages pass through all the processor units. In parallel therewith, microprocessor 35 processes the start-addressing messages and makes the transition to the storage mode.

In the addressing operation, the address message must only be passed on by the processor via parallel-serial converter 25 but must not be sent at the same into the two directions. The data arriving at input El are processed by serial-parallel converter 23, the data appearing at input E2 are processed in serial-parallel converter 27. Thus, microprocessor recognizes the direction from which the data arrive. In the storage mode, control lines Stl and control lines St7 are therefore activated so that the output Al or A2, which is not involved In the transmission, is set to high potential through commutator 19 or 47 and the pull-up resistor 18 or 48, respectively.

Signal collector 20 is connected with microprocessor 35 via interface module 21, serial-parallel converter 22, and parallel-serial converter 23.

Signal collector 20 inputs the monitoring data of the monitored intermediate regenerator or monitored line terminal unit via interface module 21 into microprocessor 35 and, if necessary, receives the control information contained in a call message of the locating module for passing the control information on to a signal-collecting unit not shown.

Depending upon the use of the processor unit in the line terminal unit or the intermediate regenerator, the monitoring data are transmitted from processor 35 via parallel-serial converter 26, via three of the four commutators 13, 19, 43, 47 to three of the four outputs Al, A2, A3, A4 and are emitted from three of the four terminals Kl, K2, K3, K4.

V/

28- If, at a net node, a plurality of terminals K3 are interconnected by a bidirectional bus, the following sequence results for switching on and off a bus driver: In the idle condition, all the drivers are inactive and therefore have a high-impedance output. When data are inputted through terminal Kl or K2, the edge of the starting bit starts timer circuit 14b which activates the driver for at least two characters. The ensuing halt and switch-off is effected by microprocessor 35 to which the data are inputted in parallel.

The processor unit illustrated in Figure 8 substantially coincides with that of Figure 7. In distinction, no bus terminal K4 is provided.

Hence, switching means 40, 41, 42, 43, 44a, 44b, 45, 46, and 28 have been omitted. Double-exclusive OR gates lla, 17a, and 39a are provided in place of the triple OR gates 11, 17, and 39 of Figure 7.

The output of exclusive OR gate lla Is connected with one of the inputs of OR gate 15 through device 14a for edge recognition and through device 14b connected in series therewith. The other input of OR gate together with one control input of devices 14a and 14b, is connected to control line St3 from microprocessor As in Figure 7, the control input of the emitter-receiver module is connected with the output of OR gate 15. By distinction from Figure 7, driver D or receiver R can be optionally activated with the aid of the control signal applied to the control input. The output pulse passes through OR gate 15 to emitter-receiver module 10 and immediately switches on driver D and switches off receiver R.

In normal operation, the messages are directly passed on from data input El via exclusive OR gate 17a and commutator 19 to output A2. In the backward direction, the messages pass from input E2 via exclusive OR gate 39a and switch 37 to output Al.

The exclusive OR gate 1la, 17a or 39a ensures that no data are transmitted when data arrive simultaneously at inputs El and E2 or El and E3 or E2 and E3. Since in operation without malfunction, data must not appear simultaneously at input El, E2, and E3, data are blocked by the exclusive OR gates lla, 49a, and 17a only in the case of malfunctions.

T 41 i-l- I 29 The with that provided.

17a, 39a, operation terminals processor unit illustrated in Figure 9 substantially coincides of Figure 8. In distinction therefrom, no bus terminal K3 is Consequently, the switching means 10, lla, 12, 14a, 14b, and 24 have been omitted. The processor unit is designated for in an intermediate regenerator and, apart from the four-wire K1 and K2, has only a terminal for the local signal collector

Claims (8)

1. 2. The method according to claim 1, wherein given a plurality of transmission sections connected in chain, the processor unit that is situated at that end of the transmission section lying opposite the addressing unit or the first processor unit of a following transmission section increments both the first as well as the second sub-address. 31
2. 3. The method according to claim 1, wherein given a plurality of transmission sections connected in chain, the processor unit that is situated at that end of the transmission section lying opposite the addressing unit ;r the first processor unit of a following transmission section increments the first sub-address and resets the second sub-address to an initial value.
3. 4. The method according to claim 1, 2 or 3, wherein the telegram transmission network is a star network having a structure composed of a plurality of line networks each respectively containing at least one transmission section; and wherein addressing units situated at nodes of the star network are respectively pre-set to a given address in the first address part and, given reception of a start-addressing telegram, output an addressing telegram that is the pre-set address of the appertaining transmission section in the first address part and is its own ordering number in the appertaining transmission section in the second address part.
4. 5. The method according to claim 1, wherein at least two :.processor units connected in cascade are provided at a network node of the telegram transmission network.
5. 6. The method according to claim 5, wherein the telegram transmission network is a star network having a structure composed of a plurality of line networks each respectively containing at least one transmission section and wherein, after the reception of an addressing telegram processor units situated at nodes of the network can be set to an address by the first sub-address and, given reception of a start-addressing telegram, output an addressing telegram that is the set address of the appertaining transmission section in the first sub-address and is its own ordering number in the appertaining transmission section in the second sub-address.
6. 7. The method according to any one of the preceding claims, wherein when a processor unit is replaced in the transmission communication equipment, the processor units are switched into a condition wherein they transmit a request telegram during a time slot respectively provided following the polling cycle, as a result whereof IAD/1443o 32 the respectively at located addressing unit is initiated to send out an addressing telegram.
7. 8. The method according to claim 7, wherein given the replacement of a processor unit that is not an addressing unit, the monitor unit is initiated by a request telegram to lend the time slot a duration adequate for the addressing procedure.
8. 9. The method according to any one of the preceding claims, wherein the processor unit, in a first operating mode (normal mode), through-connects telegrams and, in a second operating mode (store-and- forward mode), does not forward telegrams until after a storing of the telegrams. A method for addressing processor units substantially as described herein with reference to the drawings. DATED this EIGHTEENTH day of FEBRUARY 1992 N.V. Philips Gloeilampenfabrieken Siemens Aktiengesellschaft Patent Attorneys for the Applicants SPRUSON FERGUSON a. *a a a IAD/1443o