AU603482B2

AU603482B2 - Digital error logger

Info

Publication number: AU603482B2
Application number: AU21882/88A
Authority: AU
Inventors: James Frederick Adamthwaite; John Christopher Livsey; Leonard Andrew Thistlethwaite
Original assignee: Australian Telecommunications Corp
Current assignee: Telstra Corp Ltd
Priority date: 1987-09-03
Filing date: 1988-09-05
Publication date: 1990-11-15
Anticipated expiration: 2008-09-05
Also published as: AU2188288A

Description

CO0M MO0N WE AL TH O F A US T RA LIA PATENT ACT 1952 COMPLETE SPECIFICATION

(ORIGINAL)

FOR OFFICE USE 6t 0 2 CLASS INT. CLASS 4 4 F4 C 4 4 FC *4 4 *9 eq..4 0 0 9 0 0 4 44 4 0 o 40 J 0 4 4 44 9 Application Number: Lodged: Complete Specification Lodged: Accepted: Published: Priority: Related Art-: This dno imeu!'t containls te Secti on id ~'orCct TELECOMMUNICATIONS eoeMMTSS1To NAME OF APPLICANT:

AUSTRALIAN

ADDRESS OF APPLICANT: 199 William Street, Melbourne, in the State of Victoria, Commonwealth of Australia NAME(S) OF INVENTOR(S) ADDRESS FOR SERVICE: DAVIES COLLISON, Patent Attorneys 1 Little Collins Street, Melbourne, 3000.

-COMPLETE-SPEIFCATON FOR THE INVENTION ENTITLED: DIGITAL ERROR LOGGER The following statement is a full description of this invention, including the best method of performing it known to us

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DIGITAL ERROR DATA LOGGER.

This invention relates to a digital error data logger.

The monitoring of the overall performance of large digital communications systems is customarily 5 effected by transmitting through the system a suitable signal of known form which can be received where required, demodulated, and compared with the original signal to determine the extent to which the received signal is in error. This signal as transmitted may be a slow speed digital stream dedicated to performance measurements. A difficulty arises with this approach that it is costly to provide the necessary demultiplexing equipment to gain access to the "monitoring" digital stream at every location throughout the system at which it might be desired to effect this monitoring. On the other hand, it is obvious that some method of 41117

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frt af O an 0 a ao uoa ft 4 continuous in-service monitoring is desirable to enable sections of the system to be accurately assessed, as far as system performance is concerned.

The end result of the assessment made in respect of the monitoring digital stream is the production of an indication of the Bit Error Rate (BER) which represents the given number of bits of the transmitted stream which are in error over a given time interval. The results obtained as a given location within the system, for the low speed monitoring stream, need to be extrapolated to apply to the system as a whole, but this can be reliably performed by known techniques.

The invention has for its object to provide a method and apparatus for obtaining information as to performance of a digital transmission system and which can operate effectively on the normal transmitted signals through the network.

According to the present invention there is provided a method of estimating the bit error rate of a digital transmission system comprising monitoring the occurrences, in the digital signal transmitted in the system, of parity pulses which are indicative of the occurrence of a transmission error within a respective preceding frame period of the digital signal, determining therefrom a parity error count, and estimating therefrom the system bit error rate by reference to a predetermined correlation between particular parity error counts and estimated bit error rates.

According to the present invention there is further provided apparatus for determining the bit error rate of a digital transmission system comprising means for monitoring occurrences of parity pulses in the digital signal transmitted in use in the system, being parity pulses which 900813kxlspe. 008,telecom 2

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I 2a 0: 10 b 090 12 S 13 14 S 16 17 18 19 S 21 22 23 24 'i 26 27 28 29 31 32 33 34 36 37 i, \38 are indicative of the occurrence of a transmission error within a preceding frame period of the digital signal and determining therefrom a parity error count, and means for estimating therefrom a system bit error rate from said monitoring by reference to a predetermined correlation as between particular parity error counts and estimated bit error rates.

The invention is further described by way of example only with reference to the accompanying drawings of which: Figure 1 is a block diagram of a digital 900813.kxspe.008,telecom,3 -4 ii r:

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3 error data logger constructed in accordance with the invention.

Figure 2 comprises four portions labelled Figure 2a, Figure 2b, Figure 2c and Figure 2d which join on the lines W-W, X-X, Y-Y and Z-Z to form an expanded circuit diagram of the circuit of Figure 1; and.

Figures 3 to 6 are flow diagrams illustrating the manner of operation of the digital error logger of Figure 1.

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4 o 0, 44 #9 4 The digital error logger to be described is designed 15 particularly for use with a conventional 140 Mbit microwave system using a method of modulation known as 16 QAM. This is a multi-level modulation scheme involving splitting the input data stream into four slower (34 Mbit) streams prior to the digital 20 modulation process. At the receiving station, these streams are recombined to form the original 140 MBit stream. To enable correct combination of the four separate streams it is necessary to include extra bits within the transmitted data. These extra bits are known as framing bits and the method of including them is known as "Bit insertion". As well as inserting these framing bits, other bits are usually inserted at the same time. These bits are used to provide digital service channels, pilot facilities and parity information.

The parity is determined over a specified number of bits in the transmitted data stream (1152 bits, for example). At the receiving station, these parity bits are recovered and used as required. e.g. the bits may be used to enable determination of when there is a -7 0M 0 00 0 00 coo0 0 00040, a 4 very high error rate and to provide alarm and other signals. In any event, it is generally the case that systems of the kind in question will have facilities to make available, at each repeater site throughout the system, the recovered parity bits.

In conventional techniques, the parity data which is recovered at the end of each framing interval is indicative of whether the sum of the transmitted bits of data during the preceding framing period is odd or even. At low error rates, such as where only one bit in the transmitted data frame is likely to be in error, it is the case that the overall bit error rate for the system will be determinable by examining 15 whether the parity bit as generated at the end of each framing period is indicative of an occurrence of an error in that framing period. At higher bit error rates, however, the existance of a parity error is obviously less reliable as a guide to bit error rate.

For example, at high rates, the probability of the number of errors in a framing period being an even or odd number may be substantially equal so that failure to detect a parity error may only have, represent say, a 50% probability of correspondance to the absence of an error in the framing period.

Nevertheless, the invention is based on the realisation that, for practical purposes, and within certain limits, the monitoring of the parity bits and determination of whether parity errors have occurred provides a practicable and simple means for estimating, with good accuracy, the bit error rate of *a digital transmission system.

Referring now to Figure 1, a digital error logger

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constructed in accordance with the invention is shown as comprising an interface circuit 12 which has a number of inputs, sixteen in this case, to receive parity pulses from up to sixteen transmission systems or channels, which are continuously monitored by the logger. The parity pulses are passed to a counter 14.

Every 0.25 records CPU 18 receives an interrupt 99 9 request which causes the current count in counter 14 to be read. The counts are transferred via an address multiplexer 30 to a memory 32 in the form of a 64 Kbyte dynamic random access memory. The so read count for each channel is added to the previous count A, held in the memory 32.

Every one second, the accumulated counts for each.

channel is transferred to a holding memory area in A the memory 32. The accumulated counts are then converted to respective equivalent system bit error rates by operation of the central processor unit 18, the program of which is held in a read only memory 36. The manner in which this is effected is 9'described later.

Having derived the equivalent system bit error rate the channels coupled to the logger 10, these are now categorized, again by operation of the central processor unit 18 into various categories of information more particularly as follows: The number of error seconds which have occurred, (b) (c) The number of severe error seconds which have occurred The unavailability of the channel in question The number of degraded minutes which have occurred, and The average bit error rate.

(d) (e) k t a, These results are stored in short term tables in the memory 32.

Every hour, the contents of the short term tables as stored in memory 32 are transferred into long term tables, again in the memory 32, and the short term tables reset in preparation for the next hour. The long term tables are allocated on a "wraparound t 20 basis to ensure maximum retention time for data.

The information generated by the logger 10 is made selectively available on a liquid crystal display 34.

The logger has various front panel switches, generally designated by reference numeral 40 in Figure 1. and function select switches generally designated by reference numeral 42. These are coupled to a parallel interface adaptor 44 which permits accessing of various data stored for display or alternatively for readout. In the latter regard, the logger 10 also includes provision for operation to print out data on a local printer, via the ACIA 48 shown, changeover switch 50 -and interface circuit 52.

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4 *0 i E 44 4 7 Also, communication is possible with an external computer via a Modem 54 and the band pass filter Figure 2 shows one possible physical implementation of the circuit of Figure 1. Figure 3 shows a flow diagram for the way in which, internally, a remote command is performed and the way in which remote communications are effected. The Figure 4 illustrates the statistical collection functions as previously described. Figure 5 illustrates the way in which remote communications are effected, in so far as communications back to an external processor are concerned and Figure 6 illustrates the user program.

Generally speaking, the way in which the above 15 described functions are effected is not relevant to the invention. However, of importance to the invention is the way in which parity pulses, above described, are processed in order to derive the equivalent bit error rate.

As described, insofar as any one channel is concerned, the logger provides at each one second interval a count representing the number of parity pulses for the channel in question and representing the number of parity errors detected in a corresponding preceding one second interval. The central processing unit is effective to convert this accumulated count into an equivalent bit error rate via one of three possible methods, depending upon the :i C-C ii 8 detected absolute value of the prevailing count.

Thus, the digital error logger has, stored in the memory thereof, a table which provides correlation between various values of parity count for a one second time interval arranged in ascending order of magnitude and corresponding to predetermined estimated bit error rates. The table is used, in conjunction with an interpolation procedure for providing values of bit error rate corresponding to parity counts over a range running from the lowest tabulated magnitude as parity count in the table to the highest magnitude in the table. For values of detected count within the range of these highest and lowest values the procedure is that the count is compared in turn with the values of parity counts which are tabulated in the table, through increasing magnitude tabulated values, until the count is found to satisfy the condition that it lies above one tabulated value but below the next consecutive tabulated value. Then, the computer program of the digital error logger 10 is effective to compute, by linear approximation, a proportion of the difference between the two tabulated bit error rates corresponding to the two tabulated parity counts between which the actual count lies. This proportion is then added to the bit error rate corresponding to the lowest of the two tabulated parity error counts between which the actual count lies has just exceeded by the actual count. More particularly, in the first of these steps the condition is established as follows ENTRY n COUNT ENTRY n 1

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i *4 4 4* 4* 4 .4 4 4 4* 4 44 44 4 p e* p 6 6 4 4* 6 44 4 4 4 4* 9 44 4 4 4 04 440* 4 p .4 4 4 4, 44 4 44~ 4 9 Where "COUNT" is the actual parity error count determined by the digital error logger 10 and "entry n" "entry n 1" are the consecutive lower and higher count entries in the table between which the actual count is found to lie. Then, the bit error rate is computed in accordance with the following formula: BER BERBASE n (ACTUAL COUNT COUNTBASE n) x BERFACTOR (2) Where "BER" is the required bit error rate, "BERBASE n" is the bit error rate corresponding to the "ENTRY n" "COUNT" is the actual count of parity errors "COUNTBASE n" is the parity bit count at "ENTRY n" "BERFACTOR" is defined as follows: BERBASE n 1 BERBASE n BERFACTOR COUNTBASE n 1 COUNTBASE n Where "BAREBASE n" and "COUNTBASE n" have the meanings mentioned in relation to equation "BERBASE n 1" is the bit error rate corresponding to the (n 1) entry of parity error count tabulated in the table and "COUNTBASE n 1" is the value of the (n 1) n entry of parity error counts tabulated in the table.

It is not convenient, for economy of storage, to extend the table of bit error rates verses parity error counts to too great an extent and the count of parity errors for the lowest entry in the table may i urr~*r~~ be selected so that when a count less than such lowest count is determined as existing, then the digital error logger acts to compute the bit error rate in accordance with the following alternative definition.:

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BER SYSTEM DATA RATE (4) 0* 9 S8 9 94 O n 4 9 44 9 9 0) 09 o a 4 0 00^ 0 04 9m 9 04 9 94 *04 4 9 40* 94 9 9D 09 9* 6 6 4 a 4 fl 0 Where "BER" and "COUNT" have the meanings mentioned in relation to equation above and "SYSTEM DATA, RATE" is the rate of digital transmission through the channel under consideration.

Also, where the count of parity errors increases, the result may, as explained above, be that computed bit error rates are unreliable. Generally speaking, it has been found possible to provide a range of 20 tabulated parity counts and corresponding bit error rates such that the highest value of bit error rate and of parity count as tabulated still have a good correlation one between the other and which provides a sufficiently extended range of reliable resultant bit error rate calculations to give adequate results in terms of system performance accessment. However, if the bit error rate exceeds the upper limit chosen for the tabulated bit error rate the described method of calculation as used by the program of the digital error logger to compute a corresponding bit error rate may be in error. So, if the parity bit count is found to exceed the table entry for parity bit counts which is of the greatest magnitude, then the corresponding (last) tabulated 11 bit error rate, is simply adopted by the compsite program as the output result.

The described construction has been advanced fierely by way of explanation and many modifications and variations may be made thereto without departing from the spirit and scope of the invention as defined in the appended claims.

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Claims

2. A method as claimed in claim 1 wherein said parity error count is determined by counting, over a predetermined time interval, the number of transmission errors occurring in the time interval, the corresponding estimated system bit error rate being estimated by accessing a stored table which provides said predetermined correlation by correlating various values of parity error count for said time interval and corresponding predetermined estimated bit error rates.
3. A method as claimed in claim 2 including interpolating values of estimated bit error rate for values of said parity error count lying between tabulated ones thereof.
4. A method as claimed in claim 2 or claim 3 including the step of determining whether said parity error count is less than the lowest value of parity error count for which values of estimated bit error rate are stored in said table and when so determined, computing the bit error rate alternatively by dividing the parity error count by the system data rate, being the rate of digital transmission through the system.
5. A method as claimed in claim 2, 3 or 4 including the step of determining whether said parity error count exceeds 900813,kxlspe.008, teecom. 12 i; i r L 1
13- 1 the values of parity error count in said table which 2 represents the highest such stored value of parity error 3 count in the table and if so determined alternatively 4 estimating said bit error rate by adopting the highest estimated bit error rate stored in said table. 6 7 6. A method as claimed in claim 2, wherein in estimating 8 said bit error rate, it is determined whether the following 9 condition is met: *Q 9 b o 11 ENTRY COUNT ENTRY n 1 0 12 0o 13 where "COUNT" is said parity error count, and "ENTRY n" and I 14 "ENTRY n 1" are respectively consecutive lower and higher values of parity error count entries in said table between 16 which the actual parity error count is found to lie. 17 oo 18 7. A method as claimed in claim 6 wherein, in the event 0*0* 19 that the parity error count is established as meeting said 20 condition, computing the bit error rate in accordance with 21 the following: S 22 23 BER BERBASE n (COUNT COUNTBASE n) x BERFACTOR 24 25 where "BER" is the required bit error rate, "BERBASE n" is i 26 the bit error rate corresponding to the "ENTRY n" value of 27 parity error count, "COUNTBASE n" is the value of the parity 28 error count at "ENTRY n" in said table and "BERFACTOR" is 29 defined as follows: 31 BERBASE (n 1) BERBASE n 32 BERFACTOR 33 34 COUNTERBASE (n 1) COUNTERBASE n 36 where "BERBASE (n is the value of bit error rate R 37 corresponding to the (n 1) value of parity error count j38 900813,kxlspe.008,telecom.l13 L LT l 4 I If 44 f It 4 It 4~ I *4 *444*1 *4 o 4 1 4 **44 4 4441 4444 o 4. 04 4 #4 4 44 4141 440* 444 4 4 ii I fi -14 tabulated in said table and "COUNTBASE (n is the value of the 1) n" value of parity error count tabulated in said table. 8. A method as claimed in claim 6 or 7 wherein in the event that said condition is not met because the parity error count is less than the lowest parity error count stored in said table, computing the bit error rate in accordance with the following alternative definition: COUNT BER= SYSTEM DATA RATE where "SYSTEM DATA RATE" is the rate of digital transmission through the system. 9. A method as claimed in claim 6, 7 or 8 wherein in the event that said condition is not met because the parity error count is found to exceed the stored value of parity error count in said table corresponding to an estimate of system bit error rate of the greatest magnitude stored in the table, the so tabulated highest magnitude is adopted as the estimate of system bit error rate. Apparatus for determining the bit error rate of a digital transmission system comprising means for monitoring occurrences of parity pulses in the digital signal transmitted in use in the system, said parity pulses being signals which are indicative of the occurrence of a transmission error within a preceding frame period of the digital signal and determining therefrom a parity error count, and means for estimating therefrom a system bit error rate from said monitoring by reference to a predetermined correlation between particular parity error counts and estimated bit error rates.
900813.kxlspe.008. telecom, 14 7 '1 9 o o U B 10 11 12 0 13 S 14 0 4i 16 17 0s° 18 o00€ 19 20 o .0 21 O o0 22 23 ct 24 26 27 11. Apparatus as claimed in claim 10 wherein said apparatus includes count means for determining said parity error count by counting the number of transmission errors occurring in a predetermined time interval, and computinc means for computing the estimated system bit error rate from said parity error count. 12. Apparatus as claimed in claim 11 wherein said computing means includes a stored table providing correlation between various values of parity error count for said time interval and corresponding predetermined estimated bit error rates. 13. Apparatus as claimed in claim 12 wherein said computing means includes means for interpolating values of estimated bit error rate for values of said parity error count lying between tabulated ones thereof. 14. Apparatus as claimed in claim 13 wherein said computing means is effective in use to determine whether said parity error count is less than the lowest value of parity error count for which values of estimated bit error rate are stored in said table and when so determined, to compute the bit error rate alternatively by dividing the parity error count by the system data rate, being the rate of digital transmission through the system. Apparatus as claimed in claim 13 or 14 wherein said computing means includes means in use determining whether said parity error count exceeds the value of parity error count in said table which represents the highest such stored value of parity error count in the table and if so determined alternatively estimating said bit error rate by adopting the highest estimated bit error rate stored in said table. 16. Apparatus as claimed in claim 12 including computing ,M: 900813,kxspe.008,teecom. I 7 8 9 11 12 13 14 16 17 s 19 Q 2 O 20 o 21 22 23 16 means which in use is effective to estimate said bit error rate and which is effective to determine whether the following condition is met: ENTRY n COUNT ENTRY n 1 where "COUNT" is said parity error count, and "ENTRY n" and "ENTRY n 1" are respectively consecutive lower and higher values of parity error count entries in said table between which the actual parity error count is found to lie. 17. Apparatus as claimed in claim 16 wherein said computing means is effective in the event that the parity error count is established as meeting said condition, to compute the bit error rate in accordance with the following: BER BERBASE n (COUNT COUNTBASE n) x BERFACTOR where "BER" is the required bit error rate, "BERBASE n" is the bit error rate corresponding to the "ENTRY n" value of parity error count, "COUNTBASE n" is the value of the parity error count at "ENTRY n" in said table and "BERFACTOR" is defined as follows: BERBASE (n 1) BERBASE n BERFACTOR COUNTERBASE (n 1) COUNTERBASE n where "BERBASE (n is the value of the bit error rate corresponding to the (n 1) value of parity error count tabulated in said table and "COUNTBASE (n is the value of the 1) n" value of parity error count tabulated in said table. 18. Apparatus as claimed in claim 16 or 17 wherein said computing means is effective in the event that' said 900813,kxlspe.008,telecom.16 US.. *9 4 9 B 'I x ;I i_ i 17 condition mentioned is not met because the parity error count is less than the lowest parity error count stored in said table, to compute the bit error rate in accordance with the following definition: COUNT BER 9 0 r* 11 o 12 S13 0 0 S. 14 0 a 15 16 17 18 19 e e 0" 20 0. 21 22 23 24 25 26 27 28 29 SYSTEM DATA RATE where "SYSTEM DATA RATE" is the rate of digital transmission through the system. 19. Apparatus as claimed in any one of claims 16, 17 and 18 wherein said computing means is effective in the event that said condition is not met because the parity error count is found to exceed the stored value of parity error count in said table corresponding to an estimate of system bit error rate of the greatest magnitude stored i.i the table, to adopt the so tabulated highest magnitude as the estimate of system bit error rate. 20. A method of estimating the bit error rate of a digital transmission system substantially as hereinbefore described with reference to the accompanying drawings. 21. Apparatus for estimating the bit error rate of a digital transmission system substantially as hereinbefore described with reference to the accompanying drawings. PB DATED this 13th day of August, 1990. AUSTRALIAN TELECOMMUNCIATIONS CORPORATION By its Patent Attorneys DAVIES COLLISON 900813.kxlspe.008 telecom, 17