AU603276B2 - Audio alarm clock - Google Patents

Description

C,.

M T 72A I)itir COMMONWEALTH OF AUSTRALIA The Patents Act 1952-1969 Name of Applicant(s): KEITH OSCAR FORSTER Address of Applicant(s): 24 Barellan Avenue, Kawana Waters, Queensland, 4574, Australia, I if 944 4 4 44 o 41 .4 1 I 4 I tif .44, I if 44 I 4 Actual Inventor(s): Address for Service: KEITH OSCAR FORSTER GR. CULLEN COMPZNY, Patent Trade Ma.. Attorneys, Dalgety House, 79 Eagle Street, Brisbane, Qld. 4000, Australia.

COMPLETE 0"PFCIPICATION FOR THE INVENTION ENTITLED: ~4JJ 9~A2$V\ CLocX..

DLU3TflI 3ALL~ 0]ThUBATUI2 ci3UHBti The following statement is a full description of the invention including the best method of performing it known to me.

i' 2

V

THIS INVENTION relates to a novelty alarm clock, and in particular to an alarm clock which generates an audio alarm in the characteristic sound of a theme element visually depicted on the clock. Typically, the theme element is a bird and the alarm is in the form of the characteristic call of the depicted bird.

Audio alarms generated by conventional alarm clocks typically include ringing bells, buzzing, beeps and o. ther monotonous sounds. Such audio alarms are often annoying or irritating to those who may have been awoken by such alarms.

To overcome the monotony and irritating nature of such alarms, talking alarm clocks have been proposed, for example as described in U.S. patent no. 4,701,862. However, such talking alarm clocks generally provide a synthesised human voice output which, in many cases, is only slightly less monotonous and irritating than buzzing sounds or beeps.

It is an object of the present invention to provide a novelty alarm clock which overcomes the abovedescribed problem of known alarm clocks or at least provides the consumer with a useful choice.

In one broad form, the present invention provides a clock comprising a housing depicting a theme element having a characteristic sound; a timepiece mounted on the housing; and alarm signal generating means connected to the time piece and responsive to a predetermined time indication thereof to generate an audio alarm corresponding to the characteristic 4 sound, the alarm signal generating means including input means connected to the timepiece, an electronic memory containing digital data representative of the characteristic sound, a loud speaker, and means for deriving an audio signal in the characteristic sound from the digital data and outputting the audio signal to the loud speaker; and means for connecting the alarm signal generating means to a power supply at the predetermined time indication for the duration of the audio alarm.

Preferably, the housing is a three dimensional representation of the theme element which typically is a bird. For example, the housing may be a ceramic sculpture of a bird, and the audio alarm emitted by the alarm clock is a reproduction of the bird's call. Such an audio alarm is melodic and pleasing to the ear, and is similar to nature's own sounds. This interruption to the user's sleep is therefore unlikely to create the adverse reaction from the awakened sleeper which conventional alarm clocks often create.

Moreover, by depicting the theme element on the housing, the alarm clock can itself be a decorative item in the bedroom, unlike the purely utilitarian appearance of conventional alarm clocks. The housing of the alarm clock can be a three dimensional representation of the theme element, and the clock mechanism and alarm generating circuit can be concealed within the housing.

Preferably, the electronic memory is housed in an interchangeable electric circuit component, such as an A interchangeable IC package. In this manner, the electronic 7* r~ I- 4 memory can be interchanged with another memory containing data representative of a different sound.

Advantageously, the alarm circuit is supplied with power only during the currency of a signal from the timepiece indicating that the predetermined time has been reached. In this manner, power consumption is minimised, thereby enabling the alarm circuit to be powered from the same battery which would normally power the timepiece.

In order that the invention may be more fully understood and put into practical effect, preferred embodiments thereof will now be described with reference to the accompanying drawings, in which: Fig. 1 illustrates an alarm signal generating circuit according to a first embodiment of the invention; and Figs. 2 and 3 illustrate a second alarm signal generating circuit according to another embodiment of the invention.

The novelty alarm clock of the preferred embodiment comprises a housing (not shown) which is in the form of a theme element, such as a bird. A timepiece is mounted in the *housing in a suitable manner, such that the time display of the timepiece is easily seen. The timepiece may be a conventional electrically operated analogue ot digital clock.

The clock further comprises alarm signal gener-ating means in the form of an alarm circuit 10 which is electrically connected to the timepiece. Upon coincidence of the real time displayed by the timepiece and a predetermined alarm time, the circuit 10 generates an audio alarm which corresponds to the characteristic sound of the theme element depicted by or on the housing.

In the embodiment of Fig. 1, the alarm circuit includes an input circuit 11, a memory circuit 12 and an output circuit 13. The input circuit 11 includes two input terminals 14 and 15 which are connected to the timepiece (not shown) to receive an output AC or DC electrical signal from the timepiece upon a preset time being reached by the timepiece, according to known techniques. The terminals 14 and 15 are connected to a switching circuit 16, the output 17 of which is connected a timer circuit 18, typically being a If 555 timer. The switching circuit 16 includes transistor 31 O 4 and inverters 32, 33. The output 19 of the timer circuit 18 04 0 S, of this embodiment produces a 9kHz clock signal in response to a high logic signal being applied on output line 17.

0o The memory circuit 12 includes digital memory which 4 4 in this embodiment is a 27512 EPROM 20 have 216 memory addresses for storing data as 8 bit words. The addresses of memory 20 are addressed sequentially by 12 stage binary counters 36 and 37 which are cascaded to count up to 216 in *response to the high to low transitions of the clock signal.

A latch 23 buffers the data outputs of the memory. The latch in this case is a 74C273 octal D type flip flop which is clocked by line 24. Data is transferred to the outputs Qi L i i i through Q8 from the inputs D1 through D8 on the low to high transition of the clock signal.

The output circuit includes a D/A convertor in the form of a resistor array 25 connected to a filter 26, a power amplifier 27 and a smoothing network 30. A speaker 29 is driven by the output circuit. The power supply is provided by an 8 volt AC supply which is rectified by a three terminal voltage regulator 39 to provide the 5 volt logic supply.

The operation of the alarm circuit 10 will now be described.

When an alarm output signal from the timepiece is received by terminals 14 and 15, transistor 31 will conduct and the input to invertor 32 will go low taking the input to

LA

i'i J 1 7 i invertor 33 high and its output will go low. The other input to NOR gate 34 is normally low, Thus on the application of an alarm signal to terminals 14 and 15,whether that signal is DC or AC, a high will be applied along line 17 and will remain until the alarm signal ceases whereafter line 17 will go low.

The transistor input circuit and series invertors are used to condition the signal applied to the timer 18.

Thus a low alarm voltage applied to terminals 14 and 15 will o still activate the timer.

The timer 18 in this embodiment, when activated as above, sends a 9kHz clock signal to the counters 36 and 37.

The cascaded counters 36 and 37 then count in cycles of 2 as long as an alarm output signal remains on terminals 14 and 15. When the alarm signal to terminals 14 and 15 ceases the 9kHz clock signal will also cease and the output from the timer along line 19 will be held low and counting will cease.

Thus the counters 36 and 37 will sequentially address the memory 20. The chip enable 21 and output enable 22 of the memory 20 are held low and the data appears sequentially shortly after each negative going edge of the clock signal.

The data is applied to the latch 23 which is positive edge triggered, Thus data is transferred from the inputs Dl through D8 of the latch to the Q1 through Q8 outputs shortly after the negative edge triggering of the @Al 8 counters 36 and 37.

The Q outputs of the latch 23 are then applied to the 316 resistor array and the analogue equivalent passes through low pass filter 26 along line 28 to the power amplifier 27. The output from the power amplifier 27 is applied via the filter network 30 to the speaker 29.

Thus the new a~lrm signal will be played over speaker 29 for the duration of the alarm output signal as applied to terminals 14 and 15. An output from counter 37 along line 35 can be utilised to terminate the alarm output as an alternative to the signal applied to terminals 14 and Referring to Figs. 2 and 3 a modified embodiment of the circuit of Fig. 1 will be described. Like numerals have been used to illustrate like features. As in Fig. 1 the circuit includes an input circuit 11, a memory circuit 12 and an output circuit 13.

The memory 12 in this case is an 27256 EPROM which is detachably connected to an Integrated circuit 45, the integrated circuit 45 is a hybrid which performs the function of the counters 36, 37, the latch 23, the timer 18 and the resistor array 25 as depicted in Fig. 1 and these elements have been similarly numbered in Fig. 3.

The hybrid is actually much smaller than the EPROM 12 and is wired to an EPROM mounting block so that EPROMS can be interchanged thereby enabling the circuit to generate i I iu L "~r~i i- 9 different sounds depending on the EPROM which is at the time connected in circuit.

It will be appreciated however, that the internal circuitry of the hybrid need not be exactly as shown, the main purpose of the hybrid in this embodiment being to reduce circuit size but still allowing the EPROM to be changeable while the hybrid still performs substantially the same function as the timer, counters, latch and resistor array of Fig. 1.

The input circuit 11 includes terminals 14 and which can be connected to a suitable AC or DC supply which might come from an alarm clock as an AC or DC alarm signal.

The terminals 14 and 15 are connected to a switching circuit 16 comprising transistors 40 and 41.

The terminal 42 of transistor 41 is connected to a battery power supply. When an AC or DC signal is applied to the terminals 14, 15 transistor 40 switches on, thereby drawing a small current through resistors 43 and 44 and also generating a current in the base of transistor 41. This switches transistor 41 on and thereby provides the power supply for the whole circuit. This arrangement ensures that power is only used when a signal is present at the terminals 14, When transistor 41 switches on, power is supplied to the timer 18 to generate a 30kHz clock signal. At the same time the reset circuit 46 receives a rising 5 volt pulse which is delivered to pin 6 of the hybrid to reset the counters 36 and 37. The counters 36 and 37 then sequentially address the memory 12 and the latch 23 and the resistor array 25 operate as previously described in relation to Fig, 1 to deliver an analogue signal from the hybrid along lines 47 and 48 to the output circuit 13.

The output circuit 13 includes a preamplifier 48, a low pass filter 49, a buffer stage 50 for impedance matching and an audio amplifier 51.

The other circuit elements in Fig. 2 include the external components for the 555 timer which are shown at 52 and a rectifier circuit 53 for providing -3V to the op-amp pin 7 of the preamplifier 48, The output from the audio amplifier 51 is delivered to a speaker 54.

It will be appreciated that the circuit of Figs, 2 and 3 operate in substantially the same fashion as the circuit of Fig, 1 insofar as when a first alarm signal is applied to terminals 14 and 15 the second alarm signal is O 0 clocked from the EPROM 12 through the output circuit and provides an audible sound through speaker 54 as long as the first alarm signal is maintained at terminals 14 and L Although the preferred embodiment refers to the application of an alarm signal to terminals 14 and 15 it will be apparent that an AC or DC signal applied to the terminals will activate theo irn6ef4eo o circuit to generate the xpoo 11 alarm. For example, a manual switch and an associated timer circuit may be connected to the terminals.

If a different sound is required, it is only a matter of changing the EPROM memory. In addition, there is no need to reconfigure the output from any circuit applied to terminals 14 and 15 as they are responsive to either an AC or DC voltage.

The housing may suitably be in the form of a ceramic sculpture or moulding, of bird shape, the generated alarm being the sound characteristic of the particular bird depicted by the sculpture. Digital data representative of this sound is preprogrammed in the memory. Any alarm clock which provides an alarm output signal could be connected to the alarm circuit terminals.

3 The foregoing describes only some embodiments of the invention, and modifications which are obvious to those skilled in the art may be made thereto without departing from the scope of the invention as defined in the following claims.

Claims (9)

1. 2. A clock as claimed in claim 1, wherein said housing includes a three dimensional representation of the theme element.
2. 3. A clock as claimed in claim 1 or 2, wherein the theme element is a bird, and the characteristic sound is the bird's call.
3. 4. A clock as claimed in any preceding claim wherein the electronic memory is a digital programmable read only memory. A clock &s claimed in any preceding claim, wherein I ~I t u I ai 4O 9 oto 4 9,I 99 the electronic memory is housed in an interchangeable electrical circuit component of the alarm signal generating means whereby the electronic memory may be interchanged with another electronic memory.
4. 6. A clock as claimed in any preceding claim, wherein the til.epiece provides a first electrical signal to the input means of the alarm signal generating means upon the predetermined time being reached by the timepiece.
5. 7. A clock as claimed in claim 6, wherein the power supply is a battery, and the connecting means connects the alarm signal generating means to the battery only while the first electrical signal is provided by the timepiece.
6. 8. A clock as claimed in any preceding claim, wherein the means for deriving an audio signal includes a digital to analogue convertor, and the means for outputting the audio signal includes an audio amplifier.
7. 9. A clock as claimed in any preceding claim, wherein the alarm signal generating means is mounted within the housing. A clock comprising a timepiece; an alarm signal generating means connected to the timepiece and responsive to a predetermined time indication thereof to generate an audio alarm in the form of a characteristic sound of an animal; wherein the alarm signal generating means comprises input means connected to the timepiece, an interchangeable electronic memory containing digital data representative of the characteristic animal sound, a loud speaker, and means for deriving an audio signal in the characteristic animal 14 sound from the digital data and outputting the audio signal to the loudspeaker, further comprising means for connecting the alarm signal generating means to a power supply at the predetermined time indication for the duration of the audio alarm.
8. 11. A clock as claimed in claim 10 further comprising a housing depicting the animal, said timepiece being mounted on said housing.
9. 12. A clock comprising a housing depicting a theme element having a characteristic sound; a timepiece mounted on the housing; and an alarm signal generating means connected to the timepiece and responsive to a predetermined time indication thereof to generate an audio alarm corresponding to the characteristic sound, the alarm signal generating means being substantially as hereinbefore described with reference to Fig. 1, or Figs. 2 and 3, of the accompanying drawings. DATED this sixth day of August 1990 KEITH OSCAR FORSTER By his Patent Attorneys CULLEN CO. II I- I I I I I