AU596531B2 - Switching control and monitoring apparatus - Google Patents

Description

i v- d iYa S596531 COMMONWEALTH OF AUSTRALIA The Patents Act 1952-1969 Name of Applicant: Address of Applicant: Actual Inventor: Address for Service: t I I 4(#I ftrt A I ft At Ar A A A t .4 A A A LI 1ff At

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QUEENSLAND ELECTRICITY COMMISSION 10 Mary Street, Brisbane, Queensland, 4000.

Peter Gerard.Cristaudo, Paxton Street, North Ward, Townsville, Queensland, 4810.

G.R. CULLEN COMPANY, Patent Trade Mark Attorneys, Dalgety House, 79 Eagle Street, Brisbane, Qld. 4000, Australia.

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t A A A r t r ee COMPLETE SPECIFICATION FOR THE INVENTION ENTITLED: SWITCHING CONTROL AND MONITORING APPARATUS The following statement is a full description of the invention including the best method of performing it known to us: i rr 2 This invention relates to apparatus for monitoring and controlling a solid state switching circuit. In particular, the invention is directed to apparatus for monitoring and controlling solid state switching circuits used in the remote switching of high voltage power lines so as to render such switching circuits failsafe.

Control systems for high voltage power line grids normally comprise a central control station and a plurality of remote terminal units distributed arr-cnd the transmission *o .0 network. Operation of circuit breakers in the power grid or network is performed by respective remote terminal units ,which, in turn, are controlled by the central control station. Each remote terminal unit contains at least one switching or "control output" circuit for controlling the operation of the circuit breakers. Generally, each control 4' output circuit drives an interposing relay which operates a respective circuit breaker in the high voltage switchyard.

Q* oThe control output circuits used in such control systems are required to conform to the following criteria: 1. they must operate when required; 2. they must not operate spuriously; 3. any single component failure which reduces the security of the syste must cause the system to close down and report an error; and 4. any single component failure which reduces the reliability of the system without affecting the security of the remaining functions must report an error.

Known control output circuits use relays for the control output interface, i.e. as the switching devices for the interposing relays. These relays are usually grouped in some array which requires ,wer, to be applied to each side of each relay coil in order for each relay to operate. Once the control system has decided which relay to operate, a voltage is supplied on one side of the relay coil matrix and the voltage levels are monitored by independent logic and fed back to the ntrol system for verification. This voltage is then removed, checked, and a reverse potential applied on the .0 10 other side of the relay coil matrix and then checked.

Following the successful verification of proper operation, according to electronic sensing devices; power is applied to both sides of the coil which should then result in the proper relay operating.

However, the known relay-based control input circuits possess several inherent disadvantages, including:

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°o The output of each relay is not monitored and thus no guarantee of its proper operation is given. An open circuited relay coil or dirty contact could result in the non-execution of a control command.

The system is only checked whenever a control is performed.

To date, relay coilE; have been used in preference to solid state switches since solid state switches have no predictable failure mode. They can fail to either open or closed states (or even in-between). Unlike relays, solid state switches do not possess extra sets of relay contacts for monitoring their operation. However, solid state devices 4 are not limited by the inherent unreliability of electromechanical devices.

It is an object of the present invention to overcome or avoid the disadvantages of prior art relay-based control output circuits by using control output circuits which are solid state yet meet the criteria set forth above. The present invention provides apparatus for controlling and monitoring such solid state control output circuits so a3 to render them failsafe.

10 In one broad form therefore, the present invention provides apparatus for controlling and monitoring the operation of one or more solid state switching circuits, said apparatus comprising: input means for receiving switching control information, first microcomputer means having an input connected to said input means and an output connectable to each said S."o switching circuit for operating same, means for monitoring operation of said switching S 20 circuits, second microcomputer means having an input connected to said monitoring means, and a communication path between said first and second microcomputer means, wrherein said switching circuits are selectively operable by said first microcomputer means and the operation of said switching circuits is monitored by said second microcomputer means.

In the preferred embodiment, each solid state switching circuit is a control output circuit of a remote terminal unit in a power distribution network. Each switching circuit drives an interposing relay which is used to operate a circuit breaker in the distribution network.

The first microcomputer means is typically a microprocessor which selectively switches any one of the plurality of control output circuits. Preferably, the main switching element in each control output circuit is an opticallycoupled transistor device, typically an Opto Mos transistor.

In the preferred embodiment, the means for monitoring operation of the control output circuits takes the form of an optoelectronic device connected in series with the Opto Mos in each respective control output circuit.

Typically, the optoelectronic device is an optically-coupled transistor switch, the output of which is fed to the second t 4$ microcomputer means, typically, a microprocessor. The first and second microprocessors are in continuous communication.

In this manner, the first microcomputer is able to control the switching of the control output circuits, while the r second microprocessor monitors such switching.

During control operations, the control output r circuits are switched so as to connect a first power supply to a respective interposing relay. However, it is not necessary to perform actual control operations in order to check the integrity of the control output circuits. By utilising a reversed biased diode (back-diode) which is wired across each interposing relay, the apparatus of the

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0 b0 *9 00o o 0 present invention is able to continuously check the output circuits without forming actual operations. This is achieved by using a second power supply. The second power supply is a reversed biased voltage supply (hereinafter referred to as the "spy" supply). The microprocessors selectively switch the reversed biased voltage supply to the control output circuits to pass reversed biased current through the solid state switching devices and the back-diode (thus bypassing the output relay coil) whilst monitoring that current via "spy" Opto couplers on a continuous basis. The voltage and current of the second power oupply are limited such that the reverse biased voltage is insufficient to operate the interposing relay. Thus, the operation of each control output circuit can be tested under quiescent conditions by using the spy power supply and the back diode.

Preferably, monitoring light emitting diodes are located in the respective control output circuits to provide visual indication of the operation of the circuits. By using dual direction red/green monitoring LEDs, it is possible to tell at a glance whether the control output circuit is being operated with the control powT: supply or spy power supply.

The use of thR abovedescribed apparatus provides the following advantages: 1. all output circuits are continuously monitored; 2. each solid state switching device is checked continuously for short or open circuit errors; 3. all decodi g and encoding logic and the Microprocessors can be checked continuously; p 0l) p OP p 00 pa *0 0t p0 0 i 0 0 1 1 r It 9t 1 I I I It I L I I I (I I 999 I Ir I 91 44 9 *e 9 94 44 4

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9It 4 Ii 4. the main power supply or "control" supply is monitored continuously since it is used to generate the reverse biased "spy" voltage supply; the separation of the "control" and "spy" circuitry eliminates the possibility of a single component error effecting both microprocessors; 6. the use of microprocessors allows the diagnosis and reporting of faults. The report indicates whether the device has shorted or become open-circuited.

10 A preferred embodiment of the invention will now be described by way of example with reference to the accompanying drawings, in which: Fig. 1 is a schematic diagram of a remote terminal unit incorporating the control and monitoring apparatus of 15 the preferred embodiment; Fig. 2 is a circuit diagram of a single switching or control output circuit of Fig. 1; and Fig. 3 is a schematic diagram of the matrix configuration of the control output circuits of Fig. 1.

As shown in Fig. 1, the apparatus of the preferred embodiment is used to monitor and control a plurality of switching circuits such as control output circuits 24 in a remote terminal unit in a substation of a power transmission network. In the illustrated embodiment, up to 64 control output circuits 24 can be used. Each control output circuit, shown in more detail in Fig. 2, drives a relay 14. The relay 14 is the last interposing relay between the remote control equipment and a corresponding circuit breaker in the n :I J 8 substation switchyard. That is, when the relay 14 is closed, a circuit breaker in the substation switchyard is also closed to effect a connection between high voltage power lines.

Typically, the relay 14 is a 4T/C trip and close relay. As 1 5 wired in the circuit of Fig. 1, each relay 14 is tripped by a negative voltage, e.g. -50 volts. Any positive voltage applied to the relay 14 will be shorted through its associated back diode 23. However, the relay 14 can be wired so as to be tripped by a positive voltage, the polarity of S 10 the back diode 23 being reversed accordingly.

The voltage required to trip each relay 14 is derived from a sub-station or control battery 15 and switched 4" through a series connection of a control block switch 16, two power Opto Mos switches 17, 18 and a respective "control" Opto Mos switch 12. The control Opto Mos switches 12 are controlled by a first microcomputer means, typically a o o 0'oS micropr oessor (hereinafter referred to as the "control" microprocessor 10), via decoder 11.

Current flowing in each output circuit 24 is detected by a respective Opto switch 22 (hereinafter referred to as a "spy" Opto) connected in series with the relay 14. The outputs of the spy Optos 22 are fed via a decoder 21 to a second microcomputer means, typically a microprocessor 20 (hereinafter referred to as the "spy" microprocessor).

Monitoring light emitting diodes 13 are also provided in the respective control output circuits 24. The 'jEDs 13 emit red in response to current flowing therethrough r 9 in one direction, and green for current flowing therethrough in the opposite direction. The monitoring LEDs provide a visual indication of current flow in the control output circuits 24.

The switching control philosophy is based on complete duplication, from the control centre actuators to the sub-station output circuits and including a duplication of the control message. In keeping with this philosophy, the sub-station decoder is made up of a duplicated system. Thus, any single component breakdown will render the system safe 0*e0 and inoperative.

*0 As can be seen from Fig. 1, the duplication does not 0 Qq°° consist of two identical parallel systems requiring a two out I of two decision. Rather, the system consists of two identical processors, the control processor 10 activating the j selected output circuit, and the spy processor 20 monitoring o ao o the operation of the control processor 10 and continuously S checking the state of the output circuits 24. Both processors control the "control" voltage supply and a "spy" 20 power supply to ensure that a failure of one does not cause S' an unwanted operation.

The microprocessors 10, 20 communicate in a very strict sequence as described hereinafter, and an improper or Ao missing reply from one microprocessor causes the other to close down and report an error.

Under normal, quiescent conditions, the two microprocessors 10, 20 carry out a check on all control output circuits 24 through the back diodes 23, ensuring that r there are no open circuits, no short circuits and no control Opto Mos faults. The monitoring operation during quiescent conditions will be described in more detail later.

When a control message is transmitted from the central control station, it is demodulated and passed to input 26 where it is fed to both microprocessors 10, Each microprocessor receives and decodes the whole duplicated me-sage, checks the BCH code and compares the two halves of the duplicated message. The station number is checked against a preset station identification number, typically strapped on the back plane of the remote terminal unit.

A "spy" check, described more fully later, is performed to ensure that both processors have received the same command. If the spy check is satisfactory, the process is repeated using the real control supply. '"ter the control is repeated, the microprocessors return to their checking task.

The control Opto Mos 12 for each trip/close function needs to be tested for open or short circuits. To enable such testing to be done, the back diodes 23 for the respective relays 14 are utilized. Namely, by testing each control Opto Mos 12 with a reverse biased power supply (the "spy" supply) the test or spy current is able to flow through the control Opto Mos 12 via the back diode 23. In order to prevent inadvertent operation t riy of the relays 14 in the event of an open circuit of a back diode 23, the spy power supplied is limited to below the threshold operating voltage and current for the relay. In the illustrated embodiment, *i 0 0 4 a' c *B 0L 9 0, r .9" i p 0a ij 1 0 4~ 11 the spy power supply is limited to a maximum of 12 volts, with a current limit of 10mA, which is too low to operate any 4T/C relay in the system. Typically, the spy power supply is derived from the sub-station or control battery 15 via a DC/DC converter 25. Preferably, the DC/DC converter includes two series diodes (not shown) to prevent inadvertent connection of a "forward" negative) voltage to the relays via the spy power supply.

S.r The current flowing through each control Opto Mos 12 10 is detected by its respective spy Opto 22 which, in turn, is

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0 read by the spy processor 20. When a control Opto Mos 12 is S turned on for checking by passing a reversed biased current r* through the back diode, all spy Optos 22 are read i; sequence. If only the corresponding spy Optos detects I 15 current, the test is satisfactory, i.e. it means that only the selected control Opto Mos has been turned on. In the e vent of a control Opto Mos failure (open circuit), or of an open circuit in the external circuit, including the back diode 23, the corresponding spy Opto 22 provides no output, 0 20 signalling a fault in that particular part of the circuit. A short circuit in a control Opto Mos is detected during each test cycle, as only one spy Opto 22 should signal current Utherethrough.

.i The control power switches 17, 18 and spy power switches 27, 28 are then tested individually. The detection of any serious error closes down the system and signals an alarm to the central control station; non-serious faults result in an alarm only. A VDU (not shown) can be plugged

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r_ 1 1h 4 4. 4 4 4," 4 4 I 4444 4 L 0 *9 0 4 4 4 40 4 D 4 1944 into the control microprocessor 20 to report any open circuits, short circuits in any Op' in the system and other faults relating to the operation of the microprocessors.

The monitoring and checking operations during quiescent operation and upon receipt of a control command will now be described in more detail.

QUIESCENT OPERATION A. The control microprocessor 10 outputs no address and no data and the power Opto Mos switches 17, 18 are turned off.

B. The control processor 10 transmits a "data ready" signal to the spy microprocessor 20 and waits for the spy processor to send a "ready" signal C. The control processor, on receipt of transmits an address in binary to the decoder 11. The address is decoded into one of sixteen possible address lines. The control processor 10 also transmits data, being one of eight possible data lines.

D. The spy processor 20 then commences its oiecking operations: 20 40 A check is first made for the absence of any current in any of the control circuits 24 a "no power" check. The output of all spy Optos 22 are OR'ed and the result is put in the first byte of a spy check "Answer" buffer, (ii) The spy processor 20 sends a "yes power" signal to the control processor 10. On rsoeipt of the Y 13 signal, the control processor turns on its "spy" Opto Mos z switch 28 (SOM2) and echoes a Y signal back to the spy processor as acknowledgment.

(iii) The spy processor then checks all spy Optos 22 again as per above.

(iv) The spy processor 20 turne on its own power Opto Mos switch 27 (SOM1) and again checks all sixteen aadresses of the spy Optos 22, storing its results in a sixteen byte answer buffer following the power check byte.

During the scan, the spy processor checks and exclusive ORs the bits expected from the data received from the control processor with the data read from the spy Optos 22 at the appropriate address. If all is well, one would expect sixteen bytes of zeros to be generated; i.e. the data read is id!ntical to the data expected.

The spy processor 20 then sends a "no power" S* signal to the control processor which, in turn, turns its spy Optos mos switch 28 (SOM2) off and echoes an N signal back to the spy processor as acknowledgement.

(vi) The spy processor performs a further "no power" cheek .s per above.

(vii) The spy processor 20 turns its power Opto Mos switch 27 (SOM1) off and does a further "no power" check as per above.

(viii) The spy processor 20 sends a "data ready for transmission" signal to the control processor. The control processor then sends a "ready" signal back to the spy processor indicating that it is now ready to receive

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14 data.

(ix) The spy processor 20, on receipt of R, transmits the seventeen bytes in its Answer buffer the power byte and sixteen address checking bytes) in binary to the control processor. The data is transmitted in mostly non-viewable characters, but not necessarily non-audible.

The control processor 10 can now analyse the data for errors: If the power byte is not zero, a "power error" is output to the VDU. A power error flag is set and the system ti't is shut down after a cor.pletion of checking of all seventeen bytes and the reporting of any other error found. A comms.

alarm is output and a power error LED is illuminated.

If any of the other sixteen bytes in the data are 15 non-zero, there are two possibilities: If the bit set corresponds to the control Opto Mos 12 under test, this indicates an open circuit error which is reported on the VDU, the comms. alarm is output and an open circuit error LED is illuminated. This error (if it is S 20 the only error) can be accepted locally by pressing an 4 "accept" button until the comms. alarm LED is extinguished.

(ii) If any other bit is found set, this is considered as a short circuit error which is fatal. The error is reported on the VDU, an output LED is illuminated, the comms. alarm is output and the system shuts down.

In order to test all control circuits, the tests are conducted in the following order: 1. The first address is output with no data and the i complete testing sequence described above is performed.

2. The data is then set to the first of eight positions and the sequence repeated.

3. The data is shifted and the sequence is repeated for all eight possibilities.

4. The address is the incremented and the whole procedure just described (1 3) is repeated.

This process continues for as many times as needed for the cards fitted.

(It should be noted that the pause between each address group is the zero data test).

CONTROL COMMAND RECEIPT When a control message is received from the centra, control station, the regular checking of both processors is t 15 interrupted and each decodes the incoming message. On completion of a successful decode, the control processor "sends a signal to the spy processor 20. The spy processor, on completion of a successful decode and on receipt of sends a (yes power) to the control 20 processor The following checks are performed before a control takes place; A "spy" check on the control circuit for the selected breaker,, identical to that described in paragraphs to above for quiescent operation is performed.

(ii) Following these tests and if no errors are d.sicovered, an independent check of the two power Opto Mos switches 17, 18 (POM1 and POM2) is carried out identical to 16 that described in paragraph However, instead of checking SOM2 as per paragraph and SOM1 as per paragraph the checks are carried out on POM2 and POM1, respectively. Thus, during the test outlined in paragraph on the power Opto Mos switches, the actual control takes place. The further tests described in paragraphs to are carried out subsequently to secure the integrity of POM1 for future operations.

It should be noted that the majority of tests on el 10 POM1 and POM2 are carried out during "dummy" circuit breaker I operations. However, the tests are also conducted during actual circuit breaker operations.

t"S By virtue of its low component count, its low power consumption, the use of PC boards and the absence of 15 electromechanical components, the solid state switching device of this application is highly reliable in its operation.

The foregoing describes only one embodiment of the invention, and modifications which are obvious to those 20 skilled in the art may be made thereto without departing from the scope of the invention as claimed in the following claims. For example, while the preferred embodiment has been described with reference to its application to a remote terminal unit in a transmission system sub-station, the invention can also be applied to check the integrity of other switching systems and to render them failsafe. For example, the invention has application to programmable controllers and control systems added to personal computers. Furthermore, 17 with suitable modification, the invention can be usea to control and monitor the operation of more than 64 switching circuits.

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Claims (9)

1. 2. Apparatus as claimed in Claim 1, wherein each said solid state switching circuit is a control output. circuit of a remote terminal unit in a power distribution network, each t^ ,control output circuit being adapted to operate a respective circuit breaker in the distribution network.
2. 3. Apparatus as claimed in Claim 2, wherein each control output circuit includes an interposing relay for operating the respective circuit breaker for said output circuit. It 41 t% 4j tr 4 cr 44 19
3. 4. Apparatus as claimed in Claim 3, further comprising a reversed biased diode connected in parallel with each respective interposing relay; and power supply switching means for selectively applying a voltage supply of opposite polarity to said control output circuits, said power supply switching means being controlled by said first and/or second microcomputer means. Apparatus as claimed in any preceding claim, wherein the means for monitoring operation of the switching circuits comprises electronic monitoring devices connected in series with respective switching circuits.
4. 6. Apparatus as claimed in Claim 5, wherein each electronic monitoring device is an optically-coupled transistor switch having an output connected to said second microcomputer means.
5. 7. Apparatus as claimed in any preceding claim, wherein the principal switching element in each switching circuit is an optically-coupled transistor device.
6. 8. Apparatus as claimed in any preceding claim, wherein said first microcomputer means comprises a microprocessor for selectively sitching any one of said switching circuits and said second microcomputer means comprises a second microprocessor connected to said first microprocessor.
7. 9. Apparatus for monitoring and controlling the operation of one or more solid state switching circuits each having a switch element therein, said apparatus comprising: input means for receiving switching co;.trol information, i tt first microcomputer means having an input connected to said input means and an output connectable to each said switching circuit for operating the switch element thereof, an operative element associated with each respective switching circuit which is responsive to the switch element of the respective circuit, means for monitoring operation of each said switch element, said monitoring means comprising solid state electronic devices connected in series with respective operative elements, second microcomputer means having an input connected to the output of each of said electronic devices, and a communication path between said first and second microcomputer means, wherein said switching circuits are selectively operable by said first microcomputer means and the operation of said switching circuits is monitored by said second microcomputer means.
8. 10. Apparatus as claimed in claim 9, further comprising a reverse bias diode connected in parallel with each respective operative element, and means for selectively applying supply voltage of opposite polar ity to said switching circuits, said means being controlled by said first and/or second microcomputer means.
9. 11. Apparatus for monitoring and controlling the operavion of one or more solid state switching circuits, said apparatus being substantially as hereinbefore described with t at t 1* 'r t 90 9 a 91 a. 21 reference to the accompanying drawings. DATED this 27th day of June, 1988. QUEENSLAND ELECTRICITY COMMISSION By their Patent Attorneys G.R. CULLEN CO. 4 a 4 BMW".