AU5954594A - Method and apparatus for transforming an arbitrary acyclic topology collection of nodes into an acyclic directed graph - Google Patents

Method and apparatus for transforming an arbitrary acyclic topology collection of nodes into an acyclic directed graph

Info

Publication number
AU5954594A
AU5954594A AU59545/94A AU5954594A AU5954594A AU 5954594 A AU5954594 A AU 5954594A AU 59545/94 A AU59545/94 A AU 59545/94A AU 5954594 A AU5954594 A AU 5954594A AU 5954594 A AU5954594 A AU 5954594A
Authority
AU
Australia
Prior art keywords
acyclic
transforming
nodes
directed graph
arbitrary
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
AU59545/94A
Inventor
Florin Oprescu
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Apple Inc
Original Assignee
Apple Computer Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Apple Computer Inc filed Critical Apple Computer Inc
Publication of AU5954594A publication Critical patent/AU5954594A/en
Abandoned legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
    • H04L12/40—Bus networks
    • H04L12/40052—High-speed IEEE 1394 serial bus
    • H04L12/40078—Bus configuration
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G06F15/163—Interprocessor communication
    • G06F15/173—Interprocessor communication using an interconnection network, e.g. matrix, shuffle, pyramid, star, snowflake
    • G06F15/17337—Direct connection machines, e.g. completely connected computers, point to point communication networks
    • G06F15/17343—Direct connection machines, e.g. completely connected computers, point to point communication networks wherein the interconnection is dynamically configurable, e.g. having loosely coupled nearest neighbor architecture

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Software Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Small-Scale Networks (AREA)
AU59545/94A 1992-12-21 1993-12-16 Method and apparatus for transforming an arbitrary acyclic topology collection of nodes into an acyclic directed graph Abandoned AU5954594A (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US99411792A 1992-12-21 1992-12-21
US994117 1992-12-21
PCT/US1993/012325 WO1994015305A1 (en) 1992-12-21 1993-12-16 Method and apparatus for transforming an arbitrary acyclic topology collection of nodes into an acyclic directed graph

Publications (1)

Publication Number Publication Date
AU5954594A true AU5954594A (en) 1994-07-19

Family

ID=25540301

Family Applications (1)

Application Number Title Priority Date Filing Date
AU59545/94A Abandoned AU5954594A (en) 1992-12-21 1993-12-16 Method and apparatus for transforming an arbitrary acyclic topology collection of nodes into an acyclic directed graph

Country Status (2)

Country Link
AU (1) AU5954594A (en)
WO (1) WO1994015305A1 (en)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5608649A (en) * 1994-05-16 1997-03-04 Gopinath; Bhaskarpillai Directly programmable networks
SG77163A1 (en) 1998-03-06 2000-12-19 John Francis Chong A method of implementing an acyclic directed graph structure using a relational database
DE69819301D1 (en) 1998-05-01 2003-12-04 Hewlett Packard Co Procedure for managing dynamic decision trees
DE69829645T2 (en) * 1998-05-01 2006-03-09 Hewlett-Packard Development Co., L.P., Houston Method for changing dynamic decision trees
EP1079580A3 (en) * 1999-08-23 2003-08-06 Sanyo Electric Co., Ltd. Method and apparatus for avoiding loop connection
US8407340B2 (en) * 2010-04-09 2013-03-26 Microsoft Corporation Page load performance analysis

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06500655A (en) * 1990-10-03 1994-01-20 スィンキング　マシンズ　コーポレーション parallel computer system
FR2676558B1 (en) * 1991-05-15 1993-07-23 Opticable METHOD FOR AUTOMATICALLY DETERMINING THE CONFIGURATION OF A NETWORK.

Also Published As

Publication number Publication date
WO1994015305A1 (en) 1994-07-07

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