AU541542B2 - Processing a t.d.m signal - Google Patents
Processing a t.d.m signalInfo
- Publication number
- AU541542B2 AU541542B2 AU22557/83A AU2255783A AU541542B2 AU 541542 B2 AU541542 B2 AU 541542B2 AU 22557/83 A AU22557/83 A AU 22557/83A AU 2255783 A AU2255783 A AU 2255783A AU 541542 B2 AU541542 B2 AU 541542B2
- Authority
- AU
- Australia
- Prior art keywords
- parity bit
- frame code
- odd
- sum
- determinate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Ceased
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J3/00—Time-division multiplex systems
- H04J3/02—Details
- H04J3/06—Synchronising arrangements
- H04J3/0602—Systems characterised by the synchronising information used
- H04J3/0605—Special codes used as synchronising signal
Landscapes
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Time-Division Multiplex Systems (AREA)
- Detection And Prevention Of Errors In Transmission (AREA)
- Communication Control (AREA)
- Radar Systems Or Details Thereof (AREA)
- Synchronisation In Digital Transmission Systems (AREA)
- Mobile Radio Communication Systems (AREA)
- Selective Calling Equipment (AREA)
Abstract
1. A method of monitoring the synchronisation of a t.d.m. system and of initiating resynchronisation at a predetermined value of the frequency of non-conformity between an expected frame code word and the bit pattern actually occuring at this position, characterized in that at the transmitting end, during a determinate measuring period (M1, M3, M5... Mn), in a determinate time relationship to the frame code, it is determined whether the sum of all the transmitted bits of a logic state is even or odd, that a parity bit is formed, the logic status of which provides a statement as to whether evenness or oddness has been determined, that the parity bit is inserted into an unoccupied time slot of the pulse frame, that at the receiving end, during the same measuring period, in the same time relationship to the recognised but possibly incorrect frame code, it is determined whether the sum of all the received bits of the logic state which has been selected at the transmitting end is even or odd and that the receiving-end result is compared with the statement contained in the received parity bit.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| DE3247304 | 1982-12-21 | ||
| DE19823247304 DE3247304A1 (en) | 1982-12-21 | 1982-12-21 | METHOD AND ARRANGEMENT FOR MONITORING THE SYNCHRONIZATION OF A TIME MULTIPLEX SYSTEM |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| AU2255783A AU2255783A (en) | 1984-06-28 |
| AU541542B2 true AU541542B2 (en) | 1985-01-10 |
Family
ID=6181283
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| AU22557/83A Ceased AU541542B2 (en) | 1982-12-21 | 1982-12-20 | Processing a t.d.m signal |
Country Status (8)
| Country | Link |
|---|---|
| EP (1) | EP0111913B1 (en) |
| JP (1) | JPS59119939A (en) |
| AT (1) | ATE20992T1 (en) |
| AU (1) | AU541542B2 (en) |
| BR (1) | BR8306985A (en) |
| DE (2) | DE3247304A1 (en) |
| GR (1) | GR79483B (en) |
| NO (1) | NO834655L (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| FR2565444B1 (en) * | 1984-06-05 | 1988-08-05 | Bojarski Alain | FRAME LOCKING METHOD IN A DIGITAL SIGNAL AND CORRESPONDING DEVICES FOR GENERATING AND RECOVERING FRAME LOCK. |
| DE4337097C2 (en) * | 1992-11-02 | 1996-03-14 | Toyota Motor Co Ltd | Supporting structure for a ceramic throttle valve assembly |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3963869A (en) * | 1974-12-02 | 1976-06-15 | Bell Telephone Laboratories, Incorporated | Parity framing of pulse systems |
| JPS52142403A (en) * | 1976-05-21 | 1977-11-28 | Mitsubishi Electric Corp | Signal synchronous system |
-
1982
- 1982-12-20 AU AU22557/83A patent/AU541542B2/en not_active Ceased
- 1982-12-21 DE DE19823247304 patent/DE3247304A1/en not_active Withdrawn
-
1983
- 1983-12-09 JP JP58231594A patent/JPS59119939A/en active Pending
- 1983-12-16 EP EP83112709A patent/EP0111913B1/en not_active Expired
- 1983-12-16 NO NO834655A patent/NO834655L/en unknown
- 1983-12-16 DE DE8383112709T patent/DE3364776D1/en not_active Expired
- 1983-12-16 AT AT83112709T patent/ATE20992T1/en not_active IP Right Cessation
- 1983-12-19 GR GR73281A patent/GR79483B/el unknown
- 1983-12-20 BR BR8306985A patent/BR8306985A/en unknown
Also Published As
| Publication number | Publication date |
|---|---|
| BR8306985A (en) | 1984-07-24 |
| JPS59119939A (en) | 1984-07-11 |
| EP0111913A1 (en) | 1984-06-27 |
| DE3247304A1 (en) | 1984-06-28 |
| DE3364776D1 (en) | 1986-08-28 |
| NO834655L (en) | 1984-06-22 |
| AU2255783A (en) | 1984-06-28 |
| ATE20992T1 (en) | 1986-08-15 |
| GR79483B (en) | 1984-10-30 |
| EP0111913B1 (en) | 1986-07-23 |
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