AU3763500A - Multi-atm layer, multi-phy layer bus architecture - Google Patents

Multi-atm layer, multi-phy layer bus architecture

Info

Publication number
AU3763500A
AU3763500A AU37635/00A AU3763500A AU3763500A AU 3763500 A AU3763500 A AU 3763500A AU 37635/00 A AU37635/00 A AU 37635/00A AU 3763500 A AU3763500 A AU 3763500A AU 3763500 A AU3763500 A AU 3763500A
Authority
AU
Australia
Prior art keywords
layer
bus architecture
atm
phy
phy layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
AU37635/00A
Inventor
Randall B. Sharpe
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Pliant Systems Inc
Original Assignee
Pliant Systems Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Pliant Systems Inc filed Critical Pliant Systems Inc
Publication of AU3763500A publication Critical patent/AU3763500A/en
Abandoned legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/54—Store-and-forward switching systems 
    • H04L12/56—Packet switching systems
    • H04L12/5601—Transfer mode dependent, e.g. ATM
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/10—Packet switching elements characterised by the switching fabric construction
    • H04L49/104—Asynchronous transfer mode [ATM] switching fabrics
    • H04L49/105—ATM switching elements
    • H04L49/107—ATM switching elements using shared medium
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/30—Peripheral units, e.g. input or output ports
    • H04L49/3081—ATM peripheral units, e.g. policing, insertion or extraction
    • H04L49/309—Header conversion, routing tables or routing tags
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/54—Store-and-forward switching systems 
    • H04L12/56—Packet switching systems
    • H04L12/5601—Transfer mode dependent, e.g. ATM
    • H04L2012/5629—Admission control
    • H04L2012/5631—Resource management and allocation
    • H04L2012/5632—Bandwidth allocation
    • H04L2012/5635—Backpressure, e.g. for ABR
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/54—Store-and-forward switching systems 
    • H04L12/56—Packet switching systems
    • H04L12/5601—Transfer mode dependent, e.g. ATM
    • H04L2012/5678—Traffic aspects, e.g. arbitration, load balancing, smoothing, buffer management
    • H04L2012/5679—Arbitration or scheduling
AU37635/00A 1999-06-02 2000-03-20 Multi-atm layer, multi-phy layer bus architecture Abandoned AU3763500A (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US32457899A 1999-06-02 1999-06-02
US09324578 1999-06-02
PCT/US2000/007340 WO2000074317A1 (en) 1999-06-02 2000-03-20 Multi-atm layer, multi-phy layer bus architecture

Publications (1)

Publication Number Publication Date
AU3763500A true AU3763500A (en) 2000-12-18

Family

ID=23264222

Family Applications (1)

Application Number Title Priority Date Filing Date
AU37635/00A Abandoned AU3763500A (en) 1999-06-02 2000-03-20 Multi-atm layer, multi-phy layer bus architecture

Country Status (2)

Country Link
AU (1) AU3763500A (en)
WO (1) WO2000074317A1 (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE10112811A1 (en) * 2001-03-16 2002-10-02 Siemens Ag Method for utilizing hardware-assisted segmentation/reassembling with non-ATM-communication interfaces on microcontrollers splits a data packet into cells given a correct header address and fed to a multiplexer.
CN1330146C (en) * 2003-05-21 2007-08-01 华为技术有限公司 Asynchronous transmission mode layer port processing expansion module

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CA2034878C (en) * 1990-03-08 2002-04-02 Craig S. Hyatt Programmable controller communication module
CA2181293C (en) * 1995-07-17 2000-06-06 Charles Kevin Huscroft Atm layer device

Also Published As

Publication number Publication date
WO2000074317A1 (en) 2000-12-07

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Legal Events

Date Code Title Description
MK6 Application lapsed section 142(2)(f)/reg. 8.3(3) - pct applic. not entering national phase