AU3563697A - A method, an apparatus and a network for clock recovery - Google Patents
A method, an apparatus and a network for clock recoveryInfo
- Publication number
- AU3563697A AU3563697A AU35636/97A AU3563697A AU3563697A AU 3563697 A AU3563697 A AU 3563697A AU 35636/97 A AU35636/97 A AU 35636/97A AU 3563697 A AU3563697 A AU 3563697A AU 3563697 A AU3563697 A AU 3563697A
- Authority
- AU
- Australia
- Prior art keywords
- network
- clock recovery
- clock
- recovery
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
- H03L7/091—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector using a sampling device
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
- H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
- H03L7/181—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a numerical count result being used for locking the loop, the counter counting during fixed time intervals
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J3/00—Time-division multiplex systems
- H04J3/02—Details
- H04J3/06—Synchronising arrangements
- H04J3/062—Synchronisation of signals having the same nominal but fluctuating bit rates, e.g. using buffers
- H04J3/0632—Synchronisation of packets and cells, e.g. transmission of voice via a packet network, circuit emulation service [CES]
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04Q—SELECTING
- H04Q11/00—Selecting arrangements for multiplex systems
- H04Q11/04—Selecting arrangements for multiplex systems for time-division multiplexing
- H04Q11/0428—Integrated services digital network, i.e. systems for transmission of different types of digitised signals, e.g. speech, data, telecentral, television signals
- H04Q11/0478—Provisions for broadband connections
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/54—Store-and-forward switching systems
- H04L12/56—Packet switching systems
- H04L12/5601—Transfer mode dependent, e.g. ATM
- H04L2012/5614—User Network Interface
- H04L2012/5616—Terminal equipment, e.g. codecs, synch.
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/54—Store-and-forward switching systems
- H04L12/56—Packet switching systems
- H04L12/5601—Transfer mode dependent, e.g. ATM
- H04L2012/5672—Multiplexing, e.g. coding, scrambling
- H04L2012/5674—Synchronisation, timing recovery or alignment
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/54—Store-and-forward switching systems
- H04L12/56—Packet switching systems
- H04L12/5601—Transfer mode dependent, e.g. ATM
- H04L2012/5678—Traffic aspects, e.g. arbitration, load balancing, smoothing, buffer management
- H04L2012/5681—Buffer or queue management
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
SE9602823 | 1996-07-19 | ||
SE9602823A SE9602823L (en) | 1996-07-19 | 1996-07-19 | A method, a device and a network to recover the clock |
PCT/SE1997/001168 WO1998004063A2 (en) | 1996-07-19 | 1997-06-27 | A method and an apparatus for recovery of the clock of a constant bit-rate service |
Publications (1)
Publication Number | Publication Date |
---|---|
AU3563697A true AU3563697A (en) | 1998-02-10 |
Family
ID=20403436
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
AU35636/97A Abandoned AU3563697A (en) | 1996-07-19 | 1997-06-27 | A method, an apparatus and a network for clock recovery |
Country Status (3)
Country | Link |
---|---|
AU (1) | AU3563697A (en) |
SE (1) | SE9602823L (en) |
WO (1) | WO1998004063A2 (en) |
Families Citing this family (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE60038251T2 (en) * | 1999-12-13 | 2009-03-12 | Broadcom Corp., Irvine | LANGUAGE TRANSMISSION DEVICE WITH LANGUAGE SYNCHRONIZATION IN DOWNWARD DIRECTION |
US7027424B1 (en) | 2000-05-24 | 2006-04-11 | Vtech Communications, Ltd. | Method for avoiding interference in a digital communication system |
GB0100094D0 (en) | 2001-01-03 | 2001-02-14 | Vtech Communications Ltd | System clock synchronisation using phased-lock loop |
GB2401764B (en) * | 2001-01-03 | 2005-06-29 | Vtech Communications Ltd | System clock synchronisation using phase-locked loop |
DE10232988B4 (en) * | 2002-07-19 | 2007-11-22 | Infineon Technologies Ag | Method and device for the clocked output of asynchronously received digital signals |
WO2009010891A1 (en) * | 2007-07-17 | 2009-01-22 | Nxp B.V. | A method and a device for data sample clock reconstruction |
US8401007B2 (en) * | 2009-04-06 | 2013-03-19 | Avaya Inc. | Network synchronization over IP networks |
US8238377B2 (en) | 2009-04-06 | 2012-08-07 | Avaya Inc. | Network synchronization over IP networks |
WO2010141514A2 (en) * | 2009-06-01 | 2010-12-09 | Bit Cauldron Corporation | Method of stereoscopic synchronization of active shutter glasses |
GB201002217D0 (en) | 2010-02-10 | 2010-03-31 | Zarlink Semiconductor Inc | Clock recovery method over packet switched networks based on network quiet period detection |
Family Cites Families (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR2682244B1 (en) * | 1991-10-04 | 1995-01-13 | Cit Alcatel | SYNCHRONIZATION DEVICE FOR THE END EQUIPMENT OF A DIGITAL TELECOMMUNICATIONS NETWORK WITH TRANSFER IN ASYNCHRONOUS MODE. |
US5425061A (en) * | 1993-06-07 | 1995-06-13 | Texas Instruments Incorporated | Method and apparatus for bit stream synchronization |
JPH0766814A (en) * | 1993-08-24 | 1995-03-10 | Anritsu Corp | Atm clock regeneration equipment |
NL9401525A (en) * | 1994-09-21 | 1996-05-01 | Nederland Ptt | Clock recovery for ATM receiver. |
-
1996
- 1996-07-19 SE SE9602823A patent/SE9602823L/en not_active Application Discontinuation
-
1997
- 1997-06-27 AU AU35636/97A patent/AU3563697A/en not_active Abandoned
- 1997-06-27 WO PCT/SE1997/001168 patent/WO1998004063A2/en active Application Filing
Also Published As
Publication number | Publication date |
---|---|
SE9602823D0 (en) | 1996-07-19 |
WO1998004063A3 (en) | 1998-03-12 |
SE9602823L (en) | 1998-01-20 |
WO1998004063A2 (en) | 1998-01-29 |
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