AU2018233019B2 - Video decoder with reduced dynamic range transform with inverse transform shifting memory - Google Patents
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Abstract
- 18 Abstract An apparatus for decoding video, the apparatus comprising one or more processors and one or more storage devices storing instructions that when 5 executed by the one or more processors cause the one or more processors to perform operations comprising: (a) receiving quantized coefficients representative of a block of video representative of a plurality of pixels; (b) descaling the quantized coefficients by multiplying the quantized coefficients with numbers dependent on a coefficient index and a transform 10 size of the block to generate descaled coefficients; (c) applying an adjustment to the descaled coefficients to generate adjusted descaled coefficients, wherein the adjustment is a variable based on the transform size;(d) clipping the adjusted descaled coefficients to a predetermined bit depth to generate clipped coefficients; (e) one-dimensional inverse 15 transforming the clipped coefficients in a first direction to generate first direction inverse transformed coefficients; (f) shifting the first direction inverse transformed coefficients to generate shifted coefficients; (g) clipping the shifted coefficients to the predetermined bit depth to generate second clipped coefficients; and (h) one-dimensional inverse transforming 20 the second clipped coefficients in a second direction to determine a decoded residue, wherein the applying the adjustment is performed after the descaling, and wherein the shifting is performed after the one-dimensional inverse transforming in the first direction and prior to the one-dimensional inverse transforming in the second direction.
Description
VIDEO DECODER WITH REDUCED DYNAMIC RANGE TRANSFORM WITH INVERSE TRANSFORM SHIFTING MEMORY
TECHNICAL FIELD
The present invention relates to image decoding with reduced dynamic range.
io BACKGROUND
Existing video coding standards, such as H.264 /AVC, generally provide relatively high coding efficiency at the expense of increased computational complexity. As the computational complexity increases, the encoding and/ or decoding speeds tend is to decrease. Also, the desire for increased higher fidelity tends to increase over time which tends to require increasingly larger memory requirements and increasingly larger memory bandwidth requirements. The increasing memory requirements and the increasing memory bandwidth requirements tends to result in 20 increasingly more expensive and computationally complex circuitry, especially in the case of embedded systems.
Referring to FIG. 1, many decoders (and encoders) receive (and encoders provide) encoded data for blocks of an image. Typically, the image is divided into blocks and each of the blocks 25 is encoded in some manner, such as using a discrete cosine transform (DCT), and provided to the decoder. The decoder
- 2 2018233019 21 Sep 2018 receives the encoded blocks and decodes each of the blocks in some manner, such as using an inverse discrete cosine transform. In many cases, the decoding of the image coefficients of the image block is accomplished by matrix multiplication. The 5 matrix multiplication may be performed for a horizontal direction and the matrix multiplication may be performed for a vertical direction. By way of example, for 8-bit values, the first multiplication can result in 16-bit values, and the second multiplication can result in 24-bit values in some cases. In io addition, the encoding of each block of the image is typically quantized, which maps the values of the encoding to a smaller set of quantized coefficients used for transmission. Quantization requires de-quantization by the decoder, which maps the set of quantized coefficients used for transmission to approximate is encoding values. The number of desirable bits for de-quantized data is a design parameter. The potential for large values resulting from the matrix multiplication and the de-quantization operation is problematic for resource constrained systems, especially embedded systems.
It is desired to address or ameliorate one or more disadvantages or limitations associated with the prior art, or to at least provide a useful alternative.
SUMMARY
In one example aspect there is provided an apparatus for decoding video, the apparatus comprising one or more processors
- 3 2018233019 21 Sep 2018 and one or more storage devices storing instructions that when executed by the one or more processors cause the one or more processors to perform operations comprising:
(a) receiving quantized coefficients representative of a block 5 of video representative of a plurality of pixels;
(b) descaling the quantized coefficients by multiplying the quantized coefficients with numbers dependent on a coefficient index and a transform size of the block to generate descaled coefficients;
io (c) applying an adjustment to the descaled coefficients to generate adjusted descaled coefficients, wherein the adjustment is a variable based on the transform size;
(d) clipping the adjusted descaled coefficients to a predetermined bit depth to generate clipped coefficients;
is (e) one-dimensional inverse transforming the clipped coefficients in a first direction to generate first direction inverse transformed coefficients;
(f) shifting the first direction inverse transformed coefficients to generate shifted coefficients;
(g) clipping the shifted coefficients to the predetermined bit depth to generate second clipped coefficients; and (h) one-dimensional inverse transforming the second clipped coefficients in a second direction to determine a decoded residue, wherein the applying the adjustment is performed after the 25 descaling, and wherein the shifting is performed after the one- 4 2018233019 21 Sep 2018 dimensional inverse transforming in the first direction and prior to the one-dimensional inverse transforming in the second direction.
In another example aspect there is provided a method for decoding video comprising:
(a) receiving quantized coefficients representative of a block of video representative of a plurality of pixels;
(b) descaling the quantized coefficients by multiplying the quantized coefficients with numbers dependent on a coefficient index and a transform size of the block to generate descaled io coefficients;
(c) applying an adjustment to the descaled coefficients to generate adjusted descaled coefficients, wherein the adjustment is a variable based on the transform size;
(d) clipping the adjusted descaled coefficients to a is predetermined bit depth to generate clipped coefficients;
(e) one-dimensional inverse transforming the clipped coefficients in a first direction to generate first direction inverse transformed coefficients;
(f) shifting the first direction inverse transformed 20 coefficients to generate shifted coefficients;
(g) clipping the shifted coefficients to the predetermined bit depth to generate second clipped coefficients; and (h) one-dimensional inverse transforming the second clipped coefficients in a second direction to determine a decoded residue, wherein the applying the adjustment is performed after the descaling, and
- 5 2018233019 21 Sep 2018 wherein the shifting is performed after the one-dimensional inverse transforming in the first direction and prior to the onedimensional inverse transforming in the second direction.
s BRIEF DESCRIPTION OF THE DRAWINGS
Preferred embodiments of the present invention are hereinafter described, by way of example only, with reference to the accompanying drawings, in which:
FIG. 1 illustrates an encoder and a decoder.
io FIG. 2 illustrates a decoder with a dequantizer and an inverse transform.
FIGS. 3A and FIG. 3B illustrates a modified dequantizer.
FIG. 4 illustrates a modified inverse transform.
FIG. 5 illustrates another decoder, is FIG. 6 illustrates yet another decoder.
DETAILED DESCRIPTION
Referring to FIG. 2 (prior art), a decoder for the dequantization and inverse transformation of the received 20 quantized coefficients from the encoder for a block of the image is illustrated, in relevant part. The decoder receives the quantized coefficients 200 at a dequantizing section (dequantizer) 210. The coefficients resulting from the dequantizer 210 are stored in memory 220. The coefficients stored in memory 220 are then 25 processed by a pair of inverse transforms by a inverse transforming section 230 to determine a decoded residue 310.
- 6 2018233019 21 Sep 2018
The inverse transform maps data from a transform domain to a spatial domain using a matrix multiplication operator.
The dequantizer 210 includes the descaling process by a descaling section 240. The descaling process by the descaling 5 section 240 descales the quantized coefficients 200. The descaling process corresponds to multiplying level values (also referred to as quantized coefficients 200) with one integer number dependent on quantization parameter (QP), coefficient index, and transform size (N). An example of the descaling io process by the descaling section 240 may include Level*IntegerValue(Remainder, coefficient index)* 16 for a dequantizer used prior to an 8x8 inverse transform and Level*IntegerValue (Remainder, coefficient index) for a dequantizer used prior to other transform sizes. The is descaling process by the descaling section 240 is preferably based upon a function of a remainder, transform size (N), and/ or a coefficient index (e.g., position), to determine an intermediate set of values 250. The remainder is the sum of the quantization parameter (QP) +P*Bitincrement modulo P 20 ((QP+P*BitIncrement)%P). Modulo as defined in the H.264 /AVC standard is defined as: x % y, as remainder of x divided by y, defined only for integers x and y with x>= 0 and y>0. In one embodiment P may take on the value 6. An adjustment mechanism A 260 may be applied to the values 25 250, which may be a variable dependent on transform size (N) and/ or a function of a received Period. The Period is the sum
- 7 2018233019 21 Sep 2018 of the quantization parameter (QP) + P*BitIncrement divided by P ((QP+P*BitIncrement)/P), where Bitincrement is the bit depth increment. The 7 as defined in the H.264/AVC standard is defined as: integer division with truncation of the 5 result towards zero. For example, 7/4 and -7/-4 are truncated to 1 and -7/4 and 7/-4 are truncated to -1. In one embodiment P may take on the value 6. The resulting values 250, possibly further modified by mechanism A 260, may be further modified by a factor of 2(Penod+B) by a modifying io section 270. B is a variable that is dependent on the transform size. The results of the modification by the modifying section 270 are stored in the memory 220. The inverse transforming section 230 may perform a 1dimensional inverse horizontal transform by an inverse is horizontal transforming section 280, the result of which is stored in memory 290. The inverse transforming section 230 may also perform a 1-dimensional inverse vertical transform by an inverse vertical transforming section 300, which results in the decoded residue 310. The transforming sections 280 20 and 300 may be swapped with each other, as desired.
The memory bandwidth of the video decoder illustrated in FIG. 2, when implemented within the Part 10: Advanced Video Coding, ISO publication: ISO/IEC 14496-10:2005 Information Technology - Coding Of Audio-Visual Objects 25 (incorporated by reference herein) (H.264/AVC standard), may be limited by using a constraint. For example, in section
- 8 2018233019 21 Sep 2018
8.5.10 of the H.264/AVC standard, the width of the memory access for 4x4 luma DC transform coefficients is limited by including the following statements: The bitstream shall not contain data that result in any element fy of f with i, j = 0..3 5 that exceeds the range of integer values from -2(7 + bltDepth) to
2(7 + bltDepth) _ 1, inclusive. and The bitstream shall not contain data that result in any element dcYij of dcY with i, j = 0..3 that exceeds the range of integer values from -2(7 + bltDepth) to 2(7 + bltDepth) _ 1, inclusive. The H.264/AVC standard io includes similar memory limitation for other residual blocks.
In addition to including a complex memory bandwidth limitation, the H.264/AVC standard includes no mechanism to ensure that this limitation is enforced. Similarly, the JCTVC, Draft Test Model Under Consideration, JCTVC-A205, is JCT-VC Meeting, Dresden, April 2010 (JCT-VC), incorporated by reference herein, likewise does not include a memory bandwidth enforcement mechanism. For robustness, a decoder must be prepared to accept bitstreams which may violate these limits as may be caused by transmission errors 20 damaging a compliant bitstream or a non-conforming encoder.
To alleviate such potential limitations the decoder frequently includes additional memory bandwidth, at added expense and complexity, to accommodate the non-compliant bit streams that are provided.
In order to provide a more computationally robust decoder with limited memory bandwidth and/or memory
- 9 2018233019 21 Sep 2018 storage requirements, the decoder should be modified in a suitable manner. However, while modifying the decoder to reduce the memory requirements, the corresponding rate distortion performance of the video should not be 5 substantially degraded. Otherwise, while the memory requirements may be reduced, the resulting quality of the video will not be suitable for viewing by the audience. The modification by the modifying section 270 results in a doubling of the coefficient value for every 6 steps in the io quantization parameter, and thus may substantially increase the size of the memory requirements. The increased value results in one or more zeros being included as the least significant bits.
Referring to FIG. 3A, with this understanding of the is operation of the dequantizer 210 (see FIG. 2, prior art) an improved dequantizing section (inproved dequantizer, modified dequantizer) 400 (see FIGS. 3A and 3B, not prior art) receives the quantized coefficients 405 and descales, by a descaling section 410, the quantized coefficients, preferably 20 based upon a function of a remainder, transform size (N), and/ or a coefficient index (e.g., position), to determine an intermediate set of values 420. An optional adjustment mechanism C 430 may be applied, which is preferably a variable dependent on transform size (N) or a function of a 25 received quantization parameter (QP), to determine resulting data 440. The resulting data 440 from the quantized
- 10 2018233019 21 Sep 2018 coefficients 405 may include rogue data or otherwise is not compliant with a standard, and accordingly the modified dequantizer 400 should impose a fixed limit on the resulting data 440. The resulting data 440 is preferably clipped, by a 5 clipping section 450, to a predetermined bit depth, and thus an NxN block of data is stored in memory within the dequantizer 400. For example the clipping by the clipping section 450 for a predetermined bit depth of 16 bits results in any values over 32,767 being set to the maximum value, io namely, 32,767. Likewise for a predetermined bit depth of 16 bits results in any values less than -32,768 being set to the minimum value, namely, -32,768. Other bit depths and clipping values may likewise be used. In this manner, the maximum memory bandwidth required is limited by the is system, in a manner independent of the input quantized coefficients 405. This reduces the computational complexity of the system and reduces the memory requirements, which is especially suitable for embedded systems.
After imposing the clipping by the clipping section 450, 20 the data with the maximum predetermined bit depth is modified by a factor of 2(Period+B) by a modifying section 460. The results of the modification by the modifying section 460 are provided as coefficients 470. The result of performing the 2(Penod+B) tbe modifying section 460 after the clipping by 25 the clipping section 450 reduces the rate distortion loss.
Preferably, the adjustment mechanism C 430 used for 8x8
- 11 2018233019 21 Sep 2018 transform coefficients is 2(5-period) and the 2(Period+B) by the modifying section 460 is 2(Period-6). The process by the modifying section 460 may be based upon, if desired, a function of the transform size (N) or a function of a received 5 quantization parameter (QP). Also, the adjustment mechanism C 430 used for other sized transform coefficients (such as 4x4, 16x16, and 32x32) is preferably zero, and the valued of 2(Penod+B) by the modifying section 460 is 2(Penod). Also, B may be a function of N and C may be a function of N. io Referring to FIG. 3B, a particular implementation of FIG. 3A is illustrated.
Referring to FIG. 4, the coefficients 470 from the dequantizer 400 (see FIGS. 3A and 3B) are provided to an inverse transforming section 480 designed to provide a is decoded residue 490 that has an acceptable rate distortion loss. The coefficients 470 are preferably transformed by a 1dimensional inverse horizontal (or vertical) transform by an inverse horizontal (or vertical) transforming section 500. Based upon a desirable number of output bits to maintain an 20 acceptable rate distortion loss, the output of the transforming section 500 may be modified by a right bit shift process by a bit shifting section 5 10 for a desirable number of bits. In this manner, a selected number of the least significant bits are discarded in order to reduce the memory requirements of the 25 system. For example, if 19 bits are likely to result from the inverse transforming section 500 and it is desirable to have a
- 12 2018233019 21 Sep 2018 bit outcome, then the right bit shift process by the bit shifting section 510 removes the 3 least significant bits. The resulting shifted bits are clipped by a clipping section 520 to a predetermined threshold. An example of a predetermined 5 threshold may be 16-bits. The clipping by a clipping section
520 further enforces a memory bandwidth limitation, the results of which are stored in memory 530. The data stored in memory 530 is substantially reduced as a result of the shifting by the bit shifting section 510 removing the least io significant bit(s). The data stored in the memory 530 is then shifted left by a left bit shift process by a bit shifting section 540, preferably by the same number of bits as the right bit shift process by the bit shifting section 510. The shifting results in zeros in the least significant bit(s). The shifted is data is then preferably transformed by a 1-dimensional inverse vertical (or horizontal) transform by an inverse vertical (or horizontal) transforming section 550, resulting in the decoded residue 490.
The rate distortion loss is dependent on the number of 20 bits used in the processing and the data block size.
Preferably, the right bit shift process by the bit shifting section 510 and the left bit shift process by the bit shifting section 540 are dependent on the size N of the block (number of horizontal pixels x number of vertical pixels for a square 25 block of pixels). For example, for a 4x4 block the shift may be 3, for an 8x8 block the shift may be 2, for a 16x16 block
- 13 2018233019 21 Sep 2018 the shift may be 8, and for a 32x32 block the shift may be 9. Alternatively, the right bit shift process by the bit shifting section 510 and the left bit shift process by the bit shifting section 540 may be determined based upon a parameter, such 5 as a quantization parameter (QP), passed in the bit stream, internal bit-depth increment (IBDI), the transform precision extension (TPE) parameters, or otherwise selectable by the decoder.
Referring to FIG. 5, in another embodiment the decoder io receives the quantized coefficients which are processed by any suitable dequantizing section (dequantizer) 600 and any suitable inverse transforming section 6 10. It is desirable to include an express memory bandwidth limitation which is preferably implemented by including a clipping function by a is clipping section 620. After the clipping function by the clipping section 620, the data may be stored in memory 630, which is thereafter used for the inverse transform by the inverse transforming section 610.
Referring to FIG. 6, in another embodiment the decoder receives the quantized coefficients which are processed by any suitable dequantizing section (dequantizer) 700 and any suitable inverse transforming section 7 10. For example, the inverse transform by the inverse transforming section 7 10 may be the one illustrated in FIG. 4. It is desirable to include 25 an express memory bandwidth limitation to reduce the computation complexity which is preferably implemented by including a clipping function by a clipping section 720. After
- 14 2018233019 21 Sep 2018 the clipping function by the clipping section 720, the data may be stored in memory 730, which is thereafter used for the inverse transform by an inverse transforming section 710. It is further desirable to include an explicit memory bandwidth 5 limitation which is preferably implemented by including a clipping function by a clipping section 740 between a pair of 1-dimensional transforms. The 1-dimensional transforms may be performed in any order or manner. After the clipping function by a clipping section 740, the data may be stored in io memory 750.
The terms and expressions which have been employed in the foregoing specification are used therein as terms of description and not of limitation, and there is no intention, in the use of such terms and expressions, of excluding is equivalents of the features shown and described or portions thereof, it being recognized that the scope of the invention is defined and limited only by the claims.
Throughout this specification and the claims which follow, unless the context requires otherwise, the word comprise, and 20 variations such as comprises and comprising, will be understood to imply the inclusion of a stated integer or step or group of integers or steps but not the exclusion of any other integer or step or group of integers or steps.
The reference in this specification to any prior publication (or information derived from it), or to any matter which is known, is not, and should not be taken as an acknowledgment or
- 15 2018233019 21 Sep 2018 admission or any form of suggestion that that prior publication (or information derived from it) or known matter forms part of the common general knowledge in the field of endeavour to which this specification relates.
Claims (1)
1. An apparatus for decoding video, the apparatus comprising one or more processors and one or more storage 5 devices storing instructions that when executed by the one or more processors cause the one or more processors to perform operations comprising:
(a) receiving quantized coefficients representative of a block of video representative of a plurality of pixels;
io (b) descaling the quantized coefficients by multiplying the quantized coefficients with numbers dependent on a coefficient index and a transform size of the block to generate descaled coefficients;
(c) applying an adjustment to the descaled coefficients to
15 generate adjusted descaled coefficients, wherein the adjustment is a variable based on the transform size;
(d) clipping the adjusted descaled coefficients to a predetermined bit depth to generate clipped coefficients;
(e) one-dimensional inverse transforming the clipped 20 coefficients in a first direction to generate first direction inverse transformed coefficients;
(f) shifting the first direction inverse transformed coefficients to generate shifted coefficients;
(g) clipping the shifted coefficients to the predetermined bit
25 depth to generate second clipped coefficients; and
- 17 2018233019 21 Sep 2018 (h) one-dimensional inverse transforming the second clipped coefficients in a second direction to determine a decoded residue, wherein the applying the adjustment is performed after the descaling, and
5 wherein the shifting is performed after the one-dimensional inverse transforming in the first direction and prior to the onedimensional inverse transforming in the second direction.
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AU2018233019A AU2018233019B2 (en) | 2011-01-18 | 2018-09-21 | Video decoder with reduced dynamic range transform with inverse transform shifting memory |
AU2020200449A AU2020200449B2 (en) | 2011-01-18 | 2020-01-22 | Video decoder with reduced dynamic range transform with inverse transform shifting memory |
AU2021203402A AU2021203402B2 (en) | 2011-01-18 | 2021-05-25 | Video decoder with reduced dynamic range transform with inverse transform shifting memory |
AU2023201244A AU2023201244A1 (en) | 2011-01-18 | 2023-03-01 | Video decoder with reduced dynamic range transform with inverse transform shifting memory |
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US13/008,658 | 2011-01-18 | ||
US13/008,658 US9807395B2 (en) | 2011-01-18 | 2011-01-18 | Video decoder with reduced dynamic range transform with inverse transform shifting memory |
AU2012207827A AU2012207827B2 (en) | 2011-01-18 | 2012-01-18 | Video decoder with reduced dynamic range transform with inverse transform shifting memory |
PCT/JP2012/051480 WO2012099269A1 (en) | 2011-01-18 | 2012-01-18 | Video decoder with reduced dynamic range transform with inverse transform shifting memory |
AU2016219700A AU2016219700B2 (en) | 2011-01-18 | 2016-08-26 | Video decoder with reduced dynamic range transform with inverse transform shifting memory |
AU2018233019A AU2018233019B2 (en) | 2011-01-18 | 2018-09-21 | Video decoder with reduced dynamic range transform with inverse transform shifting memory |
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AU2020200449A Active AU2020200449B2 (en) | 2011-01-18 | 2020-01-22 | Video decoder with reduced dynamic range transform with inverse transform shifting memory |
AU2021203402A Active AU2021203402B2 (en) | 2011-01-18 | 2021-05-25 | Video decoder with reduced dynamic range transform with inverse transform shifting memory |
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US6882685B2 (en) * | 2001-09-18 | 2005-04-19 | Microsoft Corporation | Block transform and quantization for image and video coding |
US6975773B1 (en) * | 2002-07-30 | 2005-12-13 | Qualcomm, Incorporated | Parameter selection in data compression and decompression |
US7760950B2 (en) * | 2002-09-26 | 2010-07-20 | Ntt Docomo, Inc. | Low complexity and unified transforms for video coding |
US8849884B2 (en) * | 2006-03-29 | 2014-09-30 | Qualcom Incorporate | Transform design with scaled and non-scaled interfaces |
US8385424B2 (en) * | 2006-06-26 | 2013-02-26 | Qualcomm Incorporated | Reduction of errors during computation of inverse discrete cosine transform |
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AU2016219700B2 (en) | 2018-06-28 |
AU2021203402B2 (en) | 2022-12-08 |
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AU2020200449A1 (en) | 2020-02-13 |
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