AU2012203464A1 - Circuitry for optimization of power consumption in a system employing multiple electronic components, one of which is always powered on - Google Patents

Abstract

Circuitry for conserving power in a system employing multiple electronic components of which a first electronic component operates at a first frequency and is 5 continuously powered on by a power source. The system further includes a second electronic component operating at a second frequency different than that of the first frequency of the first electric component, the second electronic component being maintained in a powered off state in which no energy whatsoever is consumed by the second electronic component until energized in response to a power enabling signal 10 generated by the first electronic component based on demand of the particular function to be performed by the second electronic component. The fist and second electronic components may be processors, wherein the frequency of the first processor is lower than that of the second processor. Is

Description

CODMAN NEURO SCIENCES SARL AUSTRALIA Pstcnts Act 1990 PATENT SPECIFICATION FOR THE INVENTION ENTITLED "CIRCUITRY FOR OPTIMIZATION OF POWER CONSUMPTION IN A SYSTEM EMPLOYING MULTIPLE ELECTRONIC COMPONENTS, ONE OF WHICH IS ALWAYS POWERED ON" This invention is described in the following statement: 1 Circuitry for Optimization of Power Consumption in a System Employing Multiple Electronic Components, One of Which Is Always Powered On 5 Cross-Reference to Related Applications This Application is a divisional of the Applicant's Australian Patent Application No. 2006202249 and the whole contents thereof are included herein by reference. 10 BACKGROUND OF THE INVNTOQN Field of the Invention The present invention is directed to power consumption optimization circuitry for a 15 system having multiple electronic components of which at least one is always powered on and at least one is normally powered off until otherwise powered on to perform a specific task or function. In particular, the invention is directed to a system including multiple processors of which at least one processor remains continuously powered on at all times, whereas at least one other processor is only powered on in response to a request to perform a specific task or 20 function by that device. DescrIptIon of Related Art When power consumption is not a design consideration or factor, a single processor may be used to perform different tasks of varying complexity, As a general rule, the more 25 complex the task or function to be performed by the processor, the higher the clock speed needed. Therefore, when utilizing a single processor the clock frequency selected is the highest frequency necessary for performing the most complex task. This design configuration is advantageous in that it requires less components and thus a smaller footprint, but disadvantageously requires that the processor operate continuously at the highest clock speed 30 for performing the most complex task. The most complex operation or task may only be performed occasionally. Therefore, to expend the power necessary to continuously operate 2 the processor at the highest clock speed required is extremely inefficient from an energy consumption perspective. To optimize power consumption, heretofore systems have been designed to employ multiple processors operating at different frequencies. U.S. Patent No. 4,407,288 discloses an 5 implantable heart stimulator controlled by a plurality of processors providing multiple modes of operation for performing various electrical heart stimulation techniques. Each processor is selected by virtue of its design for performing operations of a given type. in one embodiment, two processors arc used, one selected for the performance of long term operations, simple in type that consume low power; the other processor is selected for the performance of more 10 complex operations that are shorter in term and consumer more power. To further reduce power consumption, one or more components may be placed in a sleep mode (low power mode) when not in use. U.S. Patent No. 5,464,435 discloses a multi function implantable medical device having a plurality of microprocessor used to perform functionality of varying complexity. Specifically, in one example the functions to be 15 performed continuously are allocated to a dedicated master processor, wbile advanced fmctions that may be only periodically required, are allocated among one or more slave processors. With this master/slave arrangement of the parallel processors power consumption is reduced by causing the slave processors to enter a standby or "sleep" mode when not called upon to perform a task thereby consuming a reduced amount of energy than that while in 20 active mode. The master processor upon encountering a task to be allocated or performed by a slave, activates and directs the slave processor to begin executing the desired code. Placing the slave processor in sleep mode, as described in the patented device, still consumes energy, albeit less than that required when the processor is fully powered up (in active mode). In the context of an implantable medical device in a closed system relying on the limited energy 25 drawn from an internal power source, even a reduced amount of energy, expended by the implant while in sleep mode disadvantageously reduces the lifespan of the power source. It is therefore desirable to optimize power consumption in a device employing multiple electronic components wherein at least one electronic component remains continuously powered on while one or more other electronic components are powered down 30 or off until otherwise energized (powered on) when required to perform a specifle task, finction or operation. In contrast to the patented sleep mode operation, when in a powered 3 off state the electronic components consume no energy whatsoever until activated to perform a specific task, function or operation. Summa of he Inention 5 One aspect of the present invention is to develop a system including multiple electronic components at lean one of which remains continuously powered on while one or more other electronic components arc only powered on in response to performing a specific operation, fumtion or task. Another object of the present invention is to design a device including multiple 10 processors or controllers one of which remains continuously powered on while at least one other is normally powered offend energized only in response to performing a specific operation. The present invention is directed to circuitry for conserving power in a system employing multiple electronic components of which a first electronic component operates at a 15 first frequency pnd is continuously powered on by a power source. The system further includes a second electronic component operating at a second frequency different than that of the first frequency of the first electric component, the second electronic component being maintained in a powered off state in which no energy whatsoever is conmed by the second electronic component until energized in response to a power enabling signal generated by the 20 first electronic component based on demand ofth particular function to be performed by the second electonic component. The first and second electronic components may be processors, wherein the frequency ofthe frst prcessor is lower than that of the second processor. A particular application of the present invention circuitry for optimization of power consumption is employed in a closed system including an external control device in 25 communication with and separated by a boundary from an internal device. The internal device has a first processor operating at a first frequency and continuously powered by an internal power source. A second processor operating at a second frequency higher than that of the first frequency of the first processor is maintained in a powered off state in which no energy is consumed until powered on in response to a power enabling signal generated by the 30 first processor based on demand to perform a particular task by the second processor. Power supplied to the second processor is adjusted or regulated by a voltage regulator disposed between the internal power source and second processor. A switch electrically connects the 4 internal power source to the regulator. The switch remains in an open state until closed in response to the power enable signal generated by the first processor. Furthermore, the internal device includes a voltage level translator electrically coupled as an interface between the first and second processors operating at different supply voltage levels to translate a logic 5 signal from a first power supply voltage of the first processor to a second power supply voltage of the second processor. Another aspect of the invention relates to a method for optimizing power consumption in a system as described in the preceding paragrphs. Initially a power enable signal is generated by the first electronic component. The second electronic component is energized in 10 response to receiving the power enable signal generated by the first electronic component. While the second electronic component is in an energized state, a logic data signal converted by a voltage level translator electrically coupled as an interface between the first and second electronic components operating at differnt supply voltage levels from a first power supply voltage of the first electronic component to a second power supply voltage of the second 15 electronic component prior to being transmitted to the second electronic component. On the other hand, while the second electronic component is maintained in a powered off state, the voltage level translator prohibits transmission of the data signal to the second electronic component. 20 Brie Decription of the 2Din The foregoing and other features of the present invention will be more readily apparent from the following detailed description and drawings of illustrative embodiments of the invention wherein like reference ninnbers refer to similar elements throughout the several views and in which, 25 Figure 1 is an exemplary schematic high level block diagram of a multi-processor system in accordance with the present invention including a first processor that is always powered on and a second processor that is normally powered off and energized only in response to a request to perform a specific operation; and Figure 2 is a block diagram of an exemplary implementation of the present invention 30 for use in an implantable medical device. 5 DetagedDescrDtin of the Invention Figure 1 is an exemplary high level block diagram of a multi-processor system 100 including two processors, controllers or miemcontrollen, i.e., a first processor 105 and a second processor 110. Processors 105, 110 preferably operate at different clock speeds or 5 frequencies depending on the task or finctionality perforned by each. The first processor 105 preferably operates at as low a clock speed as possible, for example, approximately 32 KHz, and remains directly powered on at all times by power source or supply (c.g, battery) 115. Due to its low clock speed and continuously powered on status the flint processor 105 may, for example, be used to provide a real time clock signal for the system that continuously 10 counts down 24 hour periods. The second processor 110 performs more complex tasks or functions and operates at a clock frequency higher than that of the first processor 105. Since the tasks or functions performed by the second processor 110 are more complex than those of the first processor 105 the second processor requires a substantially higher clock fequency thereby consuming a greatr amount of energy than that of the first processor 105. Processor 15 110 performs specific complex tasks or functionality that need not be operational at all times. Accordingly, the second processor 110 is normally maintained in a powered off state (expending zero energy) and is only powered on based on demand of a particular operation, task or function for which it is to perform. In the exemplary configuration shown in Figure 1, the output data signal from the 20 second processor 110 Is transmitted for further processing by peripheral circuitry denoted generically by block 135. Although presented as a single block, peripheral circuiry may be more than one component or device. Peripheral circuitry or block 135 may represent one or more circuits or components that perform operations or processing on the data prior to being input to and/or after being output from the second processor 110. By way of example, 25 peripheral circuitry 135 may Include signal conditioning circuitry. Regulated power provided to the second processor 110 is supplied by a regulator 130. In order to conserve energy regulator 130, second processor 110, and peripheral block 135 are normally maintained in a powered off or down state and powered on based on demand in rapons to a power enable signal from the first processor 105. The power enable signal may be triggered by the first 30 processor 105 after acknowledging a particular operation, task or function to be performed by one or more of the powered down components (e.g., regulator 130, second processor 110 and peripheral block 135). Specifically, in response to a power enable signal generated by the 6 first processor 105, a switch 125 is closed thereby supplying power from the power source or supply 115 to the regulator 130 whicb, in turn, energizes the second processor 110 and peripheral block 135. Due to their different speeds processors 105, 110 most likely operate in different 5 voltage domains. A voltage level translator 120 electrically connected as an interface permits communication between the first and second processors operating at different voltage supply levels by translating or converting a logic signal from a first power supply voltage to a second power supply voltage. In addition, level trnslator 120 toggles or switches the supply of power and data to the second processor 110 completely on/off corresponding to a powered 10 on/off stat, respectively. Specifically, level translator 120 is connected to both processor 105, 110 and determines the appropriate power level for each either directly from the power source 115 or the regulated output from the regulator 130. When the high speed processor secondd processor) 110 is powered off, the level translator 120 is powered only on the low speed processor side, In such a case, the level translator 120 prohibits the toggle of a signal 15 incoming to the low speed processor (first processor) 105 from toggling of a translated signal on the high speed processor side that otherwise may damage the high speed processor 110 In the case where power is provided to the high speed processor 110, both sides of the level translator 120 are energized or powered on thereby enabling translation or conversion of signals between the two voltage donains. Since both processors are energized, when an 20 incoming signal from the low speed processor 105 toggles, a corresponding translated signal also toggles on the high speed processor side of the level translator 120, and vice versa. In operation, the first processor 105 is continuously and directly powered by the power source 115 (e.g, a battery). The regulator 130, second processor 110 and peripheral device 135 are nonnally cut off from the power source 115 via open switch 125. When a task or 25 fumction to be performed by the second processor 110 is elicited in response to a particular demand or request, the first processor 105 generates and transmits a power unable signal to close switch 12$ thereby energizing regulator 130. In turn, regulator 130 produces a regulated voltage output that supplies power to the second processor 110 and peripheral device 135. Once power is received by the second processor 110, the level translator 120 30 permits data to pas between the two processors 105, 110. Accordingly, this general design Configuration advantageOusly allows continuous operation of one processor while another intermittenty operational processor is normally maintained in a powered off state consuming no energy whatsoever. The second processor 110 is powered on only as needed in response to an enabling'signal generated by the first processor 105 based on demand for a particular operation, ibncdon or task to be performed by the second processor. Figure 2 shows a specific exemplary application of the present inventive power 5 consumption optimization circuitry for use in a closed system such as an medical implant application system. The closed system includes an internal device 200 (e.g, an inplantable medical device such as a drug infusion pump, stimulator, or sensor) in telemetric communication across a boundary (e.g., skin) with an external device 202 such as a controller, processor or personal digital assistant (PDA). During communication an RFp communication 10 signal is sent from the external device to the implantable medical device, In a preferred embodiment the RF communication signal includes a data stream or signal and an RF energy signal. The RF energy signal when received by the implantable medical device induces a voltage therein. In the preferred embodiment shown in Figure 2, the first processor 205 operates at a 15 relatively low speed (e.g., 32 KHz) and is powered on continuously and directly by energy supplied by an internal power source (e.g., battery) 215. First processor 205 is preferably used to continuously operate a real time clock that continuously counts down a 24 hour time period. A voltage level translator 220 is electrically connected to interface between the first processor 205 and second processor 210 operating at different voltage domains as well as to 20 toggle on/off data being transmitted to the second processor 210. Accordingly, in the toggled off state (when no power is supplied to the second processor 210), the level translator 220 will cut off or prohibit the supply of data to the second processor 210. In operation, an incoming RF modulated signal froin the external device 202 is received at an antenna or coil 203 of the implantable medical device 200 and output from a 25 matching network 240. Demodulator 245 receives as Input the RF modulated signal from the matching network 240 and outputs a demodulated data signal that is received by the second processor 210 and a signal conditioning circuit 235'. Information collected by sensor 235" is processed by a signal conditioning circuit 235' prior to being received as input to the high speed processor 210. In response to the RF communication signal from the external device 30 202, the implantable medical device 200 transmits a responsive communication signal generated by the processor 210 and modulated by block 250 prior to being passed through matching network 240. The modulated responsive communication signal is then transmitted 8 via wireless radio communication from the implantable medical device 200 back to the external device 202. Regulator 230, modulator 250, demodulator 245, high speed processor 210, sensor 235", and signal conditioning circuit 235' need not be operational at all times and thus remain 5 powered down or off until receiving a power enable signal generated by the first or low speed processor 205. In the exemplary embodiment shown In Figure 2, the power enable signal is generted by the first processor 205 in response to at least one of the following conditions: (i) the expiration of a predetermined period of time for initiating automatic self-testing sequencing or (ii) detecting the presence of an RF communication signal (i.e., during 10 communication fom the external device). In response to either of these two conditions, the first processor 205 generates a power enable signal to close switch 225 thereby energizing regulator 230 with power supplied from the power source 215. Regulator 230 receives an input voltage (e.g., approximately 2.8V supplied from the power source 215) and produces a regulated output voltage (e.g., approximately 18V) which, in turn, energizes or powers 15 modulator 250, demodulator 245, high speed processor 210, sensor 235", and signal conditioning circuit 235'. In the absence of RF communication from the external device 202 to the implantable medical device 200, regulator 230, demodulator 245, modulator 250, high speed processor 210, sensor 235" and signal conditioning circuit 235', are nonally maintained in a powered 20 off state. While the second processor is powered down or off thereby consuming no energy whatsoever, level translator 220 prohibits the passage of data from the first processor to the second processor. It is advantageous to automatically and periodically perform self-testing on one or more components of the implantable medical device to ensure their proper operation. Accordirigly, at the expiration of a predetermined period of time as counted down by the real 25 time clock, the first processor 205 initiates a power on enable signal that closes switch 225 thereby energizing the previously powered down components (i.e., regulator 230, demodulator 245, modulator 250, high speed processor 210, sensor 235" and signal conditioning circuit 235') In preparation for self-testing operations. After completion of the self-testing sequencing regulator 230, demodulator 245, modulator 250, high speed processor 30 210, sensor 235" and signal conditioning circuit 235' are once again powered down. Aside from the periodic powering on of the previously powered down components to perform automatic self testing, another condition for enabling the power on signal is in the 9 presence of RF energy, During communication, extemal device 202 transmits an RF communication signal that is received by antenna 203 and output from matching network 240. As previously noted, the RF communication signal preferably includes both a data stream signal and an RF energy signal. Prior to receipt of the RF communication signal by the 5 implmntable medical device 200 (i.e., in the absence of an RF energy signal) the regulator 230, demodulator 245, modulator 250, high speed processor 210, sensor 235" and signal conditioning circuit 235', am normally maintained powered down (except for powering on in Msponse to the countdown of the predetermined period of time for automatic self-testing). During communication, the presence of the RF energy signal enables the power on signal that 10 closes switch 225. Approximately 2.SV of power from the power source 215 is supplied as input to regulator 230 whose output regulated voltage of approximately 1.8V energizes regulator 230, demodulator 245, modulator 250, high speed processor 210, sensor 235" and signal conditioning circuit 235'. With the components powered on the RF modulated signal output from the matching IS network 240 is demodulated by demodulator 245 prior to being received and processed by the high speed processor 210. In response to the received RP communication signal from the extenal device, the high speed processor 210 receives information output by sensor 235" and processed by the signal conditioning circuit 235' to produce a responsive communication signal. Block 250 modulates the responsive communication signal prior to being passed 20 through the matching network and transmitted wirelessly to the external device 202. The present invention has been illustrated and described with respect to a system erploying multiple processors at least one of which is always powered on while one or more other processors main powered down only to be energized in response to a request to perform a particular operation, task or function. It is contemplated and within the intended 25 scope of the present invention to apply this same concept to powering on/off of any electronic components. Energy consumption is optimized by maintaining one or more electronic components that arc intermittently operational and require a relatively high power level to renaiin n a normally powered off state until enabled to perform a particular task or function. The power enable signal may be triggered or generated, as desired, by a first electronic 30 component that is continuously energized based on a particular application and design configuration in response to one or more conditions that when satisfied energize an otherwise normally powered down second electronic component. 10 Thus, while there have been shown, described, and pointed out fundamental novel features of the invention as applied to a preferred embodiment thereof, it will be understood that various omissions, substitutions, and changes in the form and details of the devices illustrated, and in their opemtion, may be made by those skilled in the art without departing 5 from the spirit and scope of the invention, For example, it is expressly Intended that .ll combinations of those elements and/or steps that perform substantially the same function, in substantially the same way, to achieve the same results be within the scope of the invention. Substitutions of elements from one described embodiment to another are also fully intended and contemplated. It is also to be understood that the drawings are not necessarily drawn to 10 scale, but that they are merely conceptual in nature. It is the intention, therefore, to be limited only as indicated by the scope of the claims appended hereto, Every issued patent, pending patent application, publication, journal article, book or any other reference cited herein is each incorporated by reference in their entirety. Throughout this specification and the claims which follow, unless the context requires otherwise, the word "comprise", and variations such as "comprises" and "comprising", will be understood to imply the inclusion of a stated integer or step or group of integers or steps but not the exclusion of any other integer or step or group of integers or steps. The reference to any prior art in this specification is not, and should not be taken as, an acknowledgment or any form or suggestion that the prior art forms part of the common general knowledge in Australia, 11

Claims (23)

1. Chuitry for conserving power in a system having multiple electronic components, 5 comprising: a power source; a first electronic component operating at a first frequency and continuously powered on by the power source; and a second electronic component operating at a second frequency different than that 10 of the first frequency of the first electric component, the second electronic component being maintained in a powered off state in which no energy is consumed by the second electronic component until energized in response to a power enabling signal generated by the first electronic component based on demand of the particular function to be performed by the second electronic component. 15

2. The circuitry in accordance with claim 1, wherein the system further comprises a regulator for adjusting a power supply voltage to the second electronic component, the regulator and second electronic component being maintained in a powered down state until powered on in response to the power enabling signal generated by the first 20 electronic component based on demand of the particular function to be perfonned by the second electronic component.

3. The circuitry in accordance with claim 2, further comprising a switch electrically coupled between the power source and the regulator, the switch being maintained in an 25 open state until toggled to a closed state in response to the power enabling signal received from the first electronic component.

4. The circuitry in accordance with claim 1, fAuther comprising a voltage level translator electrically coupled as an interface between the first and second processors operating at 30 different voltage supply levels; when the second electronic component is enered, the voltage level translator converting a logic data signal received as input to the first 12 electronic component from a first power supply voltage to a second power supply voltage prior to transmission to the second electronic component; and the voltage level translator prohibiting transmission of the data signal when the second electronic component is in a powered off state. 5

5. The circuitry in accordance with claim 1, wherein the system is a closed system comprising an internal device separated from an external device by a boundary, and wherein the first processor, second processor and power source re disposed within the internal device. 10

6. The circuitry in accordance with claim 1, wberein the first and second electronic components are first and second processors operating at different frequencies.

7. The circuitry in accordance with claim 6, wherein the first frequency of the first 15 processor is lower than that of the second frequency of the second processor,

8. The circuitry in accordance with claim 1, wherein the first processor generates a real time clock signal to continuously count down a 24 hour time period. 20

9. A closed system including: an external control device; an intemal device separated from the external device by a boundary and adapted to receive communications from the external control device, the internal device comprising: 25 an internal power source; a first processor operating at a first frequency and continuously powered by the internal power source; a second processor operating at a second frequency higher than that of the first frequency of the first processor, the second processor being maintained in a powered 30 off state in which no energy is consumed until powered on in response to a power - 13 enabling signal generated by the first processor based on demand to perform a particular task by the second processor; a regulator electrically connected to adjust power supplied to the second processor; 5 a switch electrically connected between the internal power source and the regulator, the switch remaining in an open state until closed in response to the power enable signal generated by the first processor; and a voltage level translator electrically coupled as an interface between the first and second proessors operating at different supply voltage levels to translate a logic 10 signal from a first power supply voltage of the first processor to a second power supply voltage of the second processor.

10. The closed system in accordance with claim 9, wherein the regulator and second processor are maintained in a powered down state until powered on in response to the 15 power enabling signal generated by the first processor based on demand of the particular function to be performed by the second processor.

11. The closed system In accordance with claim 9, wherein the internal device further comprises a demodulator electrically coupled to the second processor, the demodulator 20 being maintained in a powered down state until powered on in response to the power enabling signal generated by the first processor based on demand of the particular function to be performed by the second processor.

12. The closed system in accordance with claim 9, wherein the first frequency is lower 25 than that of the second frequency.

13. The closed system in accordance with claim 12, wherein the first processor is a real time clock for continuously counting down a 24 hour time period. 30

14. A method for optimizing power consumption in a system including a first electronic component operating at a first frequency and being continuously powered on by a power 14 source, and a second electronic component electrically coupled to the first electonic component by a voltage level translator and operating at a second frequency different than that of the first frequency of the first electric component, the second electronic component being normally maintained in a powered off state in which no energy is 5 consumed by the second electronic component, comprising the steps of: generating a power enable signal by the first electronic component; energizing the second electronic component in response to receiving the power enable signal generated by the first electronic component; and when the second electronic component is in an energized state, transmiting a 10 logic data signal converted from a first power supply voltage of the first electronic component to a second power supply voltage of the second electronic component using a voltage level translator electrically coupled as an interface between the first and second electronic components operating at different supply voltage levels; while prohibiting transmission of the data signal to the second electronic component while in a powered off 15 state.

15. The method in accordance with claim 14, wherein the first awd second electronic components are first and second processors. 20

16. The method in accordance with claim IS, wherein the first frequency is lower than the second frequency.

17, The method in accordance with claim 15, wherein the first processor is a real time clock continuously counting down a24 hour time period. 25

18. The method in accordance with claim 15, wherein the system is a closed system including an external device separated by a boundary from and in communication with an internal device; the power source, the first processor and the second processor being disposed within the internal device. 30 15

19. The method in accordance with claim 18, wherein the power enable signal is generated by the first processor in response to at least one of (i) expiration of a predetermined time period for initiating automatic self-testing sequencing of the internal device; or (ii) receiving at the internal device an RF communication signal tansmitted 5 from the external device,

20. The method in accordance with claim 14, wherein the energizing step comprise: closing a switch electrically coupled between the power source and a voltage regulator, the switch being normally maintained in an open state and powering on the 10 voltage regulator and second electronic component in response to receiving the power enable signal from the first electronic component.

21. Circuitry for conserving power in a system having multiple electronic components, substantially as hereinbefore described with reference to the accompanying drawings.

22. A closed system substantially as hereinbefore described with reference to the accompanying drawings.

23. A method for optimizing power consumption, substantially as hereinbefore described with reference to the accompanying drawings. 16