AU2003232331A1 - Data processing system having external and internal instruction sets - Google Patents

Data processing system having external and internal instruction sets

Info

Publication number
AU2003232331A1
AU2003232331A1 AU2003232331A AU2003232331A AU2003232331A1 AU 2003232331 A1 AU2003232331 A1 AU 2003232331A1 AU 2003232331 A AU2003232331 A AU 2003232331A AU 2003232331 A AU2003232331 A AU 2003232331A AU 2003232331 A1 AU2003232331 A1 AU 2003232331A1
Authority
AU
Australia
Prior art keywords
external
data processing
processing system
instruction sets
internal instruction
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
AU2003232331A
Inventor
Krisztian Flautner
Andrew Christopher Rose
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
ARM Ltd
Original Assignee
ARM Ltd
Advanced Risc Machines Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by ARM Ltd, Advanced Risc Machines Ltd filed Critical ARM Ltd
Publication of AU2003232331A1 publication Critical patent/AU2003232331A1/en
Abandoned legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/3017—Runtime instruction translation, e.g. macros
    • G06F9/30174—Runtime instruction translation, e.g. macros for non-native instruction set, e.g. Javabyte, legacy code
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3802—Instruction prefetching
    • G06F9/3808—Instruction prefetching for instruction reuse, e.g. trace cache, branch target cache
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3842—Speculative instruction execution
    • G06F9/3844—Speculative instruction execution using dynamic branch prediction, e.g. using branch history tables
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3854—Instruction completion, e.g. retiring, committing or graduating
    • G06F9/3858—Result writeback, i.e. updating the architectural state or memory
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3861—Recovery, e.g. branch miss-prediction, exception handling

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Advance Control (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Debugging And Monitoring (AREA)
  • Executing Machine-Instructions (AREA)
AU2003232331A 2002-09-20 2003-05-15 Data processing system having external and internal instruction sets Abandoned AU2003232331A1 (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
GB0221916A GB2393274B (en) 2002-09-20 2002-09-20 Data processing system having an external instruction set and an internal instruction set
GB0221916.0 2002-09-20
PCT/GB2003/002092 WO2004027601A1 (en) 2002-09-20 2003-05-15 Data processing system having external and internal instruction sets

Publications (1)

Publication Number Publication Date
AU2003232331A1 true AU2003232331A1 (en) 2004-04-08

Family

ID=9944499

Family Applications (1)

Application Number Title Priority Date Filing Date
AU2003232331A Abandoned AU2003232331A1 (en) 2002-09-20 2003-05-15 Data processing system having external and internal instruction sets

Country Status (13)

Country Link
US (1) US7406585B2 (en)
EP (1) EP1540464B1 (en)
JP (1) JP3820261B2 (en)
KR (1) KR101086801B1 (en)
CN (1) CN1682181B (en)
AU (1) AU2003232331A1 (en)
DE (1) DE60308201T2 (en)
GB (1) GB2393274B (en)
IL (1) IL165987A (en)
MY (1) MY127780A (en)
RU (1) RU2005107713A (en)
TW (1) TWI263169B (en)
WO (1) WO2004027601A1 (en)

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US7636856B2 (en) * 2004-12-06 2009-12-22 Microsoft Corporation Proactive computer malware protection through dynamic translation
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US7769983B2 (en) * 2005-05-18 2010-08-03 Qualcomm Incorporated Caching instructions for a multiple-state processor
US7711927B2 (en) * 2007-03-14 2010-05-04 Qualcomm Incorporated System, method and software to preload instructions from an instruction set other than one currently executing
US9672019B2 (en) 2008-11-24 2017-06-06 Intel Corporation Systems, apparatuses, and methods for a hardware and software system to automatically decompose a program to multiple parallel threads
US10621092B2 (en) 2008-11-24 2020-04-14 Intel Corporation Merging level cache and data cache units having indicator bits related to speculative execution
US8533859B2 (en) * 2009-04-13 2013-09-10 Aventyn, Inc. System and method for software protection and secure software distribution
US8775153B2 (en) 2009-12-23 2014-07-08 Intel Corporation Transitioning from source instruction set architecture (ISA) code to translated code in a partial emulation environment
US9201652B2 (en) 2011-05-03 2015-12-01 Qualcomm Incorporated Methods and apparatus for storage and translation of entropy encoded software embedded within a memory hierarchy
US9092236B1 (en) * 2011-06-05 2015-07-28 Yong-Kyu Jung Adaptive instruction prefetching and fetching memory system apparatus and method for microprocessor system
US10120692B2 (en) 2011-07-28 2018-11-06 Qualcomm Incorporated Methods and apparatus for storage and translation of an entropy encoded instruction sequence to executable form
WO2013048468A1 (en) 2011-09-30 2013-04-04 Intel Corporation Instruction and logic to perform dynamic binary translation
WO2013104107A1 (en) * 2012-01-10 2013-07-18 Intel Corporation Isa bridging with callback
US10146545B2 (en) 2012-03-13 2018-12-04 Nvidia Corporation Translation address cache for a microprocessor
US9880846B2 (en) 2012-04-11 2018-01-30 Nvidia Corporation Improving hit rate of code translation redirection table with replacement strategy based on usage history table of evicted entries
CN103377033B (en) * 2012-04-12 2016-01-13 无锡江南计算技术研究所 Arithmetic core and instruction management method thereof
US10241810B2 (en) 2012-05-18 2019-03-26 Nvidia Corporation Instruction-optimizing processor with branch-count table in hardware
US8856769B2 (en) * 2012-10-23 2014-10-07 Yong-Kyu Jung Adaptive instruction prefetching and fetching memory system apparatus and method for microprocessor system
US20140189310A1 (en) 2012-12-27 2014-07-03 Nvidia Corporation Fault detection in instruction translations
US10108424B2 (en) 2013-03-14 2018-10-23 Nvidia Corporation Profiling code portions to generate translations
US9891936B2 (en) 2013-09-27 2018-02-13 Intel Corporation Method and apparatus for page-level monitoring
CN104679480A (en) * 2013-11-27 2015-06-03 上海芯豪微电子有限公司 Instruction set transition system and method
CN104679481B (en) * 2013-11-27 2020-04-28 上海芯豪微电子有限公司 Instruction set conversion system and method
CN104915180B (en) * 2014-03-10 2017-12-22 华为技术有限公司 A kind of method and apparatus of data manipulation
US10346168B2 (en) 2015-06-26 2019-07-09 Microsoft Technology Licensing, Llc Decoupled processor instruction window and operand buffer
US20160378488A1 (en) * 2015-06-26 2016-12-29 Microsoft Technology Licensing, Llc Access to target address
US11755484B2 (en) 2015-06-26 2023-09-12 Microsoft Technology Licensing, Llc Instruction block allocation
US10120688B2 (en) * 2016-11-15 2018-11-06 Andes Technology Corporation Data processing system and method for executing block call and block return instructions
CN108988931B (en) * 2018-06-26 2020-10-09 上海卫星工程研究所 Satellite measurement and control coprocessor
US10958670B2 (en) 2018-11-06 2021-03-23 Bank Of America Corporation Processing system for providing console access to a cyber range virtual environment
US10924481B2 (en) 2018-11-06 2021-02-16 Bank Of America Corporation Processing system for providing console access to a cyber range virtual environment
US10901878B2 (en) 2018-12-19 2021-01-26 International Business Machines Corporation Reduction of pseudo-random test case generation overhead
US10972789B2 (en) * 2019-06-03 2021-04-06 At&T Intellectual Property I, L.P. Methods, systems, and devices for providing service differentiation for different types of frames for video content
US11698789B2 (en) 2020-10-12 2023-07-11 Microsoft Technology Licensing, Llc Restoring speculative history used for making speculative predictions for instructions processed in a processor employing control independence techniques

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Also Published As

Publication number Publication date
US20040059897A1 (en) 2004-03-25
GB2393274B (en) 2006-03-15
DE60308201T2 (en) 2007-08-23
GB2393274A (en) 2004-03-24
EP1540464A1 (en) 2005-06-15
KR101086801B1 (en) 2011-11-25
US7406585B2 (en) 2008-07-29
TWI263169B (en) 2006-10-01
KR20050084558A (en) 2005-08-26
CN1682181A (en) 2005-10-12
IL165987A0 (en) 2006-01-15
CN1682181B (en) 2010-05-26
EP1540464B1 (en) 2006-09-06
RU2005107713A (en) 2005-11-20
TW200410143A (en) 2004-06-16
JP2005539321A (en) 2005-12-22
IL165987A (en) 2010-05-31
GB0221916D0 (en) 2002-10-30
WO2004027601A1 (en) 2004-04-01
DE60308201D1 (en) 2006-10-19
MY127780A (en) 2006-12-29
JP3820261B2 (en) 2006-09-13

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Legal Events

Date Code Title Description
MK6 Application lapsed section 142(2)(f)/reg. 8.3(3) - pct applic. not entering national phase