AU2001289737A1 - Integrated circuit - Google Patents

Integrated circuit

Info

Publication number
AU2001289737A1
AU2001289737A1 AU2001289737A AU8973701A AU2001289737A1 AU 2001289737 A1 AU2001289737 A1 AU 2001289737A1 AU 2001289737 A AU2001289737 A AU 2001289737A AU 8973701 A AU8973701 A AU 8973701A AU 2001289737 A1 AU2001289737 A1 AU 2001289737A1
Authority
AU
Australia
Prior art keywords
integrated circuit
integrated
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
AU2001289737A
Inventor
Volker Baumgarte
Gerd Ehlers
Armin Nuckel
Martin Vorbach
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Pact Informationstechnologie GmbH
Original Assignee
Pact Informationstechnologie GmbH
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from DE10036627A external-priority patent/DE10036627A1/en
Priority claimed from PCT/EP2001/006703 external-priority patent/WO2002013000A2/en
Application filed by Pact Informationstechnologie GmbH filed Critical Pact Informationstechnologie GmbH
Publication of AU2001289737A1 publication Critical patent/AU2001289737A1/en
Priority claimed from DE10129237A external-priority patent/DE10129237A1/en
Abandoned legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
    • G06F15/7867—Architectures of general purpose stored program computers comprising a single central processing unit with reconfigurable architecture
AU2001289737A 2000-07-24 2001-07-24 Integrated circuit Abandoned AU2001289737A1 (en)

Applications Claiming Priority (17)

Application Number Priority Date Filing Date Title
DE10036221.4 2000-07-24
DE10036221 2000-07-24
DE10036627A DE10036627A1 (en) 2000-07-24 2000-07-27 Integrated cell matrix circuit has at least 2 different types of cells with interconnection terminals positioned to allow mixing of different cell types within matrix circuit
DE10036627.9 2000-07-27
EPPCT/EP00/10516 2000-10-09
EPPCT/EP00/10516 2000-10-09
EP01102674 2001-02-07
EP01102674.7 2001-02-07
DE10110530.4 2001-03-05
DE10110530 2001-03-05
DE10111014.6 2001-03-07
DE10111014 2001-03-07
EPPCT/EP01/06703 2001-06-13
PCT/EP2001/006703 WO2002013000A2 (en) 2000-06-13 2001-06-13 Pipeline configuration unit protocols and communication
DE10129237.6 2001-06-20
PCT/EP2001/008534 WO2002008964A2 (en) 2000-07-24 2001-07-24 Integrated circuit
DE10129237A DE10129237A1 (en) 2000-10-09 2002-06-20 Integrated cell matrix circuit has at least 2 different types of cells with interconnection terminals positioned to allow mixing of different cell types within matrix circuit

Publications (1)

Publication Number Publication Date
AU2001289737A1 true AU2001289737A1 (en) 2002-02-05

Family

ID=56290174

Family Applications (1)

Application Number Title Priority Date Filing Date
AU2001289737A Abandoned AU2001289737A1 (en) 2000-07-24 2001-07-24 Integrated circuit

Country Status (3)

Country Link
EP (1) EP1377919A2 (en)
AU (1) AU2001289737A1 (en)
WO (1) WO2002008964A2 (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8127061B2 (en) 2002-02-18 2012-02-28 Martin Vorbach Bus systems and reconfiguration methods
FR2838208B1 (en) * 2002-04-03 2005-03-11 Centre Nat Rech Scient LOGICAL CALCULATION ARCHITECTURE COMPRISING MULTIPLE CONFIGURATION MODES

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5361373A (en) * 1992-12-11 1994-11-01 Gilson Kent L Integrated circuit computing device comprising a dynamically configurable gate array having a microprocessor and reconfigurable instruction execution means and method therefor
EP0688659A3 (en) * 1994-06-23 1997-10-08 Illig Maschinenbau Adolf Forming and punching tool for producing thermoplastic containers
US5636368A (en) * 1994-12-23 1997-06-03 Xilinx, Inc. Method for programming complex PLD having more than one function block type
GB9611994D0 (en) * 1996-06-07 1996-08-07 Systolix Ltd A field programmable processor
DE19654595A1 (en) * 1996-12-20 1998-07-02 Pact Inf Tech Gmbh I0 and memory bus system for DFPs as well as building blocks with two- or multi-dimensional programmable cell structures
DE19654846A1 (en) * 1996-12-27 1998-07-09 Pact Inf Tech Gmbh Process for the independent dynamic reloading of data flow processors (DFPs) as well as modules with two- or multi-dimensional programmable cell structures (FPGAs, DPGAs, etc.)
EP0858168A1 (en) * 1997-01-29 1998-08-12 Hewlett-Packard Company Field programmable processor array
US6094726A (en) * 1998-02-05 2000-07-25 George S. Sheng Digital signal processor using a reconfigurable array of macrocells

Also Published As

Publication number Publication date
EP1377919A2 (en) 2004-01-07
WO2002008964A3 (en) 2003-10-23
WO2002008964A2 (en) 2002-01-31

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