AU2001288209A1 - A method and system for performing permutations using permutation instructions based on modified omega and flip stages - Google Patents
A method and system for performing permutations using permutation instructions based on modified omega and flip stagesInfo
- Publication number
- AU2001288209A1 AU2001288209A1 AU2001288209A AU8820901A AU2001288209A1 AU 2001288209 A1 AU2001288209 A1 AU 2001288209A1 AU 2001288209 A AU2001288209 A AU 2001288209A AU 8820901 A AU8820901 A AU 8820901A AU 2001288209 A1 AU2001288209 A1 AU 2001288209A1
- Authority
- AU
- Australia
- Prior art keywords
- instructions based
- permutation instructions
- modified omega
- performing permutations
- flip stages
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/76—Arrangements for rearranging, permuting or selecting data according to predetermined rules, independently of the content of the data
- G06F7/762—Arrangements for rearranging, permuting or selecting data according to predetermined rules, independently of the content of the data having at least two separately controlled rearrangement levels, e.g. multistage interconnection networks
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30003—Arrangements for executing specific machine instructions
- G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
- G06F9/30018—Bit or string instructions
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30003—Arrangements for executing specific machine instructions
- G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
- G06F9/30025—Format conversion instructions, e.g. Floating-Point to Integer, decimal conversion
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30003—Arrangements for executing specific machine instructions
- G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
- G06F9/30032—Movement instructions, e.g. MOVE, SHIFT, ROTATE, SHUFFLE
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30003—Arrangements for executing specific machine instructions
- G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
- G06F9/30036—Instructions to perform operations on packed data, e.g. vector, tile or matrix operations
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L63/00—Network architectures or network communication protocols for network security
- H04L63/04—Network architectures or network communication protocols for network security for providing a confidential data exchange among entities communicating through data packet networks
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L63/00—Network architectures or network communication protocols for network security
- H04L63/04—Network architectures or network communication protocols for network security for providing a confidential data exchange among entities communicating through data packet networks
- H04L63/0428—Network architectures or network communication protocols for network security for providing a confidential data exchange among entities communicating through data packet networks wherein the data content is protected, e.g. by encrypting or encapsulating the payload
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols
- H04L9/06—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols the encryption apparatus using shift registers or memories for block-wise or stream coding, e.g. DES systems or RC4; Hash functions; Pseudorandom sequence generators
- H04L9/0618—Block ciphers, i.e. encrypting groups of characters of a plain text message using fixed encryption transformation
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L2209/00—Additional information or applications relating to cryptographic mechanisms or cryptographic arrangements for secret or secure communication H04L9/00
- H04L2209/12—Details relating to cryptographic hardware or logic circuitry
- H04L2209/122—Hardware reduction or efficient architectures
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L63/00—Network architectures or network communication protocols for network security
- H04L63/04—Network architectures or network communication protocols for network security for providing a confidential data exchange among entities communicating through data packet networks
- H04L63/0428—Network architectures or network communication protocols for network security for providing a confidential data exchange among entities communicating through data packet networks wherein the data content is protected, e.g. by encrypting or encapsulating the payload
- H04L63/0435—Network architectures or network communication protocols for network security for providing a confidential data exchange among entities communicating through data packet networks wherein the data content is protected, e.g. by encrypting or encapsulating the payload wherein the sending and receiving network entities apply symmetric encryption, i.e. same key used for encryption and decryption
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US20224300P | 2000-05-05 | 2000-05-05 | |
US60202243 | 2000-05-05 | ||
PCT/US2001/014535 WO2001089131A2 (en) | 2000-05-05 | 2001-05-07 | A method and system for performing permutations using permutation instructions based on modified omega and flip stages |
Publications (1)
Publication Number | Publication Date |
---|---|
AU2001288209A1 true AU2001288209A1 (en) | 2001-11-26 |
Family
ID=22749043
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
AU2001288209A Abandoned AU2001288209A1 (en) | 2000-05-05 | 2001-05-07 | A method and system for performing permutations using permutation instructions based on modified omega and flip stages |
Country Status (6)
Country | Link |
---|---|
US (1) | US6952478B2 (en) |
EP (1) | EP1230589A4 (en) |
JP (1) | JP2003533829A (en) |
AU (1) | AU2001288209A1 (en) |
CA (1) | CA2375058A1 (en) |
WO (1) | WO2001089131A2 (en) |
Families Citing this family (38)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP1281254A4 (en) * | 2000-04-20 | 2003-06-04 | Noel D Matchett | Cryptographic system for data encryption standard |
US20030105945A1 (en) * | 2001-11-01 | 2003-06-05 | Bops, Inc. | Methods and apparatus for a bit rake instruction |
US7620832B2 (en) * | 2000-09-20 | 2009-11-17 | Mips Technologies, Inc. | Method and apparatus for masking a microprocessor execution signature |
US7711763B2 (en) | 2001-02-21 | 2010-05-04 | Mips Technologies, Inc. | Microprocessor instructions for performing polynomial arithmetic operations |
US7181484B2 (en) | 2001-02-21 | 2007-02-20 | Mips Technologies, Inc. | Extended-precision accumulation of multiplier output |
US7237097B2 (en) * | 2001-02-21 | 2007-06-26 | Mips Technologies, Inc. | Partial bitwise permutations |
US7162621B2 (en) | 2001-02-21 | 2007-01-09 | Mips Technologies, Inc. | Virtual instruction expansion based on template and parameter selector information specifying sign-extension or concentration |
US7318145B1 (en) | 2001-06-01 | 2008-01-08 | Mips Technologies, Inc. | Random slip generator |
US7730292B2 (en) | 2003-03-31 | 2010-06-01 | Hewlett-Packard Development Company, L.P. | Parallel subword instructions for directing results to selected subword locations of data processor result register |
US7424597B2 (en) * | 2003-03-31 | 2008-09-09 | Hewlett-Packard Development Company, L.P. | Variable reordering (Mux) instructions for parallel table lookups from registers |
US7305593B2 (en) * | 2003-08-26 | 2007-12-04 | Lsi Corporation | Memory mapping for parallel turbo decoding |
US20100067687A1 (en) * | 2004-12-06 | 2010-03-18 | The Trustees Of The Stevens Institute Of Technology | Method and apparatus for maintaining data integrity for block-encryption algorithms |
US7856579B2 (en) * | 2006-04-28 | 2010-12-21 | Industrial Technology Research Institute | Network for permutation or de-permutation utilized by channel coding algorithm |
US7761694B2 (en) * | 2006-06-30 | 2010-07-20 | Intel Corporation | Execution unit for performing shuffle and other operations |
US20080152014A1 (en) * | 2006-12-21 | 2008-06-26 | On Demand Microelectronics | Method and apparatus for encoding and decoding of video streams |
US20080162743A1 (en) * | 2006-12-28 | 2008-07-03 | On Demand Microelectronics | Method and apparatus to select and modify elements of vectors |
FR2914294B1 (en) * | 2007-03-29 | 2009-07-10 | Rexam Dispensing Systems Sas | DISTRIBUTION NOZZLE COMPRISING AN AXIS-ATTACHED CLOSURE SLEEVE |
US8285766B2 (en) | 2007-05-23 | 2012-10-09 | The Trustees Of Princeton University | Microprocessor shifter circuits utilizing butterfly and inverse butterfly routing circuits, and control circuits therefor |
US9529592B2 (en) | 2007-12-27 | 2016-12-27 | Intel Corporation | Vector mask memory access instructions to perform individual and sequential memory access operations if an exception occurs during a full width memory access operation |
US8909901B2 (en) | 2007-12-28 | 2014-12-09 | Intel Corporation | Permute operations with flexible zero control |
GB2456775B (en) * | 2008-01-22 | 2012-10-31 | Advanced Risc Mach Ltd | Apparatus and method for performing permutation operations on data |
US8879725B2 (en) | 2008-02-29 | 2014-11-04 | Intel Corporation | Combining instructions including an instruction that performs a sequence of transformations to isolate one transformation |
US20100329450A1 (en) * | 2009-06-30 | 2010-12-30 | Sun Microsystems, Inc. | Instructions for performing data encryption standard (des) computations using general-purpose registers |
US8677209B2 (en) * | 2009-11-19 | 2014-03-18 | Lsi Corporation | Subwords coding using different encoding/decoding matrices |
US8621289B2 (en) | 2010-07-14 | 2013-12-31 | Lsi Corporation | Local and global interleaving/de-interleaving on values in an information word |
US8402324B2 (en) | 2010-09-27 | 2013-03-19 | Lsi Corporation | Communications system employing local and global interleaving/de-interleaving |
US8976876B2 (en) | 2010-10-25 | 2015-03-10 | Lsi Corporation | Communications system supporting multiple sector sizes |
US8588223B2 (en) | 2010-11-09 | 2013-11-19 | Lsi Corporation | Multi-stage interconnection networks having smaller memory requirements |
US8782320B2 (en) * | 2010-11-09 | 2014-07-15 | Lsi Corporation | Multi-stage interconnection networks having fixed mappings |
CN102737007B (en) * | 2011-04-07 | 2015-01-28 | 中兴通讯股份有限公司 | Method and device supporting random replacement of plurality of data units |
US20120286813A1 (en) | 2011-05-12 | 2012-11-15 | Murphy Morgan D | Windshield moisture detector |
WO2013006030A1 (en) | 2011-07-06 | 2013-01-10 | Mimos Berhad | Apparatus and method for performing parallel bits distribution with bi-delta network |
MY174802A (en) * | 2011-07-12 | 2020-05-15 | Mimos Berhad | Apparatus and method of performing bit separation |
RU2488161C1 (en) * | 2011-11-14 | 2013-07-20 | Федеральное Государственное Бюджетное Образовательное Учреждение Высшего Профессионального Образования "Саратовский Государственный Университет Имени Н.Г. Чернышевского" | Device for swapping and shifting of data bits in microprocessors |
MY172620A (en) | 2014-01-22 | 2019-12-06 | Mimos Berhad | System and method for arbitrary bit pemutation using bit-separation and bit-distribution instructions |
EP3001307B1 (en) * | 2014-09-25 | 2019-11-13 | Intel Corporation | Bit shuffle processors, methods, systems, and instructions |
EP3001306A1 (en) * | 2014-09-25 | 2016-03-30 | Intel Corporation | Bit group interleave processors, methods, systems, and instructions |
US10255462B2 (en) | 2016-06-17 | 2019-04-09 | Arm Limited | Apparatus and method for obfuscating power consumption of a processor |
Family Cites Families (18)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3796830A (en) | 1971-11-02 | 1974-03-12 | Ibm | Recirculating block cipher cryptographic system |
US3962539A (en) | 1975-02-24 | 1976-06-08 | International Business Machines Corporation | Product block cipher system for data security |
US4275265A (en) * | 1978-10-02 | 1981-06-23 | Wisconsin Alumni Research Foundation | Complete substitution permutation enciphering and deciphering circuit |
JPH01503028A (en) | 1986-06-09 | 1989-10-12 | データコンサルト、イ、マルメ、アクチェボラーグ | Encryption and decryption equipment |
FR2611962B1 (en) | 1987-03-06 | 1989-06-09 | Trt Telecom Radio Electr | SYSTEM AND METHOD FOR APPLIED CRYPTOGRAPHY |
US5483541A (en) | 1993-09-13 | 1996-01-09 | Trw Inc. | Permuted interleaver |
FR2721416B1 (en) * | 1994-06-20 | 1996-08-30 | Met | Device for routing data cells in asynchronous transfer mode. |
US5768493A (en) | 1994-11-08 | 1998-06-16 | International Businees Machines Corporation | Algorithm for fault tolerant routing in benes networks |
US5495476A (en) * | 1995-01-26 | 1996-02-27 | International Business Machines Corporation | Parallel algorithm to set up benes switch; trading bandwidth for set up time |
US5673321A (en) * | 1995-06-29 | 1997-09-30 | Hewlett-Packard Company | Efficient selection and mixing of multiple sub-word items packed into two or more computer words |
US6381690B1 (en) * | 1995-08-01 | 2002-04-30 | Hewlett-Packard Company | Processor for performing subword permutations and combinations |
US5956405A (en) | 1997-01-17 | 1999-09-21 | Microsoft Corporation | Implementation efficient encryption and message authentication |
US6081896A (en) | 1997-09-02 | 2000-06-27 | Motorola, Inc. | Cryptographic processing system with programmable function units and method |
US6119224A (en) | 1998-06-25 | 2000-09-12 | International Business Machines Corporation | Fast shift amount decode for VMX shift and vperm instructions |
US6275587B1 (en) | 1998-06-30 | 2001-08-14 | Adobe Systems Incorporated | Secure data encoder and decoder |
US6195026B1 (en) | 1998-09-14 | 2001-02-27 | Intel Corporation | MMX optimized data packing methodology for zero run length and variable length entropy encoding |
US6446198B1 (en) * | 1999-09-30 | 2002-09-03 | Apple Computer, Inc. | Vectorized table lookup |
US6629115B1 (en) * | 1999-10-01 | 2003-09-30 | Hitachi, Ltd. | Method and apparatus for manipulating vectored data |
-
2001
- 2001-05-07 AU AU2001288209A patent/AU2001288209A1/en not_active Abandoned
- 2001-05-07 EP EP01967928A patent/EP1230589A4/en not_active Withdrawn
- 2001-05-07 CA CA002375058A patent/CA2375058A1/en not_active Abandoned
- 2001-05-07 WO PCT/US2001/014535 patent/WO2001089131A2/en active Application Filing
- 2001-05-07 US US09/850,238 patent/US6952478B2/en not_active Expired - Lifetime
- 2001-05-07 JP JP2001585439A patent/JP2003533829A/en active Pending
Also Published As
Publication number | Publication date |
---|---|
JP2003533829A (en) | 2003-11-11 |
US20020108030A1 (en) | 2002-08-08 |
WO2001089131A2 (en) | 2001-11-22 |
EP1230589A4 (en) | 2008-03-19 |
CA2375058A1 (en) | 2001-11-22 |
EP1230589A2 (en) | 2002-08-14 |
WO2001089131A3 (en) | 2002-06-13 |
US6952478B2 (en) | 2005-10-04 |
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