AU2001286941A1 - Method for uniform polish microelectronic device - Google Patents
Method for uniform polish microelectronic deviceInfo
- Publication number
- AU2001286941A1 AU2001286941A1 AU2001286941A AU8694101A AU2001286941A1 AU 2001286941 A1 AU2001286941 A1 AU 2001286941A1 AU 2001286941 A AU2001286941 A AU 2001286941A AU 8694101 A AU8694101 A AU 8694101A AU 2001286941 A1 AU2001286941 A1 AU 2001286941A1
- Authority
- AU
- Australia
- Prior art keywords
- microelectronic device
- uniform polish
- polish microelectronic
- uniform
- polish
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
Links
- 238000000034 method Methods 0.000 title 1
- 238000004377 microelectronic Methods 0.000 title 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
- H01L21/76229—Concurrent filling of a plurality of trenches having a different trench shape or dimension, e.g. rectangular and V-shaped trenches, wide and narrow trenches, shallow and deep trenches
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/304—Mechanical treatment, e.g. grinding, polishing, cutting
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B99/00—Subject matter not provided for in other groups of this subclass
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/31051—Planarisation of the insulating layers
- H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Power Engineering (AREA)
- Semiconductor Memories (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Mechanical Treatment Of Semiconductor (AREA)
- Element Separation (AREA)
- Finish Polishing, Edge Sharpening, And Grinding By Specific Grinding Devices (AREA)
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US09/655,149 US6358816B1 (en) | 2000-09-05 | 2000-09-05 | Method for uniform polish in microelectronic device |
US09/655,149 | 2000-09-05 | ||
PCT/US2001/027078 WO2002021581A2 (en) | 2000-09-05 | 2001-08-31 | Method for uniform polish microelectronic device |
Publications (1)
Publication Number | Publication Date |
---|---|
AU2001286941A1 true AU2001286941A1 (en) | 2002-03-22 |
Family
ID=24627724
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
AU2001286941A Abandoned AU2001286941A1 (en) | 2000-09-05 | 2001-08-31 | Method for uniform polish microelectronic device |
Country Status (8)
Country | Link |
---|---|
US (2) | US6358816B1 (en) |
JP (1) | JP5113974B2 (en) |
KR (2) | KR100823464B1 (en) |
CN (1) | CN1306569C (en) |
AU (1) | AU2001286941A1 (en) |
MY (1) | MY131407A (en) |
TW (1) | TW509608B (en) |
WO (1) | WO2002021581A2 (en) |
Families Citing this family (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR20030044205A (en) * | 2001-11-29 | 2003-06-09 | 동부전자 주식회사 | Method and apparatus for fabricating semiconductor |
US7199305B2 (en) * | 2002-08-08 | 2007-04-03 | Nanoink, Inc. | Protosubstrates |
US6905967B1 (en) * | 2003-03-31 | 2005-06-14 | Amd, Inc. | Method for improving planarity of shallow trench isolation using multiple simultaneous tiling systems |
US7358586B2 (en) * | 2004-09-28 | 2008-04-15 | International Business Machines Corporation | Silicon-on-insulator wafer having reentrant shape dielectric trenches |
US7151302B1 (en) | 2005-06-24 | 2006-12-19 | Freescale Semiconductor, Inc. | Method and apparatus for maintaining topographical uniformity of a semiconductor memory array |
WO2007000823A1 (en) | 2005-06-29 | 2007-01-04 | Spansion Llc | Semiconductor device and production method therefor |
US7718505B2 (en) * | 2007-06-22 | 2010-05-18 | Infineon Technologies Austria Ag | Method of forming a semiconductor structure comprising insulating layers with different thicknesses |
US8822287B2 (en) * | 2010-12-10 | 2014-09-02 | Samsung Electronics Co., Ltd. | Methods of manufacturing semiconductor devices |
CN104979295B (en) * | 2014-04-10 | 2018-05-04 | 中芯国际集成电路制造(上海)有限公司 | The manufacture method of embedded grid flash memory device |
TWI627749B (en) | 2014-11-24 | 2018-06-21 | 聯華電子股份有限公司 | Semiconductor structure and semiconductor pattern structure |
Family Cites Families (19)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5053839A (en) * | 1990-01-23 | 1991-10-01 | Texas Instruments Incorporated | Floating gate memory cell and device |
US5498565A (en) * | 1991-11-29 | 1996-03-12 | Sony Corporation | Method of forming trench isolation having polishing step and method of manufacturing semiconductor device |
JP2874486B2 (en) * | 1991-11-29 | 1999-03-24 | ソニー株式会社 | Method for forming trench isolation with polishing step and method for manufacturing semiconductor device |
JPH07245306A (en) * | 1994-01-17 | 1995-09-19 | Sony Corp | Method for flattening film of semiconductor device |
EP0813239A1 (en) * | 1996-02-21 | 1997-12-17 | Texas Instruments Incorporated | Improvements in or relating to semiconductor devices |
US6060385A (en) * | 1997-02-14 | 2000-05-09 | Micro Technology, Inc. | Method of making an interconnect structure |
JPH10294366A (en) * | 1997-04-21 | 1998-11-04 | Matsushita Electric Ind Co Ltd | Semiconductor device and its manufacture |
KR100230421B1 (en) | 1997-04-22 | 1999-11-15 | 윤종용 | Method for forming dummy patterns in a semiconductor device |
US6072209A (en) * | 1997-07-08 | 2000-06-06 | Micro Technology, Inc. | Four F2 folded bit line DRAM cell structure having buried bit and word lines |
US5811345A (en) * | 1997-09-18 | 1998-09-22 | Taiwan Semiconductor Manufacturing Co., Ltd. | Planarization of shallow- trench- isolation without chemical mechanical polishing |
US6281049B1 (en) * | 1998-01-14 | 2001-08-28 | Hyundai Electronics Industries Co., Ltd. | Semiconductor device mask and method for forming the same |
US5920792A (en) * | 1998-03-19 | 1999-07-06 | Winbond Electronics Corp | High density plasma enhanced chemical vapor deposition process in combination with chemical mechanical polishing process for preparation and planarization of intemetal dielectric layers |
US5946592A (en) * | 1998-03-19 | 1999-08-31 | Winbond Electronics, Corp. | Combined in-situ high density plasma enhanced chemical vapor deposition (HDPCVD) and chemical mechanical polishing (CMP) process to form an intermetal dielectric layer with a stopper layer embedded therein |
JP2000156360A (en) * | 1998-06-30 | 2000-06-06 | Fujitsu Ltd | Manufacture of semiconductor device |
TW418459B (en) * | 1998-06-30 | 2001-01-11 | Fujitsu Ltd | Semiconductor device manufacturing method |
JP2000124305A (en) * | 1998-10-15 | 2000-04-28 | Mitsubishi Electric Corp | Semiconductor device |
JP2000232154A (en) * | 1999-02-12 | 2000-08-22 | Sony Corp | Semiconductor device and its manufacture |
JP3748744B2 (en) * | 1999-10-18 | 2006-02-22 | Necエレクトロニクス株式会社 | Semiconductor device |
JP4843129B2 (en) * | 2000-06-30 | 2011-12-21 | ルネサスエレクトロニクス株式会社 | Semiconductor device and manufacturing method thereof |
-
2000
- 2000-09-05 US US09/655,149 patent/US6358816B1/en not_active Expired - Lifetime
-
2001
- 2001-08-31 WO PCT/US2001/027078 patent/WO2002021581A2/en active Application Filing
- 2001-08-31 AU AU2001286941A patent/AU2001286941A1/en not_active Abandoned
- 2001-08-31 KR KR1020037003281A patent/KR100823464B1/en not_active IP Right Cessation
- 2001-08-31 KR KR1020077021589A patent/KR100857407B1/en not_active IP Right Cessation
- 2001-08-31 JP JP2002525904A patent/JP5113974B2/en not_active Expired - Fee Related
- 2001-08-31 CN CNB01815204XA patent/CN1306569C/en not_active Expired - Fee Related
- 2001-09-04 TW TW090121850A patent/TW509608B/en not_active IP Right Cessation
- 2001-09-05 MY MYPI20014165A patent/MY131407A/en unknown
- 2001-11-02 US US10/004,507 patent/US6770929B2/en not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
KR20030029159A (en) | 2003-04-11 |
US6770929B2 (en) | 2004-08-03 |
JP5113974B2 (en) | 2013-01-09 |
MY131407A (en) | 2007-08-30 |
WO2002021581A3 (en) | 2002-08-15 |
TW509608B (en) | 2002-11-11 |
CN1306569C (en) | 2007-03-21 |
KR100823464B1 (en) | 2008-04-21 |
KR100857407B1 (en) | 2008-09-08 |
US6358816B1 (en) | 2002-03-19 |
US20020037628A1 (en) | 2002-03-28 |
CN1552093A (en) | 2004-12-01 |
KR20070100934A (en) | 2007-10-12 |
WO2002021581A2 (en) | 2002-03-14 |
JP2004511086A (en) | 2004-04-08 |
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