AU2001283160A1 - Cpu accessing an extended register set in an extended register mode - Google Patents

Cpu accessing an extended register set in an extended register mode

Info

Publication number
AU2001283160A1
AU2001283160A1 AU2001283160A AU8316001A AU2001283160A1 AU 2001283160 A1 AU2001283160 A1 AU 2001283160A1 AU 2001283160 A AU2001283160 A AU 2001283160A AU 8316001 A AU8316001 A AU 8316001A AU 2001283160 A1 AU2001283160 A1 AU 2001283160A1
Authority
AU
Australia
Prior art keywords
extended register
mode
cpu accessing
register set
extended
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
AU2001283160A
Inventor
David S. Christie
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Advanced Micro Devices Inc
Original Assignee
Advanced Micro Devices Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Micro Devices Inc filed Critical Advanced Micro Devices Inc
Publication of AU2001283160A1 publication Critical patent/AU2001283160A1/en
Abandoned legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30098—Register arrangements
    • G06F9/3012—Organisation of register space, e.g. banked or distributed register file
    • G06F9/30138—Extension of register space, e.g. register cache
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/30036—Instructions to perform operations on packed data, e.g. vector, tile or matrix operations
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30076—Arrangements for executing specific machine instructions to perform miscellaneous control operations, e.g. NOP
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30098—Register arrangements
    • G06F9/30105—Register structure
    • G06F9/30112—Register structure comprising data of variable length
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30181—Instruction operation extension or modification
    • G06F9/30185—Instruction operation extension or modification according to one or more bits in the instruction, e.g. prefix, sub-opcode
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30181—Instruction operation extension or modification
    • G06F9/30189—Instruction operation extension or modification according to execution mode, e.g. mode flag
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/34—Addressing or accessing the instruction operand or the result ; Formation of operand address; Addressing modes

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Executing Machine-Instructions (AREA)
AU2001283160A 2000-08-09 2001-08-07 Cpu accessing an extended register set in an extended register mode Abandoned AU2001283160A1 (en)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US22436800P 2000-08-09 2000-08-09
US60224368 2000-08-09
US09/824,863 US6877084B1 (en) 2000-08-09 2001-04-02 Central processing unit (CPU) accessing an extended register set in an extended register mode
US09824863 2001-04-02
PCT/US2001/024738 WO2002013005A1 (en) 2000-08-09 2001-08-07 Cpu accessing an extended register set in an extended register mode

Publications (1)

Publication Number Publication Date
AU2001283160A1 true AU2001283160A1 (en) 2002-02-18

Family

ID=26918656

Family Applications (1)

Application Number Title Priority Date Filing Date
AU2001283160A Abandoned AU2001283160A1 (en) 2000-08-09 2001-08-07 Cpu accessing an extended register set in an extended register mode

Country Status (8)

Country Link
US (1) US6877084B1 (en)
EP (1) EP1320800B1 (en)
JP (1) JP2004506263A (en)
KR (1) KR100880681B1 (en)
CN (1) CN1243304C (en)
AU (1) AU2001283160A1 (en)
DE (1) DE60103414T2 (en)
WO (1) WO2002013005A1 (en)

Families Citing this family (69)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050055208A1 (en) * 2001-07-03 2005-03-10 Kibkalo Alexandr A. Method and apparatus for fast calculation of observation probabilities in speech recognition
US20030217356A1 (en) * 2002-01-10 2003-11-20 Leonid Baraz Register allocation for program execution analysis
FR2851349A1 (en) * 2003-02-17 2004-08-20 St Microelectronics Sa METHOD FOR MANAGING A MICROPROCESSOR STACK FOR BACKING UP CONTEXTUAL DATA
US7680990B2 (en) * 2003-05-30 2010-03-16 Hewlett-Packard Development Company, L.P. Superword memory-access instructions for data processor
TWI224281B (en) * 2003-07-16 2004-11-21 Sunplus Technology Co Ltd A processor executing script with different length and method thereof
US7451294B2 (en) * 2003-07-30 2008-11-11 Intel Corporation Apparatus and method for two micro-operation flow using source override
US7340588B2 (en) * 2003-11-24 2008-03-04 International Business Machines Corporation Extending the number of instruction bits in processors with fixed length instructions, in a manner compatible with existing code
US20050138330A1 (en) * 2003-12-23 2005-06-23 Maxim Integrated Products, Inc. MAXQ microcontroller
US7231509B2 (en) * 2005-01-13 2007-06-12 International Business Machines Corporation Extended register bank allocation based on status mask bits set by allocation instruction for respective code block
US7779213B2 (en) * 2005-08-29 2010-08-17 The Invention Science Fund I, Inc Optimization of instruction group execution through hardware resource management policies
US7774558B2 (en) 2005-08-29 2010-08-10 The Invention Science Fund I, Inc Multiprocessor resource optimization
US8181004B2 (en) * 2005-08-29 2012-05-15 The Invention Science Fund I, Llc Selecting a resource management policy for a resource available to a processor
US8214191B2 (en) * 2005-08-29 2012-07-03 The Invention Science Fund I, Llc Cross-architecture execution optimization
US7607042B2 (en) * 2005-08-29 2009-10-20 Searete, Llc Adjusting a processor operating parameter based on a performance criterion
US7877584B2 (en) * 2005-08-29 2011-01-25 The Invention Science Fund I, Llc Predictive processor resource management
US7627739B2 (en) * 2005-08-29 2009-12-01 Searete, Llc Optimization of a hardware resource shared by a multiprocessor
US8209524B2 (en) * 2005-08-29 2012-06-26 The Invention Science Fund I, Llc Cross-architecture optimization
US8516300B2 (en) * 2005-08-29 2013-08-20 The Invention Science Fund I, Llc Multi-votage synchronous systems
US7647487B2 (en) * 2005-08-29 2010-01-12 Searete, Llc Instruction-associated processor resource optimization
US20070050605A1 (en) * 2005-08-29 2007-03-01 Bran Ferren Freeze-dried ghost pages
US7725693B2 (en) * 2005-08-29 2010-05-25 Searete, Llc Execution optimization using a processor resource management policy saved in an association with an instruction group
US20070050604A1 (en) * 2005-08-29 2007-03-01 Searete Llc, A Limited Liability Corporation Of The State Of Delaware Fetch rerouting in response to an execution-based optimization profile
US8255745B2 (en) * 2005-08-29 2012-08-28 The Invention Science Fund I, Llc Hardware-error tolerant computing
US8281109B2 (en) 2007-12-27 2012-10-02 Intel Corporation Compressed instruction format
JP5481793B2 (en) * 2008-03-21 2014-04-23 富士通株式会社 Arithmetic processing device and method of controlling the same
US20100023733A1 (en) * 2008-04-15 2010-01-28 Vns Portfolio Llc Microprocessor Extended Instruction Set Precision Mode
US20090257263A1 (en) * 2008-04-15 2009-10-15 Vns Portfolio Llc Method and Apparatus for Computer Memory
US8060724B2 (en) * 2008-08-15 2011-11-15 Freescale Semiconductor, Inc. Provision of extended addressing modes in a single instruction multiple data (SIMD) data processor
US20100115239A1 (en) * 2008-10-29 2010-05-06 Adapteva Incorporated Variable instruction width digital signal processor
CN101853148B (en) * 2009-05-19 2014-04-23 威盛电子股份有限公司 Device and method adaptive to microprocessor
US9684632B2 (en) * 2009-06-04 2017-06-20 Micron Technology, Inc. Parallel processing and internal processors
US20110047355A1 (en) * 2009-08-24 2011-02-24 International Business Machines Corporation Offset Based Register Address Indexing
US9631528B2 (en) * 2009-09-03 2017-04-25 Clean Emissions Technologies, Inc. Vehicle reduced emission deployment
US9003170B2 (en) * 2009-12-22 2015-04-07 Intel Corporation Bit range isolation instructions, methods, and apparatus
US8914619B2 (en) * 2010-06-22 2014-12-16 International Business Machines Corporation High-word facility for extending the number of general purpose registers available to instructions
US9378019B2 (en) 2011-04-07 2016-06-28 Via Technologies, Inc. Conditional load instructions in an out-of-order execution microprocessor
EP2631786B1 (en) * 2011-04-07 2018-06-06 VIA Technologies, Inc. Load multiple and store multiple instructions in a microprocessor that emulates banked registers
US8880851B2 (en) 2011-04-07 2014-11-04 Via Technologies, Inc. Microprocessor that performs X86 ISA and arm ISA machine language program instructions by hardware translation into microinstructions executed by common execution pipeline
US9146742B2 (en) 2011-04-07 2015-09-29 Via Technologies, Inc. Heterogeneous ISA microprocessor that preserves non-ISA-specific configuration state when reset to different ISA
US9898291B2 (en) 2011-04-07 2018-02-20 Via Technologies, Inc. Microprocessor with arm and X86 instruction length decoders
US9128701B2 (en) 2011-04-07 2015-09-08 Via Technologies, Inc. Generating constant for microinstructions from modified immediate field during instruction translation
US8880857B2 (en) 2011-04-07 2014-11-04 Via Technologies, Inc. Conditional ALU instruction pre-shift-generated carry flag propagation between microinstructions in read-port limited register file microprocessor
US9043580B2 (en) 2011-04-07 2015-05-26 Via Technologies, Inc. Accessing model specific registers (MSR) with different sets of distinct microinstructions for instructions of different instruction set architecture (ISA)
US9176733B2 (en) 2011-04-07 2015-11-03 Via Technologies, Inc. Load multiple and store multiple instructions in a microprocessor that emulates banked registers
US9645822B2 (en) 2011-04-07 2017-05-09 Via Technologies, Inc Conditional store instructions in an out-of-order execution microprocessor
US9336180B2 (en) 2011-04-07 2016-05-10 Via Technologies, Inc. Microprocessor that makes 64-bit general purpose registers available in MSR address space while operating in non-64-bit mode
US9274795B2 (en) 2011-04-07 2016-03-01 Via Technologies, Inc. Conditional non-branch instruction prediction
US9141389B2 (en) 2011-04-07 2015-09-22 Via Technologies, Inc. Heterogeneous ISA microprocessor with shared hardware ISA registers
US9244686B2 (en) 2011-04-07 2016-01-26 Via Technologies, Inc. Microprocessor that translates conditional load/store instructions into variable number of microinstructions
US9032189B2 (en) 2011-04-07 2015-05-12 Via Technologies, Inc. Efficient conditional ALU instruction in read-port limited register file microprocessor
US8924695B2 (en) 2011-04-07 2014-12-30 Via Technologies, Inc. Conditional ALU instruction condition satisfaction propagation between microinstructions in read-port limited register file microprocessor
US9292470B2 (en) 2011-04-07 2016-03-22 Via Technologies, Inc. Microprocessor that enables ARM ISA program to access 64-bit general purpose registers written by x86 ISA program
US9317288B2 (en) 2011-04-07 2016-04-19 Via Technologies, Inc. Multi-core microprocessor that performs x86 ISA and ARM ISA machine language program instructions by hardware translation into microinstructions executed by common execution pipeline
US9459864B2 (en) * 2012-03-15 2016-10-04 International Business Machines Corporation Vector string range compare
EP2704001B1 (en) * 2012-08-31 2016-10-19 VIA Technologies, Inc. Microprocessor that makes 64-bit general purpose registers available in MSR address space while operating in non-64-bit mode
US9778932B2 (en) * 2013-01-23 2017-10-03 International Business Machines Corporation Vector generate mask instruction
CN104572020B (en) * 2014-12-31 2017-03-15 中国电子科技集团公司第三十八研究所 A kind of register file paging type expanding unit and its implementation
CN104809079B (en) * 2015-04-14 2018-01-16 昆腾微电子股份有限公司 The access method and device of paging registers
US20170192788A1 (en) * 2016-01-05 2017-07-06 Intel Corporation Binary translation support using processor instruction prefixes
US20170371662A1 (en) * 2016-06-23 2017-12-28 Intel Corporation Extension of register files for local processing of data in computing environments
US10255072B2 (en) * 2016-07-01 2019-04-09 Intel Corporation Architectural register replacement for instructions that use multiple architectural registers
CN106293627B (en) * 2016-07-27 2019-01-11 珠海市杰理科技股份有限公司 Register calls and the method, apparatus of call instruction coding
US20180336034A1 (en) * 2017-05-17 2018-11-22 Hewlett Packard Enterprise Development Lp Near memory computing architecture
US11544065B2 (en) * 2019-09-27 2023-01-03 Advanced Micro Devices, Inc. Bit width reconfiguration using a shadow-latch configured register file
US11275562B2 (en) * 2020-02-19 2022-03-15 Micron Technology, Inc. Bit string accumulation
US11599359B2 (en) 2020-05-18 2023-03-07 Advanced Micro Devices, Inc. Methods and systems for utilizing a master-shadow physical register file based on verified activation
US11960897B2 (en) * 2021-07-30 2024-04-16 Advanced Micro Devices, Inc. Apparatus and methods employing a shared read post register file
US11954491B2 (en) 2022-01-30 2024-04-09 Simplex Micro, Inc. Multi-threading microprocessor with a time counter for statically dispatching instructions
WO2024015445A1 (en) * 2022-07-13 2024-01-18 Simplex Micro, Inc. Vector processor with extended vector registers

Family Cites Families (59)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2230258A5 (en) 1973-05-16 1974-12-13 Honeywell Bull Soc Ind
AT354159B (en) 1975-02-10 1979-12-27 Siemens Ag ASSOCIATIVE STORAGE WITH SEPARATELY ASSOCIATED AREAS
DE2555963C2 (en) 1975-12-12 1982-10-28 Ibm Deutschland Gmbh, 7000 Stuttgart Function modification facility
US4050094A (en) 1976-04-30 1977-09-20 International Business Machines Corporation Translator lookahead controls
AU556521B2 (en) 1981-06-11 1986-11-06 Data General Corporation Arithmetic unit
US4453212A (en) 1981-07-13 1984-06-05 Burroughs Corporation Extended address generating apparatus and method
US4928223A (en) 1982-10-06 1990-05-22 Fairchild Semiconductor Corporation Floating point microprocessor with directable two level microinstructions
US4807115A (en) 1983-10-07 1989-02-21 Cornell Research Foundation, Inc. Instruction issuing mechanism for processors with multiple functional units
EP0148478B1 (en) * 1983-12-23 1989-08-09 Hitachi, Ltd. A data processor with control of the significant bit lenghts of general purpose registers
US4972338A (en) 1985-06-13 1990-11-20 Intel Corporation Memory management for microprocessor system
EP0239081B1 (en) 1986-03-26 1995-09-06 Hitachi, Ltd. Pipelined data processor capable of decoding and executing plural instructions in parallel
JPS62237547A (en) 1986-04-09 1987-10-17 Hitachi Ltd Address conversion system
AU587714B2 (en) 1986-08-27 1989-08-24 Amdahl Corporation Cache storage queue
US4926322A (en) 1987-08-03 1990-05-15 Compag Computer Corporation Software emulation of bank-switched memory using a virtual DOS monitor and paged memory management
JPH01112450A (en) 1987-10-27 1989-05-01 Sharp Corp Memory control unit
US5226132A (en) 1988-09-30 1993-07-06 Hitachi, Ltd. Multiple virtual addressing using/comparing translation pairs of addresses comprising a space address and an origin address (sto) while using space registers as storage devices for a data processing system
US5125087A (en) 1988-11-07 1992-06-23 Microsoft Corporation Method of resetting sequence of access to extended memory disrupted by interrupt processing in 80286 compatible system using code segment register
EP0369396A3 (en) 1988-11-14 1992-10-07 Nec Corporation Arithmetic processing unit capable of performing vector/matrix processing
US5067069A (en) 1989-02-03 1991-11-19 Digital Equipment Corporation Control of multiple functional units with parallel operation in a microcoded execution unit
US5226126A (en) 1989-02-24 1993-07-06 Nexgen Microsystems Processor having plurality of functional units for orderly retiring outstanding operations based upon its associated tags
US5293592A (en) 1989-04-07 1994-03-08 Intel Corporatino Decoder for pipelined system having portion indicating type of address generation and other portion controlling address generation within pipeline
US5129067A (en) 1989-06-06 1992-07-07 Advanced Micro Devices, Inc. Multiple instruction decoder for minimizing register port requirements
US5136697A (en) 1989-06-06 1992-08-04 Advanced Micro Devices, Inc. System for reducing delay for execution subsequent to correctly predicted branch instruction using fetch information stored with each block of instructions in cache
JPH03156542A (en) 1989-08-29 1991-07-04 Hitachi Ltd Address converting device and address information control method for this device
US5175863A (en) 1989-10-23 1992-12-29 International Business Machines Corporation Signal data processing system having independently, simultaneously operable alu and macu
US5471593A (en) 1989-12-11 1995-11-28 Branigin; Michael H. Computer processor with an efficient means of executing many instructions simultaneously
US5197130A (en) 1989-12-29 1993-03-23 Supercomputer Systems Limited Partnership Cluster architecture for a highly parallel scalar/vector multiprocessor system
US5303358A (en) 1990-01-26 1994-04-12 Apple Computer, Inc. Prefix instruction for modification of a subsequent instruction
US5226130A (en) 1990-02-26 1993-07-06 Nexgen Microsystems Method and apparatus for store-into-instruction-stream detection and maintaining branch prediction cache consistency
US5053631A (en) 1990-04-02 1991-10-01 Advanced Micro Devices, Inc. Pipelined floating point processing unit
US5058048A (en) 1990-04-02 1991-10-15 Advanced Micro Devices, Inc. Normalizing pipelined floating point processing unit
DE69130588T2 (en) 1990-05-29 1999-05-27 Nat Semiconductor Corp Partially decoded instruction cache and method therefor
JP2834289B2 (en) 1990-07-20 1998-12-09 株式会社日立製作所 Microprocessor
ATE200357T1 (en) 1991-07-08 2001-04-15 Seiko Epson Corp RISC PROCESSOR WITH STRETCHABLE ARCHITECTURE
US5274834A (en) 1991-08-30 1993-12-28 Intel Corporation Transparent system interrupts with integrated extended memory addressing
SG45269A1 (en) 1992-02-06 1998-01-16 Intel Corp End bit markers for instruction decode
GB2263985B (en) 1992-02-06 1995-06-14 Intel Corp Two stage window multiplexors for deriving variable length instructions from a stream of instructions
US5438668A (en) 1992-03-31 1995-08-01 Seiko Epson Corporation System and method for extraction, alignment and decoding of CISC instructions into a nano-instruction bucket for execution by a RISC computer
US5493683A (en) * 1992-12-29 1996-02-20 Intel Corporation Register for identifying processor characteristics
IE80854B1 (en) 1993-08-26 1999-04-07 Intel Corp Processor ordering consistency for a processor performing out-of-order instruction execution
US5630149A (en) * 1993-10-18 1997-05-13 Cyrix Corporation Pipelined processor with register renaming hardware to accommodate multiple size registers
EP0651321B1 (en) 1993-10-29 2001-11-14 Advanced Micro Devices, Inc. Superscalar microprocessors
US5689672A (en) 1993-10-29 1997-11-18 Advanced Micro Devices, Inc. Pre-decoded instruction cache and method therefor particularly suitable for variable byte-length instructions
US5481684A (en) 1994-01-11 1996-01-02 Exponential Technology, Inc. Emulating operating system calls in an alternate instruction set using a modified code segment descriptor
US5758116A (en) 1994-09-30 1998-05-26 Intel Corporation Instruction length decoder for generating output length indicia to identity boundaries between variable length instructions
US5822778A (en) 1995-06-07 1998-10-13 Advanced Micro Devices, Inc. Microprocessor and method of using a segment override prefix instruction field to expand the register file
US5768574A (en) 1995-06-07 1998-06-16 Advanced Micro Devices, Inc. Microprocessor using an instruction field to expand the condition flags and a computer system employing the microprocessor
US5809273A (en) 1996-01-26 1998-09-15 Advanced Micro Devices, Inc. Instruction predecode and multiple instruction decode
US5848284A (en) 1995-11-28 1998-12-08 Intel Corporation Method of transferring data between moderately coupled integer and floating point units
US5935240A (en) 1995-12-15 1999-08-10 Intel Corporation Computer implemented method for transferring packed data between register files and memory
US5838984A (en) 1996-08-19 1998-11-17 Samsung Electronics Co., Ltd. Single-instruction-multiple-data processing using multiple banks of vector registers
US5905900A (en) 1997-04-30 1999-05-18 International Business Machines Corporation Mobile client computer and power management architecture
US5903919A (en) 1997-10-07 1999-05-11 Motorola, Inc. Method and apparatus for selecting a register bank
US6014739A (en) 1997-10-27 2000-01-11 Advanced Micro Devices, Inc. Increasing general registers in X86 processors
US6157996A (en) 1997-11-13 2000-12-05 Advanced Micro Devices, Inc. Processor programably configurable to execute enhanced variable byte length instructions including predicated execution, three operand addressing, and increased register space
US6145049A (en) 1997-12-29 2000-11-07 Stmicroelectronics, Inc. Method and apparatus for providing fast switching between floating point and multimedia instructions using any combination of a first register file set and a second register file set
EP0942357A3 (en) 1998-03-11 2000-03-22 Matsushita Electric Industrial Co., Ltd. Data processor compatible with a plurality of instruction formats
US6418527B1 (en) * 1998-10-13 2002-07-09 Motorola, Inc. Data processor instruction system for grouping instructions with or without a common prefix and data processing system that uses two or more instruction grouping methods
KR19990046279A (en) * 1999-01-30 1999-07-05 권기홍 Central Processing Unit

Also Published As

Publication number Publication date
KR100880681B1 (en) 2009-01-30
EP1320800B1 (en) 2004-05-19
CN1446332A (en) 2003-10-01
KR20030024850A (en) 2003-03-26
CN1243304C (en) 2006-02-22
DE60103414D1 (en) 2004-06-24
EP1320800A1 (en) 2003-06-25
JP2004506263A (en) 2004-02-26
US6877084B1 (en) 2005-04-05
WO2002013005A1 (en) 2002-02-14
DE60103414T2 (en) 2005-06-02

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