AU2001280848A1 - Cmi signal timing recovery - Google Patents

Cmi signal timing recovery

Info

Publication number
AU2001280848A1
AU2001280848A1 AU2001280848A AU8084801A AU2001280848A1 AU 2001280848 A1 AU2001280848 A1 AU 2001280848A1 AU 2001280848 A AU2001280848 A AU 2001280848A AU 8084801 A AU8084801 A AU 8084801A AU 2001280848 A1 AU2001280848 A1 AU 2001280848A1
Authority
AU
Australia
Prior art keywords
signal timing
timing recovery
cmi signal
cmi
recovery
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
AU2001280848A
Inventor
Michael Altmann
Namik Kocaman
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Intel Corp
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Publication of AU2001280848A1 publication Critical patent/AU2001280848A1/en
Abandoned legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
    • H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
    • H03L7/183—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between fixed numbers or the frequency divider dividing by a fixed number
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/089—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses
    • H03L7/0891—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses the up-down pulses controlling source and sink current generators, e.g. a charge pump
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/38—Synchronous or start-stop systems, e.g. for Baudot code
    • H04L25/40—Transmitting circuits; Receiving circuits
    • H04L25/49—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems
    • H04L25/4906—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems using binary codes
    • H04L25/4908—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems using binary codes using mBnB codes
    • H04L25/491—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems using binary codes using mBnB codes using 1B2B codes
    • H04L25/4912—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems using binary codes using mBnB codes using 1B2B codes using CMI or 2-HDB-3 code
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Physics & Mathematics (AREA)
  • Spectroscopy & Molecular Physics (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
AU2001280848A 2000-08-10 2001-07-26 Cmi signal timing recovery Abandoned AU2001280848A1 (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US09/637,323 US6748027B1 (en) 2000-08-10 2000-08-10 CMI signal timing recovery
US09/637,323 2000-08-10
PCT/US2001/023718 WO2002014790A2 (en) 2000-08-10 2001-07-26 Cmi signal timing recovery

Publications (1)

Publication Number Publication Date
AU2001280848A1 true AU2001280848A1 (en) 2002-02-25

Family

ID=24555452

Family Applications (1)

Application Number Title Priority Date Filing Date
AU2001280848A Abandoned AU2001280848A1 (en) 2000-08-10 2001-07-26 Cmi signal timing recovery

Country Status (6)

Country Link
US (1) US6748027B1 (en)
EP (1) EP1474900A2 (en)
CN (1) CN100459605C (en)
AU (1) AU2001280848A1 (en)
TW (1) TWI222785B (en)
WO (1) WO2002014790A2 (en)

Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6748027B1 (en) 2000-08-10 2004-06-08 Intel Corporation CMI signal timing recovery
CA2344787A1 (en) * 2001-04-19 2002-10-19 Pmc-Sierra Ltd. A phase detector customized for clock synthesis unit
US7664214B2 (en) * 2002-09-24 2010-02-16 Standard Microsystems Corporation System and method for transferring data among transceivers substantially void of data dependent jitter
US7738617B1 (en) 2004-09-29 2010-06-15 Pmc-Sierra, Inc. Clock and data recovery locking technique for large frequency offsets
US7498889B2 (en) 2006-08-03 2009-03-03 Intel Corporation Analog phase controller
WO2008095508A1 (en) * 2007-02-05 2008-08-14 Tes Electronic Solutions Gmbh Pulse generator
CN101083523B (en) * 2007-07-27 2010-08-11 华南理工大学 Method and device for realizing integrated time stamp clock synchronous phase-locked loop
CN101145897B (en) * 2007-10-19 2010-12-29 中兴通讯股份有限公司 A method and system for reducing transmission clock line based on communication hardware platform
JP4548527B2 (en) * 2008-07-31 2010-09-22 ソニー株式会社 Information processing apparatus and signal processing method
JP4548526B2 (en) * 2008-07-31 2010-09-22 ソニー株式会社 Information processing apparatus, signal processing method, and signal transmission method
JP4666030B2 (en) * 2008-09-03 2011-04-06 ソニー株式会社 Information processing apparatus and signal determination method
JP4586912B2 (en) * 2008-09-08 2010-11-24 ソニー株式会社 Information processing apparatus, encoding method, and signal transmission method
CN103675443B (en) * 2012-09-06 2016-12-21 上海航天控制工程研究所 Manned spacecraft FPGA global clock detection device
US10374785B2 (en) * 2016-12-27 2019-08-06 Intel Corporation Clock phase adjustment using clock and data recovery scheme

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4535459A (en) 1983-05-26 1985-08-13 Rockwell International Corporation Signal detection apparatus
JPH04260239A (en) * 1991-02-15 1992-09-16 Nec Corp Timing extracting circuit
US5195110A (en) * 1991-04-01 1993-03-16 Nec America, Inc. Clock recovery and decoder circuit for a CMI-encoded signal
JPH0828702B2 (en) * 1992-11-25 1996-03-21 日本電気株式会社 Clock regenerator
US5376848A (en) * 1993-04-05 1994-12-27 Motorola, Inc. Delay matching circuit
US5631587A (en) 1994-05-03 1997-05-20 Pericom Semiconductor Corporation Frequency synthesizer with adaptive loop bandwidth
US5949264A (en) * 1996-11-29 1999-09-07 Lo; Dennis C. Digital phase detector and charge pump system reset and balanced current source matching methods and systems
JP2993559B2 (en) * 1997-03-31 1999-12-20 日本電気株式会社 Phase locked loop
US6040742A (en) 1997-09-02 2000-03-21 Lucent Technologies Inc. Charge-pump phase-locked loop with DC current source
JP3019814B2 (en) * 1997-09-18 2000-03-13 日本電気株式会社 Clock recovery circuit
US6278332B1 (en) * 2000-02-15 2001-08-21 Agere Systems Guardian Corp. Charge pump for low-voltage, low-jitter phase locked loops
US6748027B1 (en) 2000-08-10 2004-06-08 Intel Corporation CMI signal timing recovery

Also Published As

Publication number Publication date
TWI222785B (en) 2004-10-21
US6748027B1 (en) 2004-06-08
EP1474900A2 (en) 2004-11-10
CN100459605C (en) 2009-02-04
WO2002014790A3 (en) 2004-05-21
WO2002014790A2 (en) 2002-02-21
CN1526221A (en) 2004-09-01

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