AU2001245894A1 - Storage efficient minimization logic - Google Patents

Storage efficient minimization logic

Info

Publication number
AU2001245894A1
AU2001245894A1 AU2001245894A AU4589401A AU2001245894A1 AU 2001245894 A1 AU2001245894 A1 AU 2001245894A1 AU 2001245894 A AU2001245894 A AU 2001245894A AU 4589401 A AU4589401 A AU 4589401A AU 2001245894 A1 AU2001245894 A1 AU 2001245894A1
Authority
AU
Australia
Prior art keywords
storage efficient
minimization logic
efficient minimization
logic
storage
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
AU2001245894A
Inventor
Brian Joseph
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Texas Instruments Inc
Original Assignee
Texas Instruments Inc
Texas Instruments Santa Rosa Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Texas Instruments Inc, Texas Instruments Santa Rosa Inc filed Critical Texas Instruments Inc
Publication of AU2001245894A1 publication Critical patent/AU2001245894A1/en
Abandoned legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/22—Arrangements for sorting or merging computer data on continuous record carriers, e.g. tape, drum, disc
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2207/00—Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F2207/22—Indexing scheme relating to groups G06F7/22 - G06F7/36
    • G06F2207/222—Binary data tree

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Complex Calculations (AREA)
  • Information Retrieval, Db Structures And Fs Structures Therefor (AREA)
AU2001245894A 2000-03-21 2001-03-21 Storage efficient minimization logic Abandoned AU2001245894A1 (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US09/532,510 US6931424B1 (en) 2000-03-21 2000-03-21 Storage efficient minimization logic
US09532510 2000-03-21
PCT/US2001/008948 WO2001071483A2 (en) 2000-03-21 2001-03-21 Determinaton of a minimum or maximum value in a set of data

Publications (1)

Publication Number Publication Date
AU2001245894A1 true AU2001245894A1 (en) 2001-10-03

Family

ID=24122100

Family Applications (1)

Application Number Title Priority Date Filing Date
AU2001245894A Abandoned AU2001245894A1 (en) 2000-03-21 2001-03-21 Storage efficient minimization logic

Country Status (6)

Country Link
US (1) US6931424B1 (en)
EP (1) EP1290542B1 (en)
AU (1) AU2001245894A1 (en)
DE (1) DE60132328T2 (en)
TW (1) TW550497B (en)
WO (1) WO2001071483A2 (en)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7161994B2 (en) * 2001-09-17 2007-01-09 Digeo, Inc. System and method for shared decoding
US20030133519A1 (en) * 2001-09-17 2003-07-17 Manish Shah Forward tracing decoder apparatus and method
US7167531B2 (en) * 2001-09-17 2007-01-23 Digeo, Inc. System and method for shared decoding using a data replay scheme
US7103868B2 (en) * 2002-11-12 2006-09-05 Lsi Logic Corporation Optimizing depths of circuits for Boolean functions
US7072922B2 (en) * 2002-12-13 2006-07-04 Lsi Logic Corporation Integrated circuit and process for identifying minimum or maximum input value among plural inputs
US7434034B2 (en) * 2004-09-13 2008-10-07 Ati Technologies Inc. SIMD processor executing min/max instructions
JP4502223B2 (en) * 2007-12-05 2010-07-14 株式会社エスグランツ Bit string merge sort apparatus, method, and program
JP4464459B1 (en) * 2009-03-29 2010-05-19 株式会社エスグランツ Code string search device, search method and program
US20200110579A1 (en) * 2018-10-05 2020-04-09 International Business Machines Corporation Argmax function analog circuit

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4100532A (en) * 1976-11-19 1978-07-11 Hewlett-Packard Company Digital pattern triggering circuit
US4821290A (en) * 1988-02-09 1989-04-11 General Electric Company Decoder for digital signal codes
JPH04180124A (en) * 1990-11-15 1992-06-26 Toshiba Corp Sort processor
US5187675A (en) 1991-09-18 1993-02-16 Ericsson-Ge Mobile Communications Holding Inc. Maximum search circuit
US5383142A (en) * 1993-10-01 1995-01-17 Hewlett-Packard Company Fast circuit and method for detecting predetermined bit patterns
US5455825A (en) * 1994-04-28 1995-10-03 Mitsubishi Electric Research Laboratories Tag-based scheduling system for digital communication switch
US5710562A (en) * 1995-08-31 1998-01-20 Ricoh Company Ltd. Method and apparatus for compressing arbitrary data

Also Published As

Publication number Publication date
WO2001071483A2 (en) 2001-09-27
US6931424B1 (en) 2005-08-16
EP1290542B1 (en) 2008-01-09
DE60132328T2 (en) 2009-01-08
TW550497B (en) 2003-09-01
WO2001071483A3 (en) 2002-03-14
DE60132328D1 (en) 2008-02-21
EP1290542A2 (en) 2003-03-12

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