AU2001239559A1 - Image processing apparatus and method - Google Patents

Image processing apparatus and method

Info

Publication number
AU2001239559A1
AU2001239559A1 AU2001239559A AU3955901A AU2001239559A1 AU 2001239559 A1 AU2001239559 A1 AU 2001239559A1 AU 2001239559 A AU2001239559 A AU 2001239559A AU 3955901 A AU3955901 A AU 3955901A AU 2001239559 A1 AU2001239559 A1 AU 2001239559A1
Authority
AU
Australia
Prior art keywords
processing apparatus
image processing
image
processing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
AU2001239559A
Inventor
Hitoshi Ebihara
Hideki Hara
Masakazu Mokuno
Kazumi Sato
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sony Interactive Entertainment Inc
Original Assignee
Sony Computer Entertainment Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Computer Entertainment Inc filed Critical Sony Computer Entertainment Inc
Publication of AU2001239559A1 publication Critical patent/AU2001239559A1/en
Abandoned legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/36—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
    • G09G5/39—Control of the bit-mapped memory
    • G09G5/393—Arrangements for updating the contents of the bit-mapped memory
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T15/00—3D [Three Dimensional] image rendering
    • G06T15/005—General purpose rendering architectures
AU2001239559A 2000-03-23 2001-03-23 Image processing apparatus and method Abandoned AU2001239559A1 (en)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
JP2000082686 2000-03-23
JP2000-082686 2000-03-23
JP2000396191 2000-12-26
JP2000-396191 2000-12-26
PCT/JP2001/002337 WO2001071519A2 (en) 2000-03-23 2001-03-23 Image processing apparatus and method

Publications (1)

Publication Number Publication Date
AU2001239559A1 true AU2001239559A1 (en) 2001-10-03

Family

ID=26588187

Family Applications (1)

Application Number Title Priority Date Filing Date
AU2001239559A Abandoned AU2001239559A1 (en) 2000-03-23 2001-03-23 Image processing apparatus and method

Country Status (5)

Country Link
EP (1) EP1266295B1 (en)
JP (1) JP3860034B2 (en)
AU (1) AU2001239559A1 (en)
TW (1) TW477912B (en)
WO (1) WO2001071519A2 (en)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003263331A (en) * 2002-03-07 2003-09-19 Toshiba Corp Multiprocessor system
US7385607B2 (en) 2004-04-12 2008-06-10 Nvidia Corporation Scalable shader architecture
US8078656B1 (en) 2004-11-16 2011-12-13 Nvidia Corporation Data decompression with extra precision
US7825936B1 (en) 2004-11-19 2010-11-02 Nvidia Corporation Method and system for texture instruction demotion optimization
US7916149B1 (en) 2005-01-04 2011-03-29 Nvidia Corporation Block linear memory ordering of texture data
JP3892016B2 (en) * 2005-02-23 2007-03-14 株式会社ソニー・コンピュータエンタテインメント Image processing apparatus and image processing method
JP5245713B2 (en) * 2008-10-24 2013-07-24 株式会社リコー Image processing apparatus, image processing method, and program
CN103984669A (en) 2013-02-07 2014-08-13 辉达公司 System and method for image processing
CN108881946A (en) * 2017-05-10 2018-11-23 北京猎户星空科技有限公司 Generation, transmission, processing method, device and its system of sensing data
WO2021245875A1 (en) * 2020-06-04 2021-12-09 三菱電機株式会社 Image compositing device and image compositing method

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4949280A (en) * 1988-05-10 1990-08-14 Battelle Memorial Institute Parallel processor-based raster graphics system architecture
CA2026527A1 (en) * 1989-10-11 1991-04-12 Douglas A. Fischer Parallel polygon/pixel rendering engine
US5557711A (en) * 1990-10-17 1996-09-17 Hewlett-Packard Company Apparatus and method for volume rendering
JPH05189549A (en) * 1991-09-10 1993-07-30 Kubota Corp Image data processor by multiprocessor
JPH06214555A (en) * 1993-01-20 1994-08-05 Sumitomo Electric Ind Ltd Picture processor
US5392393A (en) * 1993-06-04 1995-02-21 Sun Microsystems, Inc. Architecture for a high performance three dimensional graphics accelerator
JPH09212146A (en) * 1996-02-06 1997-08-15 Sony Computer Entertainment:Kk Address generation device and picture display device
KR100269106B1 (en) * 1996-03-21 2000-11-01 윤종용 Multiprocessor graphics system
JP2002519954A (en) * 1998-06-26 2002-07-02 ジェネラル・インスツルメント・コーポレイション Terminal for composing and presenting MPEG-4 video programs

Also Published As

Publication number Publication date
EP1266295B1 (en) 2011-10-19
WO2001071519A2 (en) 2001-09-27
TW477912B (en) 2002-03-01
EP1266295A2 (en) 2002-12-18
JP3860034B2 (en) 2006-12-20
WO2001071519A3 (en) 2002-06-06
JP2003528394A (en) 2003-09-24

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