AU2001233023A1 - System and method for compensating for supply voltage induced signal delay mismatches - Google Patents

System and method for compensating for supply voltage induced signal delay mismatches

Info

Publication number
AU2001233023A1
AU2001233023A1 AU2001233023A AU3302301A AU2001233023A1 AU 2001233023 A1 AU2001233023 A1 AU 2001233023A1 AU 2001233023 A AU2001233023 A AU 2001233023A AU 3302301 A AU3302301 A AU 3302301A AU 2001233023 A1 AU2001233023 A1 AU 2001233023A1
Authority
AU
Australia
Prior art keywords
delay
adjustable
buffer
signal delay
compensating
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
AU2001233023A
Inventor
Christian A. J. Lutkemeyer
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Broadcom Corp
Original Assignee
Broadcom Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Broadcom Corp filed Critical Broadcom Corp
Publication of AU2001233023A1 publication Critical patent/AU2001233023A1/en
Abandoned legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/10—Distribution of clock signals, e.g. skew
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/002—Specific input/output arrangements not covered by G06F3/01 - G06F3/16
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
    • H03L7/0812—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used
    • H03L7/0814—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used the phase shifting device being digitally controlled
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/087—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using at least two phase detectors or a frequency and phase detector in the loop

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Human Computer Interaction (AREA)
  • Pulse Circuits (AREA)
  • Manipulation Of Pulses (AREA)
  • Dc Digital Transmission (AREA)
  • Arrangements For Transmission Of Measured Signals (AREA)
  • Interface Circuits In Exchanges (AREA)
  • Networks Using Active Elements (AREA)
  • Optical Communication System (AREA)

Abstract

Various systems and methods providing signal delay compensation for circuits such as a multi-pair gigabit Ethernet transceiver are disclosed. In an analog implementation a buffer with an adjustable delay may be used to minimize the delay mismatch between clock trees. The delay of the adjustable-delay buffer is controlled by bias voltages that determine the charging and discharging current to the adjustable buffer. A phase detector circuit is used to compare the clock phases for rising and falling edges, and to adjust the bias voltages that control these edges. In a digital implementation a selector switch, responsive to a phase detector, may be used to route clock signals through circuit elements to delay clock signals.
AU2001233023A 2000-01-24 2001-01-24 System and method for compensating for supply voltage induced signal delay mismatches Abandoned AU2001233023A1 (en)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US17777600P 2000-01-24 2000-01-24
US60177776 2000-01-24
US18242100P 2000-02-14 2000-02-14
US60182421 2000-02-14
PCT/US2001/002642 WO2001053916A2 (en) 2000-01-24 2001-01-24 System and method for compensating for supply voltage induced signal delay mismatches

Publications (1)

Publication Number Publication Date
AU2001233023A1 true AU2001233023A1 (en) 2001-07-31

Family

ID=26873631

Family Applications (1)

Application Number Title Priority Date Filing Date
AU2001233023A Abandoned AU2001233023A1 (en) 2000-01-24 2001-01-24 System and method for compensating for supply voltage induced signal delay mismatches

Country Status (6)

Country Link
US (6) US6501311B2 (en)
EP (1) EP1250638B1 (en)
AT (1) ATE401597T1 (en)
AU (1) AU2001233023A1 (en)
DE (1) DE60134830D1 (en)
WO (1) WO2001053916A2 (en)

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US7180353B2 (en) * 2005-02-03 2007-02-20 Mediatek Incorporation Apparatus and method for low power clock distribution
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US7627839B1 (en) * 2005-11-14 2009-12-01 National Semiconductor Corporation Process corner indicator and estimation circuit
KR100763843B1 (en) * 2005-11-23 2007-10-05 삼성전자주식회사 Source driver and display device having the same
US7486130B2 (en) * 2005-12-14 2009-02-03 Ember Corporation Clock skew compensation
US20080174353A1 (en) * 2007-01-18 2008-07-24 John Thomas Badar Path delay adjustment circuitry using programmable driver
JPWO2008114416A1 (en) * 2007-03-20 2010-07-01 富士通株式会社 Power supply voltage adjusting device, recording medium, and power supply voltage adjusting method
JP4861256B2 (en) * 2007-06-15 2012-01-25 株式会社東芝 DLL circuit
JP5303761B2 (en) * 2007-06-18 2013-10-02 国立大学法人 長崎大学 Timing generation circuit and phase shift circuit
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US8032778B2 (en) * 2008-03-19 2011-10-04 Micron Technology, Inc. Clock distribution apparatus, systems, and methods
JP5384910B2 (en) 2008-11-11 2014-01-08 ルネサスエレクトロニクス株式会社 Semiconductor integrated circuit and clock synchronization control method
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Also Published As

Publication number Publication date
WO2001053916A3 (en) 2002-05-02
US6693475B2 (en) 2004-02-17
US6501311B2 (en) 2002-12-31
ATE401597T1 (en) 2008-08-15
US6879196B2 (en) 2005-04-12
US20010049812A1 (en) 2001-12-06
US20040145397A1 (en) 2004-07-29
DE60134830D1 (en) 2008-08-28
US20020093367A1 (en) 2002-07-18
US20020089362A1 (en) 2002-07-11
EP1250638B1 (en) 2008-07-16
US20040025075A1 (en) 2004-02-05
US20030038663A1 (en) 2003-02-27
EP1250638A2 (en) 2002-10-23
WO2001053916A8 (en) 2001-10-04
US6636091B2 (en) 2003-10-21
US6690216B2 (en) 2004-02-10
US7049868B2 (en) 2006-05-23
WO2001053916A2 (en) 2001-07-26

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