AU2001230987A1 - A programmable array logic circuit macrocell using ferromagnetic memory cells - Google Patents

A programmable array logic circuit macrocell using ferromagnetic memory cells

Info

Publication number
AU2001230987A1
AU2001230987A1 AU2001230987A AU3098701A AU2001230987A1 AU 2001230987 A1 AU2001230987 A1 AU 2001230987A1 AU 2001230987 A AU2001230987 A AU 2001230987A AU 3098701 A AU3098701 A AU 3098701A AU 2001230987 A1 AU2001230987 A1 AU 2001230987A1
Authority
AU
Australia
Prior art keywords
memory cells
logic circuit
programmable array
array logic
ferromagnetic memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
AU2001230987A
Inventor
Richard M. Lienau
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Estancia Ltd
Pageant Technologies Inc
Original Assignee
Estancia Ltd
Pageant Technologies Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Estancia Ltd, Pageant Technologies Inc filed Critical Estancia Ltd
Publication of AU2001230987A1 publication Critical patent/AU2001230987A1/en
Abandoned legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17748—Structural details of configuration resources
    • H03K19/17772—Structural details of configuration resources for powering on or off
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17736—Structural details of routing resources
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17748—Structural details of configuration resources
    • H03K19/1776—Structural details of configuration resources for memories
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/1778—Structural details for adapting physical parameters
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/1778—Structural details for adapting physical parameters
    • H03K19/17796—Structural details for adapting physical parameters for physical disposition of blocks

Landscapes

  • Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Semiconductor Memories (AREA)
  • Hall/Mr Elements (AREA)
  • Mram Or Spin Memory Techniques (AREA)
AU2001230987A 2000-01-21 2001-01-20 A programmable array logic circuit macrocell using ferromagnetic memory cells Abandoned AU2001230987A1 (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US17747800P 2000-01-21 2000-01-21
US60/177,478 2000-01-21
PCT/US2001/001790 WO2001054133A1 (en) 2000-01-21 2001-01-20 A programmable array logic circuit macrocell using ferromagnetic memory cells

Publications (1)

Publication Number Publication Date
AU2001230987A1 true AU2001230987A1 (en) 2001-07-31

Family

ID=22648754

Family Applications (1)

Application Number Title Priority Date Filing Date
AU2001230987A Abandoned AU2001230987A1 (en) 2000-01-21 2001-01-20 A programmable array logic circuit macrocell using ferromagnetic memory cells

Country Status (3)

Country Link
US (1) US6710624B2 (en)
AU (1) AU2001230987A1 (en)
WO (1) WO2001054133A1 (en)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7123050B2 (en) * 2002-09-19 2006-10-17 Lienau Richard M Programmable array logic circuit employing non-volatile ferromagnetic memory cells
US6876226B2 (en) * 2003-02-24 2005-04-05 Nokia Corporation Integrated digital circuit
US7379321B2 (en) * 2005-02-04 2008-05-27 Hitachi Global Storage Technologies Netherlands B.V. Memory cell and programmable logic having ferromagnetic structures exhibiting the extraordinary hall effect
US7411803B1 (en) 2006-02-27 2008-08-12 Richard Lienau Resistive coupled hall effect sensor

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4791604A (en) 1984-02-15 1988-12-13 Joseph J. Bednarz Sheet random access memory
US5550782A (en) * 1991-09-03 1996-08-27 Altera Corporation Programmable logic array integrated circuits
US5295097A (en) 1992-08-05 1994-03-15 Lienau Richard M Nonvolatile random access memory
US6140139A (en) 1998-12-22 2000-10-31 Pageant Technologies, Inc. Hall effect ferromagnetic random access memory device and its method of manufacture
US6288929B1 (en) 1999-03-04 2001-09-11 Pageant Technologies, Inc. Magneto resistor sensor with differential collectors for a non-volatile random access ferromagnetic memory
US6229729B1 (en) 1999-03-04 2001-05-08 Pageant Technologies, Inc. (Micromem Technologies, Inc.) Magneto resistor sensor with diode short for a non-volatile random access ferromagnetic memory
US6330183B1 (en) 1999-03-04 2001-12-11 Pageant Technologies, Inc. (Micromem Technologies, Inc.) Dual conductor inductive sensor for a non-volatile random access ferromagnetic memory
US6317354B1 (en) 1999-03-04 2001-11-13 Pageant Technologies, Inc. Non-volatile random access ferromagnetic memory with single collector sensor
US6266267B1 (en) 1999-03-04 2001-07-24 Pageant Technologies, Inc. Single conductor inductive sensor for a non-volatile random access ferromagnetic memory
US6542000B1 (en) * 1999-07-30 2003-04-01 Iowa State University Research Foundation, Inc. Nonvolatile programmable logic devices
JP2004533109A (en) * 2001-03-23 2004-10-28 インテグレイテッド・マグネトエレクトロニクス・コーポレーション Transpinner type sample hold circuit and application examples

Also Published As

Publication number Publication date
US6710624B2 (en) 2004-03-23
US20030222675A1 (en) 2003-12-04
WO2001054133A1 (en) 2001-07-26
WO2001054133A9 (en) 2002-10-17

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