AU2001222415A1 - Device and method in a semiconductor circuit - Google Patents

Device and method in a semiconductor circuit

Info

Publication number
AU2001222415A1
AU2001222415A1 AU2001222415A AU2241501A AU2001222415A1 AU 2001222415 A1 AU2001222415 A1 AU 2001222415A1 AU 2001222415 A AU2001222415 A AU 2001222415A AU 2241501 A AU2241501 A AU 2241501A AU 2001222415 A1 AU2001222415 A1 AU 2001222415A1
Authority
AU
Australia
Prior art keywords
delay
semi
circuit
clock signals
circuits
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
AU2001222415A
Inventor
Stefan Davidsson
Ulf Hansson
Mikael Lindberg
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Telefonaktiebolaget LM Ericsson AB
Original Assignee
Telefonaktiebolaget LM Ericsson AB
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Telefonaktiebolaget LM Ericsson AB filed Critical Telefonaktiebolaget LM Ericsson AB
Publication of AU2001222415A1 publication Critical patent/AU2001222415A1/en
Abandoned legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/0016—Arrangements for synchronising receiver with transmitter correction of synchronization errors
    • H04L7/0033—Correction by delay
    • H04L7/0037—Delay of clock signal
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
    • H03K5/133—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals using a chain of active delay devices
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
    • H03K5/135—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals by the use of time reference signals, e.g. clock signals
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/07—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop using several loops, e.g. for redundant clock signal generation
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
    • H03L7/0812—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used
    • H03L7/0814—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used the phase shifting device being digitally controlled
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/06—Synchronising arrangements
    • H04J3/0635—Clock or time synchronisation in a network
    • H04J3/0685—Clock or time synchronisation in a node; Intranode synchronisation
    • H04J3/0688—Change of the master or reference, e.g. take-over or failure of the master

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Pulse Circuits (AREA)
  • Electronic Switches (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Networks Using Active Elements (AREA)

Abstract

A semiconductor arrangement is provided for generating a predetermined time delay. Two clocks are connected to two parallel, redundant semi-conductor circuits emitting clock signals from multiplexers. The redundant circuits receive delayed clock signals from one of the clocks, and from the other clock, clock signals that are delayed in adjustable delay circuits to be phased in with the clock signals from the first clock. A number of delay elements and a first reference number of delay elements, providing a predetermined delay time, are connected in a reference delay circuit. A quotient of the two numbers is stored. One of the semi-conductor circuits is replaced by an alternative semi-conductor circuit, the reference delay circuit of which is set on the predetermined delay time, corresponding to a second reference number of delay elements. An adjustable delay circuit is set on the same delay time as the replaced semi-conductor circuit by means of the second reference number and the quotient.
AU2001222415A 2000-12-05 2000-12-05 Device and method in a semiconductor circuit Abandoned AU2001222415A1 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/SE2000/002434 WO2002047269A1 (en) 2000-12-05 2000-12-05 Device and method in a semiconductor circuit

Publications (1)

Publication Number Publication Date
AU2001222415A1 true AU2001222415A1 (en) 2002-06-18

Family

ID=20280286

Family Applications (1)

Application Number Title Priority Date Filing Date
AU2001222415A Abandoned AU2001222415A1 (en) 2000-12-05 2000-12-05 Device and method in a semiconductor circuit

Country Status (6)

Country Link
US (1) US6900683B2 (en)
EP (1) EP1350323B1 (en)
AT (1) ATE365996T1 (en)
AU (1) AU2001222415A1 (en)
DE (1) DE60035373T2 (en)
WO (1) WO2002047269A1 (en)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB0428417D0 (en) * 2004-12-24 2005-02-02 St Microelectronics Res & Dev Programmable digital delay
FR2882207B1 (en) * 2005-02-15 2007-04-27 Alcatel Sa CLOCK SIGNAL REDUNDANCY SYNCHRONIZATION DEVICE FOR EQUIPMENT OF A SYNCHRONOUS TRANSPORT NETWORK
US8014176B2 (en) * 2008-07-25 2011-09-06 Cirrus Logic, Inc. Resonant switching power converter with burst mode transition shaping
US20120161827A1 (en) * 2010-12-28 2012-06-28 Stmicroelectronics (Canada) Inc. Central lc pll with injection locked ring pll or dell per lane
US20130002297A1 (en) * 2011-06-28 2013-01-03 Texas Instruments, Incorporated Bias temperature instability-resistant circuits
US10095825B2 (en) 2014-09-18 2018-10-09 Samsung Electronics Co., Ltd. Computer based system for verifying layout of semiconductor device and layout verify method thereof
US9704862B2 (en) 2014-09-18 2017-07-11 Samsung Electronics Co., Ltd. Semiconductor devices and methods for manufacturing the same
US9811626B2 (en) 2014-09-18 2017-11-07 Samsung Electronics Co., Ltd. Method of designing layout of semiconductor device
US9767248B2 (en) * 2014-09-18 2017-09-19 Samsung Electronics, Co., Ltd. Semiconductor having cross coupled structure and layout verification method thereof
US10026661B2 (en) 2014-09-18 2018-07-17 Samsung Electronics Co., Ltd. Semiconductor device for testing large number of devices and composing method and test method thereof
JP2017163204A (en) * 2016-03-07 2017-09-14 ＡＰＲＥＳＩＡ Ｓｙｓｔｅｍｓ株式会社 Communication apparatus

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06188676A (en) * 1992-12-17 1994-07-08 Canon Inc Correlator
JP2863684B2 (en) * 1993-03-09 1999-03-03 株式会社日立製作所 Semiconductor integrated circuit delay optimization system and delay optimization method
US5870445A (en) * 1995-12-27 1999-02-09 Raytheon Company Frequency independent clock synchronizer
JPH1069769A (en) * 1996-08-29 1998-03-10 Fujitsu Ltd Semiconductor integrated circuit
JP3739525B2 (en) * 1996-12-27 2006-01-25 富士通株式会社 Variable delay circuit and semiconductor integrated circuit device
US6125157A (en) * 1997-02-06 2000-09-26 Rambus, Inc. Delay-locked loop circuitry for clock delay adjustment
US6157226A (en) * 1997-05-23 2000-12-05 Mitsubishi Denki Kabushiki Kaisha Clock generator
US6011732A (en) * 1997-08-20 2000-01-04 Micron Technology, Inc. Synchronous clock generator including a compound delay-locked loop
KR100261216B1 (en) * 1997-11-21 2000-07-01 윤종용 Programmable delay line
KR100269316B1 (en) * 1997-12-02 2000-10-16 윤종용 Delayed locked loop & phase locked loop merged with synchronous delay circuit
US5994938A (en) * 1998-01-30 1999-11-30 Credence Systems Corporation Self-calibrating programmable phase shifter
US6369624B1 (en) * 1998-11-03 2002-04-09 Altera Corporation Programmable phase shift circuitry
US6100735A (en) * 1998-11-19 2000-08-08 Centillium Communications, Inc. Segmented dual delay-locked loop for precise variable-phase clock generation
US6285226B1 (en) * 1999-10-25 2001-09-04 Xilinx, Inc. Duty cycle correction circuit and method
US6229358B1 (en) * 1999-12-15 2001-05-08 International Business Machines Corporation Delayed matching signal generator and frequency multiplier using scaled delay networks

Also Published As

Publication number Publication date
EP1350323B1 (en) 2007-06-27
DE60035373D1 (en) 2007-08-09
US20040012429A1 (en) 2004-01-22
US6900683B2 (en) 2005-05-31
DE60035373T2 (en) 2008-03-13
ATE365996T1 (en) 2007-07-15
EP1350323A1 (en) 2003-10-08
WO2002047269A1 (en) 2002-06-13

Similar Documents

Publication Publication Date Title
TW200717239A (en) Semiconductor integrated circuit device
TW200620839A (en) Digital frequency locked delay line
TW200618476A (en) Flip flop circuit & same with scan function
AU2001222415A1 (en) Device and method in a semiconductor circuit
BRPI0409327A (en) device for generating an output audio signal based on an input audio signal, method for providing an output audio signal based on an input audio signal and apparatus for providing an output audio signal
AU2003240534A1 (en) Memory buffer arrangement
TW429322B (en) Semiconductor test system
TW200610273A (en) Adjustable frequency delay-locked loop
ATE531131T1 (en) METHOD AND DEVICE FOR DISTRIBUTING SEVERAL SIGNAL INPUTS TO SEVERAL INTEGRATED CIRCUITS
WO2007120957A3 (en) Dynamic timing adjustment in a circuit device
WO2005013044A3 (en) Clock generator with skew control
KR20100090953A (en) Apparatus and method for generating random number
TW200629039A (en) Apparatus and method for low power clock distribution
TW200701252A (en) Semiconductor memory device
TW200419910A (en) Method and device for generating a clock signal having predetermined clock signal properties
KR950006592A (en) Low Power Consumption Pipeline Processing Unit
WO2005050842A3 (en) Apparatus and method for generating a delayed clock signal
TW200629285A (en) Apparatus and method for data outputting
TW200511314A (en) Synchronous memory device having advanced data align circuit
TW200718022A (en) Offsetcontrollable spread spectrum clock generator apparatus
TW200637155A (en) Delay circuit for synchronizing arrival of a clock signal at different circuit board points
TW200501586A (en) Delay locked loop (DLL) circuit and method for locking clock delay by using the same
TW368748B (en) Module combination device and module combination method
WO2004090682A3 (en) Minimization of clock skew and clock phase delay in integrated circuits
TW200504934A (en) Semiconductor integrated circuit device