AU1801201A - Memory system with channel multiplexing of multiple memory devices - Google Patents

Memory system with channel multiplexing of multiple memory devices

Info

Publication number
AU1801201A
AU1801201A AU18012/01A AU1801201A AU1801201A AU 1801201 A AU1801201 A AU 1801201A AU 18012/01 A AU18012/01 A AU 18012/01A AU 1801201 A AU1801201 A AU 1801201A AU 1801201 A AU1801201 A AU 1801201A
Authority
AU
Australia
Prior art keywords
channel multiplexing
memory devices
memory system
multiple memory
memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
AU18012/01A
Inventor
Abhijit Mukund Abhyankar
Richard M Barth
Catherine Yuhjung Chen
Billy Wayne Garrett Jr.
Craig E. Hampel
Thomas J. Sheffler
Donald C. Stark
Ely K. Tsern
Frederick Abbott Ware
Steven Cameron Woo
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Rambus Inc
Original Assignee
Rambus Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US09/457,155 external-priority patent/US6708248B1/en
Application filed by Rambus Inc filed Critical Rambus Inc
Publication of AU1801201A publication Critical patent/AU1801201A/en
Abandoned legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668—Details of memory controller
    • G06F13/1694—Configuration of memory controller to different memory types
AU18012/01A 1999-12-08 2000-11-24 Memory system with channel multiplexing of multiple memory devices Abandoned AU1801201A (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US09457155 1999-12-08
US09/457,155 US6708248B1 (en) 1999-07-23 1999-12-08 Memory system with channel multiplexing of multiple memory devices
PCT/US2000/032319 WO2001042929A1 (en) 1999-12-08 2000-11-24 Memory system with channel multiplexing of multiple memory devices

Publications (1)

Publication Number Publication Date
AU1801201A true AU1801201A (en) 2001-06-18

Family

ID=23815663

Family Applications (1)

Application Number Title Priority Date Filing Date
AU18012/01A Abandoned AU1801201A (en) 1999-12-08 2000-11-24 Memory system with channel multiplexing of multiple memory devices

Country Status (2)

Country Link
AU (1) AU1801201A (en)
WO (1) WO2001042929A1 (en)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6467013B1 (en) 1999-09-30 2002-10-15 Intel Corporation Memory transceiver to couple an additional memory channel to an existing memory channel
KR100560767B1 (en) 2003-09-02 2006-03-13 삼성전자주식회사 System including insertable and removable storage and control method thereof
US7266667B2 (en) * 2004-11-12 2007-09-04 Infineon Technologies Ag Memory access using multiple sets of address/data lines
US7702839B2 (en) 2005-04-12 2010-04-20 Nokia Corporation Memory interface for volatile and non-volatile memory devices
US7436708B2 (en) 2006-03-01 2008-10-14 Micron Technology, Inc. NAND memory device column charging
WO2008127698A2 (en) 2007-04-12 2008-10-23 Rambus Inc. Memory system with point-to-point request interconnect

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08278916A (en) * 1994-11-30 1996-10-22 Hitachi Ltd Multichannel memory system, transfer information synchronizing method, and signal transfer circuit
JP4084428B2 (en) * 1996-02-02 2008-04-30 富士通株式会社 Semiconductor memory device
US5966723A (en) * 1997-05-16 1999-10-12 Intel Corporation Serial programming mode for non-volatile memory
US6049856A (en) * 1997-05-27 2000-04-11 Unisys Corporation System for simultaneously accessing two portions of a shared memory

Also Published As

Publication number Publication date
WO2001042929A1 (en) 2001-06-14

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Legal Events

Date Code Title Description
MK6 Application lapsed section 142(2)(f)/reg. 8.3(3) - pct applic. not entering national phase