ATE483251T1 - Integrierter schaltkreis mit baublöcken - Google Patents

Integrierter schaltkreis mit baublöcken

Info

Publication number
ATE483251T1
ATE483251T1 AT03735912T AT03735912T ATE483251T1 AT E483251 T1 ATE483251 T1 AT E483251T1 AT 03735912 T AT03735912 T AT 03735912T AT 03735912 T AT03735912 T AT 03735912T AT E483251 T1 ATE483251 T1 AT E483251T1
Authority
AT
Austria
Prior art keywords
routing
integrated circuit
building blocks
grid
edges
Prior art date
Application number
AT03735912T
Other languages
English (en)
Inventor
Katarzyna Leijten-Nowak
Atul Katoch
Original Assignee
Nxp Bv
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nxp Bv filed Critical Nxp Bv
Application granted granted Critical
Publication of ATE483251T1 publication Critical patent/ATE483251T1/de

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0207—Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/118—Masterslice integrated circuits
AT03735912T 2002-06-28 2003-06-17 Integrierter schaltkreis mit baublöcken ATE483251T1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
EP02077571 2002-06-28
PCT/IB2003/002743 WO2004004008A1 (en) 2002-06-28 2003-06-17 Integrated circuit having building blocks

Publications (1)

Publication Number Publication Date
ATE483251T1 true ATE483251T1 (de) 2010-10-15

Family

ID=29797242

Family Applications (1)

Application Number Title Priority Date Filing Date
AT03735912T ATE483251T1 (de) 2002-06-28 2003-06-17 Integrierter schaltkreis mit baublöcken

Country Status (9)

Country Link
US (1) US7355443B2 (de)
EP (1) EP1520298B1 (de)
JP (1) JP4283220B2 (de)
CN (1) CN100559377C (de)
AT (1) ATE483251T1 (de)
AU (1) AU2003237005A1 (de)
DE (1) DE60334380D1 (de)
TW (1) TWI300980B (de)
WO (1) WO2004004008A1 (de)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2009001368A2 (en) * 2007-06-28 2008-12-31 Indian Institute Of Science A method and system-on-chip fabric
US7970979B1 (en) * 2007-09-19 2011-06-28 Agate Logic, Inc. System and method of configurable bus-based dedicated connection circuits
US8131909B1 (en) 2007-09-19 2012-03-06 Agate Logic, Inc. System and method of signal processing engines with programmable logic fabric
US8024690B2 (en) * 2008-05-19 2011-09-20 Arm Limited Method, system and computer program product for determining routing of data paths in interconnect circuitry providing a narrow interface for connection to a first device and a wide interface for connection to a distributed plurality of further devices
TWI406146B (zh) * 2009-02-20 2013-08-21 Accton Technology Corp 電路模組化設計方法
FR2954023B1 (fr) * 2009-12-14 2012-02-10 Lyon Ecole Centrale Matrice interconnectee de cellules logiques reconfigurables avec une topologie d'interconnexion croisee
KR101646431B1 (ko) * 2012-03-30 2016-08-05 인텔 코포레이션 프로그램가능 장치 어레이들을 위한 스핀 전달 토크 기반 메모리 요소들

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5327023A (en) * 1991-03-28 1994-07-05 Kawasaki Steel Corporation Programmable logic device
US5396126A (en) * 1993-02-19 1995-03-07 At&T Corp. FPGA with distributed switch matrix
GB2280293B (en) * 1993-07-19 1997-12-10 Hewlett Packard Co Architecture for programmable logic
US5692147A (en) * 1995-06-07 1997-11-25 International Business Machines Corporation Memory mapping method and apparatus to fold sparsely populated structures into densely populated memory columns or rows by selectively transposing X and Y address portions, and programmable gate array applications thereof
JP3063828B2 (ja) * 1997-03-27 2000-07-12 日本電気株式会社 集積回路の自動概略配線方法
WO1998055918A1 (en) * 1997-06-04 1998-12-10 Dynachip Corporation Fpga with conductors segmented by active repeaters
US6191611B1 (en) * 1997-10-16 2001-02-20 Altera Corporation Driver circuitry for programmable logic devices with hierarchical interconnection resources

Also Published As

Publication number Publication date
CN1666341A (zh) 2005-09-07
EP1520298A1 (de) 2005-04-06
US7355443B2 (en) 2008-04-08
EP1520298B1 (de) 2010-09-29
WO2004004008A1 (en) 2004-01-08
DE60334380D1 (de) 2010-11-11
CN100559377C (zh) 2009-11-11
TWI300980B (en) 2008-09-11
AU2003237005A1 (en) 2004-01-19
TW200400609A (en) 2004-01-01
JP4283220B2 (ja) 2009-06-24
JP2005531964A (ja) 2005-10-20
US20050257947A1 (en) 2005-11-24

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Legal Events

Date Code Title Description
RER Ceased as to paragraph 5 lit. 3 law introducing patent treaties