ATE396454T1 - Integrierte schaltung und verfahren zur pufferung zur optimierung der burst-länge in netzwerken auf chips - Google Patents
Integrierte schaltung und verfahren zur pufferung zur optimierung der burst-länge in netzwerken auf chipsInfo
- Publication number
- ATE396454T1 ATE396454T1 AT05739743T AT05739743T ATE396454T1 AT E396454 T1 ATE396454 T1 AT E396454T1 AT 05739743 T AT05739743 T AT 05739743T AT 05739743 T AT05739743 T AT 05739743T AT E396454 T1 ATE396454 T1 AT E396454T1
- Authority
- AT
- Austria
- Prior art keywords
- integrated circuit
- processing module
- chips
- networks
- burst length
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
- G06F13/4208—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a system bus, e.g. VME bus, Futurebus, Multibus
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Data Exchanges In Wide-Area Networks (AREA)
- Information Transfer Systems (AREA)
- Communication Control (AREA)
- Multi Processors (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
EP04102189 | 2004-05-18 |
Publications (1)
Publication Number | Publication Date |
---|---|
ATE396454T1 true ATE396454T1 (de) | 2008-06-15 |
Family
ID=34967297
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
AT05739743T ATE396454T1 (de) | 2004-05-18 | 2005-05-13 | Integrierte schaltung und verfahren zur pufferung zur optimierung der burst-länge in netzwerken auf chips |
Country Status (7)
Country | Link |
---|---|
US (1) | US8086800B2 (de) |
EP (1) | EP1751667B1 (de) |
JP (1) | JP2007538331A (de) |
CN (1) | CN100445977C (de) |
AT (1) | ATE396454T1 (de) |
DE (1) | DE602005007014D1 (de) |
WO (1) | WO2005111823A1 (de) |
Families Citing this family (15)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8254913B2 (en) | 2005-08-18 | 2012-08-28 | Smartsky Networks LLC | Terrestrial based high speed data communications mesh network |
KR100653087B1 (ko) * | 2005-10-17 | 2006-12-01 | 삼성전자주식회사 | AXI가 적용된 NoC 시스템 및 그 인터리빙 방법 |
EP1791366A1 (de) * | 2005-11-28 | 2007-05-30 | Alcatel Lucent | Vermeidung von Unterbrechungen bei der Audio-/Video- Wiedergabe durch vorzeitiges Speichern genügender Daten in einem mobilen Endgerät |
US8261025B2 (en) | 2007-11-12 | 2012-09-04 | International Business Machines Corporation | Software pipelining on a network on chip |
EP2063581A1 (de) * | 2007-11-20 | 2009-05-27 | STMicroelectronics (Grenoble) SAS | Übertragung eines Datenstroms zwischen zwei elektronischen Geräten mittels eines Netzwerk-on-chip |
US8526422B2 (en) | 2007-11-27 | 2013-09-03 | International Business Machines Corporation | Network on chip with partitions |
US8490110B2 (en) * | 2008-02-15 | 2013-07-16 | International Business Machines Corporation | Network on chip with a low latency, high bandwidth application messaging interconnect |
US8423715B2 (en) | 2008-05-01 | 2013-04-16 | International Business Machines Corporation | Memory management among levels of cache in a memory hierarchy |
US8494833B2 (en) | 2008-05-09 | 2013-07-23 | International Business Machines Corporation | Emulating a computer run time environment |
US8392664B2 (en) | 2008-05-09 | 2013-03-05 | International Business Machines Corporation | Network on chip |
US8438578B2 (en) | 2008-06-09 | 2013-05-07 | International Business Machines Corporation | Network on chip with an I/O accelerator |
US8195884B2 (en) | 2008-09-18 | 2012-06-05 | International Business Machines Corporation | Network on chip with caching restrictions for pages of computer memory |
US9110668B2 (en) * | 2012-01-31 | 2015-08-18 | Broadcom Corporation | Enhanced buffer-batch management for energy efficient networking based on a power mode of a network interface |
US10983910B2 (en) * | 2018-02-22 | 2021-04-20 | Netspeed Systems, Inc. | Bandwidth weighting mechanism based network-on-chip (NoC) configuration |
US11782865B1 (en) * | 2021-06-02 | 2023-10-10 | Amazon Technologies, Inc. | Flexible data handling |
Family Cites Families (18)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4228496A (en) * | 1976-09-07 | 1980-10-14 | Tandem Computers Incorporated | Multiprocessor system |
US4253144A (en) * | 1978-12-21 | 1981-02-24 | Burroughs Corporation | Multi-processor communication network |
US5522050A (en) * | 1993-05-28 | 1996-05-28 | International Business Machines Corporation | Bus-to-bus bridge for a multiple bus information handling system that optimizes data transfers between a system bus and a peripheral bus |
JPH07123118A (ja) | 1993-10-21 | 1995-05-12 | Fuji Xerox Co Ltd | フレーム送信回路 |
US5987552A (en) * | 1998-01-26 | 1999-11-16 | Intel Corporation | Bus protocol for atomic transactions |
JP2000209652A (ja) | 1999-01-18 | 2000-07-28 | Kobe Steel Ltd | 無線電話装置 |
US6397287B1 (en) * | 1999-01-27 | 2002-05-28 | 3Com Corporation | Method and apparatus for dynamic bus request and burst-length control |
US6493776B1 (en) * | 1999-08-12 | 2002-12-10 | Mips Technologies, Inc. | Scalable on-chip system bus |
US6393500B1 (en) * | 1999-08-12 | 2002-05-21 | Mips Technologies, Inc. | Burst-configurable data bus |
US6629253B1 (en) * | 1999-12-30 | 2003-09-30 | Intel Corporation | System for efficient management of memory access requests from a planar video overlay data stream using a time delay |
US6668308B2 (en) * | 2000-06-10 | 2003-12-23 | Hewlett-Packard Development Company, L.P. | Scalable architecture based on single-chip multiprocessing |
JP4041646B2 (ja) | 2000-09-07 | 2008-01-30 | Kddi株式会社 | Tcp通信方法 |
GB2373595B (en) * | 2001-03-15 | 2005-09-07 | Italtel Spa | A system of distributed microprocessor interfaces toward macro-cell based designs implemented as ASIC or FPGA bread boarding and relative common bus protocol |
US7012893B2 (en) * | 2001-06-12 | 2006-03-14 | Smartpackets, Inc. | Adaptive control of data packet size in networks |
AU2003299282A1 (en) | 2002-10-08 | 2004-05-04 | Koninklijke Philips Electronics N.V. | Integrated circuit and method for establishing transactions |
GB0315504D0 (en) * | 2003-07-02 | 2003-08-06 | Advanced Risc Mach Ltd | Coherent multi-processing system |
JP4729490B2 (ja) | 2003-09-04 | 2011-07-20 | コーニンクレッカ フィリップス エレクトロニクス エヌ ヴィ | データ処理システム |
US7257665B2 (en) * | 2003-09-29 | 2007-08-14 | Intel Corporation | Branch-aware FIFO for interprocessor data sharing |
-
2005
- 2005-05-13 WO PCT/IB2005/051580 patent/WO2005111823A1/en active IP Right Grant
- 2005-05-13 JP JP2007517554A patent/JP2007538331A/ja active Pending
- 2005-05-13 AT AT05739743T patent/ATE396454T1/de not_active IP Right Cessation
- 2005-05-13 CN CNB2005800158550A patent/CN100445977C/zh not_active Expired - Fee Related
- 2005-05-13 DE DE602005007014T patent/DE602005007014D1/de active Active
- 2005-05-13 EP EP05739743A patent/EP1751667B1/de not_active Not-in-force
- 2005-05-13 US US11/569,083 patent/US8086800B2/en active Active
Also Published As
Publication number | Publication date |
---|---|
US20070226407A1 (en) | 2007-09-27 |
CN100445977C (zh) | 2008-12-24 |
WO2005111823A1 (en) | 2005-11-24 |
EP1751667B1 (de) | 2008-05-21 |
JP2007538331A (ja) | 2007-12-27 |
CN1954306A (zh) | 2007-04-25 |
US8086800B2 (en) | 2011-12-27 |
DE602005007014D1 (de) | 2008-07-03 |
EP1751667A1 (de) | 2007-02-14 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
ATE396454T1 (de) | Integrierte schaltung und verfahren zur pufferung zur optimierung der burst-länge in netzwerken auf chips | |
TW200741461A (en) | Memory interface to bridge memory buses | |
DE502005008714D1 (de) | Verfahren und vorrichtung zum zugriff auf daten eines botschaftsspeichers eines kommunikationsbausteins | |
MX2009006046A (es) | Sistema y metodo para optimizacion de objetos de multimedia. | |
TW200719011A (en) | Liquid crystal apparatus and repair lines structure thereof | |
GB2438116A (en) | Memory buffers for merging local data from memory modules | |
WO2009004330A3 (en) | Clock frequency adjustment for semi-conductor devices | |
GB2434895A (en) | The Buffered continous multi-drop clock rin | |
MX2010001115A (es) | Un sistema para la enseñanza y el aprendizaje adaptativos. | |
TW200620115A (en) | Method and apparatus for fixing hold time violations in a circuit design | |
EP1814239A3 (de) | Kommunikationsvorrichtung, Kommunikationsverfahren und -programm | |
TWI350447B (en) | Electronic apparatus, method for power management, computinig system, and input buffer disabling method | |
ATE500629T1 (de) | Brennstoffzellensystem | |
FR2914810B1 (fr) | Dispositif pour connecter un appareil electronique portable a au moins un autre appareil electronique et systemes utilisant un tel dispositif. | |
TW200745867A (en) | Universal interface apparatus and method | |
TW200700959A (en) | System and method of managing clock speed in an electronic device | |
TW200630901A (en) | Image processing apparatus and image processing method | |
TW200605265A (en) | Bonding an interconnect to a circuit device and related devices | |
EP1819180A3 (de) | Steuerung alternativer Kommunikationspfadnutzung in einer mobilen Kommunikationsvorrichtung | |
ATE469397T1 (de) | Integrierte schaltung und verfahren zur transaktionszurückziehung | |
ATE415742T1 (de) | Datenübertrasgungssystem und -verfahren in einer elektronischen schaltung | |
ATE458333T1 (de) | Routing-einrichtung für ein unterseeisches elektronikmodul | |
ATE415769T1 (de) | Verfahren und anordnung zur transparenten vermittlung des datenverkehrs zwischen datenverarbeitungseinrichtungen sowie ein entsprechendes computerprogamm-erzeugnis und ein entsprechendes computerlesbares speichermedium | |
ATE404009T1 (de) | Feed-forward-entzerrer | |
WO2008120322A1 (ja) | 信号遅延評価プログラム、信号遅延評価方法、および信号遅延評価装置 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
RER | Ceased as to paragraph 5 lit. 3 law introducing patent treaties |