WO2026019559A2

WO2026019559A2 - A high electron mobility transistor device structure for robust switching performance

Info

Publication number: WO2026019559A2
Application number: PCT/US2025/035884
Authority: WO
Inventors: Kuo-Chang Robert Yang; Karthick Murukesan; Alexey Kudymov; Sorin S. Georgescu
Original assignee: Power Integrations Inc
Current assignee: Power Integrations Inc
Priority date: 2024-07-17
Filing date: 2025-06-30
Publication date: 2026-01-22
Anticipated expiration: 2027-01-17
Also published as: WO2026019559A3

Abstract

A high electron mobility device structure (HEMT) for robust switching performance is presented herein. An electron barrier may be created by a PN-junction contact potential formed between P-type and N-type semiconductor layers. The electron barrier may advantageously reduce electron ejection from the 2DEG into layers below the 2DEG. Alternatively, and additionally, a highly doped N-type layer may be regrown around the source and drain layers. The regrown highly doped N-type layer may advantageously mitigate depletion reach-through caused by a degraded 2DEG.

Description

A HIGH ELECTRON MOBILITY TRANSISTOR DEVICE STRUCTURE FOR ROBUST SWITCHING PERFORMANCE

CROSS-REFERENCE TO RELATED APPLICATION(S)

[0001] This application claims the benefit of U.S. Provisional Application No. 63/672,383, filed on July 17, 2024, incorporated by reference herein in its entirety. BACKGROUND INFORMATION

Field of the Disclosure

[0002] The present invention relates to high-electron mobility transistors (HEMTs), and more specifically to HEMT device structures for power switching applications.

Background

[0003] Gallium nitride (GaN) and other wide band-gap nitride III based direct transitional semiconductor materials exhibit high break-down electric fields and avail high current densities. In this regard GaN based semiconductor devices are actively researched as an alternative to silicon based semiconductor devices in power and high frequency applications. For instance, a GaN HEMT may provide lower specific on resistance with higher breakdown voltage relative to a silicon power field effect transistor of commensurate area.

[0004] Power field effect transistors (FETs) can be enhancement mode or depletion mode. An enhancement mode device may refer to a transistor (e.g., a field effect transistor) which blocks current (i.e., which is off) when there is no applied gate bias (i.e., when the gate to source bias is zero). In contrast, a depletion mode device may refer to a transistor which allows current (i.e., which is on) when the gate to source bias is zero.

[0005] Additionally, the specific on resistance of a power device (e.g., a power FET) may refer to a resistance multiplied by device area. In this way specific on resistance offers a figure of merit relating to how much semiconductor area may be required to realize a desired value of on resistance.

[0006] The on resistance of a HEMT, and more specifically, a GaN HEMT, depends, in part, on the successful formation of a low-impedance two-dimensional electron gas within the structure (2DEG). Ideally, during the on-state (i.e., when the HEMT is “on”), the HEMT may support large current operation due, in part, to the low impedance 2DEG; and during the off- state (i.e., when the HEMT is “off’), the HEMT may support a large drain-to-source voltage and block (prevent) current.

[0007] During switching, the on resistance and specific on resistance of a GaN HEMT may dynamically increase when electrons are expelled from the 2DEG and trapped in different parts of the HEMT device structure. This may happen with large drain voltages (i.e., large drain-to-source voltages) and during the switching of large drain voltages (e.g., one-thousand seven hundred volts). Unfortunately, this may degrade device performance and give rise to higher on resistance, current collapse, and reach through. Current collapse relates to the collapse (reduction) of operating current handling capability, while reach through relates to the inability of a switch to adequately block current. Current collapse effectively results in a dynamic increase in on resistance while reach through results in unwanted leakage current (i.e., reach through current).

[0008] One way to reduce susceptibility to current collapse is to increase device size (i.e., device area). For instance, additional field plates may be added to an existing structure thereby reducing susceptibility to current collapse at the expense of additional device area. Unfortunately, increasing device size may undesirably increase cost and specific on resistance.

[0009] Accordingly, there is a need to improve GaN HEMT device structures without increasing area and without increasing specific on resistance. More specifically, there is a need to develop a HEMT structure less susceptible to the loss of electrons from the 2DEG and less susceptible to reach through.

Summary of the Disclosure

[0010] This disclosure presents a GaN HEMT device structure for robust switching performance. Rather than increasing device area to allow for higher voltages, a two-fold approach is adopted. First, a barrier to electrons is created in the vertical direction. The electron barrier, created by a semiconductor junction, may advantageously prevent the acceleration and injection of hot carriers from the 2DEG into the GaN HEMT and allow better confinement of electrons within the 2DEG. Second, and independent of the barrier, a highly doped regrown layer may be included near the drain to reduce the deleterious effect of reach through. The first and second approaches may be adopted together or independently to provide a more robust HEMT for high power switching.

BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Non-limiting and non-exhaustive embodiments of a high electron mobility device structure for robust switching performance are described with reference to the following figures, wherein like reference numerals refer to like parts throughout the various views unless otherwise specified.

[0012] FIG. 1A illustrates a device cross section of a lateral GaN HEMT according to an embodiment of the present disclosure.

[0013] FIG. IB illustrates a device cross section of a lateral GaN HEMT according to another embodiment of the present disclosure.

[0014] FIG. 1C illustrates a device cross section of a lateral GaN HEMT according to another embodiment of the present disclosure.

[0015] FIG. 2A illustrates a device cross section of a lateral GaN HEMT according to another embodiment of the present disclosure.

[0016] FIG. 2B illustrates a device cross section of a lateral GaN HEMT according to another embodiment of the present disclosure.

[0017] FIG. 2C illustrates a device cross section of a lateral GaN HEMT according to another embodiment of the present disclosure.

[0018] FIG. 3A delineates an axis within the device cross section of the lateral GaN HEMT of FIG. 2B.

[0019] FIG. 3B compares energy bands along the delineated axis of FIG. 3 A.

[0020] FIG. 4A delineates another axis within the device cross section of the lateral GaN HEMT of FIG. 2B.

[0021] FIG. 4B compares energy bands along the delineated axis of FIG. 4A.

[0022] FIG. 4C compares and magnifies the energy bands of FIG. 4B.

[0023] Corresponding reference characters indicate corresponding components throughout the several views of the drawings. Skilled artisans will appreciate that elements in the figures are illustrated for simplicity and clarity and have not necessarily been drawn to scale. For example, the dimensions of some of the elements and layers in the figures may be exaggerated relative to other elements to help to improve understanding of various embodiments of the teachings herein. Also, common but well-understood elements, layers, and/or process steps that are useful or necessary in a commercially feasible embodiment are often not depicted in order to facilitate a less obstructed view of these various embodiments of a high electron mobility device structure for robust switching performance. DET AILED DESCRIPTION

[0024] In the following description, numerous specific details are set forth in order to provide a thorough understanding of a high electron mobility device structure for robust switching performance. It will be apparent, however, to one having ordinary skill in the art that the specific detail need not be employed to practice the teachings herein. In other instances, well-known materials or methods have not been described in detail in order to avoid obscuring the present disclosure.

[0025] As described above, the switching behavior of a GaN HEMT may become degraded as a result of electrons being ejected from the two-dimensional electron gas (2DEG). Both on-state and off-state performance are deleteriously affected by the loss of electrons from the 2DEG. For instance, the on-state resistance and specific on-resistance are increased due to the trapping of the ejected electrons. Additionally, the off-state blocking capability is degraded by reach through, a phenomenon which may occur when electrons are lost from the 2DEG.

[0026] A high electron mobility device structure (HEMT) for robust switching performance is presented herein. An electron barrier may be created by a PN-junction contact potential formed between P-type and N-type semiconductor layers. The electron barrier may advantageously reduce electron ejection from the 2DEG into layers below the 2DEG. Alternatively, and additionally, a highly doped N-type layer may be regrown around the source and drain layers. The regrown highly doped N-type layer may advantageously mitigate depletion reach-through caused by a degraded 2DEG.

[0027] FIG. 1A illustrates a device cross section of a lateral GaN HEMT 100a according to an embodiment of the present disclosure. GaN HEMT 100a includes a GaN buffer layer 102, a P-GaN epitaxial (EPI) layer 104 (i.e., P-type GaN epitaxial layer), an N-GaN EPI layer 106 (i.e., an N-type GaN epitaxial layer), an aluminum gallium nitride (AlGaN) layer 108, and a silicon nitride (SiN) layer 110. A two-dimensional electron gas (2DEG) 109 may form between the N-GaN EPI layer 106 and AlGaN layer 108. Additionally, the N-GaN EPI layer 106 may be an unintentionally doped EPI layer. For instance, carbon, an impurity and a dopant, may be introduced unintentionally during epitaxy growth.

[0028] GaN HEMT 100a further includes metallization patterns including source metallization 113s, drain metallization 113d, gate metallization 114, a gate field plate 115, and a gate field plate 116. As illustrated the gate field plates 115, 116 are successively stacked above the gate 114 and may improve an electric field profile at the surface of the lateral GaN HEMT 100a. The source metallization 113s and drain metallization 113d may be metallization patterns formed using stacked metallization processes. Also, the source metallization 113s may include a small protrusion 123s, and the drain metallization 113d may include a small protrusion 123d. Small protrusions 123s-d of about half a micron (0.5um) may be intentional and/or unintentional. For instance, protrusions 123s-d may be an unavoidable result of the manufacturing process.

[0029] As illustrated, source metallization 113s and drain metallization 113d may extend into the AlGaN layer 108, N-GaN EPI layer 106, and P-GaN EPI layer 104. Additionally, the source metallization 113s and drain metallization 113d may form Schottky contacts with the AlGaN layer 108, N-GaN EPI layer 106, and P-GaN EPI layer 104 such that the 2DEG 109 is electrically coupled with the source metallization 113s and the drain metallization 113d.

[0030] According to the teachings herein, the P-GaN EPI layer 104 is positioned between the 2DEG 109 and the GaN buffer layer 102 to form a PN-junction with the N-GaN EPI layer 106. The PN-junction may create an energy barrier to electrons thereby reducing and/or preventing electron transport from the 2DEG 109 to the GaN buffer layer 102. Thus, during high power switching, fewer electrons may be ejected from the 2DEG 109 to become trapped within the GaN buffer layer 102; and as discussed above, this may advantageously reduce and/or mitigate current collapse and the dynamic increase in on resistance. Accordingly, the P-GaN EPI layer 104 may be a barrier layer for enhancing switching performance and/or preventing current collapse.

[0031] Although lateral GaN HEMT 100a presents a barrier layer comprising P-GaN EPI layer 104, other barriers are possible. For instance, a barrier could be formed using a heterojunction; and the barrier layer could be a material (e.g., an AlGaN layer) having a larger bandgap than that of the N-GaN EPI layer 106. Alternatively, and additionally, the barrier could be formed using a high-low junction of same type (e.g., N-type) impurity as described in FIG. IB.

[0032] FIG. IB illustrates a device cross section of a lateral GaN HEMT 100b according to another embodiment of the present disclosure. GaN HEMT 100b is like GaN HEMT 100a except the barrier layer is an N‘-GaN EPI layer 124. The N‘-GaN EPI layer 124 is an N-type GaN EPI layer which has a lower concentration of N-type impurities. Therefore, the N‘-GaN EPI layer 124 may form a high-low junction with the N-GaN EPI layer 106. Like a PN- junction, the high-low junction may create an energy barrier to electrons thereby reducing and/or preventing electron transport from the 2DEG 109 to the GaN buffer layer 102.

[0033] Thus, during high power switching, fewer electrons may be ejected from the 2DEG 109 to become trapped within the GaN buffer layer 102; and as discussed above, this may advantageously reduce and/or mitigate current collapse and the dynamic increase in on resistance. Accordingly, the N‘-GaN EPI layer 124 may be a barrier layer for enhancing switching performance and/or preventing current collapse.

[0034] FIG. 1C illustrates a device cross section of a lateral GaN HEMT 100c according to another embodiment of the present disclosure. GaN HEMT 100c is like GaN HEMT 100a, except the drain metallization 113d does not extend past the N-GaN EPI layer 106. Also, like GaN HEMT 100a, there is a PN-junction between the P-GaN EPI layer 104 and the N-GaN EPI layer 106.

[0035] Having the drain metallization 113d remain within the N-GaN EPI layer 106 may further increase the barrier (i.e., electron barrier) formed by the PN-junction as a function of applied drain voltage. In turn, this may advantageously increase a maximum drain voltage (i.e., drain-to-source voltage) of GaN HEMT 100c relative to that of GaN HEMT 100a.

[0036] FIG. 2A illustrates a device cross section of a lateral GaN HEMT 200a according to another embodiment of the present disclosure. Unlike GaN HEMTs lOOa-b, GaN HEMT 200a may exclude a barrier layer (e.g., P-GaN EPI layer 104 or N‘-GaN EPI layer 124). Instead, GaN HEMT 200a includes a source regrown layer 202s and a drain regrown layer 202d. Source regrown layer 202s and drain regrown layer 202d may be formed by patterning and etching source and drain trenches and then by re-depositing N+ GaN (i.e., heavily doped N-type GaN) into the source and drain trenches. Additionally, source and drain trenches may be patterned using an ohmic via mask.

[0037] As illustrated the source regrown layer 202s and drain regrown layer 202d may be heavily doped layers (e.g., N+ doped GaN layers) in diffusive contact with the Al GaN layer 108 and the N-GaN EPI layer 106. Source metallization 113s may extend into and form an ohmic contact with source regrown layer 202s. Drain metallization 113d may extend into and form an ohmic contact with drain regrown layer 202d. The source metallization 113s and drain metallization 113d may respectively form ohmic contacts with source regrown layer 202s and drain regrown layer 202d such that the 2DEG 109 is electrically coupled with the source metallization 113s and the drain metallization 113d.

[0038] As discussed above, drain regrown layer 202d may be used to mitigate and/or reduce reach through regardless of the inclusion (or exclusion) of a barrier layer (e.g., P-GaN EPI layer 104 or N"-GaN EPI layer 124). According to the teachings herein, the drain regrown layer 202d may reduce and/or prevent reach through (punch through) to the drain metallization 113d even if the 2DEG 109 is degraded due to electron trapping.

[0039] FIG. 2B illustrates a device cross section of a lateral GaN HEMT 200b according to another embodiment of the present disclosure. Unlike GaN HEMT 200a, GaN HEMT 200b includes a P-GaN EPI layer 104, source regrown layer 212s, and drain regrown layer 212d. Source regrown layer 212s is like source regrown layer 202s except it extends further into and is in diffusive contact with P-GaN EPI layer 104. Drain regrown layer 212d is like drain regrown layer 202d except it extends further into and is in diffusive contact with P-GaN EPI layer 104. According to the teachings herein, the drain regrown layer 212d may reduce and/or prevent reach through (punch through) to the drain metallization 113d even if the 2DEG 109 is degraded due to electron trapping.

[0040] Like that of GaN 100a, the P-GaN EPI layer 104 may form a PN junction with N-GaN EPI layer 106. Thus, during high power switching, fewer electrons may be ejected from the 2DEG 109 to become trapped within the GaN buffer layer 102; and as discussed above, this may advantageously reduce and/or mitigate current collapse and the dynamic increase in on resistance.

[0041] Including both a barrier layer (e.g., P-GaN EPI layer 104 and/or N‘-GaN EPI layer 124) and a regrown layer (i.e., drain regrown layer 212d), the GaN HEMT 200b may exhibit superior switching performance compared to GaN HEMT 100a, GaN HEMT 100b, and/or GaN HEMT 200a.

[0042] FIG. 2C illustrates a device cross section of a lateral GaN HEMT 200c according to another embodiment of the present disclosure. GaN HEMT 200c is like GaN HEMT 200b except it uses a shallower drain regrown layer 202d like that of GaN HEMT 200a. As illustrated, the shallower drain regrown layer 202d extends into the N-GaN EPI layer 106 but not into the P-GaN EPI layer 104.

[0043] Having the drain regrown layer 202d d remain within the N-GaN EPI layer 106 may further increase a barrier height (i.e., electron barrier) of the PN-junction as a function of applied drain voltage (i.e., drain-to-source voltage). In turn, this may advantageously allow a higher drain voltage (i.e., a larger drain-to-source voltage) relative to that of GaN HEMT 200b.

[0044] FIG. 3A delineates an axis 300 within the device cross section of the lateral GaN HEMT 200b. Axis 300 is located near the source metallization 113s and extends from a coordinate X0 within the SiN layer 110 to a coordinate X5 within the GaN buffer layer 102. The SiN layer 110 is delineated between coordinate X0 and coordinate XI along axis 300. The AlGaN layer 108 is delineated between coordinate XI and coordinate X2 along axis 300. Additionally, the 2DEG 109 is located at coordinate X2 between the AlGaN layer 108 and the N-GaN EPI layer 106.

[0045] The N-GaN EPI layer 106 is delineated between coordinate X2 and coordinate X3 along axis 300. The N-GaN EPI layer 106 may be an unintentionally doped GaN EPI layer. The unintentional impurities (dopants) may include silicon and/or oxygen. Also, the doping concentration may be between seven times ten to the sixteenth inverse centimeters cubed (7el6 cm-3) and four times ten to the seventeenth inverse centimeters cubed (4el7 cm-3). In addition, the N-GaN EPI layer 106 may have a thickness between zero point one microns (0. lum) and zero point two microns (0.2um).

[0046] The P-GaN EPI layer 104 is delineated between coordinate X3 and coordinate X4 along axis 300. The P-GaN EPI layer 104 may be an intentionally doped GaN EPI layer; and an example of a P-type dopant is carbon. Also, the doping concentration may be between seven times ten to the sixteenth inverse centimeters cubed (7el6 cm-3) and four times ten to the seventeenth inverse centimeters cubed (4el7 cm-3). Additionally, the P-GaN EPI layer 104 may have a thickness between zero point zero five microns (0.05um) and zero point one five microns (0.15um).

[0047] FIG. 3B compares energy bands 301-304 along axis 300. The drain-to-source voltage (i.e., the voltage between the drain metallization 113d and source metallization 113s) is zero volts (0V). The gate-to-source voltage (i.e., the voltage between the gate metallization 114 and source metallization 113s) is zero volts (0 V).

[0048] Energy bands 301-302 may correspond with GaN HEMT 200b. As depicted, energy band 301 is a conduction band 301, and energy band 302 is a valence band 302. Additionally, energy bands 301-302 illustrate the energy barrier associated with a PN-junction formed by P-GaN EPI layer 104 and N-GaN EPI layer 106 of GaN HEMT 200b.

[0049] For comparison, energy bands 303-304 correspond with a device structure like GaN HEMT 200b but excluding the P-GaN EPI layer 104. For instance, the P-GaN EPI layer 104 may be replaced with the same material as N-GaN EPI layer 106. As depicted, energy band 303 is a conduction band 303, and energy band 304 is a valence band 304. In contrast and relative to energy bands 303-304, the PN-junction creates a barrier (i.e., a contact potential) of approximately three-point two electron volts (3.2eV).

[0050] FIG. 4A delineates an axis 400 within the device cross section of a lateral GaN HEMT 200b. Axis 400 is located beneath gate field plate 115 and extends from a coordinate X0 within the SiN layer 110 to a coordinate X5 within the GaN buffer layer 102. The SiN layer 110 is delineated between coordinate X0 and coordinate XI along axis 400. The Al GaN layer 108 is delineated between coordinate XI and coordinate X2 along axis 400. The N-GaN EPI layer 106 is delineated between coordinate X2 and coordinate X3 along axis 400; and the P-GaN EPI layer 104 is delineated between coordinate X3 and coordinate X4 along axis 400.

[0051] FIG. 4B compares energy bands 401-404 along axis 400. The drain-to-source voltage is seven-hundred fifty volts (750V). The gate-to-source voltage is negative fifteen volts (-15V). [0052] Energy bands 401-402 may correspond with GaN HEMT 200b. As shown, energy band 401 is a conduction band 401, and energy band 402 is a valence band 402. Additionally, energy bands 401-402 illustrate the energy barrier associated with a PN-junction formed by P-GaN EPI layer 104 and N-GaN EPI layer 106 when GaN HEMT 200b operates in the blocking state (i.e., operates with a gate-to-source voltage of -15V).

[0053] For comparison, energy bands 403-404 correspond with a device structure like GaN HEMT 200b but excluding the P-GaN EPI layer 104. For instance, the P-GaN EPI layer 104 may be replaced with the same material as N-GaN EPI layer 106. As depicted, energy band 403 is a conduction band 403, and energy band 404 is a valence band 404. In contrast and relative to energy bands 403-404, the PN-junction creates a barrier (i.e., a contact potential) which may advantageously prevent electron transport from the 2DEG 109 to the GaN buffer layer 102.

[0054] FIG. 4C compares and magnifies energy bands 401-404 along axis 400. FIG. 4C is like FIG. 4B except it also shows the energy bands 401-404 between coordinate X0 and coordinate XI along axis 400.

[0055] Reference throughout this specification to "one embodiment", "an embodiment", "one example" or "an example" means that a particular feature, structure or characteristic described in connection with the embodiment or example is included in at least one embodiment of a high electron mobility device structure for robust switching performance. Thus, appearances of the phrases "in one embodiment", "in an embodiment", "one example" or "an example" in various places throughout this specification are not necessarily all referring to the same embodiment or example. Furthermore, the particular features, structures or characteristics may be combined in any suitable combinations and/or subcombinations in one or more embodiments or examples. In addition, it is appreciated that the figures provided herewith are for explanation purposes to persons ordinarily skilled in the art and that the drawings are not necessarily drawn to scale.

[0056] Moreover, conditional language used herein, such as, among others, “can,” “could,” “might,” “may,” “e.g.,” “for example,” “such as” and the like, unless specifically stated otherwise or otherwise understood within the context as used, is generally intended to convey that certain embodiments include, while other embodiments do not include, certain features, elements and/or states. Thus, such conditional language is not generally intended to imply that features, elements and/or states are in any way required for one or more embodiments or that one or more embodiments necessarily include logic for deciding whether these features, elements and/or states are included or are to be performed in any particular embodiment. [0057] The above description of illustrated examples of the present disclosure, including what is described in the Abstract, are not intended to be exhaustive or to be limitation to the precise forms disclosed. While specific embodiments of a high electron mobility device structure for robust switching performance are described herein for illustrative purposes, various equivalent modifications are possible without departing from the broader spirit and scope of the present disclosure. Indeed, it is appreciated that the specific example device cross sections are provided for explanation purposes and that other embodiments may also be employed in accordance with the teachings herein.

Claims

CLAIMS What is claimed is:

1. A lateral high electron mobility transistor (HEMT) comprising: a buffer layer; a two-dimensional electron gas formed between a first layer and a second layer, the first layer disposed above the second layer; a regrown layer in diffusive contact with the first layer and the second layer; and a metallization pattern electrically connected to the regrown layer and configured to receive a drain-to-source voltage, the regrown layer configured to reduce reach-through due, at least in part, to the drain-to-source voltage.

2. The lateral HEMT of claim 1, wherein the drain-to-source voltage varies with time.

3. The lateral HEMT of claim 1, wherein the drain-to-source voltage is greater than five hundred volts (500V).

4. The lateral HEMT of claim 1, wherein the metallization pattern is a drain metallization pattern.

5. The lateral HEMT of claim 1, wherein the regrown layer is an N+ doped gallium nitride layer.

6. The lateral HEMT of claim 1, wherein the first layer comprises aluminum gallium nitride.

7. The lateral HEMT of claim 1, further comprising: a barrier layer disposed between the second layer and the buffer layer such that an energy barrier is formed between the two-dimensional electron gas and the buffer layer.

8. The lateral HEMT of claim 7, wherein the barrier layer forms a PN junction with the second layer.

9. The lateral HEMT of claim 7, wherein the barrier layer forms a high-low junction with the second layer.

10. The lateral HEMT of claim 7, wherein the barrier layer forms a heterojunction with the second layer.

11. The lateral HEMT of claim 7, wherein the second layer is an N-type epitaxial layer grown to have a second layer thickness between point one microns (0. lum) and point two microns (0.2um) and the barrier layer is a P-type epitaxial layer grown to have a barrier layer thickness between point zero five microns (0.05um) and zero point one five microns (0.15um).

12. A semiconductor device comprising: a buffer layer; a two-dimensional electron gas formed between a first layer and a second layer, the first layer disposed above the second layer; a source metallization and a drain metallization electrically coupled with the two- dimensional electron gas and configured to receive a drain-to-source voltage; and a third layer disposed between the second layer and the buffer layer so as to form an energy barrier between the two-dimensional electron gas and the buffer layer while the source metallization and the drain metallization receive the drain-to-source voltage.

13. The semiconductor device of claim 12, wherein the drain-to-source voltage is a time-varying voltage between zero volts (0V) and eight-hundred volts (800V).

14. The semiconductor device of claim 12, wherein the second layer and the third layer form a PN junction.

15. The semiconductor device of claim 14, wherein the PN junction has a contact potential between two electron volts (2eV) and five electron volts (5eV).

16. The semiconductor device of claim 12, wherein the energy barrier is configured to reduce a transport of electrons from the two-dimensional electron gas to the buffer layer.

17. The semiconductor device of claim 16, further comprising a gate metallization including at least one gate field plate.

18. The semiconductor device of claim 17, wherein the energy barrier is configured to reduce the transport of the electrons beneath the at least one gate field plate.

19. The semiconductor device of claim 12, further comprising: a drain regrown layer electrically coupled to the drain metallization and configured to reduce reach-through at the drain metallization.

20. The semiconductor device of claim 19, wherein the drain regrown layer is an N+ doped gallium nitride layer.