WO2025264706A1

WO2025264706A1 - Systems and methods for recovering rf energy using modular resonant circuits

Info

Publication number: WO2025264706A1
Application number: PCT/US2025/034021
Authority: WO
Inventors: Amit Kumar Singh
Original assignee: Lam Research Corp
Current assignee: Lam Research Corp
Priority date: 2024-06-21
Filing date: 2025-06-17
Publication date: 2025-12-26
Anticipated expiration: 2026-12-21

Abstract

Systems and methods for recovering radio frequency (RF) energy using modular resonant circuits are described. One of the systems includes a plurality of modular resonant circuits. Each of the plurality of modular resonant circuits includes a diode, a switch coupled in parallel to the diode to form a parallel circuit, and an inductor coupled in series with the parallel circuit to form a series circuit. The modular resonant circuit includes a capacitor coupled to the inductor through a series diode.

Description

SYSTEMS AND METHODS FOR RECOVERING RF ENERGY USING MODULAR RESONANT CIRCUITS

FIELD

[0001] The embodiments described in the present disclosure relate to systems and methods for recovering radio frequency (RF) energy using modular resonant circuits.

BACKGROUND

[0002] The background description provided herein is for the purposes of generally presenting the context of the disclosure. Work of the presently named inventors, to the extent it is described in this background section, as well as aspects of the description that may not otherwise qualify as prior art at the time of filing, are neither expressly nor impliedly admitted as prior art against the present disclosure.

[0003] In a plasma tool, a radiofrequency generator is coupled to an impedance matching circuit. The impedance matching circuit is coupled to plasma chamber. A wafer is placed within the plasma chamber. After the wafer is placed, the RF generator generates an RF signal, which is supplied to the impedance matching circuit. The impedance matching circuit modifies an impedance of the RF signal and provides the RF signal to the plasma chamber. The RF signal provided to the plasma chamber is used to etch the wafer. However, the wafer is not etched in an efficient manner by the RF signal.

[0004] It is in this context that embodiments described in the present disclosure arise.

SUMMARY

[0005] Embodiments of the disclosure provide systems and methods for recovering radio frequency (RF) energy using modular resonant circuits. The RF energy is used to process a substrate in an efficient manner. It should be appreciated that the present embodiments can be implemented in numerous ways, e g., a process, an apparatus, a system, a piece of hardware, or a method on a computer-readable medium. Several embodiments are described below.

[0006] In one embodiment, a system for recovering RF energy using a plurality modular resonant circuits is described. The system includes the plurality of modular resonant circuits. Each of the plurality of modular resonant circuits includes a diode, a switch coupled in parallel to the diode to form a parallel circuit, and an inductor coupled in series with the parallel circuit to form a series circuit. The modular resonant circuit includes a capacitor coupled to the inductor through a series diode.

[0007] In an embodiment, a system is described. The system includes a controller and a plurality of modular resonant circuits coupled to the controller. Each of the plurality of modular resonant circuits includes a diode, a switch coupled in parallel to the diode to form a parallel circuit, and an inductor coupled in series with the parallel circuit to form a series circuit. The modular resonant circuit includes a capacitor coupled to the inductor through a series diode.

[0008] In an embodiment, a system includes a computer, a plasma chamber, and a charger circuit. The charger circuit is coupled to the computer. The charger circuit generates a pulsed direct current (DC) voltage. The system also includes a resonant inductor coupled to the charger circuit to receive the pulsed DC voltage. The resonant inductor outputs a non-sinusoidal RF voltage based on the pulsed DC voltage. The resonant inductor is coupled to the plasma chamber to provide the non-sinusoidal RF voltage to the plasma chamber. The system includes an energy recovery circuit coupled to the plasma chamber to recover RF energy from the plasma chamber. The energy recovery circuit includes a plurality of modular resonant circuits. Each of the plurality of modular resonant circuits includes a diode, a switch coupled in parallel to the diode to form a parallel circuit, and an inductor coupled in series with the parallel circuit to form a series circuit. The modular resonant circuit includes a capacitor coupled to the inductor through a series diode.

[0009] In an embodiment, the systems and methods recover RF energy for a high voltage (HV) pulsed bias power source. When a power supply of the HV pulsed bias power source delivers RF power to a load, such as a plasma chamber, the power supply also charges the load's stray capacitance, which is sometimes referred to herein as a stray capacitor. The load is an HV load. An example of high voltage is a voltage greater than 3 kilovolts (kV), such as between 3 kV and 35 kV. For a fast generation of an HV pulse of a non-sinusoidal RF voltage, the stray capacitance is discharged periodically within a fall time of the HV pulse. Without energy recovery, RF energy stored in the stray capacitance is dissipated as heat. The systems and methods for recovering RF energy enables the recovery of the RF energy stored in the stray capacitor, which is then fed back to an input of the power supply. This leads to a significant reduction in power consumption and heat dissipation.

[0010] In one embodiment, the systems and methods for recovering RF energy provide a resonant approach that allows for a faster, efficient, and more controlled energy recovery. For example, the RF energy is recovered through resonance, where the stray capacitance of the load resonates with an inductive element, resulting in faster and more energy-efficient recovery. The resonant approach to energy recovery enables fast discharge, leading to a steeper fall time for the HV pulse.

[0011] In an embodiment, the systems and methods for recovering RF energy has a modular structure, including multiple modular resonant circuits to allow the multiple modular resonant circuits to be combined, to further achieve a high voltage and high-power implementation. An example of the modular resonant circuits include low voltage and low power modules. The energy recovery is actively controlled by controlling each low voltage (LV) switch of a respective one of the modular resonant circuits. An example of the low voltage is a voltage less than 2.5 kV, e.g., between 0.1 kV and 2 kV.

[0012] In one embodiment, achieve resistance against variations in switch on/off times of each of the LV switches, a method of balancing a capacitor and an inductor is employed in each of the modular resonant circuits. This method of balancing the capacitor and the inductor reduces chances of, such as prevents, over-voltage across the LV switches, even if the LV switches are not turned on/off simultaneously. Additionally, the method of balancing the capacitor and the inductor makes the modular resonant circuits practically robust and reliable. Moreover, each of the modular resonant circuits operates with low differential voltage and low power, as voltages and power are distributed across the modular resonant circuits.

[0013] In one embodiment, a modular multi-level energy recovery system includes the modular resonant circuits that are connected in series at their inputs and in parallel at their outputs, and then connected in parallel to the load. An output of multi-level energy recovery system is directed to a main DC input through an intermediate isolated DC-to-DC converter. The systems and methods for recovering RF energy provide a modular and multilevel approach to efficiently recover energy for the load.

[0014] Some advantages of the herein described systems and methods for recovering RF energy include achieving an energy recovery with higher efficiency compared to achieved using a transformer-based energy recovery system. For example, a high level of coupling between a primary winding and a secondary winding of a transformer of the transformer-based energy recovery system is utilized to achieve the energy recovery. Moreover, a high level of voltage isolation between the primary and secondary windings of the transformer-based energy recovery system occurs to achieve the energy recovery. Because the systems and methods for recovering RF energy exclude any transformers, there is no need for the high level of coupling to occur between the primary and secondary windings and no need for the isolation. The systems and methods for recovering RF energy, described herein, break a tradeoff between the high level of coupling and the high level of voltage isolation by replacing the primary and secondary windings with an inductor.

[0015] Further advantages of the herein described systems and methods for recovering RF energy include providing isolated direct current-to-direct current (DC-to-DC) converters. A voltage gain of each of the isolated DC-to-DC converters is controlled to optimize an operating point, such as a voltage, that is input to the isolated DC-to-DC converter to achieve higher efficiency in recovering RF energy. [0016] Additional advantages of the herein described systems and methods for recovering RF energy include that there is no change in a fall time of a square-shaped pulse of a non-sinusoidal RF voltage. The change does not occur because each of the isolated DC-to-DC converters is run in an open loop during processing of a substrate. In the open loop, is no measurement of voltage at an output of a respective any of the isolated DC-to-DC converters to control a gain of the isolated DC-to-DC converter.

[0017] Some other aspects will become apparent from the following detailed description, taken in conjunction with the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

[0018] The embodiments are understood by reference to the following description taken in conjunction with the accompanying drawings.

[0019] Figure 1 is a diagram of an embodiment of a system to illustrate recovery of radio frequency (RF) energy using modular resonant circuits.

[0020] Figure 2 is a diagram of an embodiment of a system to illustrate a charger circuit.

[0021] Figure 3 is a diagram of an embodiment of a system to illustrate an ion flux compensation (IFC) circuit.

[0022] Figure 4 is a diagram of an embodiment of a system to illustrate a use of RF energy that is recovered from a plasma chamber of Figure 1.

[0023] Figure 5 includes embodiments of multiple graphs to illustrate voltages and currents within the system of Figure 1.

[0024] Figure 6 is an embodiment of a circuit that illustrates a chamber load and a stray capacitance.

DETAILED DESCRIPTION

[0025] The following embodiments describe systems and methods for recovering radio frequency (RF) energy using modular resonant circuits. It will be apparent that the present embodiments may be practiced without some or all of these specific details. In other instances, well known process operations have not been described in detail in order not to unnecessarily obscure the present embodiments.

[0026] Figure 1 is a diagram of an embodiment of a system 100 to illustrate recovery of the RF energy using modular resonant circuits. The system 100 includes a host computer 102, a charger circuit (ckt.) 104, an ion flux compensation (IFC) circuit 106, a plasma chamber 108, and a magnetic energy recovery (MER) circuit 110.

[0027] Examples of the host computer 102 include a controller, a desktop computer, a laptop computer, a tablet, and a smart phone. An example of the charger circuit 104 is provided below with reference to Figure 2. An example of the IFC circuit 106 is provided below with reference to Figure 3. An example of the plasma chamber 108 is a capacitively coupled plasma (CCP) chamber. To illustrate, the plasma chamber 108, includes a substrate support, such as an electrostatic chuck (ESC), and an upper electrode. A lower electrode is embedded within the substrate support. As an example, the plasma chamber 108 is a high voltage (HV) load. For example, a voltage across the plasma chamber 108 is greater than 3 kilovolts (kV). To illustrate, a voltage between the lower electrode and the upper electrode of the plasma chamber 108 is greater than 3 kV, such as between 3 kV and 35 kV.

[0028] The MER circuit 110 includes one or more modular resonant circuits. For example, the MER circuit 110 includes an modular resonant circuit 1121 and another modular resonant circuit 112n, where n is a positive integer. Each modular resonant circuit 1121 through 112n excludes a transformer, which has a primary winding and a secondary winding. The secondary winding is proximate to the primary winding to be in electromagnetic contact with the primary winding.

[0029] As an example, each of the modular resonant circuits 1121 through 112n is a low voltage (LV) modular resonant circuit, such as a relatively low voltage modular resonant circuit. For example, an operating voltage of each of the modular resonant circuits 1121 through 112n is less than 2.5 kV, e.g., is between 0.1 kV and 2 kV. To illustrate, a voltage across each of the modular resonant circuits 1121 through 112n is the low voltage.

[0030] The modular resonant circuit 112n includes an input to a direct current-to-direct current (DC-to-DC) converter. The input to the DC-to-DC converter is illustrated as a voltage source VSn. Moreover, the modular resonant circuit 112n includes a capacitor Cnb that is coupled in parallel to the voltage source VSn to form a parallel circuit. The modular resonant circuit 112n further includes a diode Dnb that is coupled in series with the parallel circuit having the capacitor Cnb and the voltage source VSn to form a series circuit. For example, a cathode of the diode Dnb is connected to an end of the capacitor Clb and a positive terminal of the voltage source VSn.

[0031] Also, the capacitor Cnb is coupled in parallel to a circuit including the diode Dnb and an inductor Ln. The capacitor Cnb is coupled to the inductor Ln through, such as via, the diode Dnb at one end of the capacitor Cnb and is coupled to the inductor Ln at an opposite end of the capacitor Cnb. The diode Dnb is coupled to the inductor Ln via a ground potential. When the diode Dnb operates in a forward bias mode, the capacitor Cnb is parallel to the inductor Ln.

[0032] The modular resonant circuit 112n includes the inductor Ln that is coupled in parallel to the series circuit having the capacitor Cnb, the voltage source VSn, and the diode Dnb to form a parallel circuit. An anode of the diode Dnb is coupled to the inductor Ln via the ground potential. Also, the modular resonant circuit 112n includes a balancing capacitor Cna, a resistor Rn, a diode Dna, and a switch SWn. An example of a switch, as used herein, includes one or more transistors. For example, a switch, as used herein, includes a single transistor or multiple transistors coupled to each other in series. As an example, the diode Dna or the diode Dnb can be a part of a metal oxide semiconductor field effect transistor (MOSFET) body. To illustrate, the diode Dna is a MOSFET body diode. The diode Dna provides a path for current commutation when the switch SWn is off.

[0033] The switch SWn is coupled in parallel to the diode Dna to form a parallel circuit. For example, a cathode of the diode Dna is connected to one end of the switch SWn and an anode of the diode Dna is connected to another end of the switch SWn to form the parallel circuit. Also, in the example, a voltage across the diode Dna is equal to a voltage across the switch SWn to form the parallel circuit. The parallel circuit having the switch SWn and the diode Dna is coupled in series to the inductor Ln to form a series circuit. For example, the anode of the diode Dna and an end of the switch SWn are connected to an end of the inductor Ln to form the series circuit. The series circuit having the SWn, the diode Dna, and the inductor Ln is coupled in parallel to the capacitor Cna and the resistor Rn to form a parallel circuit. For example, the cathode of the diode Dna and an end of the switch SWn are coupled to one end of the capacitor Can and to one end of the resistor Rn. Also, in the example, an end of the inductor Ln is coupled to another end of the capacitor Can and another end of the resistor Rn. Also, in the example, a voltage across the capacitor Cna is equal to a sum of a voltage across the parallel circuit of the diode Dna and the switch Swn and a voltage across the inductor Ln. The voltage across the capacitor Can is equal to a voltage across the resistor Rn.

[0034] In a similar manner, the modular resonant circuit 1121 includes components, such as a voltage source VS1, a capacitor Clb, a diode Dlb, an inductor LI, a diode Dla, a switch SW1, another capacitor Cla, and a resistor Rl, and the components are coupled to each other in the same manner in which components, such as, the voltage source VSn, the capacitor Cnb, the diode Dnb, the inductor Ln, the diode Dna, the switch SWn, the capacitor Cna, and the resistor Rn, of the modular resonant circuit 112n are coupled to each other. The anode of the diode Dna is coupled to an end of the inductor LI. Each diode Dlb through Dnb is sometimes referred to herein as a series diode.

[0035] As an example, each of the switches SW1 through SWn is a low voltage switch. For example, an operating voltage of each of the switches SW1 through SWn is less than 2.5 kV, e.g., is between 0.1 kV and 2 kV. To illustrate, a voltage across each of the switches SW1 through SWn is the low voltage when the SW1 through SWn are operational, such as open or closed.

[0036] The system 100 further includes a resonant inductor 114, a voltage (V) sensor 116, a diode 118, and a blocking capacitor 120. Also, the host computer 102 includes a processor 122 and a memory device 124. Examples of the processor 122 include a microprocessor, a central processing unit (CPU), an application specific integrated circuit (ASIC), and a programmable logic device (PLD). Examples of the memory device 124 include a read-only memory (ROM) or a random access memory (RAM) or a combination thereof.

[0037] The charger circuit 104 is coupled via an RF connection 126 to a point 128. An example of an RF connection, as used herein, includes one or more RF straps, or one or more RF cables, or a combination thereof. An example of a point includes a connector. Also, the IFC circuit 106 is coupled to the point 128 via an RF connection 130. The point 128 is coupled via an RF connection 132 to the resonant inductor 114. The resonant inductor 114 is coupled to a point 134, which is coupled to the blocking capacitor 120. The blocking capacitor 120 is coupled via an RF connection 136 to the plasma chamber 108. For example, the blocking capacitor 120 is coupled to the lower electrode, and the upper electrode is coupled to a ground potential. The voltage sensor 116 is coupled to the point 134 and to the processor 122. The point 134 is coupled to an anode of the diode 118, and a cathode of the diode 118 is coupled to a cathode of the diode Dla.

[0038] The processor 122 is coupled to the switches SW1 through SWn. For example, the processor 122 is coupled via a connection 1381 to the switch SW1 and via a connection 138n to the switch SWn.

[0039] During a charging phase, the processor 122 controls the charger circuit 104 to generate and send a pulsed DC voltage 140, such as a pulsed DC voltage waveform. For example, the pulsed DC voltage 140 includes multiple DC pulses that repeat at a radio frequency (RF), such as a low frequency. An example of the low frequency is a frequency ranging from and including 100 kilohertz (kHz) to 400 kHz. To illustrate, the low frequency is a frequency of 100 kHz or 400 kHz. The low frequency is different from a high frequency, such as a frequency ranging from 57 megahertz (MHz) to 63 MHz. The pulsed DC voltage 140 is sent via the RF connection 126, the point 128, and the RF connection 132 to the resonant inductor 114. The resonant inductor 114 converts the pulsed DC voltage 140 into a non-sinusoidal RF voltage 142, such as a non-sinusoidal RF voltage waveform, which has RF energy that is transferred via the blocking capacitor 122 to the lower electrode to charge the plasma chamber 108. For example, the plasma chamber 108 acts a capacitor, which is charged by a voltage of the non-sinusoidal RF voltage 142. As another example, the non-sinusoidal RF voltage 142 is output from the resonant inductor 114 to have the same radio frequency as that of the pulsed DC voltage 140 to be based on the pulsed DC voltage 140. As yet another example, the non-sinusoidal RF voltage 142 has multiple square-shaped pulses. Also, during the charging phase, the RF energy of the non- sinusoidal RF voltage 142 is stored within the plasma chamber 108.

[0040] The RF energy of the non-sinusoidal RF voltage 142 that is applied to the lower electrode is used to process a substrate, such as a semiconductor wafer, that is placed on the substrate support. For example, in addition to the RF energy of the non-sinusoidal RF voltage 142, one or more process gases are supplied to the plasma chamber 108 to strike or maintain plasma within the plasma chamber 108. The plasma is used to deposit one or more materials on the substrate, or to etch the substrate, or to clean the substrate, or a combination thereof. The deposition, the etching, the cleaning, and the combination thereof are examples of processing the substrate.

[0041] The charging phase occurs for a fixed amount of dwell time during each RF cycle of the non-sinusoidal RF voltage 142. For example, the processor 122 controls the charger circuit 104 to generate a pulse of the pulsed DC voltage 140 for the fixed amount of dwell time and to generate another pulse of the pulsed DC voltage 140 for the fixed amount of dwell time. A pulse of the pulsed DC voltage 140 repeats at an end of each RF cycle of the non-sinusoidal RF voltage 142. A time period of each RF cycle of the non-sinusoidal RF voltage 142 is based on, such as, for example, is an inverse of, the low frequency. A clock signal having multiple clock cycles that repeat periodically, at the low frequency, is generated by the processor 122 and the pulsed DC voltage 140 is controlled to be generated in synchronization with the clock signal. When the pulsed DC voltage 140 is controlled to be generated in synchronization with the clock signal to have the low frequency, each RF cycle of the non-sinusoidal RF voltage 142 is generated to be in synchronization with a respective clock cycle of the clock signal to have the low frequency. For example, a first RF cycle of the non-sinusoidal RF voltage 142 starts at a first time at which a first clock cycle of the clock signal starts and ends at a second time at which the first clock cycle of the clock signal ends. Also, a second RF cycle of the non-sinusoidal RF voltage 142 starts at the second time at which a second clock cycle of the clock signal starts and ends at a third time at which the second clock cycle of the clock signal ends. The second clock cycle is consecutive to the first clock cycle and the second RF cycle is consecutive to the first RF cycle.

[0042] After the charging phase occurs for the fixed amount of dwell time, voltage at the point 134 increases to be greater than a voltage threshold of the diode 118 and the switches SW1 through SWn are controlled to turn on. As an example, a voltage at the point 134 of the non-sinusoidal RF voltage 142 is the high voltage. When the voltage at the point 134 increases to be greater than the voltage threshold of the diode 118, the diode 118 operates in a forward bias mode and a discharging phase starts during each RF cycle of the non-sinusoidal voltage 142. For example, the processor 122 controls the switches SW1 through SWn to turn on at an end of the fixed amount of dwell time during each RF cycle of the non-sinusoidal RF voltage 142. The switches SW1 through SWn are controlled to turn on in a manner described below.

[0043] At the beginning of the discharging phase, the processor 122 generates and sends on control signals 1461 through 146n to the switches SW1 through SWn. For example, the on control signals 1461 through 146n are output simultaneously from the processor 122 to send to the switches SW1 through SWn to turn on the switches SW1 through SWn simultaneously. To illustrate, the on control signal 1461 is sent via the connection 1381 to the switch SW1 and the on control signal 146n is sent via the connection 138n to the switch SWn. As another example, the on control signals 1461 through 146n are generated and sent at the same time the processor 122 controls the charger circuit 104 to generate the pulsed DC voltage 140.

[0044] During the discharging phase, upon receiving the on control signals 1461 through 146n, the switches SW1 through SWn turn on, such as close. When the switches SW1 through SWn are turned on, the RF energy is recovered from the plasma chamber 108 and the diodes Dlb through Dnb are reverse biased. For example, some of the RF energy is transferred from the plasma chamber 108 via the blocking capacitor 120, the point 134, the diode 118, and the switch SW1 to be stored in the inductor LI. Also, in the example, some of the RF energy is transferred from the plasma chamber 108 via the blocking capacitor 120, the point 134, the diode 118, the switch SW1, the inductor LI, and the switch SWn to be stored in the inductor Ln. In this manner, the RF energy that is recovered from the plasma chamber 108 is stored within the inductors LI through Ln.

[0045] As another example, some of the RF energy is transferred from the plasma chamber 108 via the blocking capacitor 120, the point 134, the diode 118, and the switch SW1 to be stored in the inductor LI. The RF energy is also transferred from the plasma chamber 108 via the blocking capacitor 120, the point 134, the diode 118, and the switch SW1 to be stored in the capacitor Clb and the RF energy stored in the capacitor Clb. In the example, the RF energy resonates between the inductor LI and the capacitor Clb to be stored within the inductor LI and the capacitor Clb. When the switch SW1 is turned on, the diode Dlb operates in a reverse bias mode and the inductor LI is energized. Also, in the example, some of the RF energy is transferred from the plasma chamber 108 via the blocking capacitor 120, the point 134, the diode 118, the switch SW1, the inductor LI, and the switch SWn to be stored in the inductor Ln. The RF energy is also transferred from the plasma chamber 108 via the blocking capacitor 120, the point 134, the diode 118, the switch SW1, the inductor LI, and the switch SWn to be stored in the capacitor Cnb. In the example, the RF energy resonates between the inductor Ln and the capacitor Cnb to be stored within the inductor Ln and the capacitor Cnb. When the switch SWn is turned on, the diode Dnb operates in a reverse bias mode and the inductor Ln is energized. In this manner, the RF energy that is recovered from the plasma chamber 108 is stored as resonant energy within the inductors LI through Ln and the capacitors Clb through Cnb.

[0046] Further, during the discharging phase, the processor 122 generates and sends off control signals 1481 through 148n to the switches SW1 through SWn. For example, the off control signals 1481 through 148n are output simultaneously from the processor 122 to send to the switches SW1 through SWn to turn off the switches SW1 through SWn simultaneously. To illustrate, the off control signal 1481 is sent via the connection 1381 to the switch SW1 and the off control signal 148n is sent via the connection 138n to the switch SWn. To further illustrate, the voltage sensor 116 generates a voltage measurement signal 144 and sends the voltage measurement signal 144 to the processor 122. The voltage measurement signal 144 includes a measurement of a voltage of the non-sinusoidal RF voltage 142 at the point 134. The processor 122 determines, from the voltage measurement signal 144, whether the measurement of the voltage at the point 134 is less than a predetermined threshold. When the voltage at the point 134 is less than the predetermined threshold, the switches Swl to Swn are turned off and therefore, the diode 118 becomes reverse biased and the MER circuit 110 is electrically disconnected from the plasma chamber 108..

[0047] During the discharging phase, upon receiving the off control signals 1481 through 148n, the switches SW1 through SWn turn off, such as open. When the switches SW1 through SWn are turned off, the diodes Dlb through Dnb are forward biased and the RF energy stored in the inductors LI through Ln or the capacitors Clb through Cnb or a combination of the inductors LI through Ln and the capacitors Clb through Cnb is transferred via the voltage sources VS1 through VSn to the charger circuit 104. For example, the RF energy stored in the inductor LI is transferred via the diode Dlb and the voltage source VS1 to the charger circuit 104. As another example, the RF energy stored in the inductor Ln is transferred via the diode Dnb and the voltage source VSn to the charger circuit 104. As still another example, the RF energy stored in the capacitor Clb or a combination of the inductor LI and the capacitor Clb is transferred via the voltage source VS1 to the charger circuit 104. As another example, the RF energy stored in the capacitor Cnb or a combination of the inductor Ln and the capacitor Cnb is transferred via the voltage source VSn to the charger circuit 104.

[0048] It should be noted that there is a higher voltage created by the RF energy at a positive terminal of the voltage source VS1 compared to a negative terminal of the voltage source VS1. For example, because the RF energy from the plasma chamber 108 flows from the capacitor Clb to the positive terminal of the voltage source VS1 and from the inductor LI via the diode Dlb to the positive terminal of the voltage source VS1, the positive terminal of the voltage source VS1 has the higher voltage than that of the negative terminal of the voltage source VS1. Similarly, there is a higher voltage created by the RF energy at a positive terminal of the voltage source VSn compared to a negative terminal of the voltage source VSn. For example, because the RF energy from the plasma chamber 108 flows from the capacitor Cnb to the positive terminal of the voltage source VSn and from the inductor Ln via the diode Dnb to the positive terminal of the voltage source VSn, the positive terminal of the voltage source VSn has the higher voltage than that of the negative terminal of the voltage source VSn.

[0049] The blocking capacitor 120 provides capacitive isolation between the plasma chamber 108 and the charger circuit 104. Also, the blocking capacitor 120 blocks DC voltage.

[0050] It should be noted that when the switch SW1 is closed, the diode Dla is parallel to a short circuit created by the switch SW1 and current which recovers energy from the load flows through the switch SW1. The diode Dla does not carry current. Similarly, when the switch SWn is closed, the diode Dna is parallel to a short circuit created by the switch SWn and the current which recovers energy from the load flows through the switch SWn while the diode Dna does not carry any current.

[0051] Also, an LC circuit, such as one including the inductor Ln and the capacitor Cna, is a resonant circuit that protects the switch SWn. For example, when the switch SWn is turned on before the switch SW1 is turned on in response to receiving the on control signals 1461 and 146n, a resonance that is created by a combination of the inductor Ln and the capacitor Cna results in a slow change in a voltage across the switch SWn. This slow change allows for time for the switch SW1 to turn on in response to the on control signal 1461. As such, the switch SWn is protected from failure, which can result from receiving the high voltage from the RF energy recovered from the plasma chamber 108. As another example, when the switch SWn is turned off after the switch SW 1 is turned off in response to receiving the off control signals 1481 through 148n from the processor 122, a resonance that is created by a combination of the inductor Ln and the capacitor Cna results in a slow change in a voltage across the switch SWn. This slow change allows for time for the switch SWn to turn off in response to the off control signal 1481. Accordingly, the switch SWn is protected from the failure. Similarly, an LC circuit, such as one including the inductor LI and the capacitor Cl a, is a resonant circuit that protects the switch SW 1.

[0052] Also, the resistor Rn is a bleeder register or a damper resistor that allows for discharge of energy that is stored in the capacitor Cna. For example, energy that is stored in the capacitor Cna is discharged by the resistor Rn to protect the capacitor Cna. Similarly, the resistor R1 is a bleeder register or a damper resistor that allows for discharge of energy that is stored in the capacitor Cl a.

[0053] Upon determining that the voltage measurement signal 144 is less than the predetermined threshold based on the voltage measurement signal 144, the processor 122 controls the IFC circuit 106 to provide ion flux compensation until an end of each RF cycle of the non-sinusoidal voltage 142. In this manner, the charging phase, the discharging phase, and the ion flux compensation repeat at each additional RF cycle of the non-sinusoidal voltage 142.

[0054] In one embodiment, the resistors R1 through Rn are optional and not included. For example, the modular resonant circuit 112n excludes the resistor Rn.

[0055] In an embodiment, the MER circuit 110 excludes the capacitors Clb through Cnb. For example, the voltage source VSn is connected to the cathode of the diode Dnb and to an end of the inductor Ln without being connected in parallel to the capacitor Cnb.

[0056] Figure 2 is a diagram of an embodiment of a system 200 to illustrate a charger circuit 202. The charger circuit 202 is an example of the charger circuit 104 (Figure 1). The charger circuit 202 includes a voltage source 204, a switch 206, and a diode 208. The voltage source 204 is coupled in series with the switch 206, which is coupled in series with the diode 208. The diode 208 is coupled to the point 128 via the RF connection 126.

[0057] The processor 122 is coupled to the switch 206 and to the voltage source 204. At the beginning of the charging phase of each RF cycle of the non-sinusoidal voltage 142, the processor 122 controls the switch 206 to turn on, such as close, the switch 206 for the fixed amount of dwell time. For example, the processor 122 sends an on control signal to the switch 206 to close the switch 206. When the switch 206 is closed, the pulsed DC voltage 140 is generated via the switch 206 and the diode 208, which operates in a forward bias mode, to the point 128.

[0058] At an end of the charging phase, such as, for example, after the fixed amount of dwell time has passed, during each RF cycle of the non-sinusoidal voltage 142, the processor 122 controls the switch 206 to turn off, such as open, the switch 206. For example, the processor 122 sends an off control signal to the switch 206 to open the switch 206. The processor 122 controls the switch 206 to turn off during each RF cycle of the non-sinusoidal voltage 142 until an immediately following RF cycle, such as a next RF cycle, of the non-sinusoidal voltage 142 occurs. When the switch 206 is open, the pulsed DC voltage 140 is not generated at the point 128 via the switch 206.

[0059] Figure 3 is a diagram of an embodiment of a system 300 to illustrate an IFC circuit 302. The IFC circuit 302 is an example of the IFC circuit 106 (Figure 1). The IFC circuit 302 includes a voltage source 304, a switch 306, and a resistor-inductor-diode (RLD) circuit 308. The RLD circuit 308 includes a resistor 310, an inductor 312 and a diode 314. Also, the IFC circuit 302 includes a diode 316.

[0060] The voltage source 304 is coupled in series to the switch 306. The resistor 310 is coupled in series to the inductor 312 to form a series circuit, which is coupled in parallel to the diode 314 to form a parallel circuit. The parallel circuit, which is the RLD circuit 308, is coupled in series to the switch 306 and in series to the diode 316. The diode 316 is coupled via the RF connection 130 to the point 128. Also, the processor 122 is coupled to the switch 306 and the voltage source 304.

[0061] At an end of the discharging phase, during each RF cycle of the non-sinusoidal voltage 142, the processor 122 determines whether the voltage, at the point 134 (Figure 1), indicated within the measurement signal 144 is less than the predetermined threshold. Upon determining that the voltage, at the point 134, is less than the predetermined threshold, the processor 122 sends an on control signal to the switch 306 to turn on, such as close, the switch 306. When the switch 306 is closed, a current signal 318 is output from the voltage source 304. As an example, the current signal 318 is a negative current that flows to the voltage source 304.

[0062] The current signal 318 is supplied from the voltage source 304 via the switch 306, the RLD circuit 308, the diode 316, and the RF connection 130 to the point 128 to control a slope of a ramp, such as a ramp portion, of the non-sinusoidal RF voltage 142 (Figure 1). For example, the processor 122 sends a control signal to the voltage source 304 to control an amount of voltage that is output from the voltage source 304 to further control a magnitude of the current signal 318. The magnitude of the current signal 318 is controlled control the slope of the ramp during an ion flux compensation phase, which occurs within a time period of each RF cycle of the non-sinusoidal voltage 142. It should be noted that during each RF cycle of the non- sinusoidal voltage 142, the ramp occurs between the discharging phase within the RF cycle and the charging phase within a next RF cycle, such as an immediately following RF cycle, of the non-sinusoidal voltage 142. As such, during each RF cycle of the non-sinusoidal voltage 142, the charging phase, the discharging phase, and the ion flux compensation phase occur.

[0063] Figure 4 is a diagram of an embodiment of a system 400 to illustrate a use of RF energy that is recovered from the plasma chamber 108 (Figure 1). The system 400 includes a voltage source 402, isolated DC-to-DC power supplies 4041 through 404n, multiple diodes 4061 through 406n, and a diode 408. The system 400 includes a voltage sensor 410. The voltage source 402 is an example of the voltage source 204 (Figure 2). Also, the system 400 includes a voltage source 401, which is an example of the voltage source 304 (Figure 3). The system 400 further includes a voltage sensor 403 and another voltage sensor 405. [0064] The isolated DC-to-DC power supply 4041 includes inputs Il l and 121 and outputs Oi l and 021. The output Oi l is a positive terminal and the output 021 is a negative terminal. The input Il l is coupled to the positive terminal of the voltage source VS1 and the input 121 is coupled to the negative terminal of the voltage source VS1. Similarly, the isolated DC-to-DC power supply 404n includes inputs Iln and I2n and outputs Oln and O2n. The output Oln is a positive terminal and the output O2n is a negative terminal. The input Iln is coupled to the positive terminal of the voltage source VSn and the input I2n is coupled to the negative terminal of the voltage source VSn. The outputs Oi l through Oln are coupled to each other in parallel and the outputs 021 through O2n are also coupled each other in parallel. For example, when each of the diodes 4061 through 406n operates in a forward bias mode, the outputs Oi l through Oln are coupled to each other in parallel.

[0065] It should be noted that a negative terminal of a supply system, such as a voltage source or a power source or a voltage supply or a power supply, has a lower voltage than a positive terminal of the supply system. For example, the negative terminal of the isolated DC- to-DC power supply 404n has a lower voltage than a voltage of the positive terminal of the isolated DC-to-DC power supply 404n. To illustrate, a voltage at a negative terminal is a ground potential.

[0066] The isolated DC-to-DC power supply 4041 is coupled in parallel to the capacitor Clb (Figure 1). For example, the input II 1 is coupled to one end of the capacitor Clb and the input 121 is coupled to an opposite end of the capacitor Clb. In the example, a voltage across the capacitor Clb is equal to a voltage across the isolated DC-to-DC power supply 4041. Similarly, the isolated DC-to-DC power supply 404n is coupled in parallel to the capacitor Cnb (Figure 1). For example, the input Iln is coupled to one end of the capacitor Cnb and the input I2n is coupled to an opposite end of the capacitor Cnb. In the example, a voltage across the capacitor Cnb is equal to a voltage across the isolated DC-to-DC power supply 404n.

[0067] The voltage source 402 includes an alternating current (AC) voltage source 412, an AC-to-DC converter 414, and a high-voltage (HV) source 416. An example of the AC voltage source 412 is an AC voltage supply. The AC-to-DC converter 414 has an output Oa and another output Ob. The HV source 416 has an input la and another input lb.

[0068] The voltage source 401 includes the AC voltage source 412, the AC-to-DC converter 414, and an HV source 418. The HV source 418 has an input Ic and another input Id. Each HV source 416 and 418 includes multiple HV power supplies.

[0069] The output Ol l is coupled to an anode of the diode 4061 and a cathode of the diode 4061 is coupled to an anode of the diode 408. Similarly, the output Oln is coupled to an anode of the diode 406n and a cathode of the diode 406n is coupled to the anode of the diode 408. A cathode of the diode 408 is coupled to the output Oa, a point Poutl, the input la, and the input Ic. Also, the output 021 is coupled to the input lb and the input Id. The input lb is coupled to the input Id. The output Ob is coupled via a point Pout2 to the input lb and the input Id. Also, the output Oa is coupled via the point Poutl to the input la and the input Ic.

[0070] The voltage sensor 410 is coupled to the point Poutl . Also, the voltage sensor 410 is coupled to the point Pout2. The voltage sensor 410 is coupled to the processor 122. The voltage sensor 403 is coupled to the outputs 011 and 021, and to the processor 122. The voltage sensor 405 is coupled to the outputs Oln and O2n, and to the processor 122.

[0071] The processor 122 is coupled to each of the isolated DC-to-DC power supplies 4041 through 404n for gain control. A positive output, such as a positive terminal, of the HV source 416 is coupled to the switch 206 and a negative output, such as a negative terminal, of the HV source 418 is coupled to the switch 306.

[0072] As an example, the isolated DC-DC power supply 4041 includes multiple HV power supplies, such as DC power supplies or voltage power supplies, that convert, such as increase or decrease, a DC voltage between the input H l, such as a positive terminal, and the input 121, such as a negative terminal, of the isolated DC-DC power supply 4041 from one amount to another amount. To illustrate, the HV power supplies of the isolated DC-DC power supply 4041 have inputs that are coupled in series and have outputs that are coupled in parallel. To illustrate, the HV power supplies of the isolated DC-DC power supply 4041 include a first power supply, a second power supply, and a third power supply coupled to each other. The negative terminal of the voltage source VS1 is coupled to a first input of the first power supply, a first input of the second power supply, and a first input of the third power supply. The first inputs are coupled to each other to form the input 121. Also, second inputs of the first, second, and third power supplies are coupled to the positive terminal of the voltage source VS1 and to each other to form the input Il l. A first output of the first power supply is coupled to a first output of the second power supply and the first output of the second power supply is coupled to a first output of the third power supply to form the output Oi l. Also, second outputs of the first through third power supplies are coupled to each other to form the output 021. Each of the first through third HV power supplies of the isolated DC-to-DC power supply 4041 has a respective enable input. The enable inputs of the HV power supplies of the isolated DC-to-DC power supply 4041 are coupled to the processor 122.

[0073] As another example, the isolated DC-to-DC power supply 404n includes multiple HV power supplies, such as DC power supplies or voltage power supplies, that convert, such as increase or decrease, a DC voltage between the input Iln, such as a positive terminal, and the input I2n, such as a negative terminal, of the isolated DC-DC power supply 4041 from one amount to another amount. To illustrate, the HV power supplies of the isolated DC-DC power supply 404n have inputs that are coupled in series and have outputs that are coupled in parallel. To illustrate, the HV power supplies of the isolated DC-DC power supply 404n include a first power supply, a second power supply, and a third power supply coupled to each other. The negative terminal of the voltage source VSn is coupled to a first input of the first power supply, a first input of the second power supply, and a first input of the third power supply. The first inputs are coupled to each other to form the input I2n. Also, second inputs of the first, second, and third power supplies are coupled to each other and to the positive terminal of the voltage source VSn to form the input Iln. A first output of the first power supply is coupled to a first output of the second power supply and the first output of the second power supply is coupled to a first output of the third power supply to form the output Oln. Also, second outputs of the first through third power supplies are coupled to each other to form the output O2n. Each of the first through third HV power supplies of the isolated DC-to-DC power supply 404n has a respective enable input. The enable inputs of the HV power supplies of the isolated DC-to-DC power supply 404n are coupled to the processor 122.

[0074] As an example, the HV source 416 includes multiple HV power supplies and the HV source 418 includes multiple HV power supplies. Enable inputs of the HV power supplies of the HV source 416 are coupled to the processor 122. Also, enable inputs of the HV power supplies of the HV source 418 are coupled to the processor 122.

[0075] The processor 122 controls the isolated DC-to-DC power supply 4041 to modify, such as increase or decrease, the voltage received between the inputs Il l and 121 to output a voltage between the outputs Oi l and 021. The voltage between the inputs Il l and 121 is modified based on a gain control signal 4201 that is received from the processor 122. For example, the gain control signal 4201 indicates amounts of pulse width modulation or amounts of variable frequency modulation or a combination thereof of voltage that is output from the HV supplies of the DC-to-DC power supply 4041. To illustrate, when the gain control signal 4201 includes a first primary amount of pulse width modulation to modify a voltage output from a first HV power supply of the isolated DC-to-DC power supply 4041 to have a first primary duty cycle of the first primary amount and includes a second primary amount of pulse width modulation to modify a voltage output from a second HV power supply of the isolated DC-to- DC power supply 4041 to have a second primary duty cycle of the second primary amount, a first primary gain, such as a modification, of the voltage received between the inputs 111 and 121 is achieved. Alternatively, when the gain control signal 4201 includes a third primary amount of pulse width modulation to modify a voltage output from the first HV power supply of the isolated DC-to-DC power supply 4041 to have a third primary duty cycle of the third primary amount and includes a fourth primary amount of pulse width modulation to modify a voltage output from the second HV power supply of the isolated DC-to-DC power supply 4041 to have a fourth primary duty cycle of the fourth primary amount, a second primary gain, such as a modification, of the voltage received between the inputs II 1 and 121 is achieved. In the example, when the first primary amount is greater than the third primary amount and the second primary amount is greater than the fourth primary amount, the first primary gain is greater than the second primary gain to increase the voltage between the inputs II 1 and 121. The voltage between the inputs II 1 and 121 is increased by the first primary gain or the second primary gain to output the voltage between the outputs Oi l and 021.

[0076] Similarly, the processor 122 controls the isolated DC-to-DC power supply 404n to modify, such as increase or decrease, the voltage received between the inputs Iln and I2n to output a voltage between the outputs Oln and O2n. The voltage between the inputs Iln and I2n is modified based on a gain control signal 420n that is received from the processor 122. For example, the gain control signal 420n indicates amounts of pulse width modulation or amounts of variable frequency modulation or a combination thereof of voltage that is output from the HV supplies of the DC-to-DC power supply 404n. To illustrate, when the gain control signal 420n includes a first secondary amount of pulse width modulation to modify a voltage output from a first HV power supply of the isolated DC-to-DC power supply 404n to have a first secondary duty cycle of the first secondary amount and includes a second secondary amount of pulse width modulation to modify a voltage output from a second HV power supply of the isolated DC-to- DC power supply 404n to have a second secondary duty cycle of the second secondary amount, a first secondary gain, such as a modification, of the voltage received between the inputs Iln and I2n is achieved. Alternatively, when the gain control signal 420n includes a third secondary amount of pulse width modulation to modify a voltage output from the first HV power supply of the isolated DC-to-DC power supply 404n to have a third secondary duty cycle of the third secondary amount and includes a fourth secondary amount of pulse width modulation to modify a voltage output from the second HV power supply of the isolated DC-to-DC power supply 404n to have a fourth secondary duty cycle of the fourth secondary amount, a second secondary gain, such as a modification, of the voltage received between the inputs Iln and I2n is achieved. In the example, when the first secondary amount is greater than the third secondary amount and the second secondary amount is greater than the fourth secondary amount, the first secondary gain is greater than the second secondary gain to increase the voltage between the inputs Iln and I2n. The voltage between the inputs Iln and I2n is increased by the first secondary gain or the second secondary gain to output the voltage between the outputs Oln and O2n. [0077] The voltage between the outputs Oi l and 021 is controlled by the processor 122, by applying a gain, such as the first primary gain or the second primary gain, to the voltage between the outputs Il l and 121 until the voltage between the outputs Oi l and 021 is greater than a voltage between the inputs la and Id. For example, the voltage sensor 410 measures voltages at the points Poutl and Pout2 to generate a voltage measurement signal 422. The voltage measurement signal 422 includes the voltages measured at the inputs la and lb. The voltage measured at the point Poutl is equal to the voltage measured at the input la and the voltage measured at the point Pout2 is equal to the voltage measured at the input lb. Also, in the example, the voltage sensor 403 measures voltages at the outputs Oi l and 021 to generate a voltage measurement signal 424. Upon receiving the voltage measurement signals 422 and 424, the processor 122 calculates a first primary voltage, which is a difference between the voltages measured at the points Poutl and Pout2, and calculates a second primary voltage, which is a difference between the voltages measured at the outputs Oi l and 021. The processor 122 determines whether the second primary voltage is greater than the first primary voltage. Upon determining that the second primary voltage is not greater than the first primary voltage, the processor 122 controls, such as increases, the gain of the isolated DC-to-DC power supply 4041 until the second primary voltage is greater than the first primary voltage. On the other hand, upon determining that the second primary voltage is greater than the first primary voltage, the processor 122 maintains the gain of the isolated DC-to-DC power supply 4041.

[0078] Similarly, the voltage between the outputs Oln and O2n is controlled by the processor 122, by applying a gain, such as the first secondary gain of the second secondary gain, to the voltage between the outputs Un and I2n until the voltage between the outputs Oln and O2n is greater than a voltage between the inputs Ic and Id. For example, the voltage sensor 410 measures voltages at the points Poutl and Pout2 to generate the voltage measurement signal 422. The voltage measurement signal 422 includes the voltages measured at the inputs Ic and Id. The voltage measured at the point Poutl is equal to the voltage measured at the input Ic and the voltage measured at the point Pout2 is equal to the voltage measured at the input Id. Also, in the example, the voltage sensor 405 measures voltages at the outputs Oln and O2n to generate a voltage measurement signal 426. Upon receiving the voltage measurement signals 422 and 426, the processor 122 calculates a first secondary voltage, which is a difference between the voltages measured at the points Poutl and Pout2, and calculates a second secondary voltage, which is a difference between the voltages measured at the outputs Oln and O2n. The processor 122 determines whether the second secondary voltage is greater than the first secondary voltage. Upon determining that the second secondary voltage is not greater than the first secondary voltage, the processor 122 controls, such as increases, the gain of the isolated DC-to-DC power supply 404n until the second secondary voltage is greater than the first secondary voltage. On the other hand, upon determining that the second secondary voltage is greater than the first secondary voltage, the processor 122 maintains the gain of the isolated DC-to-DC power supply 404n.

[0079] When the voltage between the outputs Oi l and 021 is greater than the voltage between the inputs la and lb, the diodes 4061 and 408 are forward biased and voltage between the outputs Oi l and 021 is applied between the inputs la and lb of the HV source 416. Similarly, when the voltage between the outputs Oln and O2n is greater than the voltage between the inputs Ic and Id, the diodes 406n and 408 are forward biased and voltage between the outputs Oln and O2n is applied between the inputs Ic and Id of the HV source 418.

[0080] It should be noted that the diodes 4061 and 408 reduce chances of power being reflected from the HV source 416 to the isolated DC-to-DC power supply 4041. For example, when the voltage between the inputs la and lb is greater than the voltage between the outputs Oi l and 021, the diodes 4061 and 408 are reverse biased between the output Oi l and the input la to prevent the power being reflected from the HV source 416 to the isolated DC-to-DC power supply 4041. Similarly, it should be noted that the diodes 406n and 408 reduce chances of power being reflected from the HV source 416 to the isolated DC-to-DC power supply 404n. For example, when the voltage between the inputs Ic and Id is greater than the voltage between the outputs Oln and O2n, the diodes 406n and 408 are reverse biased between the output Oln and the input Ic to prevent the power being reflected from the HV source 416 to the isolated DC-to- DC power supply 404n.

[0081] The AC voltage source 412 outputs an AC voltage , such as an AC voltage waveform, to the AC-to-DC converter 414. Upon receiving the AC voltage, the AC-to-DC converter 414 converts the AC voltage into a DC voltage, such as a DC voltage waveform, that is provided between the outputs Oa and Ob. The DC voltage provided between the outputs Oa and Ob is modified, such as increased, to the voltage between the points Poutl and Pout2.. The voltage that is between the points Poutl and Pout2 and that is generated from the RF energy recovered from the plasma chamber 108 modifies the DC voltage provided between the outputs Oa and Ob. Similarly, the DC voltage provided between the outputs Oa and Ob is modified, such as increased, to the voltage between the inputs Ic and Id. As such, the voltage that is between the inputs Ic and Id and that is generated from the RF energy recovered from the plasma chamber 108 modifies the DC voltage provided between the outputs Oa and Ob.

[0082] The processor 122 controls the HV source 416 to modify, such as increase or decrease, the voltage between the inputs la and lb to output a voltage at the positive terminal of the HV source 416. For example, processor 122 enables a first number of one or more of the HV power supplies of the HV source 416 and disables a second number of remaining ones of the HV power supplies of the HV source 416 to increase the voltage received between the inputs la and lb by a first amount to output a first voltage at the positive terminal of the HV source 416. In the example, the processor 122 enables a third number of one or more of the HV power supplies of the HV source 416 and disables a fourth number of remaining ones of the HV power supplies of the HV source 416 to increase the voltage received between the inputs la and lb by a second amount to output a second voltage at the positive terminal of the HV source 416. Further, in the example, when the first number is greater than the third number, the second number is less than the fourth number and the first amount is greater than the second amount. On the other hand, when the first number is less than the third number, the second number is greater than the fourth number and the first amount is less than the second amount.

[0083] Similarly, the processor 122 controls the HV source 418 to modify, such as increase or decrease, the voltage between the inputs Ic and Id to output a voltage at a negative terminal of the HV source 418. For example, processor 122 enables a first number of one or more of the HV power supplies of the HV source 418 and disables a second number of remaining ones of the HV power supplies of the HV source 418 to decrease the voltage received between the inputs Ic and Id by a first amount to output a first voltage at the negative terminal of the HV source 418. In the example, it should be noted that each of the HV power supplies of the HV source 418 output a negative voltage. In the example, the processor 122 enables a third number of one or more of the HV power supplies of the HV source 418 and disables a fourth number of remaining ones of the HV power supplies of the HV source 418 to decrease the voltage received between the inputs Ic and Id by a second amount to output a second voltage at the negative terminal of the HV source 418. Further, in the example, when the first number is greater than the third number, the second number is less than the fourth number and the first amount is lower than the second amount. On the other hand, when the first number is less than the third number, the second number is greater than the fourth number and the first amount is greater than the second amount.

[0084] In one embodiment, there is no use of the voltage sensors 410, 403, and 405 in the system 400 during processing of the substrate within the plasma chamber 108. For example, multiple gains, such as the first primary gain or the second primary gain and the first secondary gain or the second secondary gain, of the isolated DC-to-DC power supplies 4041 through 404n are determined by the processor 122 in the manner described above before processing the substrate until voltage between the outputs Oi l and 021 is greater than a voltage between the inputs la and lb or Ic and Id. To illustrate, the gains of the isolated DC-to-DC power supplies 4041 through 404n are determined when a dummy substrate is placed in the plasma chamber 108. Then, when the substrate is placed within the plasma chamber 108 for processing, the processor 122 controls the isolated DC-to-DC power supplies 4041 through 404n to achieve the gains without connecting the voltage sensors 410, 403, and 405 in the system 400. As such, open loop control of the isolated DC-to-DC power supplies 4041 through 404n is achieved.

[0085] As another example, a gain, such as the first secondary gain or the second secondary gain, is determined by the processor 122 in the manner described above before processing the substrate until voltage between the outputs Oln and O2n is greater than a voltage between the inputs la and lb or Ic and Id. To illustrate, the gain, such as the first secondary gain or the second secondary gain, is determined when the dummy substrate is placed in the plasma chamber 108. Then, when the substrate is placed within the plasma chamber 108 for processing, the processor 122 controls the isolated DC-to-DC power supply 404n to achieve the gain, such as the first secondary gain or the second secondary gain, without connecting the voltage sensors 410, 403, and 405 in the system 400.

[0086] Figure 5 includes embodiments of a graph 500, a graph 502, a graph 504, a graph 506, and a graph 508 to illustrate voltages and currents within the system 100 (Figure 1). The graph 500 plots a voltage on a y-axis and time t on an x-axis. Similarly, the graph 502 plots a voltage on a y-axis and the time t on an x-axis, and the graph 504 plots a voltage on a y-axis and the time t on an x-axis. The graph 506 plots a current on a y-axis and the time t on an x-axis. Similarly, the graph 508 plots a current on a y-axis and the time t on an x-axis.

[0087] The graph 500 includes a plot 510 to illustrate a voltage of the non-sinusoidal RF voltage 142 (Figure 1). As illustrated, the voltage of the non-sinusoidal RF voltage 142 does not have a sinusoidal shape. During each RF cycle, such as an RF cycle 1, an RF cycle 2, and an RF cycle 3 of the non-sinusoidal voltage 142, the plot 510 includes a square-shaped pulse followed by a ramp portion, which is illustrated as being horizontally oriented. To further illustrate, during the RF cycle 1, the voltage of the non-sinusoidal RF voltage 142 includes a square-shaped pulse 512, which is immediately followed by a ramp portion 514. In the further illustration, the ramp portion 514 has a slope of substantially zero, such as zero, to be horizontally oriented.

[0088] During each RF cycle of the non-sinusoidal voltage 142, the plot 510 has the charging phase, the discharging phase, and the ion flux compensation phase. For example, the plot 510 transitions, during the RF cycle 1, from a low level of zero volts, to a high level of 30 kV during the charging phase. Moreover, in the example, the plot 510 transitions from the high level to the low level during the discharging phase, which occurs during the RF cycle 1. After the transition to the low level, during the RF cycle 1, the plot 510 remains horizontally oriented for a time period of the ion flux compensation phase. In this manner, the plot 510 transitions from the low level to the high level and further transitions from the high level to the low level to remain at the low level for the time period of the ion flux compensation phase at each RF cycle of the non-sinusoidal voltage 142 to repeat the charging phase, the discharging phase, and the ion flux compensation phase.

[0089] The graph 502 includes a plot 516 of a sheath of plasma formed within the plasma chamber 108 (Figure 1) when the non-sinusoidal RF voltage 142 (Figure 1) is applied to the plasma chamber 108. It should be noted that a shape of the plot 516 is similar to, such as the same as, a shape of the voltage of the non-sinusoidal RF voltage 142. For example, the voltage of the plasma sheath has a square-shaped pulse immediately followed by a ramp portion during each RF cycle of the non-sinusoidal voltage 142.

[0090] The graph 504 includes a plot 518 of a voltage across each of the switches SW1 through SWn (Figure 1) of the MER circuit 110. As illustrated by the plot 518, during each RF cycle of the non-sinusoidal voltage 142, the voltage across any of the switches SW1 through SWn has a square-shaped pulse, which precedes a ramp portion of the voltage.

[0091] The graph 506 includes a plot 520 of an energy recovery current to illustrate a storage of the RF energy recovered from the plasma chamber 108 (Figure 1) into one of the inductors LI through Ln (Figure 1) and a transfer of the RF energy stored within the inductor via one of the respective voltage sources VS1 through VSn (Figure 1), the isolated DC-to-DC power supply 404n (Figure 4), the diode 406n, and the diode 408 to the HV sources 416 and 418 (Figure 4).

[0092] It should be noted, based on a relationship between the plots 518 and 520 immediately after a time at which the voltage across one of the switches SW1 through SWn of a respective one of the modular resonant circuits 1121 through 112n decreases from a high voltage level, such as 7.2 kV, to a low voltage level, such as 0 kV, the energy recovery current flows into one of the inductors LI through Ln of the modular resonant circuit. For example, at a time the switch SWn closes, a voltage across the switch SWn transitions from 7.2 kV to zero kV, and there is a sharp increase in the energy recovery current flowing to the inductor Ln from the plasma chamber 108.

[0093] After the RF energy from the plasma chamber 108 is stored in the inductor Ln, the switch SWn is controlled by the processor 122 (Figure 1) to open. When the switch SWn is open, the RF energy that is stored in the inductor Ln is transferred via the diode Dnb, the voltage source VSn, the isolated DC-to-DC power supply 404n, the diode 406n, and the diode 408 to the HV sources 416 and 418.

[0094] The graph 508 includes a plot 522 to illustrate a charging current, such as a resonant current, of the non-sinusoidal RF voltage 142 (Figure 1). The charging current charges the plasma chamber 108 with the RF energy [0095] Figure 6 is an embodiment of a circuit 600 that illustrates a chamber load, such as a plasma chamber 108 (Figure 1). The plasma chamber 108 has a stray capacitance 602. The circuit 600 includes a first portion 606, a second portion 608, and a third portion 608. The first portion 606 represents the ESC, the second portion 608 represents the plasma formed within the plasma chamber 108, and the third portion 610 represents a ground potential. The stray capacitance 602 is between the ESC and the ground potential.

[0096] Embodiments, described herein, may be practiced with various computer system configurations including hand-held hardware units, microprocessor systems, microprocessorbased or programmable consumer electronics, minicomputers, mainframe computers and the like. The embodiments, described herein, can also be practiced in distributed computing environments where tasks are performed by remote processing hardware units that are linked through a computer network.

[0097] In some embodiments, a controller is part of a system, which may be part of the above-described examples. The system includes semiconductor processing equipment, including a processing tool or tools, chamber or chambers, a platform or platforms for processing, and/or specific processing components (a wafer pedestal, a gas flow system, etc.). The system is integrated with electronics for controlling its operation before, during, and after processing of a semiconductor wafer or substrate. The electronics is referred to as the “controller,” which may control various components or subparts of the system. The controller, depending on processing requirements and/or a type of the system, is programmed to control any process disclosed herein, including a delivery of process gases, temperature settings (e.g., heating and/or cooling), pressure settings, vacuum settings, power settings, RF generator settings, RF matching circuit settings, frequency settings, flow rate settings, fluid delivery settings, positional and operation settings, wafer transfers into and out of a tool and other transfer tools and/or load locks connected to or interfaced with the system.

[0098] Broadly speaking, in a variety of embodiments, the controller is defined as electronics having various integrated circuits, logic, memory, and/or software that receive instructions, issue instructions, control operation, enable cleaning operations, enable endpoint measurements, and the like. The integrated circuits include chips in the form of firmware that store program instructions, digital signal processors (DSPs), chips defined as ASICs, PLDs, one or more microprocessors, or microcontrollers that execute program instructions (e.g., software). The program instructions are instructions communicated to the controller in the form of various individual settings (or program files), defining operational parameters for carrying out a process on or for a semiconductor wafer. The operational parameters are, in some embodiments, a part of a recipe defined by process engineers to accomplish one or more processing steps during the fabrication of one or more layers, materials, metals, oxides, silicon, silicon dioxide, surfaces, circuits, and/or dies of a wafer.

[0099] The controller, in some embodiments, is a part of or coupled to a computer that is integrated with, coupled to the system, otherwise networked to the system, or a combination thereof. For example, the controller is in a “cloud” or all or a part of a fab host computer system, which allows for remote access for wafer processing. The controller enables remote access to the system to monitor current progress of fabrication operations, examines a history of past fabrication operations, examines trends or performance metrics from a plurality of fabrication operations, to change parameters of current processing, to set processing steps to follow a current processing, or to start a new process.

[00100] In some embodiments, a remote computer (e g. a server) provides process recipes to the system over a computer network, which includes a local network or the Internet. The remote computer includes a user interface that enables entry or programming of parameters and/or settings, which are then communicated to the system from the remote computer. In some examples, the controller receives instructions in the form of settings for processing a wafer. It should be understood that the settings are specific to a type of process to be performed on a wafer and a type of tool that the controller interfaces with or controls. Thus as described above, the controller is distributed, such as by including one or more discrete controllers that are networked together and working towards a common purpose, such as the fulfilling processes described herein. An example of a distributed controller for such purposes includes one or more integrated circuits on a chamber in communication with one or more integrated circuits located remotely (such as at a platform level or as part of a remote computer) that combine to control a process in a chamber.

[00101] Without limitation, in various embodiments, a plasma system, described herein, includes a plasma etch chamber, a deposition chamber, a spin-rinse chamber, a metal plating chamber, a clean chamber, a bevel edge etch chamber, a physical vapor deposition (PVD) chamber, a chemical vapor deposition (CVD) chamber, an atomic layer deposition (ALD) chamber, an atomic layer etch (ALE) chamber, an ion implantation chamber, a track chamber, or any other semiconductor processing chamber that is associated or used in fabrication and/or manufacturing of semiconductor wafers.

[00102] It is further noted that although the above-described operations are described with reference to a parallel plate plasma chamber, e g., a capacitively-coupled plasma (CCP) chamber, etc., in some embodiments, the above-described operations apply to other types of plasma chambers, e.g., a plasma chamber including an inductively coupled plasma (ICP) reactor, a transformer coupled plasma (TCP) reactor, conductor tools, dielectric tools, a plasma chamber including an electron cyclotron resonance (ECR) reactor, etc. For example, an X MHz RF generator, a Y MHz RF generator, and a Z MHz RF generator are coupled to an inductor within the ICP plasma chamber.

[00103] As noted above, depending on a process operation to be performed by the tool, the controller communicates with one or more of other tool circuits or modules, other tool components, cluster tools, other tool interfaces, adjacent tools, neighboring tools, tools located throughout a factory, a main computer, another controller, or tools used in material transport that bring containers of wafers to and from tool locations and/or load ports in a semiconductor manufacturing factory.

[00104] With the above embodiments in mind, it should be understood that some of the embodiments employ various computer-implemented operations involving data stored in computer systems. These computer-implemented operations are those that manipulate physical quantities.

[00105] Some of the embodiments also relate to a hardware unit or an apparatus for performing these operations. The apparatus is specially constructed for a special purpose computer. When defined as a special purpose computer, the computer performs other processing, program execution or routines that are not part of the special purpose, while still being capable of operating for the special purpose.

[00106] In some embodiments, the operations, described herein, are performed by a computer selectively activated, or are configured by one or more computer programs stored in a computer memory, or are obtained over a computer network. When data is obtained over the computer network, the data may be processed by other computers on the computer network, e.g., a cloud of computing resources.

[00107] One or more embodiments, described herein, can also be fabricated as computer- readable code on a non-transitory computer-readable medium. The non-transitory computer- readable medium is any data storage hardware unit, e.g., a memory device, etc., that stores data, which is thereafter read by a computer system. Examples of the non-transitory computer- readable medium include hard drives, network attached storage (NAS), ROM, RAM, compact disc-ROMs (CD-ROMs), CD-recordables (CD-Rs), CD-rewritables (CD-RWs), magnetic tapes and other optical and non-optical data storage hardware units. In some embodiments, the non- transitory computer-readable medium includes a computer-readable tangible medium distributed over a network-coupled computer system so that the computer-readable code is stored and executed in a distributed fashion.

[00108] Although some method operations, described above, were presented in a specific order, it should be understood that in various embodiments, other housekeeping operations are performed in between the method operations, or the method operations are adjusted so that they occur at slightly different times, or are distributed in a system which allows the occurrence of the method operations at various intervals, or are performed in a different order than that described above.

[00109] It should further be noted that in an embodiment, one or more features from any embodiment described above are combined with one or more features of any other embodiment without departing from a scope described in various embodiments described in the present disclosure.

[00110] Although the foregoing embodiments have been described in some detail for purposes of clarity of understanding, it will be apparent that certain changes and modifications can be practiced within the scope of appended claims. Accordingly, the present embodiments are to be considered as illustrative and not restrictive, and the embodiments are not to be limited to the details given herein, but may be modified within the scope and equivalents of the appended claims.

Claims

1. An energy recovery system, comprising: a plurality of modular resonant circuits, wherein each of the plurality of modular resonant circuits includes: a diode; a switch coupled in parallel to the diode to form a parallel circuit; an inductor coupled in series with the parallel circuit to form a series circuit; and a first capacitor coupled to the inductor.

2. The energy recovery system of claim 1, wherein the switch is configured to close to store radio frequency (RF) energy recovered from a plasma chamber within the inductor or the first capacitor or a combination thereof.

3. The energy recovery system of claim 2, wherein the switch is configured to open to transfer the RF energy from the inductor or the first capacitor or the combination thereof to a charger circuit.

4. The energy recovery system of claim 1, wherein each of the plurality of modular resonant circuits excludes a transformer.

5. The energy recovery system of claim 1, further comprising a direct current-to-direct current (DC-to-DC) power supply coupled in parallel to the first capacitor.

6. The energy recovery system of claim 5, further comprising one or more diodes, wherein the DC-to-DC power supply is coupled to the one or more diodes, wherein the one or more diodes are configured to be coupled to a high voltage (HV) source.

7. The energy recovery system of claim 6, wherein the DC-to-DC power supply has an output, wherein the DC-to-DC power supply has a gain that is configured to be adjusted to achieve a voltage at the output that is greater than a voltage at an input of the HV source.

8. The energy recovery system of claim 1, further comprising a second capacitor coupled to the series circuit.

9. A system comprising: a controller; and a plurality of modular resonant circuits coupled to the controller, wherein each of the plurality of modular resonant circuits includes: a diode; a switch coupled in parallel to the diode to form a parallel circuit; an inductor coupled in series with the parallel circuit to form a series circuit; and a first capacitor coupled to the inductor.

10. The system of claim 9, wherein the controller is configured to close the switch to store radio frequency (RF) energy recovered from a plasma chamber within the inductor or the first capacitor or a combination thereof.

11. The system of claim 10, wherein the controller is configured to open the switch to transfer the RF energy from the inductor or the first capacitor or the combination thereof to a charger circuit.

12. The system of claim 9, wherein each of the plurality of modular resonant circuits excludes a transformer.

13. The system of claim 9, further comprising a direct current-to-direct current (DC-to-DC) power supply coupled in parallel to the first capacitor.

14. The system of claim 13, further comprising one or more diodes, wherein the DC-to-DC power supply is coupled to the one or more diodes, wherein the one or more diodes are configured to be coupled to a high voltage (HV) source.

15. The system of claim 14, wherein the DC-to-DC power supply has an output, wherein the controller is configured to adjust a gain of the DC-to-DC power supply at the output to achieve a voltage at the output that is greater than a voltage at an input of the HV source.

16. The system of claim 9, wherein each of the plurality of modular resonant circuits includes a second capacitor coupled to the series circuit.

17. A system comprising: a computer; a plasma chamber; a charger circuit coupled to the computer, wherein the charger circuit is configured to generate a pulsed direct current (DC) signal; a resonant inductor coupled to the charger circuit to receive the pulsed DC voltage, wherein the resonant inductor is configured to output a non-sinusoidal radio frequency (RF) signal based on the pulsed DC voltage, wherein the resonant inductor is coupled to the plasma chamber to provide the pulsed DC voltage to the plasma chamber; and an energy recovery circuit coupled to the plasma chamber to recover RF energy from the plasma chamber, wherein the energy recovery circuit includes a plurality of modular resonant circuits, wherein each of the plurality of modular resonant circuits includes: a diode; a switch coupled in parallel to the diode to form a parallel circuit; an inductor coupled in series with the parallel circuit to form a series circuit; and a first capacitor coupled to the inductor.

18. The system of claim 17, wherein the computer is configured to close the switch to store the RF energy from the plasma chamber within the inductor or the first capacitor or a combination thereof.

19. The system of claim 18, wherein the computer is configured to open the switch to transfer the RF energy from the inductor or the first capacitor or the combination thereof to the charger circuit.

20. The system of claim 17, wherein each of the plurality of modular resonant circuits excludes a transformer.

21. The system of claim 17, further comprising a DC-to-DC power supply coupled in parallel to the first capacitor.

22. The system of claim 21, wherein the charger circuit includes a high voltage (HV) source, the system further comprising: one or more diodes, wherein the DC-to-DC power supply is coupled to the one or more diodes, wherein the one or more diodes are coupled to the HV source, wherein the DC-to-DC power supply has an output, wherein the computer is configured to adjust a gain of the DC-to-DC power supply at the output to achieve a voltage at the output that is greater than a voltage at an input of the HV source.

23. The system of claim 17, wherein each of the plurality of modular resonant circuits includes a second capacitor coupled to the series circuit.