WO2025256728A1

WO2025256728A1 - Cache controller and method to schedule cache lockdown operations dynamically

Info

Publication number: WO2025256728A1
Application number: PCT/EP2024/066054
Authority: WO
Inventors: Claudio SCORDINO; Jianlong CAO
Original assignee: Shenzhen Yinwang Intelligent Technology Co Ltd
Current assignee: Shenzhen Yinwang Intelligent Technology Co Ltd
Priority date: 2024-06-11
Filing date: 2024-06-11
Publication date: 2025-12-18
Anticipated expiration: 2026-12-11

Abstract

A cache controller configured to schedule cache lockdown operations dynamically, the cache controller being configured to execute a cache scheduler module configured to schedule a cache lockdown for a given cache location and for a given time, wherein the cache controller is configured to receive information on a memory operation to be executed, the memory operation indicating a memory address and an access type, obtaining information on periodic timing of the memory operation, determine if the memory address is accessed by a task belonging to a critical processing chain, and if so operate the lock/unlock of the cache corresponding to the memory address.

Description

CACHE CONTROLLER AND METHOD TO SCHEDULE CACHE LOCKDOWN OPERATIONS DYNAMICALLY

TECHNICAL FIELD

The present disclosure relates generally to the field of memory management and more specifically, to a cache controller configured to schedule cache lockdown operations dynamically and a method for a controlling a cache to schedule cache lockdown operations dynamically.

BACKGROUND

Typically, modem software applications across various industrial domains, such as automotive and industrial automation, are designed as processing chains utilizing a component-based design. Each software component periodically receives data from the previous component in the chain, performs specific computations, and then provides the computed data to the next component. Moreover, when software components are executed on the same platform, then, in that case, the communication is performed through shared memory to reduce the overall processing overhead and communication latency, which introduces more latency than the data accessed from a cache memory. In addition, critical processing chains are required to be executed with reduced overall processing time and high accuracy, while non-critical processing chains are required to be executed on a best-effort basis. Therefore, the data, which is required to be accessed by the critical processing chains is required to be kept in the cache memory. Moreover, the data stored in the cache memory is required to be analysed in order to prevent the data eviction, such as the data eviction due to intra-task interference, intra-core interference, inter-core interference, and the like in order to ensure the presence of the data in the cache memory.

Conventionally, certain attempts have been made to reduce cache interference and ensure the data availability in the cache memory, such as cache lockdown, cache portioning, cache colouring, and the like. However, such attempt fails due to many reasons, such as by not ensuring the data retention in the cache memory, as both cache partitioning and cache colouring can result in data being evicted by the task itself or by the degradation of the cache memory due to inefficient cache usage, requiring oversized partitions that lead to higher cache failures and memory pressure. In addition, error-prone configurations and fine- tuning of conventional systems complicate the execution of the critical processing chains. Thus, there exists a technical problem of how to reduce cache interference and ensure data retention in the cache memory with reduced performance degradation, complexity, and error-prone configurations.

Therefore, in light of the foregoing discussion, there exists a need to overcome the aforementioned drawbacks associated with the conventional controllers and conventional methods for optimizing data caching in processing chains.

SUMMARY

The present disclosure provides a cache controller configured to schedule cache lockdown operations dynamically. Furthermore, the present disclosure provides a method for a controlling a cache to schedule cache lockdown operations dynamically. The present disclosure provides a solution to the existing problem of how to reduce cache interference and ensure data retention in the cache memory with reduced performance degradation, complexity, and error-prone configurations. An objective of the present disclosure is to provide a solution that overcomes at least partially the problems encountered in the prior art and provides the cache controller and the method for controlling a cache to schedule cache lockdown operations dynamically, such as by optimizing data caching in processing chains.

One or more objectives of the present disclosure are achieved by the solutions provided in the enclosed independent claims. Advantageous implementations of the present disclosure are further defined in the dependent claims. In one aspect, the present disclosure provides a cache controller configured to schedule cache lockdown operations dynamically. The cache controller is configured to execute a cache scheduler module configured to schedule a cache lockdown for a given cache location and for a given time, wherein the cache controller is configured to receive information on a memory operation to be executed, the memory operation indicating a memory address and an access type, obtaining information on periodic timing of the memory operation, determine if the memory address is accessed by a task belonging to a critical processing chain, and if so operate the lock/unlock of the cache corresponding to the memory address.

Advantageously, the cache controller is configured to dynamically schedule the cache lockdown operations to ensure that critical data remains in the cache due to which the overall execution time for critical processing chains is reduced. Furthermore, the cache controller is configured to optimize the cache usage by minimizing the reserved cache space, thereby enhancing the overall performance of a memory system. Moreover, the cache controller is configured to enhance data retention by preventing the eviction of the required data and ensuring that the required data is always available especially when needed. Additionally, the cache controller is configured to provide flexibility and adaptability to various tasks and memory operations thereby reducing the overall configuration complexity through automated lock/unlock memory operations based on the periodic timing of memory operations.

In another aspect, the present disclosure provides a method for controlling a cache to schedule cache lockdown operations dynamically. The method includes scheduling a cache lockdown for a given cache location and for a given time by receiving information on a memory operation to be executed, the memory operation indicating a memory address and an access type, obtaining information on the periodic timing of the memory operation, determining if the memory address is accessed by a task belonging to a critical processing chain, and if so, operating the lock/unlock of the cache corresponding to the memory address.

The method achieves all the advantages and technical effects of the cache controller of the present disclosure.

It is to be appreciated that all the aforementioned implementation forms can be combined.

It has to be noted that all devices, elements, circuitry, units, and means described in the present application could be implemented in the software or hardware elements or any kind of combination thereof. All steps which are performed by the various entities described in the present application, as well as the functionalities described to be performed by the various entities are intended to mean that the respective entity is adapted to or configured to perform the respective steps and functionalities. Even if, in the following description of specific embodiments, a specific functionality or step to be performed by external entities is not reflected in the description of a specific detailed element of that entity which performs that specific step or functionality, it should be clear for a skilled person that these methods and functionalities can be implemented in respective software or hardware elements, or any kind of combination thereof. It will be appreciated that features of the present disclosure are susceptible to being combined in various combinations without departing from the scope of the present disclosure as defined by the appended claims.

Additional aspects, advantages, features, and objects of the present disclosure would be made apparent from the drawings and the detailed description of the illustrative implementations construed in conjunction with the appended claims that follow.

BRIEF DESCRIPTION OF THE DRAWINGS

The summary above, as well as the following detailed description of illustrative embodiments, is better understood when read in conjunction with the appended drawings. For the purpose of illustrating the present disclosure, exemplary constructions of the disclosure are shown in the drawings. However, the present disclosure is not limited to specific methods and instrumentalities disclosed herein. Moreover, those in the art will understand that the drawings are not to scale. Wherever possible, like elements have been indicated by identical numbers. Embodiments of the present disclosure will now be described, by way of example only, with reference to the following diagrams wherein:

FIG. 1 is a block diagram that illustrates a cache controller configured to schedule cache lockdown operations dynamically, in accordance with an embodiment of the present disclosure;

FIG. 2 is a flowchart of a method for controlling a cache to schedule cache lockdown operations dynamically, in accordance with an embodiment of the present disclosure;

FIG. 3 is a diagram that illustrates a scheduling cache lockdown operations dynamically, in accordance with an embodiment of the present disclosure;

FIG. 4 is a diagram that illustrates an exemplary scenario for controlling a cache to schedule cache lockdown operations dynamically, in accordance with an embodiment of the present disclosure;

FIG. 5 is a diagram that illustrates an exemplary scheduling of the cache lockdown operations without a processing chain profiler, in accordance with an embodiment of the present disclosure;

FIG6 6 is a diagram that illustrates a collection of run-time information for scheduling the cache lockdown dynamically, in accordance with an embodiment of the present disclosure; and

FIG. 7 is a diagram that illustrates a receiving of information by a cache scheduler from critical tasks, in accordance with an embodiment of the present disclosure.

In the accompanying drawings, an underlined number is employed to represent an item over which the underlined number is positioned or an item to which the underlined number is adjacent. A non-underlined number relates to an item identified by a line linking the non-underlined number to the item. When a number is non-underlined and accompanied by an associated arrow, the non-underlined number is used to identify a general item at which the arrow is pointing.

DETAILED DESCRIPTION OF EMBODIMENTS

The following detailed description illustrates embodiments of the present disclosure and ways in which they can be implemented. Although some modes of carrying out the present disclosure have been disclosed, those skilled in the art would recognize that other embodiments for carrying out or practicing the present disclosure are also possible.

FIG. 1 is a block diagram that illustrates a cache controller configured to schedule cache lockdown operations dynamically, in accordance with an embodiment of the present disclosure. With reference to FIG. 1, there is shown a memory system 102 that includes a cache controller 104, a memory 106, a cache scheduler module 108, and a processing chain profiler module 110.

The cache controller 104 is configured to schedule cache lockdown operations dynamically. Examples of the cache controller 104 may include but are not limited to a central data processing device, a microprocessor, a microcontroller, a complex instruction set computing (CISC) processor, an application-specific integrated circuit (ASIC) processor, a reduced instruction set (RISC) processor, a very long instruction word (VLIW) processor, a state machine, and other processors or control circuitry.

The memory 106 is configured to store memory information received by the cache controller 104. Examples of implementation of the memory 106 may include, but are not limited to, Electrically Erasable Programmable Read-Only Memory (EEPROM), Dynamic Random Access Memory (DRAM), Random Access Memory (RAM), Read-Only Memory (ROM), Hard Disk Drive (HDD), Flash memory, a Secure Digital (SD) card, Solid-State Drive (SSD), and/or CPU cache memory.

There is provide the cache controller 104 configured to schedule cache lockdown operations dynamically. The cache lockdown memory operations refer to memory operations of locking specific cache locations to prevent the data from these specific cache locations to be evicted and further unlocking them when the data is no longer needed. The dynamic scheduling of the cache lockdown operations is used to overcome the limitations of static cache management and optimize the overall performance and reliability of the memory system 102. Additionally, the cache controller 104 is configured to reduce data configuration complexity thereby offering enhanced flexibility and adaptability to various tasks and memory operations of the memory system 102.

Moreover, the cache controller 104 is configured to execute the cache scheduler module 108 configured to schedule a cache lockdown for a given cache location and for a given time. The cache scheduler module 108 is executed to receive information about memory operations, including memory addresses and timing. Moreover, such information is further utilized to identify the memory addresses that are accessed by tasks in critical processing chains and further locks the cache locations at specified times. In addition, the cache scheduler module 108 is configured to schedule the cache lockdown for the given cache location by the time the critical processing chains are executed. As a result, the execution of the cache scheduler module 108 prevents the eviction of crucial data from the cache, which is critical for maintaining low latency and high performance in processing chains, especially for tasks that are time- sensitive.

In accordance with an embodiment, the cache scheduler module 108 is further configured to determine if the memory address is accessed by a task belonging to a critical processing chain by determining that the memory address is both read and written to by two or more tasks belonging to the critical processing chain. In other words, the cache scheduler module 108 is configured to identify whether the memory address belongs to the critical processing chain by checking if the memory address is both read and written to by multiple tasks within that processing chain, in order to ensure that the data required for the execution of the critical processing chain is retained in the cache, thereby maintaining the performance and reliability of time- sensitive operations. In an implementation, the cache scheduler module 108 is configured to monitor the memory operations by monitoring the memory addresses and cache locations that are accessed for both read and write operations by two or more tasks in the critical processing chain. Moreover, if such memory addresses are found, then, in that case, such memory addresses are marked as critical and scheduled for cache lockdown to prevent eviction. As a result, the determination of the memory address that is accessed by a task belonging to a critical processing chain by determining that the memory address is both read and written to by two or more tasks belonging to the critical processing chain is used to ensure that critical data is available in the cache memory thereby leading to the execution of the processing chains with reduced overall processing time and reduced timing jitter. Additionally, such determination is also used to optimize the cache usage by only locking necessary data, thereby enhancing the overall performance of the memory system 102 and reducing the complexity of the cache management through automated, dynamic operations.

Furthermore, the cache controller 104 is configured to receive information on a memory operation to be executed, the memory operation indicating a memory address and an access type. In an implementation, the cache controller 104 is configured to receive information on a memory operation to be executed, the memory operation indicating a memory address and an access type, which is the read access type. In another implementation, the cache controller 104 is configured to receive information on a memory operation to be executed, the memory operation indicating a memory address and an access type, which is the write access type. Moreover, the receiving of the information on the memory operations to be executed is used to manage and optimize cache usage effectively, ensuring that critical data is retained, and non-essential data can be evicted as needed. The cache controller 104 is configured to monitor the incoming memory operations and further capture both the memory address and the type of access being requested. After that, the captured data is then used to determine which cache locations should be locked or unlocked, based on the requirement and frequency of the data accessibility. As a result, by monitoring the memory operations accurately, the cache controller 104 is configured to ensure that critical data remains in the cache, improving execution times and reducing latency for important tasks. Additionally, the cache controller 104 is also configured to allow efficient cache management, such as by optimizing the overall performance of the memory system 102 and reducing unnecessary memory utilization.

Furthermore, the cache controller 104 is configured to obtain information on periodic timing of the memory operation. The cache controller 104 is configured to monitor the memory operations in order to determine the timings of the memory operations. Moreover, such information is further utilized to predict future operations and schedule cache lock/unlock operations, accordingly, ensuring that critical data is locked in the cache. The information on the periodic timing of the memory operation is used for optimizing the scheduling of cache lock/unlock operations in order to ensure that the cache is managed efficiently and that critical data remains available when needed, minimizing the latency of the memory system 102.

Furthermore, the cache controller 104 is configured to determine if the memory address is accessed by a task belonging to a critical processing chain, and if so, operate the lock/unlock of the cache corresponding to the memory address. In an implementation, the cache controller 104 is configured to determine that the memory address is accessed by the task belonging to the critical processing chain, then, in that case, the cache controller 104 is configured to operate the lock of the cache of corresponding to the memory address. In another implementation, the cache controller 104 is configured to determine that the memory address is not accessed by the task belonging to the critical processing chain, then, in that case, the cache controller 104 is configured to operate the unlock of the cache of corresponding to the memory address. The cache controller 104 is configured to monitor memory operations and identify the memory addresses that are accessed by the critical processing chain. Moreover, if the memory address is accessed by the critical processing chain, the cache controller 104 is configured to lock the corresponding cache location to prevent eviction. However, when the data is no longer required, the cache controller 104 is configured to unlock the cache location to make space for other data. As a result, the cache controller 104 is configured to maintain the overall performance with a reduced latency thereby avoiding the overhead of frequent data retrieval from the memory.

In accordance with an embodiment, the cache controller 104 is further configured to maintain a list of critical processing chains and maintain a memory timers list. Moreover, the list of memory timers includes a Read timer and a Write timer for each memory address entry, each timer indicating a timing period and a timing offset. The cache controller 104 is further configured to receive the memory operation to be executed and determine if the task belongs to a critical chain by comparing the list of critical processing chains. In an example, the cache controller 104 is configured to maintain the list of critical processing chains, such as "LIST 1". Furthermore, the cache controller 104 is configured to maintain the memory timers list, such as "LIST 2". When a memory operation is received, the cache controller 104 is configured to check if the task is part of a critical processing chain or not, such as by comparing the task to the list of critical processing chains. The determination if the task belongs to the critical processing chain or not enables the cache controller 104 to ensure that the cache controller 104 can accurately identify and prioritize critical tasks thereby maintaining the required data in the cache memory for the corresponding tasks in order to improve the overall performance of the memory system 102 and reduce the overall latency required to execute the critical processing chains.

In accordance with an embodiment, the cache controller 104 is further configured to execute a processing chain profiler module 110 configured to maintain a list of memory operations. The list of memory operations including an access type and a memory address for each entry determines whether the memory address is in the list of memory operations for the same task and for the same type of access, and if so, determines the timing period and timing offset for the memory operation to be stored in the memory timers list, and, if not, generate an entry for the memory address to be entered in the list of memory operations, and then retrieve a next operation to be executed. The processing chain profiler module 110 maintains the list of the memory operations, such as "LIST 3" including the access types (i.e., read access type and write access type) and the memory addresses. When a memory operation is executed, then, the processing chain profiler module 110 is configured to check if the memory address, which is required for the corresponding memory operation is already listed for the same task and access type or not. In an implementation, if the memory address is in the list of memory operations for the same task and for the same type of access, then, in that case, the cache controller 104 is configured to determine the timing period and timing offset for the memory operation to be stored in the memory timers list. In another implementation, if the memory address is not in the list of memory operations for the same task and for the same type of access, then, in that case, the cache controller 104 is configured to generate an entry for the memory address to be entered in the list of memory operations, and then retrieve a next operation to be executed thereby ensuring continuous and dynamic updating of the memory operations. As a result, the cache controller 104 is configured to accurately track and profile the memory operations that are further utilized for optimizing cache management for critical processing chains, such as by maintaining up-to-date timing and access information. Additionally, the cache controller 104 is configured to minimize the cache usage by only locking required data, leading to improved overall efficiency and performance of the memory system 102.

In an implementation, the next operation to be executed is the same operation but for another memory address. When the cache controller 104 completes an operation for one memory address, then, the cache controller 104 is configured to retrieve and execute the next operation for a different memory address, such as by the processing chain profiler module 110. Moreover, such an operation is executed concurrently in order to allow the cache controller 104 to manage a sequence of memory operations systematically to ensure that each memory address is appropriately handled according to the access type and timing requirements. As a result, the systematic management of the memory operations for different memory addresses by the cache controller 104 is used to ensure comprehensive and efficient cache management, such as by maintaining an optimal cache usage with reduced latency, and also ensures that the critical data is retained as per the requirement.

In accordance with an embodiment, the cache controller 104 is further configured to execute the processing chain profiler module 110 configured to update the corresponding entry in the list of memory operations with a time for accessing the memory according to the operation to be executed. In other words, when a memory operation is executed, the processing chain profiler module 110 is configured to update the corresponding entry in the list of memory operations with the exact time for accessing the memory. Moreover, the updating of the list of memory operations is required to ensure that each of the memory operations has an accurate timestamp, reflecting the accessibility of the memory for the corresponding memory operation. As a result, updating the list with precise access times ensures accurate profiling and timing of memory operations, which is crucial for optimizing cache management and maintaining critical data availability with enhanced overall efficiency of the memory system 102 by ensuring that critical data is retained in the cache when required, optimizing cache usage, and minimizing unnecessary cache locks.

In accordance with an embodiment, the cache scheduler module 108 is configured to operate the lock/unlock of the cache corresponding to the memory address by retrieving an entry from the memory timers list. The cache scheduler module 108 is further configured to determine if the Read timer and the Write timer are set. Moreover, the Read timer and the Write timer each indicate a time period, and if so, determine if a current time is a multiple of a time period for the Read timer or for the Write timer, and if so, execute the memory operation according to the Read and Write timers. The cache scheduler module 108 is configured to operate the lock/unlock of the cache corresponding to the memory address by retrieving an entry from the memory timers list. Further, the cache scheduler module 108 is configured to determine if the Read timer and the Write timer are set. After that, if the Read timer and the Write timer are set, then, in that case, the cache scheduler module 108 is configured to determine if the current time is the multiple of the time period for the Read timer or for the Write timer, such as through a timer. Finally, the cache scheduler module 108 is configured to execute the memory operation according to the Read and Write timers. In an implementation, the cache scheduler module 108 is configured to operate the lock/unlock of the cache corresponding to the memory address on a specific cache as each cache has specific and different assembly instructions, without affecting the scope of the present disclosure. As a result, the cache scheduler module 108 is configured to dynamically and precisely manage cache operations, ensuring that critical data is available in the cache when required.

Advantageously, the cache controller 104 is configured to dynamically schedule the cache lockdown operations to ensure that critical data remains in the cache due to which the overall execution time for critical processing chains is reduced. Furthermore, the cache controller 104 is configured to optimize the cache usage by minimizing the reserved cache space, thereby enhancing the overall performance of a memory system. Moreover, the cache controller 104 is configured to enhance data retention by preventing the eviction of the required data and ensuring that the required data is always available especially when needed. Additionally, the cache controller 104 is configured to provide flexibility and adaptability to various tasks and memory operations thereby reducing the overall configuration complexity through automated lock/unlock memory operations based on the periodic timing of memory operations.

FIG. 2 is a flowchart of a method for a controlling a cache to schedule cache lockdown operations dynamically, in accordance with an embodiment of the present disclosure. FIG. 2 is described in conjunction with elements from FIG. 1. With reference to FIG. 2, there is shown a flowchart of method 200 that includes steps 202, and 202A to 202D. The cache controller 104 of the FIG. 1 is configured to execute the method 200.

There is provided the method 200 for a controlling a cache to schedule cache lockdown operations dynamically. The dynamic scheduling of the cache lockdown operations is used to overcome the limitations of static cache management and optimize the overall performance and reliability of the memory system 102. Additionally, the cache controller 104 is configured to reduce data configuration complexity thereby offering enhanced flexibility and adaptability to various tasks and memory operations of the memory system 102.

At step 202, the method 200 includes scheduling a cache lockdown for a given cache location and for a given time by receiving information on a memory operation to be executed, the memory operation indicating a memory address, and an access type, such as at step 202A. The information on the memory operations that are to be executed is used to prevent the eviction of crucial data from the cache, which is critical for maintaining low latency and high performance in processing chains, especially for tasks that are time- sensitive. Furthermore, at step 202B, the method 200 includes obtaining information on periodic timing of the memory operation. The information on the periodic timing of the memory operation is used for optimizing the scheduling of cache lock/unlock operations in order to ensure that the cache is managed efficiently and that critical data remains available when needed, minimizing the latency of the memory system 102. At step 202C, the method 200 includes determining if the memory address is accessed by a task belonging to a critical processing chain, and if so, operating the lock/unlock of the cache corresponding to the memory address, such as at step 202D. In an implementation, the cache controller 104 is configured to determine that the memory address is accessed by the task belonging to the critical processing chain, then, in that case, the cache controller 104 is configured to operate the lock of the cache of corresponding to the memory address. In another implementation, the cache controller 104 is configured to determine that the memory address is not accessed by the task belonging to the critical processing chain, then, in that case, the cache controller 104 is configured to operate the unlock of the cache of corresponding to the memory address. The cache controller 104 is configured to monitor memory operations and identify the memory addresses that are accessed by the critical processing chain. Moreover, if the memory address is accessed by the critical processing chain, the cache controller 104 is configured to lock the corresponding cache location to prevent eviction. However, when the data is no longer required, the cache controller 104 is configured to unlock the cache location to make space for other data. As a result, the cache controller 104 is configured to maintain the overall performance with reduced latency thereby avoiding the overhead of frequent data retrieval from the memory.

Advantageously, the method 200 is used to dynamically schedule the cache lockdown operations to ensure that critical data remains in the cache due to which the overall execution time for critical processing chains is reduced. Furthermore, the cache controller 104 is configured to optimize the cache usage by minimizing the reserved cache space, thereby enhancing the overall performance of a memory system. Moreover, the method 200 is used to enhance data retention by preventing the eviction of the required data and ensuring that the required data is always available especially when needed. Additionally, the method 200 is used to provide flexibility and adaptability to various tasks and memory operations thereby reducing the overall configuration complexity through automated lock/unlock memory operations based on the periodic timing of memory operations. The steps 202A to 202D are only illustrative, and other alternatives can also be provided where one or more steps are added, one or more steps are removed, or one or more steps are provided in a different sequence without departing from the scope of the claims herein.

There is further provided a computer program product comprising program instructions for performing the method 200 when executed by one or more processors in the memory system 102. The computer program product is implemented as an algorithm, embedded in a software stored in a non-transitory computer-readable storage medium. The non-transitory computer-readable storage means may include but are not limited to, an electronic storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination of the foregoing. Examples of implementation of computer-readable storage medium, but are not limited to, Electrically Erasable Programmable Read-Only Memory (EEPROM), Random Access Memory (RAM), Read Only Memory (ROM), Hard Disk Drive (HDD), Flash memory, a Secure Digital (SD) card, Solid-State Drive (SSD), a computer-readable storage medium, and/or CPU cache memory.

FIG. 3 is a diagram that illustrates a scheduling cache lockdown operations dynamically, in accordance with an embodiment of the present disclosure. FIG. 3 is described in conjunction with elements from FIG. 1. With reference to FIG. 3, there is shown a diagram 300 of the scheduling cache lockdown operations dynamically, to ensure that the required data for communication is locked in the cache till the corresponding data is required and then the corresponding data gets unlocked when not required. The memory system 102 includes a CPU profiler 302, a memory profiler 304, a timer 308, a time reference 306, tasks 310, run-time application programming interface (API) 312, a processing chain profiler 314, a cache scheduler 316, a cache 318, and cache control registers 320 for lockdown.

In an implementation scenario, the CPU profiler 302 is configured to monitor the CPU and gather information about the tasks 310 that are being executed, and the memory profiler 304 is configured to gather information about the memory addresses that are being accessed and the type of memory operations (i.e., the read/write memory operation) that are being performed. Moreover, the timer 308 refers to a hardware or a software timer, which is configured to provide time reference 306 for scheduling tasks and cache operations. The processing chain profiler 314 (i.e., the processing chain profiler module 110 of FIG. 1 ) refers to a processing chain profiler that is configured to collect and analyze data from the CPU profiler 302, the memory profiler 304, and the timer 308 in order to understand the cause-effect relationship between tasks and memory operations. Furthermore, the cache scheduler 316 (i.e., the cache scheduler module 108 of FIG. 1 ) is configured to operate the lock/unlock operations for the cache 318 based on the timing and address information provided by the processing chain profiler 314 (or a cause-effect profiler). The cache scheduler 316 is configured to schedule lock/unlock operations on specific cache locations at specific times and can be implemented in either hardware or software, or both, such as through an API or by providing a configuration file. The cache scheduler 316 is configured to provide information about the tasks 310 that belongs to critical chains, memory addresses that can be accessed by the corresponding tasks for communication, and the timing (i.e., periodicity) of read and write memory operations along with the information about how the specific cache is structured and how the lock/unlock operations can be performed. Moreover, the scheduling of lock/unlock operations can be either time-driven (e.g., triggered by a hardware or a software timer) or event-driven (e.g., explicitly triggered by a software component which could be the critical tasks themselves). Additionally, the locking or unlocking operations are performed by writing the cache control registers 320 for controlling the lockdown functionality. Furthermore, the cache 318 refers to the memory in which the data is stored temporarily in order to access the data with reduced overall processing time and the cache control registers 320 for the lockdown are used to manage which parts of the cache 318 are locked or unlocked. As a result, the scheduling of the cache lockdown operations dynamically ensures that the critical data for communication remains locked in the cache 318 until required, reducing latency and optimizing the overall performance of the memory system 102. FIG. 4 is a diagram that illustrates an exemplary scenario for controlling a cache to schedule cache lockdown operations dynamically, in accordance with an embodiment of the present disclosure. FIG. 4 is described in conjunction with elements from FIG. 1 to 3. With reference to FIG. 4, there is shown a diagram 400 for controlling the cache to schedule the cache lockdown operations dynamically through a processing chain profiler 314.

In an exemplary scenario, the processing chain profiler 314 is configured to receive information of the memory operations and further allow the cache controller 104 to lock/unlock the cache accordingly. The CPU profiler 302 is configured to provide information about the task, which is being executed, and the memory profiler 304 is configured to provide an information about the memory address that is being accessed and the type of the memory operation (i.e., read or write), which is executed. Furthermore, the processing chain profiler 314 is configured to maintain a list of memory operations, the list of memory operations including an access type and a memory address for each entry, and determine whether the memory address is in the list of memory operations for the same task and for the same type of access, and if so, determine the timing period and timing offset for the memory operation to be stored in the memory timers list, and, if not, then, generate an entry for the memory address to be entered in the list of memory operations, and then retrieve a next operation to be executed. Furthermore, the cache scheduler 316 is configured to provide information about the cache (e.g., vendor- specific cache) to operate the lock/unlock operations by executing vendor- specific assembly instructions for the cache control registers 320 in the cache 318. In an implementation, the processing chain profiler 314 and the cache scheduler 316 can be implemented in a software. In another implementation, the processing chain profiler 314 and the cache scheduler 316 can be implemented in a hardware. A detailed explanation of the operation of the lock/unlock scenario is described in detail in FIG. 6. As a result, the scheduling of the cache lockdown operations based on the information, such as memory address and the access type is used to provide an enhanced cache management that reduces the overall processing time, which is required for the execution of the critical processing chains.

FIG. 5 is a diagram that illustrates an exemplary scheduling of the cache lockdown operations without a processing chain profiler, in accordance with an embodiment of the present disclosure. FIG. 5 is described in conjunction with elements from FIG. 1 to 4. With reference to FIG. 5, there is shown a diagram 500 of the scheduling of the cache lockdown operations without the processing chain profiler 314.

In an exemplary scenario, tasks 310 (e.g., tasks at start-up time) directly sends the list of memory addresses of the memory operations (i.e. read memory operations and write memory operations) to be locked along with the timing information (i.e., period offset) to the cache scheduler 316, such as during start-up time or run-time. In an implementation, the time reference 306 provides the timing information and the timer 308 is used for time-driven events in order to provide information about the memory operations. Furthermore, the run-time API or library 312 facilitates the interaction between the tasks 310 and the cache scheduler 316. Finally, the cache scheduler 316 is configured to operate the lock/unlock operations by executing the vendorspecific assembly instructions for the cache control registers 320 in the cache 318 in order to ensure efficient cache management with an improved performance of the memory system 102.

FIG 6 is a diagram that illustrates a collection of run-time information for scheduling the cache lockdown dynamically, in accordance with an embodiment of the present disclosure. FIG. 6 is described in conjunction with elements from FIG. 1 to 5. With reference to FIG. 6, there is shown a diagram 600 of that depicts the collection of run-time information for scheduling the cache lockdown dynamically.

In an implementation, the processing chain profiler 314 is configured to collect the run-time information either autonomously or from existing software component and allow the cache scheduler 316 to operate the lock/unlock operations according to the collected run-time information. The processing chain profiler 314 is configured to compute and store the periodicity of read and write memory operations for the critical tasks. At operation 602, the processing chain profiler 314 is configured to get information about the currently running task and at operation 604, the processing chain profiler 314 is configured to determine if the running task belongs to a critical chain or not. In an implementation, a first list 626 that includes the information about critical tasks is used to determine if the running task belongs to the critical chain or not by the processing chain profiler 314. Further, if the running task belongs to the critical chain, then operation 606 is performed and if not, then, the processing chain profiler 314 is configured to again get the information about another currently running task. At operation 606, the processing chain profiler 314 is configured to get the next accessed memory address and read- write memory operation type, such as from the time reference 306. Thereafter, at operation 608, the processing chain profiler 314 is configured to determine if the memory address is already there in a third list 628 for the same task and the same type of read/write memory operation or not. Moreover, the third list 628 includes the information about the task, read/write memory operation, memory address, size, and the time of the corresponding operation. Furthermore, if the memory address is not there in a third list 628 for the same task and the same type of read/write memory operation, then, the processing chain profiler 314 is configured to record the corresponding memory operation, memory size, memory address and the time in the third list 628, such as at operation 610 and if the memory address is there in a third list 628 for the same task and the same type of read/write memory operation, then the processing chain profiler 314 is configured to compute the offset and period of the same memory operation and maintain the same in the second list 616, such as at operation 612. Moreover, the second list 616 includes the memory address, memory size, the period, and offset for the read and write memory operations. At operation 614, the processing chain profiler 314 is configured to update the last access time in the third list 628. On the other hand, at operation 618, the cache scheduler 316 is configured to get the next row from second list 616, and at operation 620, the cache scheduler 316 is configured to determine if the current timings (i.e., period and offset) for both read and write memory operations on the corresponding memory address are set or not. Moreover, if the timing conditions are set, then, in that case, the cache scheduler 316 is configured to determine the frequency and time period for the read or write memory operations based on the current time from the time reference 306, such as at operation 622. However, if the timings for read and write memory operations are not set or if the frequency and time period for the read or write memory operations are not multiple, then operation 618 is performed. Furthermore, if the frequency and time period for the read or write memory operations based on the current time from the time reference 306 are multiple, then the cache scheduler 316 is configured to operate the cache lock/unlock operations on that memory address based on whether it is a read or write operation, such as by interacting with the cache control registers 320 for lockdown that are included in the cache 318 of the memory system, at operation 624. As a result, the cache lock/unlock memory operations are performed in order to optimize cache management and reduce the overall processing time for critical processing chains (or critical tasks).

FIG. 7 is a diagram that illustrates a receiving of information by a cache scheduler from critical tasks, in accordance with an embodiment of the present disclosure. FIG. 7 is described in conjunction with elements from FIG. 1 to 6. With reference to FIG. 7, there is shown a diagram 700 that depicts the receiving of the information from the critical tasks by the cache scheduler 316.

In an implementation, the critical tasks that are listed in the first list 626 are sent directly to the cache scheduler 316. Furthermore, the cache scheduler 316 is configured to perform the lock/unlock operations according to the received information. At operation 702, the cache scheduler 316 is configured to receive programming information (e.g., information about memory operations, memory address, size, offset, period) from a new critical task. Furthermore, at operation 704, the cache scheduler 316 is configured to determine if the running task belongs to a critical chain or not, such as by referring to the first list 626, which contains the critical tasks. Moreover, if the task does not belong to a critical chain, then, the cache scheduler 316 is configured to again perform operation 702, which is to receive information for the next new task. However, if the task belongs to a critical chain, then, the received information is inserted into the second list 616, which maintains the memory addresses, access sizes, timing periods, and offsets for read and write memory operations for the critical tasks, such as at operation 706. Additionally, the second list 616 is used by the cache scheduler 316 to manage the cache lockdown and unlock operations based on the timing information provided. At operation 708, the cache scheduler 316 is configured to get the next row from second list 616, and at operation 710, the cache scheduler 316 is configured to determine if the current timings (i.e., period and offset) for both read and write memory operations on the corresponding memory address are set or not. Moreover, if the timing conditions are set, then, in that case, the cache scheduler 316 is configured to determine the frequency and time period for the read or write memory operations based on the current time from the time reference 306, such as at operation 712. However, if the timings for read and write memory operations are not set or if the frequency and time period for the read or write memory operations are not multiple, then operation 708 is performed. Furthermore, if the frequency and time period for the read or write memory operations based on the current time from the time reference 306 are multiple, then the cache scheduler 316 is configured to operate the cache lock/unlock operations on that memory address based on whether it is a read or write operation, such as by interacting with the cache control registers 320 for lockdown that are included in the cache 318 of the memory system, such as at operation 714. As a result, the cache lock/unlock memory operations are performed in order to optimize cache management and reduce the overall processing time for critical processing chains (or critical tasks).

Modifications to embodiments of the present disclosure described in the foregoing are possible without departing from the scope of the present disclosure as defined by the accompanying claims. Expressions such as "including", "comprising", "incorporating", "have", "is" used to describe and claim the present disclosure are intended to be construed in a non-exclusive manner, namely allowing for items, components or elements not explicitly described also to be present. Reference to the singular is also to be construed to relate to the plural. The word "exemplary" is used herein to mean "serving as an example, instance or illustration". Any embodiment described as “exemplary” is not necessarily to be construed as preferred or advantageous over other embodiments or to exclude the incorporation of features from other embodiments. The word "optionally" is used herein to mean "is provided in some embodiments and not provided in other embodiments". It is appreciated that certain features of the present disclosure, which are, for clarity, described in the context of separate embodiments, may also be provided in combination in a single embodiment. Conversely, various features of the invention, which are, for brevity, described in the context of a single embodiment, may also be provided separately or in any suitable combination or as suitable in any other described embodiment of the disclosure.

Claims

1. A cache controller (104) configured to schedule cache lockdown operations dynamically, the cache controller (104) being configured to execute a cache scheduler module (108) configured to schedule a cache lockdown for a given cache location and for a given time, wherein the cache controller (104) is configured to receive information on a memory operation to be executed, the memory operation indicating a memory address and an access type, obtaining information on periodic timing of the memory operation, determine if the memory address is accessed by a task belonging to a critical processing chain, and if so operate the lock/unlock of the cache corresponding to the memory address.

2. The cache controller (104) according to claim 1, wherein the cache scheduler module (108) is further configured to determine if the memory address is accessed by a task belonging to a critical processing chain by determining that the memory address is both read and written to by two or more tasks belonging to the critical processing chain.

3. The cache controller (104) according to claim 1 or 2, wherein the cache controller (104) is further configured to maintain a list of critical processing chains, maintain a memory timers list, the list of memory timers including a Read timer and a Write timer for each memory address entry, each timer indicating a timing period and a timing offset, receive the memory operation to be executed, determine if the task belongs to a critical chain by comparing the list of critical processing chains

4. The cache controller (104) according to claim 3, wherein the cache controller (104) is further configured to execute a processing chain profiler module (110) configured to maintain a list of memory operations, the list of memory operations including an access type and a memory address for each entry, determine whether the memory address is in the list of memory operations for the same task and for the same type of access, and if so, determine the timing period and timing offset for the memory operation to be stored in the memory timers list, and, if not, generate an entry for the memory address to be entered in the list of memory operations, and then retrieve a next operation to be executed.

5. The cache controller (104) according to claim 4, wherein the next operation to be executed is the same operation but for another memory address.

6. The cache controller (104) according to claim 4 or 5, wherein the cache controller (104) is further configured to execute a processing chain profiler module (110) configured to update the corresponding entry in the list of memory operations with a time for accessing the memory according to the operation to be executed.

7. The cache controller (104) according to any of claims 3 to 6, wherein the cache scheduler module (108) is configured to operate the lock/unlock of the cache corresponding to the memory address by retrieving an entry from the memory timers list, determine if the Read timer and the Write timer are set, wherein the Read timer and the Write timer each indicates a time period, and if so determine if a current time is a multiple of a time period for the Read timer or for the Write timer, and if so execute the memory operation according to the Read and Write timers.

8. A method (200) for a controlling a cache to schedule cache lockdown operations dynamically, the method (200) comprising scheduling a cache lockdown for a given cache location and for a given time by receiving information on a memory operation to be executed, the memory operation indicating a memory address and an access type, obtaining information on periodic timing of the memory operation, determining if the memory address is accessed by a task belonging to a critical processing chain, and if so operating the lock/unlock of the cache corresponding to the memory address.

9. A computer program product comprising program instructions for performing the method according to claim 8, when executed by one or more processors in a memory system (102).