WO2025255347A1

WO2025255347A1 - Anomaly detecting edge device with quantized deep neural network on fpga, asic, or soc

Info

Publication number: WO2025255347A1
Application number: PCT/US2025/032447
Authority: WO
Inventors: Muhammad Sabir ALAM; Walid Ai MISBA; Jayasimha Atulasimha
Original assignee: Virginia Commonwealth University
Current assignee: Virginia Commonwealth University
Priority date: 2024-06-05
Filing date: 2025-06-05
Publication date: 2025-12-11
Anticipated expiration: 2026-12-05

Abstract

Systems and methods are described for an edge device with a chip-implemented, reduced-bit-quantized neural network (NN)-based anomaly detector, including a preprocessing logic block for preprocessing the sensor data, and a quantized, processing-in-memory (PIM) based NN block. The quantized PIM-based NN block includes quantized multiply-accumulate units (MACs) with quantized PIM logic that uses quantized-arithmetic-result lookup tables. The quantized MACs are arranged to function as quantized, PIM-based NN block kernels. Optionally, the quantized PIM- based NN block is implemented as an autoencoder with a quantized NN encoding and a quantized NN decoding section. The quantized NN encoder section performs NN-based, quantized dimensionality reduction of the processed sensor data, outputting a quantized lower-dimensional latent representation. The quantized NN decoder section reconstructs the quantized lower-dimensional latent representation, producing a quantized reconstructed input pattern. The quantized NN encoder and decoder sections include quantized MACs with PIM logic using quantized- arithmetic-result lookup tables.

Description

Anomaly Detecting Edge Device with Quantized Deep Neural Network on FPGA, ASIC, or SoC

CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application claims benefit of United States Provisional Application 63/656,366 filed June 5, 2024, the complete contents of which are incorporated herein by reference.

BACKGROUND

Technical Field

[0002] The present disclosure generally relates to detection of anomalies, and more particularly to using quantized synaptic weights based neural networks implemented on hardware to achieve anomaly detection with low-power consumption and low hardware resources suitable for edge applications.

Description of Related Art

[0003] Conventional edge devices used for anomaly detection systems often utilize general- purpose programmable computing devices, i.e., von Neumann microcontrollers configured with stored instructions. The instructions are sequentially executed and, for processing rates sufficient to provide real-time edge detecting of anomalies, the computing resources may consume significant power and hardware resources. These costs, in various applications, can render conventional neural network-based anomaly detection systems unsuitable for edge devices due to their limited computational and power resources.

[0004] Accordingly, there is a need for edge-device- supportable, low-power-consumption, and low hardware requirement, neural network -based anomaly detection systems.

[0005] SUMMARY

[0006] This Summary presents example features and aspects and is not an exclusive or exhaustive description of disclosed subject matter. Whether or not a feature is included in this Summary is not intended as an indication of the feature’s relative importance or benefit.

[0007] One example system can comprise an anomaly-detecting edge device that can include, configured as supportable by and/or attachable to an edge device support structure: a chip, an interface circuit, implemented on or proximal to the chip and configured to receive a sensor signal carrying a sensor data, and preprocessing circuit, implemented on the chip, communicatively connected to the interface circuit, and configured to preprocess the sensor data, and correspondingly output processed sensor data. The example system can further comprise, according to one or more embodiments, a quantized neural network (NN) circuit, which can be communicatively connected to the preprocessing circuit. The quantized NN circuit can comprise one or more multiply-accumulate units (MACs), each including a quantized processing-in-memory (PIM) unit comprising a quantized multiplication product lookup table. The system can include an anomaly detecting circuit, which can be implemented in the chip and configured to determine, based at least in part on the quantized NN circuit output, an anomaly.

[0008] BRIEF DESCRIPTION OF DRAWINGS

[0009] A further understanding of the nature and advantages of the embodiments may be realized by reference to the following drawings. It will be understood that the drawings show illustrative, not limitative, features and examples. It will also be understood that the drawing graphics are scaled for readability and that graphic representations of functions and features are not necessarily drawn to a scale consistent with their physical implementations. Also, in the drawings, similar components or features may have the same reference label.

[0010] FIG. 1 illustrates a functional block schematic of one arrangement for one example chip- implemented processing-in-memory (PIM)-based, quantized neural network unit for edge device anomaly detection systems according to various embodiments.

[0011] FIG. 2 is a graphic rescaling of FIG. 1, also illustrating a functional block schematic of one arrangement of a PIM-based quantized multiplier- accumulator (MAC) unit of the chip- implemented PIM-based quantized neural network.

[0012] FIG. 3 illustrates an operational flow diagram of quantization-aware training and deployed operations of an edge device with a chip-implemented quantized NN-based anomaly detector according to various embodiments.

[0013] FIG. 4 illustrates a functional block schematic for one example chip-implemented PIM- based quantized autoencoder unit for edge device anomaly detection systems according to various embodiments.

[0014] FIG. 5 is a graphic rescaling of FIG. 4 with a functional block schematic of one arrangement of the PIM-based quantized MAC units of the quantized autoencoder.

[0015] FIG. 6 illustrates a functional block schematic of one example chip-implemented, quantized FFT-quantized NN-based anomaly detection system for edge devices, according to various embodiments. DETAILED DESCRIPTION

[0016] Disclosed embodiments provide a chip-implemented processing-in-memory (PIM)-based, quantized deep neural network (NN) logic giving edge devices the capability of real-time, low- power consumption detection of anomalies. The embodiments’ chip-implemented PIM-configured quantized NN logic provides edge device anomaly detection that, using one to 7 -bit synapses implemented with high-speed, low-power PIM lookup table-based arithmetic logic units (ALUs), which also provide parallel processing flows, can overcome conventional edge device computational limits.

[0017] According to various embodiments, the PIM-based quantized NN logic can comprise a plurality of quantized NN synapses that apply training-generated weights to produce outputs from which post-NN logic can detect, with application- specific acceptable accuracy, between the presence and absence of an anomaly. In an aspect, the weights can be determined through software model training and stored in the chip prior to deployment.

[0018] In an aspect, the synapses can be realized by multiply-accumulate (MAC) units arranged to execute layers of matrix-vector multiplications. According to various embodiments, arithmetic operations within the quantized NN logic, particularly the MAC computations, can be implemented using lookup-table (LUT)-based PIM. In the LUT-based PIM, low-bit precomputed products of low-bit multiplications (e.g., 3-bit x 3-bit) are stored in the LUTs, using the multiplication operands as addresses (e.g., 6-bit addresses). At runtime the LUT, in response to the multiplication operands, outputs the precomputed product. The products can be accumulated using, for example, registers or DSP slices positioned adjacent to block RAM. Such positioning can help minimize data transfer latency and reduce operating power consumption.

[0019] In various embodiments, the chip implementation can include preprocessing logic that, in a functional sense, can precede the PIM-configured quantized NN logic. The functions of the preprocessing logic can comprise, e.g., noise filtering and/or normalizing of the sensor data.

[0020] In one or more embodiments, the chip implementation can include anomaly detection logic. The functions of the anomaly detection logic can include determining, at least in part from the NN logic output, whether the sensor data indicates an anomaly.

[0021] Chip implementation can be in a Field-Programmable Gate Array (FPGA), an application-specific integrated circuit (ASIC), or a System-on-Chip (SoC).

[0022] Disclosed embodiments’ combination of quantized NN low-latency, low-complexity PIM-implemented ALUs, and the reduced precision of the calculations (quantization) to 1-7 bits, enables the system to operate effectively with much lower resource demands. FPGAs, ASICs, and SoCs arc employed for in-memory computing, enhancing processing speed and efficiency by minimizing data transfer bottlenecks.

[0023] In operation, the edge device’s chip-implemented combination of function blocks, implemented on an FPGA, ASIC, or SoC, comprising at least the preprocessor, the low-bit resolution quantized PIM-implemented NN, and the anomaly detection logic, can collect real-time data from its environment or connected sensors, preprocess the data, and feed the processed data into the quantized NN including transformers. As is known to persons of ordinary skill in the relevant arts, transformer neural networks are distinguished by their use of self-attention mechanisms. The mechanisms allow the model to assign varying levels of importance to different parts of an input sequence. This enables the network to capture complex temporal or contextual dependencies, making it especially effective for analyzing real-time sensor data. In practices according to various disclosed embodiments, quantized transformer NNs may be employed as part of the low-bitwidth neural network implemented using processing-in-memory techniques on FPGA, ASIC, or SoC hardware.

[0024] The operation of the chip -implemented combination can process the sensor data to detect deviations from normal patterns (anomalies) in real-time. In an aspect, in the chip or external to the chip can be a logic that, responsive to detecting an anomaly, can generate an alert or take, e.g., predefined actions to mitigate potential of risk. Alternative methods of construction and/or operation include using hybrid models, for example, combining cloud-based processing for more complex tasks while maintaining edge-level real-time detection via a quantized NN, for simpler anomalies.

[0025] In some embodiments, the PIM-configured quantized NN logic can be arranged as a PIM-configured quantized autoencoder. In an aspect,, the PIM-configured quantized autoencoder can include a PIM configured a quantized encoder section, configured with weights to generate a latent space representation. The PIM-configured quantized autoencoder can also include a PIM- configured quantized decoder section, also configured with weights to perform a reconstruction process that, using the latent space representation as inputs, can generate a reconstructed estimation of the sensor data.

[0026] In the example, the preprocessing unit can feed the processed sensor data into the encoder section of the quantized autoencoder, where weights and activations can be represented using, for example, 1-7 bits. The quantized encoder can be configured to perform a dimensionality reduction, creating a compressed latent space representation. The quantized encoder section can output the compressed latent representation to the quantized decoder section of the quantized autocncodcr. The quantized decoder section, using a process flow through a plurality of NN synapses that apply training-generated decoding weights, can generate reconstructed input patterns.

[0027] The FPGA-implemented quantized encoder and decoder modules can be composed of layers of matrix-vector multiplications executed, for example, by MAC units described above As described, the MAC units can be implemented using LUT-based PIM techniques, e.g., . In the LUT implementation of PIM, low-bit multiplications (e.g., 3-bit x 3-bit) can be performed by accessing, using the multiplication operands as addresses, precomputed results stored in the LUTs. The stored multiplication products output from the LUT can be accumulated using, for example, registers or DSP slices positioned adjacent to block RAM. As also described, such positioning can help minimize data transfer latency and reduce operating power consumption.

[0028] In an aspect, the reconstructed input patterns generated by the quantized decoder can be passed to an anomaly detection logic, compared against the expected reconstruction and, based on the difference, deviations can be identified. In some embodiments, one or more concluding operations can be performed after the detection of an anomaly. The concluding operations can comprise, for example, triggering an alert or actuating an intervening action if anomalies are detected, enabling real-time intervention.

[0029] Example Benefits and Advantages

[0030] Systems and methods according to disclosed embodiments can provide numerous advantages. By utilizing lower data resolution quantized neural networks, the system can function effectively with significantly less hardware and lower power consumption, making it highly resource efficient. The combination of PIM-implemented, quantized NN designs and FPGA, ASIC, or SoC-based computing enables real-time anomaly detection. The real-time anomaly detection can be crucial for timely interventions in various applications. This efficiency also translates to cost savings for both deployment and operation. Moreover, the system design is scalable. This provides system adaptability, e.g., to different applications and edge devices with different resource constraints.

[0031] In terms of its nature, embodiments constitute a new process by employing a combination of (1) low-resolution quantized neural networks (2) implementation on a FPGA, ASIC or SoC specifically using processing-in-memory computing (3) for the specific purpose of anomaly detection. Embodiments can also enable new apparatuses and/or products specifically designed for efficient anomaly detection on edge devices. In addition, systems and methods according to this disclosure and its appended claims can embody a plurality of significant improvements over existing edge device computing and anomaly detection. In terms of technology and performance, improvements include enhancing accuracy, efficiency, and applicability in resource-constrained environments, providing a robust, efficient, and scalable solution for various industries requiring real-time monitoring and anomaly detection.

[0032] Illustrative Applications

[0033] Applications for systems and methods according to disclosed embodiments are extensive and span multiple industries. Reasons include, e.g., the embodiments’ provision of efficient realtime anomaly detection capabilities on edge devices. Applications of systems and methods according to one or more embodiments can include cybersecurity, e.g., for loT network security, including but not limited to monitoring and detecting anomalies, and for enhanced security through identifying potential threats in real-time. Applications in healthcare include, but are not limited to, deploying systems according to one or more embodiments to monitor patient vital signs and, through edge device quantized NN-based anomaly detection resources according to one or more embodiments, swiftly detecting abnormalities, and enabling timely medical interventions.

[0034] Environmental monitoring could be revolutionized by deploying, e.g., in edge devices in autonomous underwater vehicles (AUVs) and/or unmanned aerial vehicles (UAVs), chip- implemented quantized NN-based anomaly detection units, e.g., FPGAs, ASICs, and/or SoCs, according to one or more embodiments, together with sensors. The functionalities of such systems can include, for example and without limitation, real-time detection of pollution-producing events and a range of natural disasters. Such real-time detection capability can, in turn, enable proactive measures.

[0035] AUVs and UAVs deployed with edge device quantized NN-based anomaly detection resources according to various embodiments can provide remote inspection of infrastructure, by detecting, for example, leaks and structural damage in pipelines and offshore platforms, and so forth. Additionally, edge devices equipped with quantized NN-based anomaly detection units according to various embodiments can be used, generally, in any vehicle or machinery to detect, e.g., faulty operating conditions or deliberate attacks.

[0036] In transportation, anomaly-detecting edge devices according to various embodiments may be integrated into, for example, autonomous vehicles and public transportation systems. Such integration can provide, for example, improvements in safety and efficiency through real-time data monitoring and corresponding enabling of timely response.

[0037] Retail and supply chain management can benefit from detecting anomalies in inventory levels, logistics, and customer behavior patterns, optimizing operations, and improving decisionmaking.

[0038] Wearable technology can incorporate this system for real-time health monitoring, anomaly detection and in-situ intervention, leading to personalized health management. Healthcare providers could use it for patient monitoring, improving treatment outcomes.

[0039] Additionally, defense and aerospace applications could benefit from enhanced monitoring and security of critical systems, ensuring timely detection of potential threats or system failures. [0040] Technology companies specializing in edge computing, Al, and cybersecurity could integrate it into their solutions to enhance efficiency and security. Manufacturing entities can benefit from real-time anomaly detection to prevent equipment failures and optimize processes. Financial institutions could deploy it for fraud detection and risk management. Municipalities aiming for smart city initiatives could utilize systems and methods according to various embodiments for infrastructure monitoring and public safety. Telecom companies could employ it for network performance monitoring, while defense and aerospace industries could enhance system security. Overall, this disclosure appeals to a broad range of industries seeking to improve efficiency, security, and real-time decision-making in resource-constrained environments.

[0041] EXAMPLES

[0042] Example 1 - FPGA Implemented Quantized NN-Based Anomaly Detector

[0043] FIG. 1 illustrates a functional block schematic of an arrangement 100 of one example chip-implemented PIM-based, quantized neural network unit for edge device anomaly detection systems according to various embodiments. In the arrangement 100, a region of the FPGA device 101 is programmed as a sensor interface logic block 102 configured to receive sensor data. The sensor data may be generated, for example, by a measurement sensor in the edge device. The sensor data may be generated, as another example, by an external sensor. The external sensor could be, for example, a strain gauge attached, e.g., to a bridge truss. In such an example, the edge device could be a piloted or autonomous drone, and communication of the strain gauge data could be provided by, for example, equipping the gauge and the edge device with Near Field Communication (NFC) chips.

[0044] In the arrangement 100, another region of the FPGA device 101 may be programmed as a preprocessing logic block 104 that can receive sensor data from the sensor interface logic block 102, e.g., through programmed FPGA connections. Functionality of the preprocessing logic block 104 may include, for example, noise filtering of the sensor data. The block 104 functionality may also include normalization of the sensor data.

[0045] With continuing reference to FIG. 1, a significantly dimensioned area of the FPGA device 101 may be programmed as a quantized NN logic block 106. The programming of the FPGA quantized NN logic block 106 can be configured to form a plurality of MAC units arranged and interconnected in an array -like architecture.

[0046] The FPGA 101 quantized NN logic block 106 can arrange the MAC units to perform layers of matrix-vector multiplications. The MAC units can be implemented using PIM techniques, as described in more detail in Example 2 below. Arithmetic operations throughout the NN logic block, particularly MAC computation, can be implemented using LUT-based PIM techniques. In this implementation, low-bit multiplications (e.g., 3-bit x 3-bit) are resolved through precomputed results stored in FPGA lookup tables (LUTs). The multiplication products output from the LUTs can be accumulated using registers or DSP slices positioned adjacent to block RAM, minimizing data transfer latency and operational energy.

[0047] According to various embodiments, another area of the FPGA device 101 may be programmed as on-chip anomaly detection logic 108 that, by operations such as comparing the quantized NN logic block 106 output(s) to thresholds, can identify anomalies in the environment. Finally, another area of the FPGA device 101 can be programmed as an alert-notification-actuation logic 110. The thresholds can be configured, for example, to avoid false alarms, enabling real-time intervention.

[0048] It will be understood that the Example 1 system is not limited to FPGAs. Persons having ordinary skill in the arts relating to this disclosure, and possessing and referencing this entire disclosure for guidance, can adapt this Example 1 and Example 2 to implement these, for example, in an ASIC or an SoC without undue experimentation.

[0049] Example 2 - PIM-Based Quantized Multiplier-Accumulator (MAC) Unit

[0050] FIG. 2 is a graphic rescaling of FIG. 1, also illustrating a functional block schematic of one arrangement of a PIM -based quantized MAC unit 202 of the FIG. 1 chip-implemented PIM- based quantized NN anomaly detector 101. [0051] The FPGA-based PIM-implemented quantized NN logic block 106 can be composed of layers of matrix-vector multiplications executed by MAC units. As shown in the FIG. 2 block schematics of the MAC units 202, arithmetic operations throughout the PIM-based quantized NN 106, particularly MAC computations, can be implemented with LUT 206 PIM techniques. As seen in FIG. 2 PIM implementation of the low-bit multiplications (e.g., 3-bit x 3-bit) can be resolved by using the multiplication operands as addresses to retrieve precomputed products from the LUTs 206. The products can be accumulated using registers or DSP slices 208, which can be positioned adjacent to block RAM, minimizing data transfer latency and operational energy.

[0052] Example 3 - Operation Flow - Quantization- A ware Training, and

Edge Device Process of Real-Time Detection of Anomalies

[0053] FIG. 3 illustrates an operational flow diagram 300 of quantization-aware training and operations in a process for real-time detection, on an edge device with a chip-implemented quantized NN -based anomaly detector, of anomalies in an environment.

[0054] In one example, operations can include, at 302, receiving a design description into a commercially available FPGA software design tool, and the tool converting the description into hardware logic compatible with FPGA implementations. The design description can be a high- level architectural description, and one example design tool is the AMD(TM) (previously Xilinx(TM)) Vivado (TM) High-Level Synthesis (HLS), which is available from Advanced Micro Devices, Inc., 2485 Augustine Drive, Santa Clara, CA 95054, United States. The Vivado HLS and equivalents from other vendors enable conversion of the high-level architectural descriptions into hardware logic compatible with FPGA implementations.

[0055] . During the design 302 , certain architecture- specific considerations are addressed that differ from conventional neural network practices. For example:

[0056] MAC units are implemented using PIM LUT-based logic configured to support low-bit width operands (e.g., 1-7 bits), rather than standard 16- or 32-bit arithmetic pipelines. This modification enables compatibility with in-memory computing strategies and minimizes resource utilization. Activation function implementations are simplified using fixed-segment logic or piecewise-linear approximations rather than full arithmetic evaluation, further reducing hardware complexity, and memory interfacing is adapted to minimize data movement by physically colocating BRAM or SRAM blocks with DSP slices or logic tiles, supporting the in-memory compute paradigm central to the invention. [0057] Operation also includes, beginning at block 306, input data being received from one or more sensors or data sources. At block 308, the data is prcproccsscd using standard techniques such as normalization, scaling, or noise filtering. The preprocessed data is then split into training and testing datasets at block 310.

[0058] At block 314, the designed network is trained using a quantization-aware training algorithm and a training dataset (block 312). The resulting quantized model is then deployed onto the target FPGA, ASIC, or SoC device at block 316. In one embodiment, implementation includes mapping the trained network’s quantized weights and operations to fixed-point logic blocks within the FPGA. At block 318, the testing dataset (block 318) is evaluated using the deployed model. For each input, an anomaly score (AS) is generated. This score is compared to a predefined threshold value. If the anomaly score is below the threshold, the data sample is classified as normal (block 320). If the score exceeds the threshold, the sample is classified as malicious or anomalous (block 322), triggering appropriate system responses.

[0059] Example 4 - FPGA Implemented Quantized Autoencoder-Based Anomaly Detector [0060] FIG. 4 illustrates a functional block schematic 400 for one example chip-implemented PIM-based quantized autoencoder unit for edge device anomaly detection systems according to various embodiments. FIG. 5 is a graphic rescaling of FIG. 4 with a functional block schematic of one arrangement of the PIM-based quantized MAC units of the quantized autoencoder.

[0061] Referring to FIG. 4, in the arrangement 400, a region of the FPGA device 401 may be programmed as a preprocessing logic block 402 that can receive sensor data from the sensor interface logic block 102, e.g., through programmed FPGA connections. Functionality of the preprocessing logic block 402 may be similar to, or even identical to the functionality of preprocessing logic block 104 of the FIG. 1 system 100, i.e., noise filtering of the sensor data and/or normalization of the sensor data. Differences may arise, though, due to the autoencoder configuration of FIG. 4 function blocks 404 and 406.

[0062] With continuing reference to FIG. 4, a significantly dimensioned area of the FPGA device 401 may be programmed as a quantized NN encoder logic block 404. The programming of the quantized NN encoder logic block 106 can be configured to form the block as a plurality of quantized MAC units arranged and interconnected in an array- 1 ike architecture. The architecture can be configured such that functionality of the quantized NN encoder logic block 404 includes dimensionality reduction of the processes sensor data from preprocessing logic block 402, creating a compressed latent representation, as visible in FIG. 4. According to various embodiments, another significantly dimensioned area of the FPGA device 401 may be programmed as a quantized NN decoder logic block 406. The programming forming the quantized NN decoder logic block 406 can be configured to form another plurality of MAC units, also arranged and interconnected in an array-like architecture. The block 406 MAC units and their arrangement and interconnection can be configured such that the quantized NN decoder logic block 406 functionality includes a decoding that generates, from the compressed latent representation, reconstructed input patterns.

[0063] The FPGA-based encoder 404 and decoder 406 sections or modules can be composed of layers of matrix-vector multiplications executed by the MAC units. The MAC units can be implemented using PIM techniques, as described in Example 2 above. Arithmetic operations throughout the quantized NN encoder 404 and quantized NN decoder 406, particularly MAC computation, can be implemented using LUT-based PIM techniques. This can be the same implementation described above in reference to FIG. 2, e.g., low-bit multiplications (e.g., 3-bit x 3-bit), using precomputed results stored in FPGA LUTs, and multiplication products accumulated using registers or DSP slices positioned adjacent to block RAM, minimizing data transfer latency and operational energy.

[0064] In some embodiments, another area of the FPGA device 401 may be programmed as on- chip anomaly detection logic 408 that, by operations such as comparing the decoded signals with the expected reconstruction, can identify anomalies in the environment. Another area of the FPGA device 401 can be programmed as an alert-notification-actuation logic 410. The thresholds can be configured, for example, to avoid false alarms, enabling real-time intervention.

[0065] Example 5 - FPGA Implemented Quantized FFT-Quantized NN-based Anomaly Detection System for Edge Devices.

[0066] FIG. 6 illustrates a functional block schematic 600 of one example chip-implemented, quantized FFT-quantized PIM, NN-based anomaly detection system for edge devices, according to various embodiments. The implementation can be comparable to Example 1 described above, with the only difference being the quantized frequency domain transformer unit 602 functionally positioned between the preprocessing unit 104 and the quantized PIM-based NN 106.

[0067] It is to be understood that practices that are within the scope of the appended claims are not limited to particular embodiments described, as embodiments described herein are susceptible to various modifications and alternative forms. Embodiments are disclosed by way of example in the drawings and arc described in detail herein. The example embodiments described, though, arc not limited to the particular explicit implementations, configurations, arrangements, and forms disclosed. Rather, the instant disclosure supports all modifications, equivalents, and alternatives that fall within the scope of the appended claims.

[0068] It is also to be understood that the terminology used herein is for the purpose of describing particular embodiments only, and is not intended to be limiting, as the scope of exclusivity will be limited only by the appended claims.

[0069] Where a range of values is provided, it is understood that each intervening value, to the tenth of the unit of the lower limit unless the context clearly indicates or dictates otherwise, between the upper limit and lower limit of that range and any other stated or intervening value in that stated range, is encompassed within the range. The upper and lower limits of these smaller ranges may independently be included in and encompassed in the smaller ranges, subject to any specifically excluded limit in the stated range. Where the stated range includes one or both of the limits, ranges excluding either or both of those included limits are also included.

[0070] Ordinal terms such as “first,” “second,” “third,” etc., as used in this specification and the appended claims to modify, e.g., step(s), functional block(s), signal(s), instruction(s), element(s) are to be understood as a labelling to individually reference separate step(s), functional block(s), signal(s), instruction(s), and/or element(s), and are not to be understood, except where expressly stated or clearly indicated as otherwise, to be any indication of any ordering of the step(s), functional block(s), signal(s), instruction(s), and/or element(s), in terms of time, spatial arrangement, priority, or to be any indication of the presence or inclusion of any of ordinal term referenced step(s), functional block(s), signal(s), instruction(s), and/or element(s) being conditional on the presence or inclusion of any different ordinal term referenced step(s), functional block(s), signal(s), instruction(s), and/or element(s) indication of relative priority.

[0071] Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art(s) to which this disclosure relates.

[0072] Representative and illustrative methods and materials are described herein. Methods and materials similar or equivalent to those described herein can also be used in practices according to disclosed embodiments.

[0073] It is to be understood that, as used herein and in the appended claims, the singular forms "a", "an", and "the" include plural referents unless the context clearly dictates otherwise. It is further noted that the claims may be drafted to exclude any optional clement. As such, this statement is intended to serve as support for the recitation in the claims of such exclusive terminology as "solely," "only" and the like in connection with the recitation of claim elements, or use of a "negative" limitations, such as "wherein [a particular feature or element] is absent", or "except for [a particular feature or element]", or "wherein [a particular’ feature or element] is not present (included, etc.)...".

[0074] As will be apparent to those of skill in the ail upon reading this disclosure in its entirety, each of the individual embodiments described and illustrated herein has discrete components and features that may be readily separated from the embodiment or combined with features of any of the other several embodiments without departing from the scope or spirit of the present invention. [0075] It is to be understood that various methods and operations are described as a plurality of separate actions, steps, or operations but it will also be understood that such description can be for further assisting the reader in gaining an understanding of, for example, concepts and/or logic relationships and should not be understood as limiting the order in which the actions, steps, or operations can be performed and that these can be carried out in the temporal order or spatial arrangement recited or in any other order or arrangement that is logically possible.

[0076] While the disclosure describes features and aspects in terms of its several exemplary embodiments, those skilled in the ail will recognize that the invention can be practiced with modification within the spirit and scope of the appended claims. Accordingly, the appended claims are not limited to the embodiments as described above, but should further include all modifications and equivalents thereof within the spirit and scope of the description provided herein.

Claims

CLAIMS Wc claim:

1. An anomaly-detecting edge device, comprising: an interface circuit, configured to receive a sensor data; a preprocessing circuit, communicatively connected to the interface circuit and configured to preprocess the sensor data, and correspondingly output processed sensor data: a quantized neural network (NN) circuit, communicatively connected to the preprocessing circuit, wherein: the quantized NN circuit is configured to perform an NN-based quantized dimensionality reduction processing of the processed sensor data, outputting a quantized lower-dimensional latent representation, the quantized NN circuit comprises one or more multiply-accumulate units (MACs), each including a quantized processing-in-memory (PIM) unit that includes at least one quantized-arithmetic-result (QAR) lookup table, , and an anomaly detecting circuit, configured to determine, based at least in part on the quantized reconstructed input pattern data, a reconstruction error value and to detect, based at least in part on a magnitude of the reconstruction error value, an anomaly.

2. The anomaly-detecting edge device of claim 1 , wherein at least one of the quantized MACS is configured to perform 1 -bit to 4-bit quantized computation.

3. The anomaly-detecting edge device of claim 1, further comprising a field-programmable gate array (FPGA) chip, wherein the interface circuit comprises a first region of the FPGA chip, programmed with an interfacing functionality that includes interfacing the sensor device and receiving, from the sensor device, the sensor data, and the preprocessing circuit comprises a second region of the FPGA chip, programmed with a preprocessing functionality that includes normalizing the sensor data, or filtering noise from the sensor data, or both. nomaly-detecting edge device of claim 1 , , wherein: the quantized NN circuit includes a quantized NN encoding section and a quantized NN decoding section, the quantized NN encoder section is configured to perform an NN-based quantized dimensionality reduction processing of the processed sensor data, outputting a quantized lower-dimensional latent representation, the quantized NN decoder section is configured to perform an NN-based quantized reconstructive decoding processing of the quantized lower-dimensional latent representation, outputting a quantized reconstructed input pattern data, the quantized NN encoder section comprises one or more encoder section quantized MACs, each including an encoder section quantized PIM unit that includes at least one encoder section quantized-arithmetic-result lookup table, and the quantized NN decoder section comprises one or more decoder section quantized MACs, each including a decoder section quantized PIM unit that includes at least one decoder section quantized- arithmetic result lookup table, and the anomaly detecting circuit is further configured to: determine, based at least in part on the quantized reconstructed input pattern data, a reconstruction error value, and detect the anomaly further based at least in part on the magnitude of the reconstruction error value.