WO2025251683A1 - 指令处理方法、装置、电子设备和计算机程序产品 - Google Patents

指令处理方法、装置、电子设备和计算机程序产品

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Publication number
WO2025251683A1
WO2025251683A1 PCT/CN2025/077836 CN2025077836W WO2025251683A1 WO 2025251683 A1 WO2025251683 A1 WO 2025251683A1 CN 2025077836 W CN2025077836 W CN 2025077836W WO 2025251683 A1 WO2025251683 A1 WO 2025251683A1
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Prior art keywords
target
physical register
data
register
physical
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English (en)
French (fr)
Inventor
谢瑞祺
蒋昭
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Alibaba China Co Ltd
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Alibaba China Co Ltd
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30098—Register arrangements
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/3004—Arrangements for executing specific machine instructions to perform operations on memory

Definitions

  • This application relates to the field of processors, and more specifically, to an instruction processing method, apparatus, electronic device, and computer program product.
  • registers are high-speed storage units within the processor, accessed much faster than main memory.
  • the processor needs to perform data operations, it can use write instructions to load data from memory into registers. Once the data is loaded into the registers, the processor can quickly process and compute it without waiting for memory access.
  • the processor writes the corresponding data into the register for each data write instruction executed.
  • Multiple data write operations consume a lot of power and take a long time.
  • This application provides an instruction processing method, apparatus, electronic device, and computer program product to at least solve the technical problem of high power consumption and long time consumption during multiple data write operations when the processor executes data write instructions multiple times.
  • an instruction processing method comprising: receiving a target data write instruction, wherein the target data write instruction carries a target memory address where the target data to be written to a physical register is located; responding to the target data write instruction, searching for whether there is a target physical register corresponding to the target memory address based on the correspondence between physical registers and memory addresses; and if the search result indicates that there is a target physical register corresponding to the target memory address, returning a data write result indicating that the target data has been written to the target physical register.
  • an instruction processing apparatus including: a receiving module, configured to receive a target data write instruction, wherein the target data write instruction carries a target memory address where the target data to be written to a physical register is located; a response module, configured to, in response to the target data write instruction, search for whether a target physical register corresponding to the target memory address exists based on the correspondence between physical registers and memory addresses; and a return module, configured to, if the search result indicates that a target physical register corresponding to the target memory address exists, return a data write result indicating that the target data has been written to the target physical register.
  • a computer-readable storage medium which includes a stored executable program, wherein, when the executable program is running, it controls the device where the storage medium is located to execute the instruction processing methods in various embodiments of this application.
  • a computer program product including a computer program that, when executed by a processor, implements the instruction processing methods in various embodiments of this application.
  • a mapping between physical registers and memory addresses is established.
  • a target data write instruction is received, carrying the target memory address where the target data to be written to the physical register is located.
  • a search is conducted to determine if a target physical register corresponding to the target memory address exists. If the search result indicates the existence of a target physical register corresponding to the target memory address, a data write result indicating that the target data has been written to the target physical register is returned. This achieves the goal of directly using the target physical register for subsequent processing when the target physical register storing the data at the target memory address is found, eliminating the need to write the data at the target memory address to the physical register again. This reduces the power consumption and time required for the processor to execute data write instructions, thereby solving the technical problem of high power consumption and long processing time during multiple data write operations when the processor executes data write instructions multiple times.
  • Figure 1 shows a hardware block diagram of a RISC-V system for implementing instruction processing methods
  • FIG. 2 shows a schematic diagram of a System-on-Chip (SOC) using the RISC-V architecture shown in Figure 1 above;
  • FIG. 3 is a flowchart of the instruction processing method according to Embodiment 1 of this application.
  • FIG. 4 is a schematic diagram of the processing matrix instructions provided according to an optional embodiment of this application.
  • Figure 5 is a schematic diagram of the physical matrix register file provided according to an optional embodiment of this application.
  • Figure 6 is a schematic diagram of the physical matrix register state table provided according to an optional embodiment of this application.
  • Figure 7 is a schematic diagram of an instruction processing method provided according to an optional embodiment of this application.
  • FIG. 8 is a structural block diagram of the instruction processing apparatus according to Embodiment 2 of this application.
  • Figure 9 is a structural block diagram of an electronic device according to an embodiment of this application.
  • Registers Structures that can be directly accessed by CPU instructions and are used to store data.
  • Architectural Register A software concept of register status.
  • Architectural register is a concept in computer architecture.
  • Computer architecture is the interface between computer hardware and software, defining how the computer executes instructions, stores data, and processes input and output.
  • registers are high-speed storage units used to store instructions, data, and control information.
  • Architectural registers refer to registers explicitly defined in computer architecture, which have specific functions and operating rules in different instruction set architectures (ISAs).
  • the main functions of architectural registers include: (1) Storing instruction addresses: The program counter (PC) is a common architectural register that stores the address of the currently executing instruction. (2) Data transfer: General Purpose Registers (GPRs) are used to store temporary data, such as operation results and variables.
  • PC program counter
  • GPRs General Purpose Registers
  • Status control Status Registers (SRs) or Flag Registers are used to store processor status information, such as interrupt flags and condition codes.
  • Control Registers are used to control specific functions of the processor, such as exception handling and interrupt masking. Architecture registers are typically explicitly defined in the instruction set architecture (ISA), and programmers must follow these rules to access and manipulate these registers when writing programs. Different computer architectures may have different architecture registers, but their basic functions and roles are similar.
  • Physical registers Register entities implemented in hardware that can act as mappings of architectural registers and be visible to software.
  • Register file A collection of multiple registers.
  • Cache A storage device used to temporarily store data at certain addresses in memory.
  • Memory access Reading or writing data from memory or cache.
  • Load instruction An instruction used to move data from a specified address in memory into a register.
  • Store instructions Instructions used to write data from a register to a specified address in memory.
  • Stride In matrix load or store instructions, the difference in memory addresses between two adjacent rows of a register.
  • Base address The starting address of memory accessed by matrix load or store instructions.
  • Cache line The smallest data granularity managed by the cache, typically 64 bytes in size.
  • Cache hit The memory data required by the load instruction is already fully present in the cache.
  • Register renaming The hardware maps architectural registers to physical registers of a certain entity, and subsequent access to that physical register represents access to the corresponding architectural register.
  • a matrix coprocessor is a hardware device or software component designed for matrix operations. Matrix operations are a crucial computational task in computer science and engineering, including linear algebra, image processing, signal processing, and machine learning. Matrix coprocessors can significantly improve overall computational efficiency by optimizing the performance of these matrix operations.
  • the main features and functions of a matrix coprocessor include: (1) Dedicated hardware: A matrix coprocessor may be a standalone hardware device or a specific hardware module integrated into a CPU or other processor. This hardware is specifically designed for efficient matrix operations. (2) Optimized algorithms: Compared to a CPU, a matrix coprocessor typically employs optimized algorithms and data structures to process matrix operations, which helps reduce computation time and resource consumption.
  • Matrix coprocessors typically support parallel processing, allowing the simultaneous processing of multiple matrix elements, thereby increasing computational speed.
  • Floating-point arithmetic capability Since matrix operations often involve a large number of floating-point operations, matrix coprocessors are usually equipped with powerful floating-point units.
  • Memory management Matrix coprocessors may optimize memory access patterns to reduce the impact of memory latency and bandwidth limitations on performance.
  • Software support Matrix coprocessors typically have corresponding software libraries or APIs, allowing programmers to easily call upon the functions of these hardware components in their programs.
  • Application-specific optimization Some matrix coprocessors may be optimized for specific types of matrix operations or applications, such as graphics processing and machine learning algorithms. Using matrix coprocessors can significantly improve the performance of specific types of computational tasks, especially in application scenarios that require a large number of matrix operations. However, they are generally not suitable for general-purpose computing tasks because their design focuses on specific computational patterns.
  • an instruction processing method is provided. It should be noted that the steps shown in the flowchart in the accompanying drawings can be executed in a computer system such as a set of computer-executable instructions. Furthermore, although a logical order is shown in the flowchart, in some cases, the steps shown or described may be executed in a different order than that shown here.
  • FIG. 1 shows a hardware structure block diagram of a RISC-V system for implementing the instruction processing method.
  • the RISC-V system 100 can be divided into the following layers from bottom to top: Reduced Instruction Set Architecture 101 (including basic instruction set 101-1 and extended instruction set 101-2), hardware layer 102 (including processor 102-1, peripheral hardware circuits 102-2, etc.), interface layer 103, operating system layer 104 (supporting multiple operating systems 104-1, 104-2, ..., 104-n, such as Linux, FreeSBD, RT-Tread, etc.), middleware and library layer 105 (including system library 105-1, API 105-2, and middleware service 105-3), and application layer 106 (including multiple user programs and services 106-1, 106-2, ..., 106-n).
  • Reduced Instruction Set Architecture 101 including basic instruction set 101-1 and extended instruction set 101-2
  • hardware layer 102 including processor 102-1, peripheral hardware circuits 102-2, etc.
  • interface layer 103 interface layer 103
  • operating system layer 104 supporting multiple operating systems 104-1, 104-2, ..., 104-n, such as Linux, FreeSBD, RT-Tread,
  • the RISC-V system 100 also includes a toolchain 107 that runs from the underlying hardware to the application layer.
  • This toolchain may include compilers and assemblers 107-1, linkers 107-2, debuggers 107-3, simulators and emulators 107-4, integrated development environments 107-5, hardware description language tools 107-6, performance analysis tools 107-7, and version control systems 107-8, etc.
  • the instruction set architecture 101 defines the basic operations and instruction sets supported by the processor 102-1, including the basic instruction set and the extended instruction set.
  • the basic instruction set represents the basic integer instruction set, such as RV32I and RV64I, while the extended instruction set can be floating-point, atomic operations, compressed instructions, etc.
  • Interface layer 103 includes the specific design of the processor, such as pipeline design, cache structure, execution units, branch prediction, etc. This layer is the process of mapping abstract instructions to physical hardware.
  • the operating system layer 104 sits above the hardware, providing a hardware abstraction layer and management mechanisms, enabling applications to interact with the hardware through system calls.
  • the operating system is responsible for managing processor resources, memory, device drivers, task scheduling, and more.
  • the middleware and library layer 105 provides a rich set of services and interfaces to help applications run more efficiently.
  • the standard library provides functions such as file operations and mathematical calculations, while middleware can provide complex services such as network communication and graphical user interfaces.
  • the application layer 106 utilizes the functions and services provided by the lower layer to implement specific application logic. These applications can be command-line tools, graphical interface applications, server-side services, etc.
  • the layered design of the RISC-V architecture allows for decoupling between different layers, enabling each layer to be developed and optimized independently.
  • Figure 2 illustrates a schematic diagram of a System-on-Chip (SOC) using the RISC-V architecture shown in Figure 1.
  • the SOC contains at least one RISC-V core 202 (only one is shown in the figure).
  • the RISC-V core 202 is connected to peripheral devices via bus 204, including but not limited to ROM 206, RAM 208, timer 210, UART (Universal Asynchronous Receiver/Transmitter) 212, GPIO (General Purpose Input/Output) 214, SPI (Serial Peripheral Interface Bus) 216, etc.
  • bus 204 including but not limited to ROM 206, RAM 208, timer 210, UART (Universal Asynchronous Receiver/Transmitter) 212, GPIO (General Purpose Input/Output) 214, SPI (Serial Peripheral Interface Bus) 216, etc.
  • registers are high-speed storage units inside the processor, and their access speed is much faster than that of memory.
  • the processor needs to perform data operations, it can quickly process and calculate the data written to the registers without waiting for memory access.
  • Step S301 Receive target data write instruction, wherein the target data write instruction carries the target memory address where the target data to be written to the physical register is located.
  • the execution entity can be the processor, and the target data write instruction is used to write the target data into the physical register, which includes the target memory address where the target data is located in memory.
  • the processor can locate the target data in memory according to the target memory address and copy the target data into the physical register so that the processor can quickly read the data from the physical register and process it when processing the target data.
  • the instruction processing method provided by this invention can be applied to the operation of matrix data.
  • the execution entity can be a matrix coprocessor
  • the target data can be matrix data.
  • the target data write instruction can be a target matrix load instruction.
  • multiple physical registers need to be set up to store the matrix data.
  • Each physical register can be a two-dimensional structure containing multiple rows, and each row can store data.
  • Figure 4 is a schematic diagram of processing matrix instructions according to an optional embodiment of this application.
  • a matrix coprocessor when processing matrix instructions, can be configured to handle the matrix instructions.
  • the extended matrix register, the newly added matrix instruction execution unit, the matrix memory access subsystem, the matrix data cache, and other hardware structures can be implemented inside the "matrix coprocessor" outside the CPU core, decoupled from the CPU core.
  • the matrix coprocessor and the CPU core are connected via a bus and can communicate with each other.
  • the matrix coprocessor and the CPU core share a certain level of cache.
  • the matrix coprocessor works as follows: the CPU fetches the instruction stream from the instruction memory and decodes it. If the CPU determines that an instruction is a matrix instruction, it sends the instruction to the external matrix coprocessor via the bus. The matrix coprocessor is then responsible for the specific execution process of this matrix instruction, including accessing the matrix register file, performing matrix operations, accessing the internal matrix data cache, and initiating access requests to the shared cache.
  • Step S302 In response to the target data write instruction, based on the correspondence between physical registers and memory addresses, search for whether there is a target physical register corresponding to the target memory address.
  • the processor can search based on the previously established correspondence between physical registers and memory addresses to determine whether there is a target physical register that has already stored the target data at the target memory address. In other words, in the correspondence between physical registers and memory addresses, it is determined that the memory address corresponding to the target physical register is the same as the target memory address.
  • mapping between physical registers and memory addresses can be updated synchronously each time data is written to the current physical register. This ensures that the memory address corresponding to the current physical register is the memory address where the data stored in the current physical register is located.
  • Step S303 If the search result shows that a target physical register corresponding to the target memory address exists, return the data write result of the target data being written to the target physical register.
  • the system searches the mapping between physical registers and memory addresses to determine if a target physical register exists corresponding to the target memory address. This confirms that target data has already been stored in the target physical register. At this point, it can be directly determined that the target data write instruction has been completed, as the target data has been written to the target physical register. The system then returns the data write result. In other words, the data write result indicates that the target data has been successfully written to the target physical register.
  • the instruction processing method provided by this invention can also be used. Based on the established correspondence between physical registers and memory addresses, it can be determined whether there is a target physical register that has already stored the target data. If so, the data writing result that the target data has been written to the target physical register can be returned directly.
  • a mapping between physical registers and memory addresses is established.
  • a target data write instruction is received, carrying the target memory address where the target data to be written to the physical register is located.
  • a search is conducted to determine if a target physical register corresponding to the target memory address exists. If the search result indicates the existence of a target physical register corresponding to the target memory address, a data write result indicating that the target data has been written to the target physical register is returned. This achieves the goal of directly using the target physical register for subsequent processing when the target physical register storing the data at the target memory address is found, eliminating the need to write the data at the target memory address to the physical register again. This reduces the power consumption and time required for the processor to execute data write instructions, thereby solving the technical problem of high power consumption and long processing time during multiple data write operations when the processor executes data write instructions multiple times.
  • the method before searching for the existence of a target physical register corresponding to the target memory address based on the correspondence between physical registers and memory addresses in response to a data write instruction, the method further includes: receiving one or more data write instructions, wherein the one or more data write instructions respectively carry the memory address where the data to be written to the physical register is located; writing data to the physical register in response to the one or more data write instructions; and establishing a correspondence between the physical registers for which data has been written based on the one or more data write instructions and the corresponding memory addresses.
  • This embodiment enables the instruction processing method to effectively receive and execute data write instructions before performing data write operations, while simultaneously establishing the correspondence between physical registers and memory addresses. This not only improves data processing efficiency but also facilitates subsequent data access and operations.
  • this optional embodiment is applied to the matrix data processing process, a correspondence can be established between the memory address where the matrix data is located and the physical register where the matrix data is written. Therefore, when it is necessary to write the matrix data to the physical register later, the correspondence can be used to determine whether the matrix data to be written has been previously written to a certain physical register. If so, there is no need to write the matrix data again, saving the energy consumption of repeatedly writing matrix data and improving the processing efficiency of matrix data.
  • a target physical register corresponding to the target memory address including: determining a target physical register group from multiple groups of physical registers according to the target memory address; matching the target memory address with the memory addresses corresponding to the physical registers included in the target physical register group, and finding that there is a target physical register corresponding to the target memory address.
  • processors typically use multiple physical registers to store data
  • searching through all of them to find the target physical register would be tedious, time-consuming, and energy-intensive.
  • all data-storing physical registers can be grouped according to certain rules to obtain multiple groups. Then, the search is performed within the target physical register group to confirm whether the target physical register exists within that group. This narrows the search to the target physical register group, instead of searching all data-storing physical registers, thus reducing time and energy consumption.
  • the grouping rules of physical registers can be set to be related to the memory addresses corresponding to the physical registers. That is, physical registers can be grouped according to their respective memory addresses, or, after grouping the physical registers, the memory addresses corresponding to the data that each group of physical registers can store are limited to a certain range.
  • the target physical register group can be located based on the total number of physical register groups and the index of the cache block where the target memory address is located.
  • the physical register group that can store the data can be found by using the memory address and the number of groups. Therefore, when searching for the target physical register that stores the target data, the target physical register group can be determined by using the target memory address and the number of groups.
  • all registers in the multiple physical registers are divided into M groups.
  • the matrix coprocessor assigns a physical register number to store data for each data write instruction, it must follow the following rules: the new physical register to be allocated must come from a specific group among the M groups in the multiple physical register files. The group number is calculated in a way that is related to the target memory address included in the data write instruction.
  • determining the target physical register group based on the index and the number of groups includes: taking the modulo of the number of groups using the index to obtain the modulo value; and using the modulo value as the group number of the target physical register group to determine the target physical register group.
  • the index of the cache block containing the target memory address can be modulo the number of groups, and the resulting modulo value is the group number of the target physical register group. It should be noted that the method of determining the group number of the target physical register group based on the modulo method is only one example, and methods of determining the group number of the target physical register group based on other calculation methods are also part of this application.
  • the method further includes: establishing a mapping between a target physical register and a target architecture register, wherein the data write instruction further includes the number of the target architecture register to which the target data is to be loaded, and the target architecture register is visible to the software.
  • the architecture register is a register that can be directly accessed by matrix instructions.
  • Each architecture register is a two-dimensional structure containing RLEN*(RLEN/32) bits, where (RLEN/32) is the row number of a matrix register, and RLEN is the number of bits in each row.
  • the number of architecture registers can be 8, numbered m0-m7 respectively. Of course, the number of architecture registers can be set according to specific needs, and can also be 16.
  • the matrix coprocessor maintains an internal physical matrix register file (multiple physical registers) consisting of K matrix registers, where the size of K depends on the specific hardware implementation but is at least greater than the number of architecture registers.
  • the matrix coprocessor selects 8 registers from the K register spaces in the physical matrix register file (22) as mappings to the 8 architecture registers m0-m7. This mapping relationship is recorded by a renaming mapping table. This table has 8 entries, each corresponding to an architecture register, and each entry records the physical register number in the physical matrix register file to which the current architecture register is mapped.
  • the process of establishing the mapping relationship between architecture registers and physical registers is also known as the register renaming strategy.
  • the above mapping relationship can be dynamically adjusted during program execution. That is, whenever a new matrix instruction is issued from the CPU core to the matrix coprocessor, if the instruction contains the destination architecture register number ⁇ md ⁇ , where ⁇ md ⁇ is a number between ⁇ m0 ⁇ and ⁇ m7 ⁇ , the matrix coprocessor will assign a new physical register mapping to that architecture register ⁇ md ⁇ and update the new physical register number in the renaming mapping table. It should be noted that the above renaming mapping table is not consistent with the correspondence between physical registers and memory addresses mentioned in this invention. The renaming mapping table establishes a correspondence between architecture registers and physical registers.
  • a mapping relationship can be established between the target physical register and the target architecture register in the data write instruction, and the rename mapping table can be updated so that the software can access the data in the physical register.
  • the target memory address when the target physical register includes multiple rows, includes a target base address and a target address step size.
  • the target base address is the starting address for writing data into the target physical register in memory
  • the target address step size is the difference between the memory addresses corresponding to two adjacent rows in the target physical register.
  • the base address corresponding to the target physical register matches the target base address
  • the address step size corresponding to the target physical register matches the target address step size.
  • This optional embodiment provides the format of the target memory address in a matrix load instruction (equivalent to a data write instruction) when processing matrix data.
  • the memory address carried by the matrix load instruction typically includes a base address and a stride.
  • the matrix load instruction loads data from different memory addresses for each row in the (RLEN/32) rows of the matrix register.
  • the starting memory address corresponding to the data loaded in the r-th row of the matrix register is calculated as "base address + r * stride", where r ranges from 0 to (RLEN/32) - 1.
  • both the target base address and the target address step size must match. Furthermore, matching means identical; only when the target base address in the target memory address is the same as the base address corresponding to a certain physical register, and the target address step size is also the same as the address step size corresponding to that physical register, is that physical register identified as the target physical register.
  • the method further includes: if the search result shows that there is no target physical register corresponding to the target memory address, determining a spare physical register; writing the target data at the target memory address into the spare physical register, and returning the data writing result that the target data has been written into the spare physical register.
  • the method for determining a spare physical register can be to find the corresponding target physical register group based on the target memory address, and then determine the spare physical register among the physical registers included in the target physical register group. Since physical registers need to establish a mapping relationship with architecture registers to be visible to software, when determining the spare physical register, it is also necessary to consider whether any architecture registers are currently being mapped to physical registers. If an architecture register is being mapped to a certain physical register, then that physical register cannot be used as a spare physical register.
  • mapping status A certain architecture register (m0-7) is currently being mapped to this physical register.
  • Cache status No architecture registers (m0-7) are currently being mapped to this physical register, but a matrix load instruction's destination register was previously mapped to this physical register, and the data loaded in this register is currently consistent with the latest data at the corresponding address in memory.
  • Idle state The physical register is in an idle state except for the two cases mentioned above.
  • FIG. 6 is a schematic diagram of the physical matrix register status table provided according to an optional embodiment of this application.
  • the correspondence between physical registers and memory addresses includes three types of information: base address, stride, and register status information.
  • the base address and stride are used to record the memory access base address and stride value of a matrix load instruction.
  • the destination matrix register of a matrix load instruction is mapped to a physical matrix register with the number pmd, then when this instruction is executed, it will not only load the data in memory into the physical matrix register with the number pmd, but also write the base address and stride information of this instruction into the position corresponding to the pmd number in the correspondence between physical registers and memory addresses, and adjust the register status corresponding to the pmd number to the mapped state.
  • Figure 7 is a schematic diagram of the instruction processing method provided according to an optional embodiment of this application.
  • the matrix coprocessor determines the type of the currently executed matrix instruction.
  • Matrix instructions are roughly divided into two categories: matrix operation instructions and matrix memory access instructions.
  • Matrix operation instructions generally specify 2-3 matrix registers from the architecture registers m0-m7 as source operands. After performing specific rule-based operations (such as floating-point/integer matrix multiplication and accumulation) on these data, the result is written into a destination matrix register specified from m0-m7.
  • Matrix memory access instructions are divided into matrix load instructions and matrix store instructions.
  • a matrix load instruction typically carries three pieces of information: the base address of the memory access, the stride of the access, and the matrix register number ⁇ md ⁇ to be loaded.
  • the matrix load instruction loads data from different memory addresses for each row in the (RLEN/32) rows of the matrix register.
  • the starting memory address corresponding to the data loaded in the r-th row of the matrix register is calculated as "base address + r * stride", where r ranges from 0 to (RLEN/32) - 1.
  • a matrix store instruction also carries three pieces of information: the base address of the memory access, the stride of the access, and the matrix register number ⁇ ms ⁇ to be stored.
  • the matrix store instruction writes each row in the (RLEN/32) rows of the matrix register numbered ⁇ ms ⁇ to different memory addresses.
  • the starting memory address corresponding to the r-th row is calculated as "base address + r * stride", where r ranges from 0 to (RLEN/32) - 1.
  • the matrix coprocessor determines that a matrix load instruction is being executed, before allocating a new physical register mapping for the destination matrix register of the instruction, it takes the index of the cache block where the base address of the matrix load instruction is located (i.e., the cacheline index) modulo M (%M means modulo M). Then, it needs to query the physical matrix register status table and check the information of N physical registers in the (Cacheline index %M)th group, including: base address, stride, and register status.
  • Scenario 1 If a register numbered pmdst0 is found among these N registers, and its register state is cached, and its base address and stride are exactly the same as the memory access base address and stride of the current matrix load instruction, then the destination matrix register of this instruction is mapped to the physical register pmdst0. This situation is called a "cache hit”. Afterwards, the instruction will be sent to the matrix memory access unit for execution. However, considering that the data required by this matrix load instruction has already been confirmed to exist in physical register pmdst0, the matrix memory access unit can directly determine that this instruction has been completed and does not need to access the shared cache again.
  • Case 2 Otherwise, map the destination matrix register of the instruction to any of the physical registers pmdst1 in the (Cacheline index % M) group that is either cached or idle. Then, the instruction will be sent to the matrix memory access unit for execution. The matrix memory access unit will retrieve the data from the shared cache between the CPU and the matrix coprocessor based on the memory address of the instruction and load it into the physical register pmdst1.
  • the matrix coprocessor determines that it is not executing a matrix load instruction, it queries the physical matrix register status table, selects a register number pmdst2 that is in a cached or idle state as the physical register number of the instruction, reads the required data from the physical matrix register file, sends it to the matrix operation unit or memory access unit for execution, and finally writes the operation result back to the register numbered pmdst2 in the physical matrix register file.
  • This solution equips the physical matrix register file with a physical matrix register status table, which records the current state of each physical register and the memory address information of its data source. Therefore, the physical matrix register file of the matrix coprocessor can be used as both a mapping of the architecture registers and a mapping of memory space, acting as a data cache.
  • This solution fully utilizes the space of the physical registers, using the portions not mapped by the architecture registers as a data cache, providing opportunities for data reuse. Matrix load instructions that hit this cache do not need to access external memory units, saving external memory access bandwidth.
  • both the architecture registers and the data cache in this solution are mapped to a unified physical register file. Matrix load instructions that hit this cache do not need to perform data movement during execution; they only need to modify the mapping relationship between the architecture registers and physical registers, reducing power consumption, hardware implementation complexity, and execution latency of matrix load instructions.
  • the user information including but not limited to user device information, user personal information, etc.
  • data including but not limited to data used for analysis, data stored, data displayed, etc.
  • the collection, use and processing of the relevant data must comply with the relevant laws, regulations and standards of the relevant countries and regions, and corresponding operation portals are provided for users to choose to authorize or refuse.
  • the receiving module 81 is configured to receive target data write instructions, wherein the target data write instructions carry the target memory address where the target data to be written to the physical register is located.
  • the receiving module 81, response module 82, and return module 83 mentioned above correspond to steps S301 to S303 in Embodiment 1.
  • the instances and application scenarios implemented by the above modules and corresponding steps are the same, but are not limited to the content disclosed in Embodiment 1.
  • the above modules or units can be hardware or software components stored in memory (e.g., memory 104) and processed by one or more processors (e.g., processors 102a, 102b, ..., 102n).
  • the above modules can also be part of a device and run in the computer terminal 10 provided in Embodiment 1.
  • the aforementioned electronic device may be located in at least one of a plurality of network devices in a computer network.
  • the computer terminal described above can execute the program code in the method.
  • the memory can be used to store software programs and modules, such as the program instructions/modules corresponding to the methods and apparatus in the embodiments of this application.
  • the processor executes various functional applications and data processing by running the software programs and modules stored in the memory, thereby implementing the methods in the above embodiments.
  • the memory may include high-speed random access memory, and may also include non-volatile memory, such as one or more magnetic storage devices, flash memory, or other non-volatile solid-state memory.
  • the memory may further include memory remotely located relative to the processor, and these remote memories can be connected to the terminal via a network. Examples of such networks include, but are not limited to, the Internet, corporate intranets, local area networks, mobile communication networks, and combinations thereof.
  • the processor can invoke information and application programs stored in memory through a transmission device to perform the following steps: receiving a target data write instruction, wherein the target data write instruction carries the target memory address where the target data to be written to the physical register is located; in response to the target data write instruction, searching for the existence of a target physical register corresponding to the target memory address based on the correspondence between physical registers and memory addresses; if the search result indicates that a target physical register corresponding to the target memory address exists, returning the data write result that the target data has been written to the target physical register.
  • the processor may also execute program code with the following steps: before searching for the existence of a target physical register corresponding to the target memory address based on the correspondence between physical registers and memory addresses in response to a data write instruction, the method further includes: receiving one or more data write instructions, wherein the one or more data write instructions respectively carry the memory address where the data to be written to the physical register is located; writing data to the physical register in response to the one or more data write instructions; and establishing a correspondence between the physical registers for which data has been written and the corresponding memory addresses based on the one or more data write instructions.
  • the processor may also execute program code with the following steps: in response to a target data write instruction, based on the correspondence between physical registers and memory addresses, searching for the existence of a target physical register corresponding to the target memory address, including: determining a target physical register group from multiple groups of physical registers according to the target memory address; matching the target memory address with the memory addresses corresponding to the physical registers included in the target physical register group, and searching for the existence of a target physical register corresponding to the target memory address.
  • the processor may also execute program code with the following steps: the method further includes: establishing a mapping between the target physical register and the target architecture register, wherein data writing is optional.
  • the processor may also execute program code with the following steps: the instructions further include the number of the target architecture register to which the target data is to be loaded, the target architecture register being visible to the software.
  • the processor may also execute program code with the following steps: when the target physical register includes multiple rows, the target memory address includes a target base address and a target address step, wherein the target base address is the starting address for writing data into the target physical register in memory, the target address step is the difference between the memory addresses corresponding to two adjacent rows in the target physical register, the base address corresponding to the target physical register matches the target base address, and the address step corresponding to the target physical register matches the target address step.
  • the processor may also execute program code with the following steps: the method further includes: if the search result shows that there is no target physical register corresponding to the target memory address, determining a spare physical register; writing the target data at the target memory address into the spare physical register, and returning the data writing result that the target data has been written into the spare physical register.
  • This application provides an instruction processing scheme. It establishes a correspondence between physical registers and memory addresses. By receiving a target data write instruction, which carries the target memory address where the target data to be written to the physical register is located, the scheme searches for a corresponding target physical register based on the correspondence between physical registers and memory addresses. If the search reveals a corresponding target physical register, it returns a result indicating that the target data has been written to the target physical register. This achieves the goal of directly using the target physical register for subsequent processing when the target physical register storing the data at the target memory address is found, eliminating the need to write the data at the target memory address to the physical register again. This reduces the power consumption and time required for the processor to execute data write instructions, thus solving the problem of high power consumption and long processing time caused by multiple data write operations during the processor's execution of multiple data write instructions.
  • the electronic device may also be a smartphone (such as an Android phone, an iOS phone, etc.), a tablet computer, a PDA, a mobile internet device (MID), a PAD, or other terminal device.
  • the electronic device may include more or fewer components (such as a network interface, a display device, etc.) than shown in the figure, or may have a different configuration than that shown in the figure.
  • the program can be stored in a computer-readable storage medium, which may include: flash drive, read-only memory (ROM), random access memory (RAM), disk or optical disk, etc.
  • Embodiments of this application also provide a computer-readable storage medium.
  • the computer-readable storage medium can be used to store program code executed by the method provided in the above embodiments.
  • the computer-readable storage medium is configured to store program code for performing the following steps: receiving a target data write instruction, wherein the target data write instruction carries the target memory address where the target data to be written to the physical register is located; in response to the target data write instruction, searching for the existence of a target physical register corresponding to the target memory address based on the correspondence between physical registers and memory addresses; if the search result indicates that a target physical register corresponding to the target memory address exists, returning a data write result indicating that the target data has been written to the target physical register.
  • the computer-readable storage medium is further configured to store program code for performing the following steps: before searching for the existence of a target physical register corresponding to a target memory address based on the correspondence between physical registers and memory addresses in response to a data write instruction, the method further includes: receiving one or more data write instructions, wherein each of the one or more data write instructions carries a memory address where data to be written to a physical register is located; writing data to a physical register in response to the one or more data write instructions; and establishing a correspondence between the physical registers for which data has been written based on the one or more data write instructions and their corresponding memory addresses.
  • the computer-readable storage medium is further configured to store program code for performing the following steps: in response to a target data write instruction, based on the correspondence between physical registers and memory addresses, searching for the existence of a target physical register corresponding to the target memory address, including: determining a target physical register group from multiple groups of physical registers according to the target memory address; matching the target memory address with the memory addresses corresponding to the physical registers included in the target physical register group, and searching for the existence of a target physical register corresponding to the target memory address.
  • the computer-readable storage medium is further configured to store program code for performing the following steps: determining a target physical register set from multiple sets of physical registers based on a target memory address, including: obtaining the number of groups of the multiple sets of physical registers; determining the index of the cache block where the target memory address is located; and determining the target physical register set based on the index and the number of groups.
  • the computer-readable storage medium is further configured to store program code for performing the following steps: determining a target physical register group based on an index and a group number, including: taking the modulo of the group number using the index to obtain a modulo value; and using the modulo value as the group number of the target physical register group to determine the target physical register group.
  • the computer-readable storage medium is also configured to store program code for performing the following steps: the method further includes: establishing a mapping between a target physical register and a target architecture register, wherein the data write instruction further includes the number of the target architecture register to which the target data is to be loaded, the target architecture register being visible to the software.
  • the computer-readable storage medium is further configured to store program code for performing the following steps: when the target physical register comprises multiple rows, the target memory address comprises a target base address and a target address step, wherein the target base address is the starting address for writing data to the target physical register in memory, the target address step is the difference between the memory addresses corresponding to two adjacent rows in the target physical register, the base address corresponding to the target physical register matches the target base address, and the address step corresponding to the target physical register matches the target address step.
  • the computer-readable storage medium is further configured to store program code for performing the following steps: the method further includes: if the search result indicates that there is no target physical register corresponding to the target memory address, determining a spare physical register; writing the target data at the target memory address into the spare physical register, and returning the data write result that the target data has been written into the spare physical register.
  • Embodiments of this application also provide a computer program product.
  • the computer program product may include a computer program that, when executed by a processor, implements the methods provided in the embodiments described above.
  • Embodiments of this application also provide a computer program product.
  • the computer program product may include a non-volatile computer-readable storage medium, which can be used to store a computer program that, when executed by a processor, implements the method provided in the above embodiments.
  • Embodiments of this application also provide a computer program.
  • the computer program when executed by a processor, it implements the method provided in the above embodiments.
  • sequence numbers of the embodiments in this application are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.
  • the units described as separate components may or may not be physically separate.
  • the components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.
  • the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.
  • the integrated unit can be implemented in hardware or as a software functional unit.
  • the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium.
  • This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this application.
  • the aforementioned storage medium includes various media capable of storing program code, such as a USB flash drive, read-only memory (ROM), random access memory (RAM), portable hard drive, magnetic disk, or optical disk.

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Abstract

本申请公开了一种指令处理方法、装置、电子设备和计算机程序产品。其中，该方法包括：接收目标数据写入指令，其中，目标数据写入指令中携带有待写入物理寄存器中的目标数据所在的目标内存地址；响应于目标数据写入指令，基于物理寄存器与内存地址的对应关系，查找是否存在与目标内存地址对应的目标物理寄存器；在查找结果为存在与目标内存地址对应的目标物理寄存器的情况下，返回目标数据已写入目标物理寄存器的数据写入结果。本申请解决了由于处理器多次执行数据写入指令的过程中，多次数据写入动作的功耗大且耗时长的技术问题。

Description

指令处理方法、装置、电子设备和计算机程序产品 技术领域
本申请涉及处理器领域，具体而言，涉及一种指令处理方法、装置、电子设备和计算机程序产品。
背景技术
在处理器执行数据运算时，数据写入指令通常用于将数据从内存中加载到处理器的寄存器中，以便进行后续的处理和计算。寄存器是处理器内部的高速存储单元，其访问速度远快于内存。当处理器需要执行数据运算时，它可以使用数据写入指令将数据从内存中加载到寄存器中。一旦数据被加载到寄存器中，处理器就可以快速地对其进行处理和计算，而无需等待内存访问。
在实际处理过程中，处理器每执行一条数据写入指令，就会将对应的数据写入寄存器中，多次数据写入动作的功耗大且耗时长。
针对上述的问题，目前尚未提出有效的解决方案。
发明内容
本申请实施例提供了一种指令处理方法、装置、电子设备和计算机程序产品，以至少解决由于处理器多次执行数据写入指令的过程中，多次数据写入动作的功耗大且耗时长的技术问题。
根据本申请实施例的一个方面，提供了一种指令处理方法，包括：接收目标数据写入指令，其中，目标数据写入指令中携带有待写入物理寄存器中的目标数据所在的目标内存地址；响应于目标数据写入指令，基于物理寄存器与内存地址的对应关系，查找是否存在与目标内存地址对应的目标物理寄存器；在查找结果为存在与目标内存地址对应的目标物理寄存器的情况下，返回目标数据已写入目标物理寄存器的数据写入结果。
根据本申请实施例的另一方面，还提供了一种指令处理装置，包括：接收模块，设置为接收目标数据写入指令，其中，目标数据写入指令中携带有待写入物理寄存器中的目标数据所在的目标内存地址；响应模块，设置为响应于目标数据写入指令，基于物理寄存器与内存地址的对应关系，查找是否存在与目标内存地址对应的目标物理寄存器；返回模块，设置为在查找结果为存在与目标内存地址对应的目标物理寄存器的情况下，返回目标数据已写入目标物理寄存器的数据写入结果。
根据本申请实施例的另一方面，还提供了一种电子设备，包括：存储器，存储有可执行程序；处理器，设置为运行程序，其中，程序运行时执行本申请各个实施例中的指令处理方法。
根据本申请实施例的另一方面，还提供了一种计算机可读存储介质，计算机可读存储介质包括存储的可执行程序，其中，在可执行程序运行时控制存储介质所在设备执行本申请各个实施例中的指令处理方法。
根据本申请实施例的另一方面，还提供了一种计算机程序产品，包括计算机程序，计算机程序在被处理器执行时实现本申请各个实施例中的指令处理方法。
在本申请实施例中，采用建立物理寄存器与内存地址的对应关系的方式，通过接收目标数据写入指令，其中，目标数据写入指令中携带有待写入物理寄存器中的目标数据所在的目标内存地址；响应于目标数据写入指令，基于物理寄存器与内存地址的对应关系，查找是否存在与目标内存地址对应的目标物理寄存器；在查找结果为存在与目标内存地址对应的目标物理寄存器的情况下，返回目标数据已写入目标物理寄存器的数据写入结果，达到了在找到存储了目标内存地址的数据的目标物理寄存器的情况下，直接采用目标物理寄存器进行后续处理的目的，无需再次将目标内存地址的数据写入物理寄存器，从而实现了减少处理器执行数据写入指令的功耗和时间的技术效果，进而解决了由于处理器多次执行数据写入指令的过程中，多次数据写入动作的功耗大且耗时长的技术问题。
容易注意到的是，上面的通用描述和后面的详细描述仅仅是为了对本申请进行举例和解释，并不构成对本申请的限定。
附图说明
此处所说明的附图用来提供对本申请的进一步理解，构成本申请的一部分，本申请的示意性实施例及其说明用于解释本申请，并不构成对本申请的不当限定。在附图中：
图1示出了一种用于实现指令处理方法的RISC-V系统的硬件结构框图；
图2示出了使用上述图1所示的RISC-V架构的片上系统(System On Chip，SOC)的示意图；
图3是根据本申请实施例1的指令处理方法的流程图；
图4是根据本申请可选实施例提供的处理矩阵指令的示意图；
图5是根据本申请可选实施例提供的物理矩阵寄存器堆的示意图；
图6是根据本申请可选实施例提供的物理矩阵寄存器状态表的示意图；
图7是根据本申请可选实施例提供的指令处理方法的示意图；
图8是根据本申请实施例2的指令处理装置的结构框图；
图9是根据本申请实施例的一种电子设备的结构框图。
具体实施方式
为了使本技术领域的人员更好地理解本申请方案，下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本申请一部分的实施例，而不是全部的实施例。基于本申请中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都应当属于本申请保护的范围。
需要说明的是，本申请的说明书和权利要求书及上述附图中的术语“第一”、“第二”等是用于区别类似的对象，而不必用于描述特定的顺序或先后次序。应该理解这样使用的数据在适当情况下可以互换，以便这里描述的本申请的实施例能够以除了在这里图示或描述的那些以外的顺序实施。此外，术语“包括”和“具有”以及他们的任何变形，意图在于覆盖不排他的包含，例如，包含了一系列步骤或单元的过程、方法、系统、产品或设备不必限于清楚地列出的那些步骤或单元，而是可包括没有清楚地列出的或对于这些过程、方法、产品或设备固有的其它步骤或单元。
首先，在对本申请实施例进行描述的过程中出现的部分名词或术语适用于如下解释：
访问：读取或者写入。
寄存器：可以由CPU指令直接访问的、用于存储数据的结构。
架构寄存器(Architectural Register)：软件概念上的寄存器状态。架构寄存器是计算机体系结构中的一个概念。计算机体系结构是计算机硬件和软件之间的接口，它定义了计算机如何执行指令、存储数据以及处理输入和输出。在计算机体系结构中，寄存器是用来存储指令、数据和控制信息的高速存储单元。架构寄存器是指在计算机体系结构中明确定义的寄存器，它们在不同的指令集架构(ISA)中具有特定的功能和操作规则。架构寄存器的主要作用包括：(1)存储指令地址：程序计数器(Program Counter,PC)是一个常见的架构寄存器，它存储当前正在执行的指令的地址。(2)数据传输：通用寄存器(General Purpose Register,GPR)用于存储临时数据，如运算结果、变量等。(3)状态控制：状态寄存器(Status Register,SR)或标志寄存器(Flag Register)用于存储处理器的状态信息，如中断标志、条件代码等。(4)控制寄存器：控制寄存器(Control Register)用于控制处理器的特定功能，如异常处理、中断屏蔽等。架构寄存器通常在指令集架构(ISA)中明确定义，程序员在编写程序时需要遵循这些规则来访问和操作这些寄存器。不同的计算机体系结构可能有不同的架构寄存器，但它们的基本功能和作用是相似的。
物理寄存器：硬件上实现的寄存器实体，可以充当架构寄存器的映射而被软件所见。
寄存器堆：多个寄存器的集合体。
缓存/Cache：用于临时存储内存空间中的部分地址下的数据的存储器。
访存：从内存或缓存读出或写入数据。
加载指令：用于将内存中的指定地址上的数据搬运到寄存器中的指令。
存储指令：用于将寄存器中的数据写入内存中的指定地址上的指令。
Stride：矩阵加载或存储指令中，寄存器的相邻两行所对应的内存地址之差。
基地址：矩阵加载或存储指令访问内存的起始地址。
缓存块/Cacheline：缓存所管理的最小的数据粒度，一般大小为64个字节。
缓存命中：加载指令所需访问的内存数据已经完整地存在于缓存中。
寄存器重命名：硬件将架构寄存器对应到某个实体的物理寄存器，此后对该物理寄存器的访问即代表了对相应架构寄存器的访问。
矩阵协处理器(Matrix Coprocessor)是一种为矩阵运算而设计的硬件设备或软件组件。在计算机科学和工程领域，矩阵运算是一类非常重要的计算任务，例如线性代数、图像处理、信号处理和机器学习等。矩阵协处理器通过优化这些矩阵运算的性能，可以显著提高整体计算效率。矩阵协处理器的主要特点和功能包括：(1)专用硬件：矩阵协处理器可能是一个独立的硬件设备，也可能是集成在CPU或其他处理器中的特定硬件模块。这些硬件专门设计可用于高效地处理矩阵运算。(2)优化算法：与CPU相比，矩阵协处理器通常采用优化的算法和数据结构来处理矩阵运算，这有助于减少计算时间和资源消耗。(3)并行处理：矩阵协处理器通常支持并行处理，可以同时处理多个矩阵元素，从而提高计算速度。(4)浮点运算能力：由于矩阵运算通常涉及大量的浮点运算，矩阵协处理器通常会配备强大的浮点运算单元。(5)内存管理：矩阵协处理器可能会优化内存访问模式，以减少内存延迟和带宽限制对性能的影响。(6)软件支持：矩阵协处理器通常会有相应的软件库或API，使得程序员可以方便地在程序中调用这些硬件的功能。(7)特定应用优化：某些矩阵协处理器可能针对特定类型的矩阵运算或应用进行优化，例如图形处理、机器学习算法等。使用矩阵协处理器可以大幅提高特定类型的计算任务的性能，特别是在需要大量矩阵运算的应用场景中。然而，它们通常不适用于通用计算任务，因为它们的设计专注于特定的计算模式。
实施例1
根据本申请实施例，提供了一种指令处理方法，需要说明的是，在附图的流程图示出的步骤可以在诸如一组计算机可执行指令的计算机系统中执行，并且，虽然在流程图中示出了逻辑顺序，但是在某些情况下，可以以不同于此处的顺序执行所示出或描述的步骤。
本申请实施例一所提供的方法实施例可以在RISC-V系统、RISC-V芯片或类似装置中执行。图1示出了一种用于实现指令处理方法的RISC-V系统的硬件结构框图。如图1所示，RISC-V系统100从底层到上层可以分为精简指令集架构101(包含基础指令集101-1和扩展指令集101-2)、硬件层102(包括处理器102-1、外围硬件电路102-2等)、接口层103、操作系统层104(支持多种操作系统104-1,104-2，…，104-n，例如Linux、FreeSBD、RT-Tread等)、中间件和库层105(包含系统库105-1、API 105-2和中间件服务105-3)和应用程序层106(包括多种用户程序和服务106-1,106-2，…，106-n)。RISC-V系统100还包含一个从底层硬件到应用程序层之间的工具链107，该工具链可以包括编译器和汇编器107-1、链接器107-2、调试器107-3、模拟器和仿真器107-4、集成开发环境107-5、硬件描述语言工具107-6、性能分析工具107-7和版本控制系统107-8等。
指令集架构101定义了处理器102-1支持的基本操作和指令集，包括基础指令集和扩展指令集，其中，基础指令集表征基础的整数指令集，如RV32I和RV64I，扩展指令集可以是浮点、原子操作、压缩指令等。
接口层103包括处理器的具体设计，如流水线设计、缓存结构、执行单元、分支预测等。这一层是将抽象指令映射到物理硬件上的过程。
操作系统层104位于硬件之上，提供了硬件抽象层和管理机制，使得应用长须能够通过系统调用与硬件交互。操作系统负责管理处理器资源、内存、设备驱动、任务调度等。
中间件和库层105提供了一组丰富的服务和接口，帮助应用程序更高效地运行。例如，标准库提供了文件操作、数学计算等功能，而中间件可以提供网络通信、图形用户界面等复杂服务。
应用程序层106利用下层提供的功能和服务来实现具体的应用逻辑，这些应用程序可以是命令行工具、图形界面应用、服务器端服务等。
工具链107是连接底层硬件到上层软件的关键组件，工具链107中的各种工具在不同层次上发挥作用，以支持从硬件设计到软件开发的整个过程，确保整个系统设计的连贯性和有效性。
需要说明的是，RISC-V架构的分层设计允许不同层次之间的解耦，使得每一层都可以独立开发和优化。
一种可选实施例中，图2示出了使用上述图1所示的RISC-V架构的片上系统(System On Chip，SOC)的示意图。如图2所示，该SOC内部包含至少一个RISC-V内核202(图中仅示出一个),RISC-V内核202通过总线204与外设设备连接，包括但不限于ROM 206、RAM 208、定时器210、UART(通用异步收发传输器，Universal Asynchronous Receiver/Transmitter)212、GPIO(通用输入/输出端口，General Purpose Input/Output)214、SPI(串行外设接口，Serial Peripheral Interface Bus)216等。
相关技术中，在处理器执行数据运算时，数据写入指令通常用于将被处理的数据从内存中加载到处理器的寄存器中，以便进行后续的处理和计算。寄存器是处理器内部的高速存储单元，其访问速度远快于内存。当处理器需要执行数据运算时，它可以快速地对寄存器中写入的数据进行处理和计算，而无需等待内存访问。
然而，在实际处理过程中，当需要处理的数据量较大或者数据结构复杂时，处理器需要执行大量的数据写入指令。在这种情况下，频繁的数据写入会导致功耗大且耗时长。更为严重的是，如果多次写入的数据中存在大量的重复数据，那么这个过程会造成资源的浪费。
以矩阵运算为例，如果多次写入的矩阵数据中存在大量的重复矩阵，那么在执行数据写入指令时，相同的矩阵数据将会被多次写入寄存器中。这不仅会导致资源的浪费，还会降低运算的效率。
为了解决这个问题，在上述运行环境下，本申请提供了如图3所示的指令处理方法。图3是根据本申请实施例1的指令处理方法的流程图。
步骤S301，接收目标数据写入指令，其中，目标数据写入指令中携带有待写入物理寄存器中的目标数据所在的目标内存地址。
本步骤中，执行主体可以是处理器，目标数据写入指令是用于将目标数据写入物理寄存器的指令，其中包括了目标数据在内存中所在的目标内存地址。处理器可以根据目标内存地址在内存中找到目标数据，并将目标数据复制写入物理寄存器中，以便处理器在对目标数据进行处理时，能够快速从物理寄存器中读取数据并进行处理。
需要说明的是，本发明提供的指令处理方法可以应用在矩阵数据的运算过程中，此时，执行主体可以是矩阵协处理器，目标数据可以是矩阵数据。对应地，目标数据写入指令可以是目标矩阵加载指令。在这种情况下，需要设置多个物理寄存器来存储矩阵数据，每个物理寄存器都可以是一个二维结构，包含多行，每行内可以存储数据。
其中，图4是根据本申请可选实施例提供的处理矩阵指令的示意图，如图4所示，在处理矩阵指令的时候，可以设置由矩阵协处理器来处理矩阵指令。其中，扩展的矩阵寄存器、新增的矩阵指令执行单元、矩阵访存子系统、矩阵数据缓存等硬件结构可实现在CPU核外的“矩阵协处理器”内部，与CPU核解耦。矩阵协处理器和CPU核通过总线连接，可以相互进行通信，矩阵协处理器和CPU核之间共享某一级缓存。
矩阵协处理器的工作方式为：CPU从指令存储器中取出程序的指令流，进行译码。若CPU判断某指令为矩阵指令，则将该指令通过总线发送到核外的矩阵协处理器，交由矩阵协处理器负责这条矩阵指令的具体执行过程，包括访问矩阵寄存器堆、完成矩阵运算、访问内部矩阵数据缓存、发起共享缓存的访问请求等。
步骤S302，响应于目标数据写入指令，基于物理寄存器与内存地址的对应关系，查找是否存在与目标内存地址对应的目标物理寄存器。
本步骤中，处理器在收到目标数据写入指令之后，可以基于之前建立的物理寄存器与内存地址的对应关系进行查找，判断是否有已经存储了目标内存地址处的目标数据的目标物理寄存器，也就是说，在物理寄存器与内存地址的对应关系中，判断目标物理寄存器对应的内存地址与目标内存地址相同。
因为在进行数据处理时，很可能会涉及到对大量的重复数据进行计算。因此，在每次将数据写入当前物理寄存器时，可以同步更新物理寄存器与内存地址的对应关系，保证物理寄存器与内存地址的对应关系中，与该当前物理寄存器对应的内存地址是当前物理寄存器内存储的数据所在内存中的地址。
步骤S303，在查找结果为存在与目标内存地址对应的目标物理寄存器的情况下，返回目标数据已写入目标物理寄存器的数据写入结果。
本步骤中，在物理寄存器与内存地址的对应关系中查找，判断存在与目标内存地址对应的目标物理寄存器，也即，确定了在之前已经有目标数据被存储在目标物理寄存器中，此时可以直接确定目标数据写入指令已完成，因为目标数据已经写入了目标物理寄存器，并返回数据写入结果。即数据写入结果用于表明目标数据已经成功写入目标物理寄存器。
需要说明的是，当写入目标数据为矩阵数据时，也可以采用本发明提供的指令处理方法，基于建立的物理寄存器与内存地址的对应关系，判断是否存在已经存储了目标数据的目标物理寄存器，如果有，也可以直接返回目标数据已写入目标物理寄存器的数据写入结果。
在本申请实施例中，采用建立物理寄存器与内存地址的对应关系的方式，通过接收目标数据写入指令，其中，目标数据写入指令中携带有待写入物理寄存器中的目标数据所在的目标内存地址；响应于目标数据写入指令，基于物理寄存器与内存地址的对应关系，查找是否存在与目标内存地址对应的目标物理寄存器；在查找结果为存在与目标内存地址对应的目标物理寄存器的情况下，返回目标数据已写入目标物理寄存器的数据写入结果，达到了在找到存储了目标内存地址的数据的目标物理寄存器的情况下，直接采用目标物理寄存器进行后续处理的目的，无需再次将目标内存地址的数据写入物理寄存器，从而实现了减少处理器执行数据写入指令的功耗和时间的技术效果，进而解决了由于处理器多次执行数据写入指令的过程中，多次数据写入动作的功耗大且耗时长的技术问题。
作为一种可选的实施例，在响应于数据写入指令，基于物理寄存器与内存地址的对应关系，查找是否存在与目标内存地址对应的目标物理寄存器之前，该方法还包括：接收一个或多个数据写入指令，其中，一个或多个数据写入指令分别携带有待写入物理寄存器中数据所在的内存地址；响应于一个或多个数据写入指令，将数据写入物理寄存器；建立基于一个或多个数据写入指令写入了数据的物理寄存器与对应内存地址之间的对应关系。
可选地，在基于物理寄存器与内存地址的对应关系查找是否存在目标物理寄存器之前，可以先建立被写入数据的物理寄存器与数据所在内存地址之间的对应关系。处理器可以根据接收的一个或多个数据写入指令，将数据写入物理寄存器中，并建立被写入数据的物理寄存器与数据在内存中的地址之间的对应关系。其中，一个或多个数据写入指令用于将指定数据从内存写入物理寄存器，每个数据写入指令都会携带有待写入物理寄存器中的数据所在的内存地址；然后可以根据数据写入指令中数据所在的内存地址，将指定的数据从内存复制到相应的物理寄存器中；在数据写入物理寄存器之后，可以建立一个映射表，记录物理寄存器与内存地址之间的对应关系。这个映射表对于后续的数据处理过程至关重要，处理器可以通过该映射表快速找到与特定内存地址相关的物理寄存器。
通过这一实施例，指令处理方法能够在执行数据写入操作之前，有效地接收并执行数据写入指令，同时建立物理寄存器与内存地址之间的对应关系。这不仅提高了数据处理的效率，还为后续的数据访问和操作提供了便利。
当本可选实施例应用在矩阵数据处理过程时，可以建立矩阵数据所在的内存地址，与写入矩阵数据的物理寄存器之间的对应关系。因此，在之后需要将矩阵数据写入物理寄存器时，可以根据对应关系进行查找，确定需要写入的矩阵数据是否在之前已经被写入某个物理寄存器中，如果是的话，就无需再次写入矩阵数据，节省了重复写入矩阵数据的能耗，提高了矩阵数据的处理效率。
作为一种可选的实施例，响应于目标数据写入指令，基于物理寄存器与内存地址的对应关系，查找是否存在与目标内存地址对应的目标物理寄存器，包括：根据目标内存地址，从多组物理寄存器中确定目标物理寄存器组；将目标内存地址与目标物理寄存器组包括的物理寄存器对应的内存地址匹配，查找是否存在与目标内存地址对应的目标物理寄存器。
可选地，由于处理器中一般会设置多个物理寄存器来存储数据，如果采用遍历的方法来寻找多个物理寄存器中是否存在目标物理寄存器会很繁琐，耗时长且能耗高。此时可以按照一定的规则，将所有能够存储数据的物理寄存器进行分组，得到多组物理寄存器，然后在其中的目标物理寄存器组中进行查找，确认目标物理寄存器组中是否存在目标物理寄存器。这样的话，可以将查找的范围缩小在目标物理寄存器组中，而不用查找所有能够存储数据的物理寄存器，因此可以减少耗时且降低耗能。
为了保证如果存在目标物理寄存器，则目标物理寄存器一定在目标物理寄存器组中，并且如果目标物理寄存器组中不存在目标物理寄存器，则其他物理寄存器中也不可能存在目标物理寄存器，可以设定物理寄存器的分组规则和物理寄存器对应的内存地址相关，也即，可以设定根据物理寄存器各自对应的内存地址将物理寄存器分组，或者说，再将物理寄存器分组之后，每组物理寄存器组能够存储的数据对应的内存地址被限定在某个范围内。
作为一种可选的实施例，根据目标内存地址，从多组物理寄存器中确定目标物理寄存器组，包括：获取多组物理寄存器的分组数；确定目标内存地址所在的缓存块的索引；根据索引和分组数，确定目标物理寄存器组。
可选地，可以根据物理寄存器总共的分组数，以及目标内存地址所在的缓存块的索引来定位目标物理寄存器组。对应地，在向寄存器存储数据时，可以按照内存地址和分组数来找到能够存储数据的物理寄存器组，所以在找寻存储了目标数据的目标物理寄存器时，可以按照目标内存地址和分组数来确定目标物理寄存器组。
具体地，多个物理寄存器中的所有寄存器被分成M组，矩阵协处理器给每一条数据写入指令的分配存储数据的物理寄存器编号时，需要遵循以下规则：被分配的新的物理寄存器必须来源于多个物理寄存器堆中的M个组中的某个特定组，该组组号的计算方式与该条数据写入指令包括的目标内存地址相关。
因此，在找寻是否存在目标物理寄存器时，可以根据目标内存地址所在的缓存块的索引和分组数来定位目标物理寄存器组。
在本可选实施例应用在矩阵运算过程中时，图5是根据本申请可选实施例提供的物理矩阵寄存器堆的示意图，如图5所示，物理矩阵寄存器堆(多个物理寄存器)包括K个物理寄存器，每个寄存器的每行可以写入数据。物理矩阵寄存器堆中的所有寄存器被分成M组，每组包含N个寄存器。这里，需要满足M*N＝K。M和N的取值取决于具体硬件实现。矩阵协处理器给每一条矩阵加载指令分配物理寄存器编号时，被分配的新的物理寄存器必须来源于物理矩阵寄存器堆中的M个组中的某个特定组，该组组号的计算方式与矩阵加载指令中携带的内存地址有关。
作为一种可选的实施例，根据索引和分组数，确定目标物理寄存器组，包括：采用索引对分组数取模，得到取模值；将取模值作为目标物理寄存器组的组号，确定目标物理寄存器组。
可选地，可以将目标内存地址所在的缓存块的索引对分组数取模，得到的取模值即为目标物理寄存器组的组号。需要说明的是，基于取模的方式确定取模值来作为目标物理寄存器组的组号的方法仅仅为一种举例，基于其他运算方式确定目标物理寄存器组的组号的方法也属于本申请的一部分。
矩阵加载指令携带的内存地址通常包括基地址和地址步长(stride)，矩阵加载指令会对物理矩阵寄存器(相当于物理寄存器)的(RLEN/32)行中的每一行，分别加载内存中不同地址的数据。其中，物理矩阵寄存器的每行所加载的数据对应的内存地址与基地址和stride相关，具体地，物理矩阵寄存器第r行所加载的数据对应的内存起始地址的计算方式为“基地址+r*stride”，r取0到(RLEN/32)-1。在本可选实施例应用在矩阵运算过程中时，可以采用矩阵加载指令中基地址所在的缓存块的索引对分组数取模，得到物理寄存器组的组号。
作为一种可选的实施例，该方法还包括：建立目标物理寄存器到目标架构寄存器之间的映射，其中，数据写入指令还包括待加载目标数据的目标架构寄存器的编号，目标架构寄存器对软件可见。
需要说明的是，在实际的数据处理过程中，物理寄存器并不是对软件直接可见的，而是要映射至架构寄存器上，才能被软件可见。因此，在数据写入指令中，会携带架构寄存器的编号，处理器会选择一个物理寄存器与架构寄存器建立映射关系，以使得软件能够访问物理寄存器中的数据。
在本可选实施例应用在矩阵计算的场景中，架构寄存器是可以被矩阵指令直接访问的寄存器，每个架构寄存器是一个二维结构，共包含RLEN*(RLEN/32)个比特位，其中(RLEN/32)是一个矩阵寄存器的行数，RLEN是每一行的比特数。架构寄存器的数量可以是8个，分别编号为m0-m7，当然，架构寄存器的数量可以根据需要具体设置，也可以是16个。
矩阵协处理器会在其内部维护一个物理矩阵寄存器堆(多个物理寄存器)，它包括K个矩阵寄存器，其中K的大小取决于具体硬件实现，但至少大于架构寄存器的数量。程序执行过程中，矩阵协处理器将从物理矩阵寄存器堆(22)中的K个寄存器空间里，选出8个寄存器，作为8个架构寄存器m0-m7的映射。该映射关系由重命名映射表来进行记录。该表有8个表项，各自对应一个架构寄存器，每个表项记录了当前该架构寄存器所映射到的物理矩阵寄存器堆中的某个物理寄存器编号。上述建立架构寄存器与物理寄存器之间的映射关系的过程，也被称为寄存器重命名策略。
上述映射关系可以在程序执行过程中进行动态调整。即：每当一条新的矩阵指令从CPU核发到矩阵协处理器时，若该矩阵指令包含了目的架构寄存器的编号md，其中，md是m0-m7之间的数字，则矩阵协处理器会为该架构寄存器md指定一个新的物理寄存器映射，同时将新的物理寄存器编号更新在重命名映射表中。需要说明的是，上述重命名映射表和本发明提及的物理寄存器与内存地址的对应关系并不一致，重命名映射表建立的是架构寄存器和物理寄存器之间的对应关系。
在确定目标物理寄存器之后，可以建立目标物理寄存器与数据写入指令中的目标架构寄存器之间的映射关系，并更新重命名映射表，以使得软件能够访问物理寄存器中的数据。
作为一种可选的实施例，在目标物理寄存器包括多行的情况下，目标内存地址包括目标基地址和目标地址步长，其中，目标基地址为在内存中目标物理寄存器写入数据的起始地址，目标地址步长为目标物理寄存器中相邻两行所对应的内存地址之差，目标物理寄存器对应的基地址与目标基地址匹配，且目标物理寄存器对应的地址步长与目标地址步长匹配。
本可选实施例提供了在处理矩阵数据时，矩阵加载指令(相当于数据写入指令)中目标内存地址的格式。矩阵加载指令携带的内存地址通常包括基地址和地址步长(stride)，矩阵加载指令会对矩阵寄存器的(RLEN/32)行中的每一行，分别加载内存中不同地址的数据。矩阵寄存器第r行所加载的数据对应的内存起始地址的计算方式为“基地址+r*stride”，r取0到(RLEN/32)-1。
在这种情况下，确定与目标内存地址匹配的目标物理寄存器时，一定是目标基地址也匹配，目标地址步长也匹配。进一步地，匹配也即相同，当目标内存地址中的目标基地址与某个物理寄存器对应的基地址相同，且目标地址步长也与该物理寄存器对应的地址步长相同时，才确定该物理寄存器为目标物理寄存器。
作为一种可选的实施例，该方法还包括：在查找结果为不存在与目标内存地址对应的目标物理寄存器的情况下，确定备用物理寄存器；将目标内存地址处的目标数据写入备用物理寄存器，并返回目标数据已写入备用物理寄存器的数据写入结果。
可选地，如果在物理寄存器和内存地址的对应关系中，没有找到与目标内存地址对应的目标物理寄存器，则只能重新确定一个备用物理寄存器来存储目标内存地址处的数据，并在将目标数据写入备用物理寄存器之后，返回目标数据已写入备用物理寄存器的数据写入结果。
具体地，在多个物理寄存器中，确定备用物理寄存器的方式，可以是根据目标内存地址找到对应的目标物理寄存器组，在目标物理寄存器组包括的物理寄存器中，确定备用物理寄存器。由于物理寄存器需要和架构寄存器建立映射关系才能被软件可见，所以在确定备用物理寄存器的时候，也要考虑到是否有架构寄存器正在被映射到物理寄存器上，如果有架构寄存器正在被映射到某个物理寄存器上，那这个物理寄存器就不能被作为备用物理寄存器。
可以设置寄存器状态信息用于标记物理矩阵寄存器当前所处的状态，并根据寄存器状态信息选取备用物理寄存器。一个物理矩阵寄存器可以处于以下三种状态之一：
映射状态：当前某个架构寄存器(m0-7)正在被映射到该物理寄存器上。
缓存状态：当前没有架构寄存器(m0-7)正在被映射到该物理寄存器上，但曾经有矩阵加载指令的目的寄存器被映射到该物理寄存器之上，且该寄存器中所加载的数据目前仍然和内存中对应地址上的最新数据保持一致。
空闲状态：除了上述两种情况之外，该物理寄存器处于空闲状态。
可以将每个物理寄存器对应的寄存器状态信息也记录在物理寄存器与内存地址的对应关系(即物理矩阵寄存器状态表)中，也即，图6是根据本申请可选实施例提供的物理矩阵寄存器状态表的示意图，如图6所示，物理寄存器与内存地址的对应关系(即物理矩阵寄存器状态表)中包括三类信息：基地址、stride和寄存器状态信息。其中，基地址和stride这两个信息用于记录一条矩阵加载指令的访存基地址和stride值。具体为：若一条矩阵加载指令的目的矩阵寄存器被映射到了某个编号为pmd的物理矩阵寄存器上，那么，这条指令在执行时，不仅会把内存中的数据加载到编号pmd的物理矩阵寄存器中，也同时会将这条指令的基地址、stride信息写入物理寄存器与内存地址的对应关系中对应pmd编号的位置上，还会对应调整pmd编号对应的寄存器状态为映射状态。
作为一种具体的实施例，图7是根据本申请可选实施例提供的指令处理方法的示意图，如图7所示，首先，矩阵协处理器会对当前执行的矩阵指令的类型进行判断，其中，矩阵指令大致分为两类：一类是矩阵运算类指令；一类是矩阵访存类指令。矩阵运算指令一般会从架构寄存器m0-m7中指定2-3个矩阵寄存器作为源操作数，对这些数据完成特定规则下的运算操作(例如浮点/整形矩阵乘累加运算)后，将所得结果写入从m0-m7中指定的一个目的矩阵寄存器中。
矩阵访存指令分为矩阵加载指令，和矩阵存储指令。矩阵加载指令一般会带有3个信息，分别是：访存的基地址、访存stride、需要加载的矩阵寄存器编号md。矩阵加载指令会对矩阵寄存器的(RLEN/32)行中的每一行，分别加载内存中不同地址的数据。其中，矩阵寄存器的第r行所加载的数据对应的内存起始地址的计算方式为“基地址+r*stride”，r取0到(RLEN/32)-1。类似地，矩阵存储指令也会带有三个信息，分别是：访存的基地址、访存stride、需要存储的矩阵寄存器编号ms。矩阵存储指令的行为是：把编号为ms的矩阵寄存器的(RLEN/32)行中的每一行，分别写入到内存中不同的地址上。其中，第r行对应的内存起始地址的计算方式为“基地址+r*stride”，r取0到(RLEN/32)-1。
其次，如果矩阵协处理器判断执行的是一条矩阵加载指令，则在为该指令的目的矩阵寄存器分配新的物理寄存器映射前，对矩阵加载指令中基地址所在缓存块的索引(即Cacheline index)对M取模(％M表示对M取模)，然后需要查询物理矩阵寄存器状态表，对第(Cacheline index％M)个组中的N个物理寄存器的信息进行检查，包括：基地址、Stride、寄存器状态。
此时存在两种情况：
情况1：如果发现在这N个寄存器中存在某个编号为pmdst0的寄存器，其寄存器状态为缓存状态，且其基地址和Stride均与当前这条矩阵加载指令的访存基地址、Stride完全相同，则将此指令的目的矩阵寄存器映射到该物理寄存器pmdst0上。这种情况称为“缓存命中”。之后，该指令将会被发送到矩阵访存单元执行，但考虑到该条矩阵加载指令所需的数据已经被确认存在于pmdst0号物理寄存器中，矩阵访存单元可以直接认定这条指令已经完成执行，不必再访问共享缓存。
情况2：否则，将该指令的目的矩阵寄存器映射到第(Cacheline index％M)个组中的任意的一个处于缓存状态或空闲状态的物理寄存器pmdst1上。之后，该指令将会被发送到矩阵访存单元执行，矩阵访存单元将会根据该指令的访存地址，从CPU与矩阵协处理器之间的共享缓存中获取数据，并加载到物理寄存器pmdst1中。
如果矩阵协处理器判断执行的不是一条矩阵加载指令，则查询物理矩阵寄存器状态表，选择一个状态处于缓存状态或空闲状态的寄存器编号pmdst2，作为该指令的物理寄存器编号，并从物理矩阵寄存器堆读出所需数据，发送到矩阵运算单元或访存单元执行，最后运算结果回写物理矩阵寄存器堆中编号为pmdst2的寄存器。
本方案为物理矩阵寄存器堆配备了一个物理矩阵寄存器状态表，该表记录了当前每一个物理寄存器所处的状态，以及其数据来源的内存地址信息。因此，矩阵协处理器的物理矩阵寄存器堆既可以用作架构寄存器的映射，也可以用作内存空间的映射，充当数据缓存。本方案充分利用了物理寄存器的空间，利用其中未被架构寄存器映射的部分作为数据缓存使用，提供了数据复用的机会。命中该缓存的矩阵加载指令不必访问外部存储单元，节省了外部访存带宽。并且本方案的架构寄存器和数据缓存均映射在一个统一的物理寄存器堆中。命中该缓存的矩阵加载指令在执行时，不需要进行数据移动，仅需修改架构寄存器到物理寄存器的映射关系，降低了功耗、硬件实现复杂度、矩阵加载指令的执行延迟。
需要说明的是，本申请所涉及的用户信息(包括但不限于用户设备信息、用户个人信息等)和数据(包括但不限于用于分析的数据、存储的数据、展示的数据等)，均为经用户授权或者经过各方充分授权的信息和数据，并且相关数据的收集、使用和处理需要遵守相关国家和地区的相关法律法规和标准，并提供有相应的操作入口，供用户选择授权或者拒绝。
需要说明的是，对于前述的各方法实施例，为了简单描述，故将其都表述为一系列的动作组合，但是本领域技术人员应该知悉，本申请并不受所描述的动作顺序的限制，因为依据本申请，某些步骤可以采用其他顺序或者同时进行。其次，本领域技术人员也应该知悉，说明书中所描述的实施例均属于优选实施例，所涉及的动作和模块并不一定是本申请所必须的。
通过以上的实施方式的描述，本领域的技术人员可以清楚地了解到根据上述实施例的方法可借助软件加必需的通用硬件平台的方式来实现，当然也可以通过硬件。基于这样的理解，本申请的技术方案本质上或者说对现有技术做出贡献的部分可以以软件产品的形式体现出来，该计算机软件产品存储在一个存储介质(如ROM/RAM、磁碟、光盘)中，包括若干指令用以使得一台终端设备(可以是手机，计算机，服务器，或者网络设备等)执行本申请各个实施例所述的方法。
实施例2
根据本申请实施例，还提供了一种用于实施上述指令处理方法的指令处理装置，图8是根据本申请实施例2的指令处理装置的结构框图，如图8所示，该装置包括：
接收模块81，设置为接收目标数据写入指令，其中，目标数据写入指令中携带有待写入物理寄存器中的目标数据所在的目标内存地址。
响应模块82，与接收模块81连接，设置为响应于目标数据写入指令，基于物理寄存器与内存地址的对应关系，查找是否存在与目标内存地址对应的目标物理寄存器。
返回模块83，与响应模块82连接，设置为在查找结果为存在与目标内存地址对应的目标物理寄存器的情况下，返回目标数据已写入目标物理寄存器的数据写入结果。
此处需要说明的是，上述接收模块81、响应模块82和返回模块83对应于实施例1中的步骤S301至步骤S303，上述模块与对应的步骤所实现的实例和应用场景相同，但不限于上述实施例1所公开的内容。需要说明的是，上述模块或单元可以是存储在存储器(例如，存储器104)中并由一个或多个处理器(例如，处理器102a、102b，……，102n)处理的硬件组件或软件组件，上述模块也可以作为装置的一部分可以运行在实施例1提供的计算机终端10中。
需要说明的是，本申请上述实施例中涉及到的优选实施方案与实施例1提供的方案以及应用场景、实施过程相同，但不仅限于实施例1所提供的方案。
实施例3
本申请的实施例可以提供一种电子设备，该电子设备可以是电子设备群中的任意一个电子设备。可选地，在本实施例中，上述电子设备也可以替换为移动终端等终端设备。
可选地，在本实施例中，上述电子设备可以位于计算机网络的多个网络设备中的至少一个网络设备。
在本实施例中，上述计算机终端可以执行方法中的程序代码。
可选地，图9是根据本申请实施例的一种电子设备的结构框图。如图9所示，该电子设备可以包括：一个或多个(图中仅示出一个)处理器102、存储器104、存储控制器、以及外设接口，其中，外设接口与射频模块、音频模块和显示器连接。
其中，存储器可用于存储软件程序以及模块，如本申请实施例中的方法和装置对应的程序指令/模块，处理器通过运行存储在存储器内的软件程序以及模块，从而执行各种功能应用以及数据处理，即实现上述实施例中的方法。存储器可包括高速随机存储器，还可以包括非易失性存储器，如一个或者多个磁性存储装置、闪存、或者其他非易失性固态存储器。在一些实例中，存储器可进一步包括相对于处理器远程设置的存储器，这些远程存储器可以通过网络连接至终端。上述网络的实例包括但不限于互联网、企业内部网、局域网、移动通信网及其组合。
处理器可以通过传输装置调用存储器存储的信息及应用程序，以执行下述步骤：接收目标数据写入指令，其中，目标数据写入指令中携带有待写入物理寄存器中的目标数据所在的目标内存地址；响应于目标数据写入指令，基于物理寄存器与内存地址的对应关系，查找是否存在与目标内存地址对应的目标物理寄存器；在查找结果为存在与目标内存地址对应的目标物理寄存器的情况下，返回目标数据已写入目标物理寄存器的数据写入结果。
可选的，上述处理器还可以执行如下步骤的程序代码：在响应于数据写入指令，基于物理寄存器与内存地址的对应关系，查找是否存在与目标内存地址对应的目标物理寄存器之前，方法还包括：接收一个或多个数据写入指令，其中，一个或多个数据写入指令分别携带有待写入物理寄存器中数据所在的内存地址；响应于一个或多个数据写入指令，将数据写入物理寄存器；建立基于一个或多个数据写入指令写入了数据的物理寄存器与对应内存地址之间的对应关系。
可选的，上述处理器还可以执行如下步骤的程序代码：响应于目标数据写入指令，基于物理寄存器与内存地址的对应关系，查找是否存在与目标内存地址对应的目标物理寄存器，包括：根据目标内存地址，从多组物理寄存器中确定目标物理寄存器组；将目标内存地址与目标物理寄存器组包括的物理寄存器对应的内存地址匹配，查找是否存在与目标内存地址对应的目标物理寄存器。
可选的，上述处理器还可以执行如下步骤的程序代码：根据目标内存地址，从多组物理寄存器中确定目标物理寄存器组，包括：获取多组物理寄存器的分组数；确定目标内存地址所在的缓存块的索引；根据索引和分组数，确定目标物理寄存器组。
可选的，上述处理器还可以执行如下步骤的程序代码：根据索引和分组数，确定目标物理寄存器组，包括：采用索引对分组数取模，得到取模值；将取模值作为目标物理寄存器组的组号，确定目标物理寄存器组。
可选的，上述处理器还可以执行如下步骤的程序代码：方法还包括：建立目标物理寄存器到目标架构寄存器之间的映射，其中，数据写入可选的，上述处理器还可以执行如下步骤的程序代码：指令还包括待加载目标数据的目标架构寄存器的编号，目标架构寄存器对软件可见。
可选的，上述处理器还可以执行如下步骤的程序代码：在目标物理寄存器包括多行的情况下，目标内存地址包括目标基地址和目标地址步长，其中，目标基地址为在内存中目标物理寄存器写入数据的起始地址，目标地址步长为目标物理寄存器中相邻两行所对应的内存地址之差，目标物理寄存器对应的基地址与目标基地址匹配，且目标物理寄存器对应的地址步长与目标地址步长匹配。
可选的，上述处理器还可以执行如下步骤的程序代码：方法还包括：在查找结果为不存在与目标内存地址对应的目标物理寄存器的情况下，确定备用物理寄存器；将目标内存地址处的目标数据写入备用物理寄存器，并返回目标数据已写入备用物理寄存器的数据写入结果。
采用本申请实施例，提供了一种指令处理的方案。采用建立物理寄存器与内存地址的对应关系的方式，通过接收目标数据写入指令，其中，目标数据写入指令中携带有待写入物理寄存器中的目标数据所在的目标内存地址；响应于目标数据写入指令，基于物理寄存器与内存地址的对应关系，查找是否存在与目标内存地址对应的目标物理寄存器；在查找结果为存在与目标内存地址对应的目标物理寄存器的情况下，返回目标数据已写入目标物理寄存器的数据写入结果，达到了在找到存储了目标内存地址的数据的目标物理寄存器的情况下，直接采用目标物理寄存器进行后续处理的目的，无需再次将目标内存地址的数据写入物理寄存器，从而实现了减少处理器执行数据写入指令的功耗和时间的技术效果，进而解决了由于处理器多次执行数据写入指令的过程中，多次数据写入动作的功耗大且耗时长的技术问题。
本领域普通技术人员可以理解，如图所示的结构仅为示意，电子设备也可以是智能手机(如Android手机、iOS手机等)、平板电脑、掌上电脑以及移动互联网设备(Mobile Internet Devices，MID)、PAD等终端设备。该图其并不对上述电子装置的结构造成限定。例如，电子设备还可包括比该图中所示更多或者更少的组件(如网络接口、显示装置等)，或者具有与该图所示不同的配置。
本领域普通技术人员可以理解上述实施例的各种方法中的全部或部分步骤是可以通过程序来指令终端设备相关的硬件来完成，该程序可以存储于一计算机可读存储介质中，存储介质可以包括：闪存盘、只读存储器(Read-Only Memory，ROM)、随机存取器(Random Access Memory，RAM)、磁盘或光盘等。
实施例4
本申请的实施例还提供了一种计算机可读存储介质。可选地，在本实施例中，上述计算机可读存储介质可以用于保存上述实施例所提供的方法所执行的程序代码。
可选地，在本实施例中，上述存储介质可以位于计算机网络中电子设备群中的任意一个电子设备中，或者位于移动终端群中的任意一个移动终端中。
可选地，在本实施例中，计算机可读存储介质被设置为存储用于执行以下步骤的程序代码：接收目标数据写入指令，其中，目标数据写入指令中携带有待写入物理寄存器中的目标数据所在的目标内存地址；响应于目标数据写入指令，基于物理寄存器与内存地址的对应关系，查找是否存在与目标内存地址对应的目标物理寄存器；在查找结果为存在与目标内存地址对应的目标物理寄存器的情况下，返回目标数据已写入目标物理寄存器的数据写入结果。
可选地，计算机可读存储介质还被设置为存储用于执行以下步骤的程序代码：在响应于数据写入指令，基于物理寄存器与内存地址的对应关系，查找是否存在与目标内存地址对应的目标物理寄存器之前，方法还包括：接收一个或多个数据写入指令，其中，一个或多个数据写入指令分别携带有待写入物理寄存器中数据所在的内存地址；响应于一个或多个数据写入指令，将数据写入物理寄存器；建立基于一个或多个数据写入指令写入了数据的物理寄存器与对应内存地址之间的对应关系。
可选地，计算机可读存储介质还被设置为存储用于执行以下步骤的程序代码：响应于目标数据写入指令，基于物理寄存器与内存地址的对应关系，查找是否存在与目标内存地址对应的目标物理寄存器，包括：根据目标内存地址，从多组物理寄存器中确定目标物理寄存器组；将目标内存地址与目标物理寄存器组包括的物理寄存器对应的内存地址匹配，查找是否存在与目标内存地址对应的目标物理寄存器。
可选地，计算机可读存储介质还被设置为存储用于执行以下步骤的程序代码：根据目标内存地址，从多组物理寄存器中确定目标物理寄存器组，包括：获取多组物理寄存器的分组数；确定目标内存地址所在的缓存块的索引；根据索引和分组数，确定目标物理寄存器组。
可选地，计算机可读存储介质还被设置为存储用于执行以下步骤的程序代码：根据索引和分组数，确定目标物理寄存器组，包括：采用索引对分组数取模，得到取模值；将取模值作为目标物理寄存器组的组号，确定目标物理寄存器组。
可选地，计算机可读存储介质还被设置为存储用于执行以下步骤的程序代码：方法还包括：建立目标物理寄存器到目标架构寄存器之间的映射，其中，数据写入指令还包括待加载目标数据的目标架构寄存器的编号，目标架构寄存器对软件可见。
可选地，计算机可读存储介质还被设置为存储用于执行以下步骤的程序代码：在目标物理寄存器包括多行的情况下，目标内存地址包括目标基地址和目标地址步长，其中，目标基地址为在内存中目标物理寄存器写入数据的起始地址，目标地址步长为目标物理寄存器中相邻两行所对应的内存地址之差，目标物理寄存器对应的基地址与目标基地址匹配，且目标物理寄存器对应的地址步长与目标地址步长匹配。
可选地，计算机可读存储介质还被设置为存储用于执行以下步骤的程序代码：方法还包括：在查找结果为不存在与目标内存地址对应的目标物理寄存器的情况下，确定备用物理寄存器；将目标内存地址处的目标数据写入备用物理寄存器，并返回目标数据已写入备用物理寄存器的数据写入结果。
实施例5
本申请的实施例还提供了一种计算机程序产品。可选地，在本实施例中，上述计算机程序产品可以包括计算机程序，上述计算机程序在被处理器执行时实现上述实施例所提供的方法。
实施例6
本申请的实施例还提供了一种计算机程序产品。可选地，上述计算机程序产品可以包括非易失性计算机可读存储介质，上述非易失性计算机可读存储介质可以用于存储计算机程序，上述计算机程序被处理器执行时实现上述实施例所提供的方法。
实施例7
本申请的实施例还提供了一种计算机程序。可选地，在本实施例中，上述计算机程序被处理器执行时实现上述实施例所提供的方法。
上述本申请实施例序号仅仅为了描述，不代表实施例的优劣。
在本申请的上述实施例中，对各个实施例的描述都各有侧重，某个实施例中没有详述的部分，可以参见其他实施例的相关描述。
在本申请所提供的几个实施例中，应该理解到，所揭露的技术内容，可通过其它的方式实现。其中，以上所描述的装置实施例仅仅是示意性的，例如所述单元的划分，仅仅为一种逻辑功能划分，实际实现时可以有另外的划分方式，例如多个单元或组件可以结合或者可以集成到另一个系统，或一些特征可以忽略，或不执行。另一点，所显示或讨论的相互之间的耦合或直接耦合或通信连接可以是通过一些接口，单元或模块的间接耦合或通信连接，可以是电性或其它的形式。
所述作为分离部件说明的单元可以是或者也可以不是物理上分开的，作为单元显示的部件可以是或者也可以不是物理单元，即可以位于一个地方，或者也可以分布到多个网络单元上。可以根据实际的需要选择其中的部分或者全部单元来实现本实施例方案的目的。
另外，在本申请各个实施例中的各功能单元可以集成在一个处理单元中，也可以是各个单元单独物理存在，也可以两个或两个以上单元集成在一个单元中。上述集成的单元既可以采用硬件的形式实现，也可以采用软件功能单元的形式实现。
所述集成的单元如果以软件功能单元的形式实现并作为独立的产品销售或使用时，可以存储在一个计算机可读取存储介质中。基于这样的理解，本申请的技术方案本质上或者说对现有技术做出贡献的部分或者该技术方案的全部或部分可以以软件产品的形式体现出来，该计算机软件产品存储在一个存储介质中，包括若干指令用以使得一台计算机设备(可为个人计算机、服务器或者网络设备等)执行本申请各个实施例所述方法的全部或部分步骤。而前述的存储介质包括：U盘、只读存储器(ROM，Read-Only Memory)、随机存取存储器(RAM，Random Access Memory)、移动硬盘、磁碟或者光盘等各种可以存储程序代码的介质。
以上所述仅是本申请的优选实施方式，应当指出，对于本技术领域的普通技术人员来说，在不脱离本申请原理的前提下，还可以做出若干改进和润饰，这些改进和润饰也应视为本申请的保护范围。

Claims (12)

  1. 一种指令处理方法，包括：
    接收目标数据写入指令，其中，所述目标数据写入指令中携带有待写入物理寄存器中的目标数据所在的目标内存地址；
    响应于所述目标数据写入指令，基于物理寄存器与内存地址的对应关系，查找是否存在与所述目标内存地址对应的目标物理寄存器；
    在查找结果为存在与所述目标内存地址对应的目标物理寄存器的情况下，返回所述目标数据已写入所述目标物理寄存器的数据写入结果。
  2. 根据权利要求1所述的方法，其中，在响应于所述数据写入指令，基于物理寄存器与内存地址的对应关系，查找是否存在与所述目标内存地址对应的目标物理寄存器之前，所述方法还包括：
    接收一个或多个数据写入指令，其中，所述一个或多个数据写入指令分别携带有待写入物理寄存器中数据所在的内存地址；
    响应于所述一个或多个数据写入指令，将所述数据写入物理寄存器；
    建立基于所述一个或多个数据写入指令写入了数据的物理寄存器与对应内存地址之间的所述对应关系。
  3. 根据权利要求1所述的方法，其中，所述响应于所述目标数据写入指令，基于物理寄存器与内存地址的对应关系，查找是否存在与所述目标内存地址对应的目标物理寄存器，包括：
    根据所述目标内存地址，从多组物理寄存器中确定目标物理寄存器组；
    将所述目标内存地址与所述目标物理寄存器组包括的物理寄存器对应的内存地址匹配，查找是否存在与所述目标内存地址对应的所述目标物理寄存器。
  4. 根据权利要求3所述的方法，其中，所述根据所述目标内存地址，从所述多组物理寄存器中确定目标物理寄存器组，包括：
    获取所述多组物理寄存器的分组数；
    确定所述目标内存地址所在的缓存块的索引；
    根据所述索引和所述分组数，确定所述目标物理寄存器组。
  5. 根据权利要求4所述的方法，其中，所述根据所述索引和所述分组数，确定所述目标物理寄存器组，包括：
    采用所述索引对所述分组数取模，得到取模值；
    将所述取模值作为所述目标物理寄存器组的组号，确定所述目标物理寄存器组。
  6. 根据权利要求1所述的方法，其中，所述方法还包括：建立所述目标物理寄存器到目标架构寄存器之间的映射，其中，所述数据写入指令还包括待加载所述目标数据的所述目标架构寄存器的编号，所述目标架构寄存器对软件可见。
  7. 根据权利要求1所述的方法，其中，
    在所述目标物理寄存器包括多行的情况下，所述目标内存地址包括目标基地址和目标地址步长，其中，所述目标基地址为在内存中所述目标物理寄存器写入数据的起始地址，所述目标地址步长为所述目标物理寄存器中相邻两行所对应的内存地址之差，所述目标物理寄存器对应的基地址与所述目标基地址匹配，且所述目标物理寄存器对应的地址步长与所述目标地址步长匹配。
  8. 根据权利要求1至7中任一项所述的方法，其中，还包括：
    在所述查找结果为不存在与所述目标内存地址对应的目标物理寄存器的情况下，确定备用物理寄存器；将所述目标内存地址处的目标数据写入所述备用物理寄存器，并返回所述目标数据已写入所述备用物理寄存器的数据写入结果。
  9. 一种指令处理装置，包括：
    接收模块，设置为接收目标数据写入指令，其中，所述目标数据写入指令中携带有待写入物理寄存器中的目标数据所在的目标内存地址；
    响应模块，设置为响应于所述目标数据写入指令，基于物理寄存器与内存地址的对应关系，查找是否存在与所述目标内存地址对应的目标物理寄存器；
    返回模块，设置为在查找结果为存在与所述目标内存地址对应的目标物理寄存器的情况下，返回所述目标数据已写入所述目标物理寄存器的数据写入结果。
  10. 一种电子设备，包括：
    存储器，存储有可执行程序；
    处理器，设置为运行所述程序，其中，所述程序运行时执行权利要求1至8中任意一项所述的指令处理方法。
  11. 一种计算机可读存储介质，所述计算机可读存储介质包括存储的可执行程序，其中，在所述可执行程序运行时控制所述存储介质所在设备执行权利要求1至8中任意一项所述的指令处理方法。
  12. 一种计算机程序产品，包括计算机程序，所述计算机程序在被处理器执行时实现根据权利要求1至8中任意一项所述的指令处理方法。
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