WO2025251547A1 - 量子比特校准图的生成方法、装置、设备及存储介质 - Google Patents

量子比特校准图的生成方法、装置、设备及存储介质

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Publication number
WO2025251547A1
WO2025251547A1 PCT/CN2024/134115 CN2024134115W WO2025251547A1 WO 2025251547 A1 WO2025251547 A1 WO 2025251547A1 CN 2024134115 W CN2024134115 W CN 2024134115W WO 2025251547 A1 WO2025251547 A1 WO 2025251547A1
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Prior art keywords
calibration
template
node
qubits
qubit
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English (en)
French (fr)
Inventor
张贞兴
徐雄
张天宇
刘福明
郑一聪
张胜誉
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Tencent Technology (Shenzhen) Co Ltd
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Tencent Technology (Shenzhen) Co Ltd
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F16/00—Information retrieval; Database structures therefor; File system structures therefor
    • G06F16/90—Details of database functions independent of the retrieved data types
    • G06F16/901—Indexing; Data structures therefor; Storage structures
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N10/00—Quantum computing, i.e. information processing based on quantum-mechanical phenomena
    • G06N10/60—Quantum algorithms, e.g. based on quantum optimisation, quantum Fourier or Hadamard transforms
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N10/00—Quantum computing, i.e. information processing based on quantum-mechanical phenomena
    • G06N10/70—Quantum error correction, detection or prevention, e.g. surface codes or magic state distillation

Definitions

  • This application relates to the field of quantum technology, and in particular to a method, apparatus, device, and storage medium for generating a quantum bit calibration map.
  • a quantum chip is the central processing unit (CPU) of a quantum computer.
  • CPU central processing unit
  • the qubits in the quantum chip need to be calibrated to maintain precise control over the quantum states of the qubits.
  • qubit calibration maps are commonly used to represent and drive calibration tasks for qubits in quantum chips.
  • the qubit calibration pattern of quantum chips is manually defined.
  • the structure of the qubit calibration pattern also needs to be manually adjusted. Therefore, the calibration efficiency of qubits is relatively low.
  • This application provides a method, apparatus, device, and storage medium for generating a quantum bit calibration map, which can improve the calibration efficiency of quantum bits.
  • the technical solution provided by this application is as follows:
  • a method for generating a quantum bit calibration map is provided, the method being executed by a computer device, the method comprising:
  • Obtain a calibration template which includes at least two template nodes and at least one first directed edge.
  • the template nodes are used to characterize a calibration process for a qubit
  • the first directed edge is used to indicate the execution order of the calibration processes represented by the two template nodes connected by the first directed edge.
  • a qubit calibration map of the quantum chip is generated, which is used to graphically represent the calibration task for the N qubits.
  • a quantum bit calibration map generation apparatus comprising:
  • An acquisition module is used to acquire a calibration template, the calibration template including at least two template nodes and at least one first directed edge, the template nodes being used to characterize a calibration process for a qubit, and the first directed edge being used to indicate the execution order of the calibration processes respectively characterized by the two template nodes connected by the first directed edge;
  • the acquisition module is also used to acquire the structural data of the quantum chip, the structural data being used to indicate the N qubits included in the quantum chip, where N is an integer greater than 1;
  • a generation module is used to generate a qubit calibration map of the quantum chip based on the calibration template and the structural data.
  • the qubit calibration map is used to graphically represent the calibration task for the N qubits.
  • a computer device including a processor and a memory, the memory storing a computer program, the computer program being loaded and executed by the processor to implement the above-described method for generating a quantum bit calibration map.
  • a computer-readable storage medium wherein a computer program is stored in the storage medium, the computer program being loaded and executed by a processor to implement the above-described method for generating a quantum bit calibration map.
  • a computer program product including a computer program stored in a computer-readable storage medium, wherein a processor reads from the computer-readable storage medium and executes the computer program to implement the above-described method for generating a quantum bit calibration map.
  • the automated generation of qubit calibration maps is achieved.
  • the template nodes in the calibration template represent a type (or class) of calibration process for the qubits
  • the structural data indicates the N qubits included in the quantum chip and the coupling between them. Therefore, by combining the structural data with a fixed calibration template, regardless of changes in the size of the quantum chip (e.g., an increase in the number of qubits or changes in the coupling relationships between qubits), a relatively complete and automatic qubit calibration map conforming to the actual structure of the quantum chip can always be generated.
  • this application improves the generation efficiency of qubit calibration maps and further enhances the calibration efficiency of qubits by automatically generating them.
  • Figure 1 is a schematic diagram of a computer system provided in an embodiment of this application.
  • Figure 2 is a schematic diagram of a method for generating a quantum bit calibration map according to an embodiment of this application
  • Figure 3 is a flowchart of a method for generating a quantum bit calibration map according to an embodiment of this application
  • Figure 4 is a schematic diagram of a calibration template provided in one embodiment of this application.
  • Figure 5 is a schematic diagram of the topology of a quantum chip provided in one embodiment of this application.
  • Figure 6 is a schematic diagram of the topology of a quantum chip provided in another embodiment of this application.
  • Figure 7 is a flowchart of a method for generating a quantum bit calibration map according to another embodiment of this application.
  • Figure 8 is a schematic diagram of the quantum bit calibration diagram of a quantum chip provided in one embodiment of this application.
  • Figure 9 is a schematic diagram of the generation process of a quantum bit calibration map provided in one embodiment of this application.
  • Figure 10 is a block diagram of a device for generating a quantum bit calibration map according to an embodiment of this application.
  • Figure 11 is a structural block diagram of a computer device provided in one embodiment of this application.
  • Quantum computing is a computing method that uses quantum logic and the properties of quantum states, such as superposition and entanglement, to rapidly complete computational tasks.
  • the basic unit for storing data in quantum computing is the qubit.
  • a qubit is a form of quantum information carrier and the basic unit of quantum computing.
  • Classical computers use 0 and 1 as the basic units of binary computation. Unlike classical computers, the state of a qubit is described by a linear combination of the computational ground state (0 or 1), often referred to as a superposition state.
  • Quantum operations are operations that manipulate qubits to process the quantum information they carry. Common quantum operations include the Pauli X, Y, Z transforms (or written as ⁇ x, ⁇ y, ⁇ z), the Hadamard transform (H), and the controlled Pauli X transform. Quantum operations include single-qubit operations on a single qubit and multi-qubit operations on multiple coupled qubits.
  • Quantum chip A chip based on the principles of quantum mechanics, serving as the central processing unit of a quantum computer. Quantum chips of different sizes contain different numbers of qubits.
  • Qubit Calibration Quantum computers utilize qubits for both storage and computation.
  • a qubit is a storage-computing integrated structure; its data storage and operational control both rely on precise control of quantum states.
  • Qubit calibration is the standardization of this control process.
  • a calibrated qubit can maintain precise control within a certain range for a period of time.
  • Quantum bit calibration graph To meet the requirements for computational computation, qubits undergo a series of calibration procedures based on physical models. These typically involve searching for the operating frequency of the quantum device, calibrating the quantum states and gates of isolated qubits, and co-calibrating multiple qubit gates, among other physical parameter calibration and setting steps. This can be abstracted as a directed graph structure containing at least two calibration nodes, called a qubit calibration graph. The qubit calibration graph indicates the dependencies between calibration nodes and drives the qubit calibration process.
  • a Directed Acyclic Graph is a graph consisting of a finite number of nodes and directed edges. Starting from any node, it is impossible to return to that node by following a number of directed edges.
  • Automated calibration The calibration process of qubits involves multiple sets of dependent calibration processes related to various quantum devices, which can be defined as qubit calibration maps.
  • the calibration nodes corresponding to these calibration processes all involve complex microwave control.
  • the corresponding control parameters are characterized by high dimensionality, multiple dependencies, and constant drift. Automating the control process of these parameters means automating calibration.
  • Figure 1 shows a schematic diagram of a computer system provided in one embodiment of this application.
  • the computer system includes: a first device 11, a second device 12, a control device 13, and a quantum computing device 14.
  • the quantum computing device 14 is a quantum chip or a quantum computer containing a quantum chip.
  • the first device 11 and the second device 12 are classical computers.
  • the first device 11 and the second device 12 can be the same computer device or different computer devices.
  • the first device 11 performs the task of generating a qubit calibration map, and the first device 11 sends the qubit calibration map generated for the quantum computing device 14 to the second device 12.
  • the second device 12 is used to control the control device 13, for example, the second device 12 sends instructions to the control device 13 sequentially, according to the qubit calibration map, indicating the calibration process for different qubits.
  • the second device 12 and the control device 13 can communicate via a network, such as a wireless or wired network.
  • the control device 13 includes a series of analog controllers for controlling the quantum computing device 14.
  • the control device 13 controls the qubits in the quantum computing device 14 by controlling the temperature of the environment in which the quantum computing device 14 is located.
  • the control device 13 performs calibration on the qubits in the quantum computing device 14 according to instructions sent by the second device 12.
  • the computer device can be the first device 11 in the computer system described above, or the second device 12, or the control device 13; this application does not limit this.
  • Figure 2 shows a schematic diagram of a method for generating a quantum bit calibration map according to an embodiment of this application.
  • a qubit calibration graph 23 for the quantum chip is generated based on two graph structures: a calibration template 21 and a topology graph 22 of the quantum chip.
  • the calibration template 21 includes at least two template nodes and at least one first directed edge.
  • the template nodes represent a calibration process for a qubit, and the first directed edge indicates the execution order of the calibration processes represented by the two template nodes connected by the first directed edge.
  • the topology graph 22 of the quantum chip includes N topology nodes. Each topology node in the topology graph represents a qubit in the quantum chip, and the connections between these topology nodes indicate the coupling relationships between the qubits.
  • the technical solution provided in this application can separate the work of quantum chip designers and quantum chip calibration personnel. Specifically, quantum chip designers design the topological structure diagram of the quantum chip, while quantum chip calibration personnel design the calibration template. Furthermore, by combining the topological structure diagram and the calibration template in a "diagram-within-a-diagram" manner, the generation of qubit calibration diagrams can be automated, improving the efficiency of quantum chip R&D.
  • FIG. 3 shows a flowchart of a method for generating a qubit calibration map according to an embodiment of this application.
  • the execution entity for each step of this method is a computer device.
  • the method includes at least one of the following steps 310 to 330.
  • Step 310 Obtain a calibration template.
  • the calibration template includes at least two template nodes and at least one first directed edge.
  • the template nodes are used to characterize a calibration process for a qubit, and the first directed edge is used to indicate the execution order of the calibration processes characterized by the two template nodes connected by the first directed edge.
  • the qubit mentioned in the embodiments of this application refers to a physical qubit with a physical structure.
  • a qubit is a superconducting qubit containing a Josephson junction.
  • Qubit parameters refer to parameters related to the qubit.
  • qubit parameters include at least one of the following: parameters describing the physical properties of the qubit, and parameters for quantum operations on the qubit.
  • parameters describing the physical properties of the qubit include the qubit's readout frequency, qubit position, qubit readout power, and qubit coherence time (including spin relaxation time t1 and decoherence time t2), etc.
  • Quantum operation parameters include quantum gate parameters, which include single-qubit gates for implementing single-qubit operations and multi-qubit gates for implementing multi-qubit operations.
  • Quantum operation parameters include parameters for single-qubit operations (including parameters for single-qubit gates) and parameters for multi-qubit operations (including parameters for multi-qubit gates).
  • a calibration template refers to a template used to implement a calibration process for a qubit. This calibration template not only reflects the type of calibration process being performed but also the execution order of the calibration processes.
  • the calibration template includes at least one calibration process for a qubit, and the execution order of different types of calibration processes.
  • a template node represents a calibration process for a qubit, and a directed edge (i.e., a first directed edge) connecting two different template nodes indicates the execution order of the calibration processes represented by the two different template nodes.
  • FIG4 is a schematic diagram of a calibration template provided in one embodiment of this application.
  • A, B, C, and D are different template nodes, corresponding to different types of calibration processes, and edges ab, ac, bd, and cd are different first directed edges, used to indicate the execution order of different types of calibration processes.
  • a calibration process represented by template node A is executed first, followed by calibration processes represented by template nodes B and C (these two calibration processes can be executed in parallel or not).
  • the calibration processes represented by template node D are executed, or after completing the calibration process represented by template node C, the calibration processes represented by template node D are executed.
  • template nodes are used to characterize a calibration process for a qubit, and different template nodes characterize different calibration processes for a qubit. As shown in Figure 4, A, B, C, and D are different template nodes, each corresponding to a different type of calibration process.
  • the first directed edge is used to indicate the execution order of the calibration processes represented by the two template nodes connected by the first directed edge.
  • the first directed edge is a directed edge connecting two template nodes.
  • the first directed edge ab is an edge connecting template node A and template node B, and pointing from template node A to template node B.
  • the first directed edge ab indicates that the calibration process corresponding to template node A is executed first, and then the calibration process corresponding to template node B is executed.
  • the template node is a single template node or a coupled template node.
  • a single template node is used to characterize a calibration process for a single qubit, while a coupled template node is used to characterize a calibration process for Q qubits that are coupled together, where Q is an integer greater than 1.
  • a single template node refers to a template node representing a calibration process that applies only to one qubit.
  • This qubit can be an isolated qubit that is not coupled to other qubits, or it can be a qubit that is coupled to other qubits.
  • a coupled template node refers to a template node representing a calibration process that applies to at least two qubits that are coupled to each other. As shown in Figure 4, template nodes A and B are two single template nodes, and template nodes C and D are two coupled template nodes.
  • the calibration process for a single qubit is used to calibrate the parameters of that single qubit.
  • the parameters of a single qubit include the parameters described above for the physical properties of the qubit, and the parameters for single-bit operation (such as the parameters of the Pauli X, Y, Z transforms).
  • the calibration process for Q qubits is used to calibrate the parameters of multi-qubit operations (such as controlled Pauli X, Y, Z transforms) for Q qubits.
  • the calibration process represented by the template node is general-purpose and not specific to one or a few qubits.
  • the calibration process represented by a single template node is applicable to all qubits in the quantum chip, meaning that the calibration process represented by a single template node can be used to calibrate certain parameters corresponding to each qubit in the quantum chip (such as the parameters of the Pauli X transform corresponding to each qubit).
  • the calibration process represented by the coupled template node is applicable to all two-qubit groups in the quantum chip.
  • a two-qubit group includes two coupled qubits in the quantum chip; that is, the calibration process represented by the coupled template node can be used to calibrate certain parameters of the two-qubit operations for each two-qubit group in the quantum chip (such as the parameters of the controlled Pauli X transform, i.e., the controlled NOT (C-Not) gate, for each two-qubit group). Therefore, in this embodiment, the calibration process represented by the template node is referred to as "a" calibration process.
  • the coupling template node is used to characterize a calibration process for two qubits that are coupled.
  • the calibration template is represented as a directed acyclic graph.
  • the calibration template includes template nodes A, B, C, and D, and first directed edges ab, ac, bd, and cd.
  • Template nodes A and B are used to characterize a calibration process for a single qubit, therefore both template nodes A and B are single template nodes.
  • Template nodes C and D are used to characterize a calibration process for two coupled qubits, therefore both template nodes C and D are coupled template nodes.
  • the first directed edge ab indicates that the calibration process represented by template node A is executed first, followed by the calibration process represented by template node B.
  • the first directed edge ac indicates that the calibration process represented by template node A is executed first, followed by the calibration process represented by template node C.
  • the first directed edge bd indicates that the calibration process represented by template node B is executed first, followed by the calibration process represented by template node D.
  • the first directed edge cd indicates that the calibration process represented by template node C is executed first, followed by the calibration process represented by template node D.
  • a calibration template is constructed using the following code:
  • Step 320 Obtain the structural data of the quantum chip.
  • the structural data is used to indicate the N qubits included in the quantum chip, where N is an integer greater than 1.
  • the aforementioned quantum chip can be a superconducting quantum chip containing superconducting qubits, or it can be a semiconductor quantum chip, an optical quantum chip, etc. This application does not limit it in this regard.
  • structural data is used to indicate the N qubits included in the quantum chip.
  • the structural data reveals the N qubits included in the quantum chip; these N qubits can be all the qubits on the quantum chip, or a subset of all the qubits on the quantum chip.
  • Figure 5 shows a schematic diagram of the structural data. Exemplarily, this structural data indicates the presence of four different qubits q1, q2, q3, and q4.
  • the structural data in addition to indicating the N qubits included in the quantum chip, is also used to indicate the coupling between the N qubits.
  • the structural data is used to indicate qubits with coupling relationships and isolated qubits that are not coupled to any other qubits. For example, as shown in FIG5, the black border between qubits q1 and q2 indicates a coupling relationship between these two qubits; the black border between qubits q2 and q4 indicates a coupling relationship between these two qubits; the black border between qubits q3 and q4 indicates a coupling relationship between these two qubits; and the black border between qubits q1 and q3 indicates a coupling relationship between these two qubits. For example, in the structural data shown in FIG5, there are no isolated qubits. For example, in the structural data shown in FIG6, there is an isolated qubit q5.
  • the structural data of a quantum chip is represented in the form of a topological diagram.
  • Figure 5 shows a schematic diagram of the topology of a quantum chip provided in one embodiment of this application.
  • the topology diagram indicates that the quantum chip includes four qubits, q1, q2, q3, and q4, and indicates that q1 and q2 are coupled, q1 and q3 are coupled, q2 and q4 are coupled, and q3 and q4 are coupled.
  • the coupling relationship between at least two qubits means that at least two qubits are directly connected in the quantum chip. In some embodiments, the coupling relationship between at least two qubits means that at least two qubits are connected through other devices in the quantum chip besides the qubits (such as capacitors and inductors).
  • At least two qubits that are not coupled through other qubits are referred to as at least two qubits with a coupling relationship.
  • q2 and q3 are both coupled to q1, but q2 and q3 are not coupled.
  • the qubits are coupled pairwise. This is merely an example of the coupling between qubits.
  • isolated qubits or multiple coupled qubits can exist.
  • Figure 6 shows a schematic diagram of the topology of a quantum chip provided in another embodiment of this application. Compared to Figure 5, the topology diagram shown in Figure 6 also indicates the isolated qubit q5, and further indicates that q1, q3, and q4 are coupled.
  • the topology diagram of a quantum chip is constructed using the following code:
  • Step 330 Based on the calibration template and structural data, generate a qubit calibration map of the quantum chip.
  • the qubit calibration map is used to graphically represent the calibration task for N qubits.
  • a calibration task for N qubits involves multiple calibration processes for at least one of the N qubits.
  • a calibration task for N qubits can be broken down into multiple local calibration processes, each of which can be represented as a calibration node in a qubit calibration graph.
  • a graphical representation of a calibration task for N qubits can be understood as using a graphical form to characterize the calibration task for N qubits, so that the execution order of the calibration tasks for N qubits and the qubits calibrated by different calibration tasks can be clearly and intuitively perceived.
  • a qubit calibration graph includes at least two calibration nodes and at least one second directed edge.
  • the calibration nodes represent a calibration process for at least one of N qubits.
  • calibration node A(q1) represents the calibration process represented by template node A performed on qubit q1
  • calibration node B(q1) represents the calibration process represented by template node B performed on qubit q1.
  • the second directed edge indicates the execution order of the calibration processes represented by the two calibration nodes connected by the second directed edge.
  • the edge connecting calibration node A(q1) and calibration node B(q1), pointing from calibration node A(q1) to calibration node B(q1) is the second directed edge. This second directed edge indicates that the calibration process represented by template node A is performed first on qubit q1, and then the calibration process represented by template node B is performed on qubit q1.
  • each calibration node corresponds to a qubit in the quantum chip; that is, the calibration process represented by the calibration node is the actual calibration process required for one or more qubits in the quantum chip. Therefore, in this embodiment, the calibration process represented by the calibration node is referred to as "one" calibration process.
  • the calibration task of the quantum chip is performed in two stages: a first stage and a second stage.
  • Corresponding qubit calibration diagrams are generated for each stage.
  • the calibration process is performed on each qubit in the quantum chip.
  • the calibration template used in the first stage only includes single template nodes, such as template nodes A and B in Figure 4.
  • the qubit calibration diagram corresponding to the first stage is used to graphically represent the calibration process performed on each of the N qubits.
  • the calibration process is performed on each group of qubits in the quantum chip.
  • Each qubit group includes Q qubits with coupling relationships (Q can be any integer greater than 1).
  • the calibration template used in the second stage only includes coupled template nodes, such as template nodes C and D in Figure 4.
  • the qubit calibration diagram corresponding to the second stage is used to graphically represent the calibration process performed on each group of qubits included in the N qubits.
  • the technical solution provided in this application generates a qubit calibration map that graphically represents a calibration task for N qubits in a quantum chip, based on a calibration template and the structural data of the quantum chip, thus achieving automated generation of the qubit calibration map.
  • the template nodes in the calibration template represent a type of calibration process for the qubits
  • the structural data indicates the N qubits included in the quantum chip and the coupling relationships between them.
  • step 330 includes at least one of the following sub-steps 332 to 334.
  • Sub-step 332 Based on the structural data, the template node is expanded into at least one calibration node in the qubit calibration diagram.
  • the calibration node is used to characterize a calibration process for at least one of the N qubits.
  • the unfolding in this application can also be understood as splitting, splitting a template node into at least one calibration node.
  • at least one calibration node obtained by unfolding from a template node can also be considered as at least one calibration node split from that template node.
  • the structural data indicates N qubits on the quantum chip.
  • there are at least two template nodes in the calibration template each template node calibrating the same or different number of qubits, thereby achieving calibration for the N qubits.
  • each calibration node is used to perform the calibration process represented by the i-th template node on one of the N qubits, where i is a positive integer.
  • the i-th template node when the calibration process represented by the i-th template node among at least two template nodes is for at least two qubits on the quantum chip that satisfy a first relation, the i-th template node is expanded into M calibration nodes.
  • Each calibration node is used to perform the calibration process represented by the i-th template node on one qubit group of N qubits, where i is a positive integer.
  • a qubit group includes at least two qubits that satisfy the first relation.
  • the first relation includes at least one of coupling relation, position relation, distance relation, etc.
  • the structure data also indicates qubits among the N qubits that have a relation.
  • this relation includes at least one of coupling relation, position relation, distance relation, etc.
  • the qubits with a relation are directly determined from the structure data, and it is determined whether the relation is the aforementioned first relation. If the relation is the aforementioned first relation, the at least two qubits that satisfy the first relation are taken as a qubit group, and the calibration process represented by the i-th template node is performed on one qubit group.
  • the N qubits on a quantum chip there may be qubits that have not been calibrated by the calibration process represented by any one of the template nodes in the calibration template.
  • the N qubits on a quantum chip there may be qubits that have been calibrated multiple times by the calibration processes represented by multiple template nodes in the calibration template.
  • the calibration process represented by a calibration node derived from a template node corresponds to the calibration process represented by the template node itself.
  • template node j is a single template node
  • calibration node k is derived from template node j
  • calibration node k can be used to represent performing the calibration process represented by template node j on one of the N qubits.
  • the calibration node is used to represent performing the calibration process represented by the template node corresponding to that calibration node on at least one of the N qubits.
  • each template node and each directed edge in the calibration template needs to be expanded according to the structural data.
  • the calibration node is a single calibration node or a coupled calibration node.
  • a single calibration node is used to characterize a calibration process for one qubit in a group of N qubits, while a coupled calibration node is used to characterize a calibration process for multiple qubits in a group of N qubits that are coupled together.
  • a coupling calibration node is used to characterize a calibration process for two coupled qubits out of N qubits.
  • sub-step 332 includes at least one of the following steps:
  • the template node is a single template node
  • the template node when the template node is a single template node, the template node is expanded according to each of the N qubits of the quantum chip indicated by the structural data to obtain N single calibration nodes, each single calibration node being used to indicate a calibration process for a qubit.
  • the i-th template node among at least two template nodes is a single template node
  • the i-th template node is expanded into N calibration nodes.
  • Each calibration node is used to perform the calibration process represented by the i-th template node on one qubit out of the N qubits.
  • the N qubits correspond to the N calibration nodes.
  • the calibration node is also called a single calibration node, indicating that the number of qubits calibrated by the calibration node is 1.
  • each of the at least two template nodes it is determined whether it belongs to a single template node. If it belongs to a single template node, for each single template node, it is expanded into a single calibration node corresponding to each of the N qubits, thereby obtaining N single calibration nodes.
  • the N single calibration nodes obtained by expanding the same single template node have the same calibration process, but the calibrated qubits are different.
  • Figure 8 shows a schematic diagram of the quantum bit calibration diagram of a quantum chip provided in one embodiment of this application.
  • the single template node A shown in Figure 4 can be expanded into single calibration nodes A(q1), A(q2), A(q3) and A(q4) in Figure 8.
  • A(q1) represents the calibration process of performing the single template node A representation for the quantum bit q1.
  • the single template node B shown in Figure 4 can be expanded into single calibration nodes B(q1), B(q2), B(q3) and B(q4) in Figure 8.
  • B(q1) represents the calibration process of performing the single template node B representation for the quantum bit q1.
  • the coupled template node is expanded into M coupled calibration nodes in the qubit calibration diagram, where M is the number of qubit groups contained in N qubits, M is a positive integer, and the qubit group includes Q qubits that are coupled.
  • the template node when the template node is a coupled template node, the template node is expanded according to the coupled qubits among the N qubits of the quantum chip indicated by the structural data to obtain M coupled calibration nodes.
  • Each coupled calibration node is used to indicate a calibration process for a set of coupled qubits.
  • the i-th template node among at least two template nodes is a coupled template node
  • the i-th template node is expanded into M calibration nodes.
  • Each calibration node is used to perform the calibration process represented by the i-th template node on one qubit group of N qubits, where i is a positive integer.
  • a qubit group includes at least two qubits that satisfy a coupling relationship.
  • the first relationship mentioned above is the coupling relationship.
  • the structural data also indicates the qubits with a relationship among the N qubits. Exemplarily, this relationship includes a coupling relationship.
  • the qubits with a relationship are directly determined from the structural data, and it is determined whether the relationship is a coupling relationship. If the relationship is a coupling relationship, the at least two qubits that satisfy the coupling relationship are considered as a qubit group, and the calibration process represented by the i-th template node is performed on one qubit group.
  • Each calibration node is used to perform the calibration process represented by the i-th template node on one qubit group of N qubits, and the M qubit groups correspond to the M calibration nodes.
  • the calibration node is also called the coupled calibration node, and the number of qubits calibrated by the calibration node is the number of qubits in a qubit group that has a coupling relationship.
  • the coupled template node For example, for each of at least two template nodes, it is determined whether it belongs to a coupled template node. If it belongs to a coupled template node, for each coupled template node, M qubit groups out of N qubits are obtained, and the coupled template node is expanded into coupled calibration nodes corresponding to each of the M qubit groups, thereby obtaining M coupled calibration nodes. For example, the M coupled calibration nodes obtained from the same coupled template node have the same calibration process, but the calibrated qubit groups are different.
  • the number of qubit groups contained in the 4 qubits is 4, namely qubit group c1_2 including q1 and q2, qubit group c1_3 including q1 and q3, qubit group c2_4 including q2 and q4, and qubit group c3_4 including q3 and q4. Therefore, the coupling template node C shown in Figure 4 can be expanded into the coupling calibration nodes C(c1_2), C(c1_3), C(c2_4), and C(c3_4) in Figure 8.
  • C(c1_2) represents the calibration process performed on the coupling template node C for qubits q1 and q2.
  • the coupling template node D shown in Figure 4 can be expanded into the coupling calibration nodes D(c1_2), D(c1_3), D(c2_4), and D(c3_4) in Figure 8.
  • D(c1_2) represents the calibration process performed on the coupling template node D for qubits q1 and q2.
  • the single template node is expanded into a single calibration node
  • the coupled template node is expanded into a coupled calibration node, so that the generated qubit calibration map can be used to perform single qubit calibration tasks for quantum chips, as well as to perform multi-qubit calibration tasks for coupled qubits in quantum chips, thus ensuring the completeness of the qubit calibration map.
  • sub-step 332 includes: when the template node is a target template node, unfolding the target template node into at least two calibration nodes connected by a third directed edge, based on the structural data.
  • the calibration process represented by the target template node is affected by the coupling relationship between qubits when applied to different qubits.
  • the impact of the coupling relationship between qubits on the calibration process represented by the target template node when applied to different qubits means that the execution order of the calibration process represented by the target template node for different qubits (different single qubits or different groups of qubits) is affected by the coupling relationship between qubits.
  • the calibration process represented by the target template node is used to calibrate the timing parameters of the qubits.
  • These timing parameters are related to the operating timing of the quantum chip, and calibration of these parameters requires consideration of the coupling relationships between the qubits.
  • the calibration process represented by the target template node is therefore affected by the coupling relationships between the qubits.
  • the calibration process represented by the target template node is used to calibrate the crosstalk parameters of the qubits.
  • the crosstalk parameters are used to describe the noise formed due to the coupling of qubits in the quantum chip.
  • the calibration of the crosstalk parameters also needs to consider the execution order for different qubits or different groups of qubits in the quantum chip according to the coupling relationship between qubits. Therefore, the calibration process represented by the target template node is affected by the coupling relationship between qubits.
  • the third directed edge is used to indicate that the calibration processes represented by the two calibration nodes connected by the third directed edge cannot be executed in parallel.
  • the third directed edge connecting B(q1) and B(q2) indicates that the calibration processes represented by B(q1) and B(q2) cannot be executed in parallel;
  • the third directed edge connecting B(q1) and B(q3) indicates that the calibration processes represented by B(q1) and B(q3) cannot be executed in parallel;
  • the third directed edge connecting B(q3) and B(q4) indicates that the calibration processes represented by B(q3) and B(q4) cannot be executed in parallel.
  • the third directed edge connecting B(q1) and B(q2) not only indicates that the calibration processes represented by B(q1) and B(q2) cannot be executed in parallel, but can also indicate that the calibration process represented by B(q1) is executed first, and then the calibration process represented by B(q2) is executed. That is, the third directed edge indicates that the calibration processes represented by the two calibration nodes connected by the third directed edge are executed serially.
  • the target template node is expanded into multiple calibration nodes connected by a third directed edge.
  • it is restricted that some calibration nodes expanded from the target template node cannot be executed in parallel. This sets a constraint on parallel execution for the calibration process represented by the target template node, ensuring the correctness of the calibration task performed according to the qubit calibration diagram.
  • the target template node is a single template node or a coupled template node.
  • the qubits corresponding to the two calibration nodes connected by the third directed edge are coupled.
  • the qubits q1 and q2 corresponding to B(q1) and B(q2) have the coupling relationship shown in Figure 4
  • the qubits q1 and q3 corresponding to B(q1) and B(q3) have the coupling relationship shown in Figure 4
  • the qubits q3 and q4 corresponding to B(q3) and B(q4) have the coupling relationship shown in Figure 4.
  • the Q qubits corresponding to the two calibration nodes connected by the third directed edge each contain the same qubit.
  • one calibration node connected by the third directed edge corresponds to q1 and q2 in Figure 4
  • the other calibration node connected by the third directed edge corresponds to q1 and q3 in Figure 4.
  • the target template node is expanded into multiple calibration nodes connected by a third directed edge using a tree search method.
  • tree search methods include BFS (Breadth First Search) and DFS (Deep First Search).
  • the BFS method if the BFS method is applied to it according to the topology diagram shown in Figure 5, it can be expanded into B(q1), B(q2), B(q3), and B(q4) connected by the third directed edge in Figure 8.
  • the order indicated by the third directed edge is the search order of the BFS method.
  • the qubit q1 in the topology diagram is taken as the starting search point of BFS, generating B(q1).
  • q2 and q3 coupled to q1 are searched to generate B(q2) and B(q3).
  • q3 is searched to q4 to generate B(q4).
  • the qubit used as the starting search point of the tree search algorithm can be set by the technician as needed, and this application does not limit it.
  • the qubits corresponding to the two calibration nodes connected by the third directed edge are coupled, or the multiple qubits corresponding to the two calibration nodes connected by the third directed edge contain the same qubit. That is, the qubits corresponding to the two calibration nodes connected by the third directed edge are physically directly related. Therefore, through the above method, the calibration process represented by the target template node can be executed separately when applied to these physically close qubits (or qubit groups) in the quantum chip. This avoids deviations in calibration results caused by simultaneously executing the calibration process represented by the target template node on coupled qubits (or two qubit groups containing the same qubit).
  • the following code addresses whether the template node in the calibration template is for a single qubit or for multiple qubits with coupling relationships, and the method for unfolding the template node:
  • Sub-step 334 Expand the first directed edge into at least one second directed edge in the qubit calibration graph.
  • the second directed edge is used to indicate the execution order of the calibration process represented by the two calibration nodes connected by the second directed edge.
  • the unfolding in this application embodiment can also be understood as splitting, splitting a first directed edge into at least one second directed edge.
  • at least one second directed edge obtained by unfolding a first directed edge can also be considered as at least one second directed edge split from the first directed edge.
  • each second directed edge connects two calibration nodes to generate a qubit calibration map.
  • the two calibration nodes connected by the second directed edge correspond to the two template nodes connected by the first directed edge corresponding to the second directed edge.
  • the second directed edge t is obtained by expanding the first directed edge r
  • the two template nodes connected by the first directed edge r are template node j and template node k
  • the two calibration nodes connected by the second directed edge t are obtained by expanding template node j and template node k, respectively.
  • the direction of the second directed edge corresponds to the direction of the first directed edge.
  • the second directed edge t is obtained by expanding the first directed edge r, and the two template nodes connected by the first directed edge r are template node j and template node k respectively, and the first directed edge r points from template node j to template node k, then the second directed edge t points from the calibration node obtained by expanding the template node j to the calibration node obtained by expanding the template node k.
  • sub-step 334 includes at least one of the following steps:
  • the first directed edge is expanded into N second directed edges in the qubit calibration graph.
  • Each of the N second directed edges connects to two single calibration nodes corresponding to the same qubit in the N qubits.
  • the first directed edge ab can be expanded into four second directed edges in Figure 8: connecting A(q1) and B(q1), connecting A(q2) and B(q2), connecting A(q3) and B(q3), and connecting A(q4) and B(q4).
  • first directed edge ab can be expanded into four second directed edges in Figure 8: connecting A(q1) and B(q1), connecting A(q2) and B(q2), connecting A(q3) and B(q3), and connecting A(q4) and B(q4).
  • N 4 is known.
  • the first directed edge is expanded into M ⁇ Q second directed edges in the qubit calibration diagram.
  • Each of the M ⁇ Q second directed edges connects a single calibration node and a coupled calibration node corresponding to the same qubit in the N qubits.
  • the first directed edge ac can be expanded into eight second directed edges in Figure 8: connecting A(q1) and C(c1_2), connecting A(q1) and C(c1_3), connecting A(q2) and C(c1_2), connecting A(q2) and C(c2_4), connecting A(q3) and C(c1_3), connecting A(q3) and C(c3_4), connecting A(q4) and C(c3_4), and connecting A(q4) and C(c2_4).
  • the second directed edge connecting A(q1) and C(c1_2) as an example, the A(q1) and C(c1_2) connected by this second directed edge correspond to qubit q1 in Figure 5.
  • the first directed edge bd can be expanded into eight second directed edges in Figure 8, connecting B(q1) and D(c1_2), connecting B(q1) and D(c1_3), connecting B(q2) and D(c1_2), connecting B(q2) and D(c2_4), connecting B(q3) and D(c1_3), connecting B(q3) and D(c3_4), connecting B(q4) and D(c3_4), and connecting B(q4) and D(c2_4).
  • the second directed edge connecting B(q1) and D(c1_2) as an example, the B(q1) and D(c1_2) connected by this second directed edge correspond to qubit q1 in Figure 5.
  • the first directed edge is expanded into P second directed edges in the qubit calibration diagram.
  • the first coupling template node characterizes a calibration process for Q1 coupled qubits
  • the second coupling template node characterizes a calibration process for Q2 coupled qubits, where Q2 is an integer greater than 1 and less than or equal to Q1.
  • P is the sum of the number of second qubit groups contained in each first qubit group (out of N qubits), and P is a positive integer.
  • the first qubit group includes the Q1 coupled qubits from the aforementioned N qubits
  • the second qubit group includes the Q2 coupled qubits from the aforementioned N qubits.
  • Each of the P second directed edges connects to two coupling calibration nodes corresponding to the same second qubit group in the N qubits.
  • the correspondence between two coupled calibration nodes and the same second qubit group in N qubits means that the calibration process represented by the two coupled calibration nodes targets qubits that include qubits in that second qubit group.
  • the C(c1_2) and D(c1_2) connected by this second directed edge correspond to the second qubit group c1_2 (i.e., qubits q1 and q2 in Figure 5).
  • Figure 9 illustrates a schematic diagram of the generation process of a qubit calibration diagram provided in an embodiment of this application.
  • the quantum chip includes qubits q5, q6, q7, and q8, wherein q5 and q6 are coupled, q6 and q7 are coupled, q7 and q8 are coupled, q5, q6, and q7 are coupled, and q5, q7, and q8 are coupled.
  • the second coupling template node E is expanded into three coupling calibration nodes: E(c5_6), E(c6_7), and E(c7_8).
  • E(c5_6) represents the calibration process represented by the second coupling template node E for qubits q5 and q6 (i.e., the second qubit group (c5_6)).
  • E(c6_7) represents the calibration process represented by the second coupling template node E for qubits q6 and q7 (i.e., the second qubit group (c6_7)).
  • E(c7_8) represents the calibration process represented by the second coupling template node E for qubits q7 and q8 (i.e., the second qubit group (c7_8)).
  • the first coupling template node F is expanded into two coupling calibration nodes, F(c5_6_7) and F(c5_7_8).
  • F(c5_6_7) represents the calibration process represented by the first coupling template node F for qubits q5, q6, and q7
  • F(c5_7_8) represents the calibration process represented by the first coupling template node F for qubits q5, q7, and q8.
  • the first directed edge ef can then be expanded into three second directed edges as shown in Figure 9: connecting E(c5_6) and F(c5_6_7), connecting E(c6_7) and F(c5_6_7), and connecting E(c7_8) and F(c5_7_8).
  • ((c5_6_7) contains (c5_6) and (c6_7)
  • E(c5_6) and F(c5_6_7) correspond to (c5_6)
  • E(c6_7) and F(c5_6_7) correspond to (c6_7)
  • E(c7_8) and F(c5_7_8) correspond to E(c7_8).
  • each second directed edge obtained by the above method can fully and accurately indicate the order of different calibration processes for each qubit or group of qubits in the quantum chip based on the coupling of each qubit in the quantum chip.
  • each template node in the calibration template is expanded into at least one calibration node, and each first directed edge is expanded into at least one second directed edge, thereby obtaining the quantum bit calibration diagram of the quantum chip.
  • the template nodes and the first directed edge in the calibration template are expanded according to the structural data of the quantum chip, thereby expanding the calibration template into a qubit calibration diagram of the quantum chip.
  • An inverted expansion method is adopted, using the relatively stable calibration template as the underlying structure instead of the topological structure of the quantum chip. This ensures the consistency of the calibration process represented by the template nodes in the calibration template when applied to the qubits in the quantum chip. Furthermore, it guarantees the stability of the underlying structure of the qubit calibration diagram, which does not change with the size and topology of the quantum chip, facilitating the instantaneous generation and optimization of the qubit calibration diagram.
  • the quantum bit calibration map of the quantum chip is generated using the following code:
  • the calibration process represented by each calibration node is executed in the execution order indicated by each second directed edge in the qubit calibration map.
  • the calibration processes represented by calibration nodes A(q1), A(q2), A(q3), and A(q4) derived from template node A in Figure 4 are executed first. Then, the calibration processes represented by calibration nodes B(q1), B(q2), B(q3), and B(q4) derived from template node B in Figure 4, as well as the calibration processes represented by calibration nodes C(c1_2), C(c1_3), C(c3_4), and C(c2_4) derived from template node C in Figure 4, are executed. Finally, the calibration processes represented by calibration nodes D(c1_2), D(c1_3), D(c3_4), and D(c2_4) derived from template node D in Figure 4 are executed.
  • the calibration process represented by each calibration node is executed according to the execution order indicated by the second directed edge obtained by expanding the first directed edge. This automates the calibration task for the quantum chip while ensuring the correctness of the execution order of each calibration process.
  • the calibration processes represented by the J calibration nodes are executed in parallel.
  • the J calibration nodes are obtained by expanding the same template node, and J is an integer greater than 1.
  • the calibration processes represented by calibration nodes A(q1), A(q2), A(q3), and A(q4) derived from template node A in Figure 4 can be executed in parallel.
  • the calibration processes represented by calibration nodes C(c1_2), C(c1_3), C(c3_4), and C(c2_4) derived from template node C in Figure 4 can be executed in parallel.
  • the calibration processes represented by calibration nodes D(c1_2), D(c1_3), D(c3_4), and D(c2_4) derived from template node D in Figure 4 can be executed in parallel.
  • the calibration processes represented by the K calibration nodes in the qubit calibration diagram are executed in parallel.
  • the K calibration nodes are obtained by expanding the same target template node, and the number of third directed edges between the K calibration nodes is greater than the first threshold.
  • B(q1) is the calibration node with the highest priority for execution.
  • the number of third directed edges between B(q2) and B(q3) is 2. If the first threshold is 1, the calibration processes represented by B(q2) and B(q3) are executed in parallel. If the first threshold is greater than or equal to 2, the calibration processes represented by B(q2) and B(q3) cannot be executed in parallel.
  • the first threshold is set by technicians according to the parameters required for calibration of the target template node and the arrangement of various devices in the quantum chip (such as qubits and devices that couple qubits), and can be 1, 2, 3, etc. This application does not limit this.
  • the qubits corresponding to the two calibration nodes connected by the third directed edge have a direct physical correlation. Therefore, the number of third directed edges between the two calibration nodes can be used to characterize the distance between the qubits or qubit groups corresponding to the two calibration nodes in the quantum chip, or in other words, the degree of mutual influence in the quantum chip. Therefore, by setting a first threshold using the above method, the calibration nodes expanded from the target template node are executed in parallel with intervals, ensuring both the efficiency of the calibration task and taking into account the actual physical structure and arrangement of the quantum chip, thereby guaranteeing the effectiveness of the calibration task.
  • FIG. 10 shows a block diagram of a qubit calibration map generation apparatus according to an embodiment of this application.
  • This apparatus has the function of implementing the above-described qubit calibration map generation method; the function can be implemented in hardware or by hardware executing corresponding software.
  • This apparatus can be a computer device or can be installed within a computer device.
  • the apparatus 1000 may include: an acquisition module 1010 and a generation module 1020.
  • the acquisition module 1010 is used to acquire a calibration template, the calibration template including at least two template nodes and at least one first directed edge, the template nodes being used to characterize a calibration process for a qubit, and the first directed edge being used to indicate the execution order of the calibration processes respectively characterized by the two template nodes connected by the first directed edge.
  • the acquisition module 1010 is also used to acquire structural data of the quantum chip, wherein the structural data is used to indicate the N qubits included in the quantum chip, where N is an integer greater than 1.
  • the generation module 1020 is used to generate a quantum bit calibration map of the quantum chip based on the calibration template and the structural data.
  • the quantum bit calibration map is used to graphically represent the calibration task for the N quantum bits.
  • the generation module 1020 includes: a node expansion submodule, an edge expansion submodule, and a generation submodule (not shown in FIG10).
  • the node expansion submodule is used to expand the template node into at least one calibration node in the qubit calibration diagram according to the structural data.
  • the calibration node is used to characterize a calibration process for at least one qubit among the N qubits.
  • An edge expansion submodule is used to expand the first directed edge into at least one second directed edge in the qubit calibration graph, wherein the second directed edge is used to indicate the execution order of the calibration process represented by the two calibration nodes connected by the second directed edge.
  • the template node is a single template node or a coupled template node.
  • the single template node is used to characterize a calibration process for a single qubit
  • the coupled template node is used to characterize a calibration process for Q qubits that are coupled.
  • the calibration node is a single calibration node or a coupled calibration node.
  • the single calibration node is used to characterize a calibration process for one qubit among the N qubits
  • the coupled calibration node is used to characterize a calibration process for Q qubits that are coupled among the N qubits, where Q is an integer greater than 1.
  • the node expansion submodule is used to expand the single template node into N single calibration nodes in the qubit calibration diagram according to the structural data when the template node is the single template node; and to expand the coupled template node into M coupled calibration nodes in the qubit calibration diagram according to the structural data when the template node is the coupled template node, wherein M is the number of qubit groups contained in the N qubits, M is a positive integer, and the qubit group includes Q qubits that are coupled.
  • the edge expansion submodule is configured to: when both template nodes connected by the first directed edge are single template nodes, expand the first directed edge into N second directed edges in the qubit calibration graph, with each of the N second directed edges connecting to two single calibration nodes corresponding to the same qubit among the N qubits; when the two template nodes connected by the first directed edge are a single template node and a coupled template node, expand the first directed edge into M ⁇ Q second directed edges in the qubit calibration graph, with each of the M ⁇ Q second directed edges connecting to a single calibration node and a coupled calibration node corresponding to the same qubit among the N qubits; when the two template nodes connected by the first directed edge are a first coupled template node and a second coupled template node.
  • the first directed edge is expanded into P second directed edges in the qubit calibration graph.
  • the first coupling template node is used to characterize a calibration process for Q1 qubits with coupling relationship
  • the second coupling template node is used to characterize a calibration process for Q2 qubits with coupling relationship.
  • Q2 is an integer greater than 1 and less than or equal to Q1.
  • P is the sum of the number of second qubit groups contained in each first qubit group, and P is a positive integer.
  • the first qubit group includes Q1 qubits with coupling relationship among the N qubits
  • the second qubit group includes Q2 qubits with coupling relationship among the N qubits.
  • Each of the P second directed edges connects to two coupling calibration nodes corresponding to the same second qubit group among the N qubits.
  • the node expansion submodule is used to expand the target template node into at least two calibration nodes connected by a third directed edge in the qubit calibration diagram according to the structural data when the template node is a target template node.
  • the calibration process represented by the target template node is affected by the coupling relationship between qubits when applied to different qubits.
  • the third directed edge is used to indicate that the calibration processes represented by the two calibration nodes connected by the third directed edge cannot be executed in parallel.
  • the target template node is a single template node or a coupled template node.
  • the single template node is used to characterize a calibration process for a single qubit
  • the coupled template node is used to characterize a calibration process for Q qubits that are coupled, where Q is an integer greater than 1.
  • the target template node is the single template node
  • the qubits corresponding to the two calibration nodes connected by the third directed edge are coupled.
  • the Q qubits corresponding to the two calibration nodes connected by the third directed edge contain the same qubit.
  • the device 1000 further includes an execution module (not shown in FIG10).
  • the execution module is used to execute the calibration process represented by each of the calibration nodes in the execution order indicated by each of the second directed edges in the qubit calibration diagram.
  • the calibration processes represented by the J calibration nodes are executed in parallel, wherein the J calibration nodes are obtained by expanding the same template node, and J is an integer greater than 1.
  • the calibration processes represented by the K calibration nodes are executed in parallel; the K calibration nodes are obtained by expanding the same target template node, and the number of third directed edges between the K calibration nodes is greater than a first threshold; wherein, when the calibration process represented by the target template node is applied to different qubits, it is affected by the coupling relationship between the qubits, and the third directed edge is used to indicate that the calibration processes represented by the two calibration nodes connected by the third directed edge cannot be executed in parallel.
  • the apparatus provided in the above embodiments is only illustrated by the division of the above functional modules when implementing its functions.
  • the above functions can be assigned to different functional modules as needed, that is, the internal structure of the device can be divided into different functional modules to complete all or part of the functions described above.
  • the apparatus and method embodiments provided in the above embodiments belong to the same concept, and the specific implementation process can be found in the method embodiments, which will not be repeated here.
  • Figure 11 exemplarily illustrates a structural block diagram of a computer device provided in an embodiment of this application.
  • computer device 1100 includes a processor 1101 and a memory 1102.
  • Processor 1101 may include one or more processing cores, such as a quad-core processor, an octa-core processor, etc.
  • Processor 1101 may be implemented using at least one hardware form selected from DSP (Digital Signal Processing), FPGA (Field Programmable Gate Array), and PLA (Programmable Logic Array).
  • Processor 1101 may also include a main processor and a coprocessor.
  • the main processor also known as the CPU, is used to process data in the wake-up state; the coprocessor is a low-power processor used to process data in the standby state.
  • processor 1101 may integrate a GPU (Graphics Processing Unit), which is responsible for rendering and drawing the content required to be displayed on the screen.
  • processor 1101 may also include an AI (Artificial Intelligence) processor, which is used to handle computational operations related to machine learning.
  • AI Artificial Intelligence
  • the memory 1102 may include one or more computer-readable storage media, which may be tangible and non-transitory.
  • the memory 1102 may also include high-speed random access memory and non-volatile memory, such as one or more disk storage devices or flash memory devices.
  • the non-transitory computer-readable storage media in the memory 1102 stores a computer program that is loaded and executed by the processor 1101 to implement the method for generating the above-described quantum bit calibration map.
  • FIG11 does not constitute a limitation on the computer device 1100, and may include more or fewer components than shown, or combine certain components, or employ different component arrangements.
  • a chip product is also provided, the chip product including programmable logic circuits and/or computer programs, which, when the chip product is run, are used to implement the above-described method for generating a quantum bit calibration map.
  • a computer-readable storage medium wherein a computer program is stored therein, the computer program being loaded and executed by a processor to implement the above-described method for generating a quantum bit calibration map.
  • the computer-readable storage medium may include: ROM (Read-Only Memory), RAM (Random-Access Memory), SSD (Solid State Drives), or optical disc, etc.
  • the random access memory may include ReRAM (Resistance Random Access Memory) and DRAM (Dynamic Random Access Memory).
  • a computer program product including a computer program stored in a computer-readable storage medium, and a processor reading from the computer-readable storage medium and executing the computer program to implement the above-described method for generating a quantum bit calibration map.
  • step numbers described herein are merely illustrative of one possible execution order. In some other embodiments, the steps may not be executed in numerical order, such as two steps with different numbers being executed simultaneously, or two steps with different numbers being executed in the reverse order of the illustration. This application does not limit this.

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Abstract

一种量子比特校准图的生成方法、装置、设备及存储介质，涉及量子技术领域。该方法包括：获取校准模板，校准模板包括至少两个模板节点和至少一条第一有向边，模板节点用于表征针对量子比特的一种校准过程，第一有向边用于指示第一有向边连接的两个模板节点所分别表征的校准过程的执行顺序(310)；获取量子芯片的结构数据，结构数据用于指示量子芯片包括的N个量子比特，N为大于1的整数(320)；根据校准模板和结构数据，生成量子芯片的量子比特校准图，量子比特校准图用于图形化表示针对N个量子比特的校准任务(330)。上述方法实现了量子芯片的量子比特校准图的自动化生成，提高了量子比特的校准效率。

Description

量子比特校准图的生成方法、装置、设备及存储介质
本申请要求于2024年06月06日提交的申请号为202410733831.3、发明名称为“量子比特校准图的生成方法、装置、设备及存储介质”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请实施例涉及量子技术领域，特别涉及一种量子比特校准图的生成方法、装置、设备及存储介质。
背景技术
量子芯片是量子计算机的中央处理器(Central Processing Unit，CPU)，要使量子计算机高效、稳定地运行，需要校准量子芯片中的量子比特来维持对量子比特量子态的精准控制。
相关技术中，普遍使用量子比特校准图来表示并驱动针对量子芯片中的量子比特的校准任务。
目前，量子芯片的量子比特校准图是人工定义的，当量子芯片的规模发生改变时，还需要人工调整上述量子比特校准图的结构。因此，量子比特的校准效率较低。
发明内容
本申请实施例提供了一种量子比特校准图的生成方法、装置、设备及存储介质，能够提高量子比特的校准效率。本申请实施例提供的技术方案如下：
根据本申请实施例的一个方面，提供了一种量子比特校准图的生成方法，所述方法由计算机设备执行，所述方法包括：
获取校准模板，所述校准模板包括至少两个模板节点和至少一条第一有向边，所述模板节点用于表征针对量子比特的一种校准过程，所述第一有向边用于指示所述第一有向边连接的两个模板节点所分别表征的校准过程的执行顺序；
获取量子芯片的结构数据，所述结构数据用于指示所述量子芯片包括的N个量子比特，N为大于1的整数；
根据所述校准模板和所述结构数据，生成所述量子芯片的量子比特校准图，所述量子比特校准图用于图形化表示针对所述N个量子比特的校准任务。
根据本申请实施例的一个方面，提供了一种量子比特校准图的生成装置，所述装置包括：
获取模块，用于获取校准模板，所述校准模板包括至少两个模板节点和至少一条第一有向边，所述模板节点用于表征针对量子比特的一种校准过程，所述第一有向边用于指示所述第一有向边连接的两个模板节点所分别表征的校准过程的执行顺序；
所述获取模块，还用于获取量子芯片的结构数据，所述结构数据用于指示所述量子芯片包括的N个量子比特，N为大于1的整数；
生成模块，用于根据所述校准模板和所述结构数据，生成所述量子芯片的量子比特校准图，所述量子比特校准图用于图形化表示针对所述N个量子比特的校准任务。
根据本申请实施例的一个方面，提供了一种计算机设备，所述计算机设备包括处理器和存储器，所述存储器中存储有计算机程序，所述计算机程序由所述处理器加载并执行以实现上述量子比特校准图的生成方法。
根据本申请实施例的一个方面，提供了一种计算机可读存储介质，所述存储介质中存储有计算机程序，所述计算机程序由处理器加载并执行以实现上述量子比特校准图的生成方法。
根据本申请实施例的一个方面，提供了一种计算机程序产品，所述计算机程序产品包括计算机程序，所述计算机程序存储在计算机可读存储介质中，处理器从所述计算机可读存储介质读取并执行所述计算机程序以实现上述量子比特校准图的生成方法。
本申请实施例提供的技术方案至少包括如下有益效果：
通过根据校准模板和量子芯片的结构数据，生成用于图形化表示针对量子芯片中的N个量子比特的校准任务的量子比特校准图，实现了量子比特校准图的自动化生成。在上述方法中，校准模板中的模板节点表征的是针对量子比特的一种(或者说一类)校准过程，结构数据用于指示量子芯片包括的N个量子比特以及这N个量子比特之间的耦合情况。故通过上述方法，将结构数据和固定的校准模板相结合，无论量子芯片的规模如何改变(如量子芯片包括的量子比特增多，量子芯片中的量子比特间的耦合关系发生改变)，总能较为完备地自动生成符合量子芯片实际结构的量子比特校准图。相比于相关技术中人工定义并调整量子比特校准图，本申请通过自动生成量子比特校准图的方式，不仅提高了量子比特校准图的生成效率，也进一步提高了量子比特的校准效率。
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图1是本申请一个实施例提供的计算机系统的示意图；
图2是本申请一个实施例提供的量子比特校准图的生成方法的示意图；
图3是本申请一个实施例提供的量子比特校准图的生成方法的流程图；
图4是本申请一个实施例提供的校准模板的示意图；
图5是本申请一个实施例提供的量子芯片的拓扑结构图的示意图；
图6是本申请另一个实施例提供的量子芯片的拓扑结构图的示意图；
图7是本申请另一个实施例提供的量子比特校准图的生成方法的流程图；
图8是本申请一个实施例提供的量子芯片的量子比特校准图的示意图；
图9是本申请一个实施例提供的量子比特校准图的生成过程的示意图；
图10是本申请一个实施例提供的量子比特校准图的生成装置的框图；
图11是本申请一个实施例提供的计算机设备的结构框图。
具体实施方式
为使本申请的目的、技术方案和优点更加清楚，下面将结合附图对本申请实施方式作进一步地详细描述。
在对本申请实施例进行介绍说明之前，首先对本申请中涉及的一些名词进行解释说明。以下相关解释作为可选方案与本申请实施例的技术方案可以进行任意结合，其均属于本申请实施例的保护范围。本申请实施例包括以下内容中的至少部分内容。
量子计算(Quantum Computation)：基于量子逻辑，利用量子态的叠加和纠缠等性质快速完成计算任务的一种计算方式。量子计算存储数据的基本单位是量子比特。
量子比特(Qubit)：量子信息的承载形式，也是量子计算的基本单元。经典计算机使用0和1作为二进制计算的基本单元。量子比特与其不同的是，其状态由计算基态(0态或1态)的线性组合描述，通常被称为叠加态。
量子操作(Quantum Operation)：操纵量子比特，从而对量子比特承载的量子信息作出处理的操作。常见的量子操作有泡利X、Y、Z变换(或写作σx、σy、σz)，哈达玛变换(H)，受控泡利X变换等。量子操作包括针对单个量子比特的单比特操作和针对多个相耦合的量子比特的多比特操作。
量子芯片(Quantum Chip)：一种基于量子力学原理的芯片，是量子计算机的中央处理器，不同规模的量子芯片中具有不同数量的量子比特。
量子比特校准(Qubit Calibration)：量子计算机的存储与计算都由量子比特进行，量子比特是一种存算一体的结构，其数据存储和运算控制都需要基于对量子态的精准控制，量子比特校准即对该控制过程的标准化。经过校准的量子比特可以在一段时间内维持一定精准范围内的精准控制。
量子比特校准图：量子比特为了满足可以形式计算的需要，会经历一系列基于物理模型的校准程序，通常会经历量子器件的工作频率搜寻、孤立量子比特的量子态和量子门的标定、多比特门的协同标定等一系列物理参数的标定和设置环节，可以抽象为一种包含至少两个校准节点的有向图结构，称为量子比特校准图。量子比特校准图可指示各个校准节点的依赖关系，并驱动量子比特校准过程。
有向无环图(Directed Acyclic Graph，DAG)：由有限个节点和有向边组成，从任意节点出发，经过若干条有向边，都无法回到该节点，满足上述条件的图，即为有向无环图。
校准自动化：量子比特的校准过程涉及与多个量子器件相关的、多组有依赖关系的、可以定义为量子比特校准图的校准过程，这些校准过程对应的校准节点都涉及复杂的微波控制。并且，相应的控制参数存在高维度、多依赖和随时漂移的特征，将对这些参数的控制过程自动化就意味着校准自动化。
请参考图1，其示出了本申请一个实施例提供的计算机系统的示意图。该计算机系统包括：第一设备11、第二设备12、控制设备13和量子计算器件14。
量子计算器件14为量子芯片或包含量子芯片的量子计算机。
第一设备11和第二设备12为经典计算机。第一设备11和第二设备12可以为同一计算机设备，也可为不同计算机设备。在一些实施例中，第一设备11执行量子比特校准图的生成任务，并且，第一设备11将针对量子计算器件14生成的量子比特校准图发送至第二设备12。在一些实施例中，第二设备12用于对控制设备13进行控制，例如第二设备12根据量子比特校准图，按顺序向控制设备13发送指示不同量子比特校准过程的指令。第二设备12和控制设备13之间可以通过网络进行通信，如无线或有线网络。
控制设备13包括一系列用于控制量子计算器件14的模拟控制器。例如，在量子计算器件14为超导量子芯片的情况下，控制设备13通过控制量子计算器件14所处环境的温度以控制量子计算器件14中的量子比特。在一些实施例中，控制设备13根据第二设备12发送的指令，对量子计算器件14中的量子比特执行校准。
在下述方法实施例中，为了便于说明，仅以各步骤的执行主体为计算机设备作介绍说明。例如，该计算机设备可以为上文计算机系统中的第一设备11，也可以为第二设备12，还可以为控制设备13，本申请对此不作限定。
请参考图2，其示出了本申请一个实施例提供的量子比特校准图的生成方法的示意图。
在该实施例中，基于校准模板21和量子芯片的拓扑结构图22等两张图结构，生成量子芯片的量子比特校准图23。其中，校准模板21包括至少两个模板节点和至少一条第一有向边，模板节点用于表征针对量子比特的一种校准过程，第一有向边用于指示第一有向边连接的两个模板节点所分别表征的校准过程的执行顺序。量子芯片的拓扑结构图22包括N个拓扑节点，拓扑结构图中的每个拓扑节点用于表征量子芯片中的一个量子比特，这些拓扑节点之间的连接关系即能够指示量子比特间的耦合关系。
本申请实施例提供的技术方案，可以实现将量子芯片设计人员和量子芯片校准人员的工作分离，即由量子芯片设计人员设计量子芯片的拓扑结构图，由量子芯片校准人员设计校准模板。并且，以“图套图”的方式，通过将拓扑结构图和校准模板相组合，即可实现量子比特校准图的自动化生成，提高了量子芯片的研发效率。
请参考图3，其示出了本申请一个实施例提供的量子比特校准图的生成方法的流程图。该方法各步骤的执行主体是计算机设备。该方法包括如下步骤310～330中的至少一个步骤。
步骤310，获取校准模板，校准模板包括至少两个模板节点和至少一条第一有向边，模板节点用于表征针对量子比特的一种校准过程，第一有向边用于指示第一有向边连接的两个模板节点所分别表征的校准过程的执行顺序。
本申请实施例中提及的量子比特是指具有物理结构的物理量子比特。例如，量子比特为包含约瑟夫森结(Josephson junction)的超导量子比特。
针对量子比特的校准过程用于校准量子比特的参数。量子比特的参数是指与量子比特有关的参数。在一些实施例中，量子比特的参数包括以下至少之一：描述量子比特物理特性的参数、针对量子比特的量子操作的参数。示例性地，描述量子比特物理特性的参数包括量子比特的读取频率，量子比特的位置，量子比特的读取功率，量子比特的相干时间(包括自旋弛豫时间t1和退相干时间t2)等。量子操作的参数包括量子门的参数，量子门包括用于实现单比特操作的单量子比特门和用于实现多比特操作的多量子比特门。量子操作的参数包括单比特操作的参数(包括单量子比特门的参数)和多比特操作的参数(包括多量子比特门的参数)。
在一些实施例中，校准模板是指用于实现针对量子比特的校准过程的模板。该校准模板不仅体现所执行的是何种校准过程，还体现校准过程之间的执行顺序。在一些实施例中，校准模板中包括针对量子比特的至少一种校准过程，以及不同种类的校准过程之间的执行顺序。示例性地，用一个模板节点来表征针对量子比特的一种校准过程，用连接两个不同的模板节点的带方向的边(也即第一有向边)来指示这两个不同的模板节点所分别表示的校准过程之间的执行顺序。在一些实施例中，如图4所示，是本申请一个实施例提供的校准模板的示意图。其中，A、B、C、D为不同的模板节点，分别对应不同种类的校准过程，边ab、边ac、边bd、边cd是不同的第一有向边，分别用于指示不同种类的校准过程的执行顺序。示例性地，如图4所示，针对量子比特，先执行模板节点A所表示的一种校准过程，再执行模板节点B和C所分别表示的校准过程(这两种校准过程可以并行执行，也可以不并行执行)。在执行完模板节点B所表示的校准过程之后，再执行模板节点D所分别表示的校准过程，或者，在执行完模板节点C所表示的校准过程之后，再执行模板节点D所分别表示的校准过程。
在一些实施例中，模板节点用于表征针对量子比特的一种校准过程，不同的模板节点表征不同的针对量子比特的校准过程。如图4所示，A、B、C、D为不同的模板节点，分别对应不同种类的校准过程。
在一些实施例中，第一有向边用于指示第一有向边连接的两个模板节点所分别表征的校准过程的执行顺序。在一些实施例中，第一有向边是带有方向的连接两个模板节点的边。示例性地，如图4所示，第一有向边ab是连接模板节点A和模板节点B，且从模板节点A指向模板节点的边。示例性地，该第一有向边ab指示先执行模板节点A所对应的校准过程，再执行模板节点B所对应的校准过程。
在一些实施例中，模板节点为单模板节点或耦合模板节点，单模板节点用于表征针对单个量子比特的一种校准过程，耦合模板节点用于表征针对存在耦合关系的Q个量子比特的一种校准过程，Q为大于1的整数。
在一些实施例中，单模板节点是指模板节点所表征的一种校准过程只针对一个量子比特，当然，该量子比特可以是与其他量子比特不存在耦合关系的量子比特(孤立量子比特)，也可以是与其他量子比特存在耦合关系的量子比特。在一些实施例中，耦合模板节点是指模板节点所表征的一种校准过程针对存在耦合关系的至少两个量子比特。如图4所示，模板节点A和模板节点B为两个单模板节点，模板节点C和模板节点D为两个耦合模板节点。
针对单个量子比特的校准过程用于校准单个量子比特的参数。
在一些实施例中，单个量子比特的参数包括上述描述量子比特物理特性的参数，和单比特操作的参数(如泡利X、Y、Z变换的参数)。
在一些实施例中，针对Q个量子比特的校准过程用于校准针对Q个量子比特的多比特操作(如受控泡利X、Y、Z变换)的参数。
需要说明的是，模板节点所表征的校准过程具有泛用性，并不针对某一个或某几个量子比特。例如，单模板节点所表征的校准过程适用于量子芯片中全部的量子比特，即单模板节点所表征的校准过程能够用于校准量子芯片中各个量子比特分别对应的某些参数(如各个量子比特分别对应的泡利X变换的参数)。又例如，若某个耦合模板节点用于表征针对存在耦合关系的两个量子比特的一种校准过程，则该耦合模板节点所表征的校准过程适用于量子芯片中全部的双量子比特组，双量子比特组中包括量子芯片中相耦合的两个量子比特，即耦合模板节点所表征的校准过程能够用于校准量子芯片中分别针对各个双量子比特组的双比特操作的某些参数(如分别针对各个双量子比特组的受控泡利X变换，即受控非(C-Not)门的参数)。因此，在本申请实施例中，将模板节点所表征的校准过程称为“一种”校准过程。
在一些实施例中，耦合模板节点用于表征针对存在耦合关系的两个量子比特的一种校准过程。
在一些实施例中，校准模板表示为有向无环图的形式。
示例性地，请参考图4，其示出了本申请一个实施例提供的校准模板的示意图。在该校准模板中，包括模板节点A、B、C、D，以及，第一有向边ab、ac、bd、cd。其中，模板节点A和B分别用于表征针对单个量子比特的一种校准过程，故模板节点A和B均为单模板节点，模板节点C和D分别用于表征针对存在耦合关系的两个量子比特的一种校准过程，故模板节点C和D均为耦合模板节点。第一有向边ab指示先执行模板节点A所表征的校准过程，再执行模板节点B所表征的校准过程。第一有向边ac指示先执行模板节点A所表征的校准过程，再执行模板节点C所表征的校准过程。第一有向边bd指示先执行模板节点B所表征的校准过程，再执行模板节点D所表征的校准过程。第一有向边cd指示先执行模板节点C所表征的校准过程，再执行模板节点D所表征的校准过程。
在一些实施例中，通过如下代码构建校准模板：
步骤320，获取量子芯片的结构数据，结构数据用于指示量子芯片包括的N个量子比特，N为大于1的整数。
上述量子芯片可以为包含超导量子比特的超导量子芯片，也可以为半导体量子芯片、光量子芯片等，本申请对此不作限定。
在一些实施例中，结构数据用于指示量子芯片包括的N个量子比特。示例性地，从结构数据中可以得知量子芯片所包括的N个量子比特，该N个量子比特可以是量子芯片上全部的量子比特，也可以是量子芯片上全部的量子比特中的一部分量子比特。如图5所示，是结构数据的示意图。示例性地，该结构数据指示了存在四个不同的量子比特q1、q2、q3以及q4。
在一些实施例中，结构数据除了用于指示量子芯片包括的N个量子比特之外，还用于指示N个量子比特之间的耦合情况。在一些实施例中，结构数据用于指示N个量子比特中，存在耦合关系的量子比特，以及，不与其他任何量子比特耦合的孤立量子比特。示例性地，如图5所示，量子比特q1、q2之间的黑边，用于指示这两个量子比特之间存在耦合关系、量子比特q2、q4之间的黑边，用于指示这两个量子比特之间存在耦合关系、量子比特q3、q4之间的黑边，用于指示这两个量子比特之间存在耦合关系、量子比特q1、q3之间的黑边，用于指示这两个量子比特之间存在耦合关系。示例性地，如图5所示的结构数据中，不存在孤立量子比特。示例性地，如图6所示的结构数据中，存在孤立量子比特q5。
在一些实施例中，量子芯片的结构数据表示为拓扑结构图的形式。
示例性地，请参考图5，其示出了本申请一个实施例提供的量子芯片的拓扑结构图的示意图。该拓扑结构图指示量子芯片中包含q1、q2、q3和q4等四个量子比特，以及，指示q1和q2存在耦合关系、q1和q3存在耦合关系、q2和q4存在耦合关系、q3和q4存在耦合关系。
在一些实施例中，至少两个量子比特存在耦合关系是指至少两个量子比特在量子芯片中直接连接。在一些实施例中，至少两个量子比特存在耦合关系是指至少两个量子比特通过量子芯片中除量子比特外的其他器件(如电容和电感)相连接。
需要说明的是，在本申请实施例中，将不通过其他量子比特而耦合的至少两个量子比特称为存在耦合关系的至少两个量子比特。例如，在图5中，q2和q3均与q1存在耦合关系，但q2和q3不存在耦合关系。
另外，还需说明的是，在图5中，量子比特两两耦合，此仅为量子比特之间的耦合情况的示例，在实际的量子芯片中，可以存在孤立量子比特，也可以存在更多量子比特相耦合的情况(如三量子比特门)。示例性地，请参考图6，其示出了本申请另一个实施例提供的量子芯片的拓扑结构图的示意图。相较图5，图6示出的拓扑结构图还指示了孤立量子比特q5，以及，还指示了q1、q3和q4存在耦合关系。
在一些实施例中，通过如下代码构建量子芯片的拓扑结构图：
步骤330，根据校准模板和结构数据，生成量子芯片的量子比特校准图，量子比特校准图用于图形化表示针对N个量子比特的校准任务。
针对N个量子比特的校准任务包含针对N个量子比特中的至少一个量子比特的多个校准过程，也即针对N个量子比特的校准任务可以拆分成多个局部的校准过程，每一个局部的校准过程可以表示为量子比特校准图中的一个校准节点。
在一些实施例中，图形化表示针对N个量子比特的校准任务可以理解为采用图形的形式，来表征针对N个量子比特的校准任务，使得对于N个量子比特的校准任务的执行先后顺序以及不同的校准任务所校准的量子比特，有着清晰直观的感知。
在一些实施例中，量子比特校准图包括至少两个校准节点和至少一条第二有向边。在一些实施例中，校准节点用于表征针对N个量子比特中的至少一个量子比特的一个校准过程。示例性地，如图8所示，校准节点A(q1)表示针对量子比特q1执行模板节点A所表征的校准过程、校准节点B(q1)表示针对量子比特q1执行模板节点B所表征的校准过程。在一些实施例中，第二有向边用于指示第二有向边连接的两个校准节点所分别表征的校准过程的执行顺序。示例性地，如图8所示，连接校准节点A(q1)和校准节点B(q1)，并从校准节点A(q1)指向校准节点B(q1)的边为第二有向边。该第二有向边用于指示先针对量子比特q1执行模板节点A所表征的校准过程，再针对量子比特q1执行模板节点B所表征的校准过程。
需要说明的是，每个校准节点与量子芯片中的量子比特是具有对应关系的，即校准节点所表征的校准过程是针对量子芯片中的某一个或某几个量子比特实际所需执行的校准过程。因此，在本申请实施例中，将校准节点所表征的校准过程称为“一个”校准过程。
在一些实施例中，将量子芯片的校准任务分第一阶段和第二阶段两个阶段执行，并且，为第一阶段和第二阶段分别生成对应的量子比特校准图。在第一阶段中，针对量子芯片中的各个量子比特分别执行校准过程，相应地，第一阶段所采用的校准模板仅包括单模板节点，如仅包括图4中的模板节点A和B，第一阶段对应的量子比特校准图用于图形化表示针对N个量子比特分别执行的校准过程。在第二阶段中，分别针对量子芯片中的各个量子比特组执行校准过程，量子比特组包括存在耦合关系的Q个量子比特(Q可以为任意大于1的整数)，相应地，第二阶段所采用的校准模板仅包括耦合模板节点，如仅包括图4中的模板节点C和D，第二阶段对应的量子比特校准图用于图形化表示针对N个量子比特所包括的各个量子比特组分别执行的校准过程。
本申请实施例提供的技术方案，通过根据校准模板和量子芯片的结构数据，生成用于图形化表示针对量子芯片中的N个量子比特的校准任务的量子比特校准图，实现了量子比特校准图的自动化生成。在上述方法中，校准模板中的模板节点表征的是针对量子比特的一种，或者说一类校准过程，结构数据用于指示量子芯片包括的N个量子比特以及这N个量子比特之间的耦合情况。故通过上述方法，将结构数据和固定的校准模板相结合，无论量子芯片的规模如何改变(如量子芯片包括的量子比特增多，量子芯片中的量子比特间的耦合关系发生改变)，总能较为完备地自动生成符合量子芯片实际结构的量子比特校准图，提高了量子比特校准图的生成效率，提高了量子比特的校准效率。
在下述实施例中，将对根据校准模板和结构数据，生成量子比特校准图的具体方法作介绍说明。
在一些实施例中，请参考图7，步骤330包括如下子步骤332～334中的至少一个子步骤。
子步骤332，根据结构数据，将模板节点展开为量子比特校准图中的至少一个校准节点，校准节点用于表征针对N个量子比特中的至少一个量子比特的一个校准过程。
在一些实施例中，本申请实施例中的展开也可以理解为分裂，将一个模板节点分裂成至少一个校准节点。在一些实施例中，从一个模板节点所展开得到的至少一个校准节点，也可以认为是从该模板节点分裂出的至少一个校准节点。在一些实施例中，结构数据指示了量子芯片上N个量子比特。在一些实施例中，在从结构数据中确定了量子芯片上的N个量子比特之后，校准模板中存在至少两个模板节点，每个模板节点所校准的量子比特的数量相同或者不同，从而实现对于N个量子比特的校准。
示例性地，当至少两个模板节点中的第i个模板节点所表征的校准过程针对量子芯片上的每个量子比特的情况下，将第i个模板节点展开为N个校准节点，每个校准节点用于对N个量子比特中的一个量子比特执行第i个模板节点所表征的校准过程，i为正整数。
示例性地，当至少两个模板节点中的第i个模板节点所表征的校准过程针对量子芯片上的满足第一关系的至少两个量子比特的情况下，将第i个模板节点展开为M个校准节点，每个校准节点用于对N个量子比特中的一个量子比特组执行第i个模板节点所表征的校准过程，i为正整数。其中，一个量子比特组中包括满足第一关系的至少两个量子比特。在一些实施例中，量子芯片上的N个量子比特中存在M个量子比特组。在一些实施例中，第一关系包括耦合关系、位置关系、距离关系等等中的至少之一。在一些实施例中，结构数据还指示了N个量子比特中存在关系的量子比特。示例性地，该关系包括耦合关系、位置关系、距离关系等等中的至少之一。示例性地，直接从结构数据中确定存在关系的量子比特，并判定该关系是否是上述第一关系。在该关系是上述第一关系的情况下，将满足第一关系的至少两个量子比特作为一个量子比特组，并对于一个量子比特组执行第i个模板节点所表征的校准过程。
示例性地，量子芯片上的N个量子比特可能存在有量子比特没有被校准模板中的任意一个模板节点所表征的校准过程所校准。当然，量子芯片上的N个量子比特可能存在有量子比特被校准模板中的多个模板节点所表征的校准过程而校准多次。
需要说明的是，由某个模板节点展开而来的校准节点所表征的校准过程与该模板节点所表征的校准过程是相对应的。示例性地，若模板节点j为单模板节点，校准节点k是由模板节点j展开得到的，则校准节点k可以用于表征针对N个量子比特中的某一量子比特执行模板节点j所表征的校准过程。也就是说，校准节点用于表征针对N个量子比特中的至少一个量子比特执行与该校准节点对应的模板节点所表征的校准过程。本申请实施例中对于校准模板中的每个模板节点以及每条有向边都分别需要根据结构数据而展开。
在一些实施例中，校准节点为单校准节点或耦合校准节点，单校准节点用于表征针对N个量子比特中的一个量子比特的一个校准过程，耦合校准节点用于表征针对N个量子比特中的存在耦合关系的多个量子比特的一个校准过程。
在一些实施例中，耦合校准节点用于表征针对N个量子比特中的存在耦合关系的两个量子比特的一个校准过程。
在一些实施例中，子步骤332包括以下步骤至少之一：
1、在模版节点为单模板节点的情况下，根据结构数据，将单模板节点展开为量子比特校准图中的N个单校准节点。
在一些实施例中，在模版节点为单模板节点，根据结构数据所指示的量子芯片的N个量子比特中的每个量子比特，分别展开该模板节点，得到N个单校准节点，每个单校准节点用于指示对于一个量子比特的一个校准过程。
具体来说，当至少两个模板节点中的第i个模板节点为单模板节点的情况下，将第i个模板节点展开为N个校准节点，每个校准节点用于对N个量子比特中的一个量子比特执行第i个模板节点所表征的校准过程，N个量子比特对应N个校准节点。此时，该校准节点也称为单校准节点，表征该校准节点所校准的量子比特的数量为1。
示例性地，对于至少两个模板节点中的每个模板节点，判断其是否属于单模板节点。在其属于单模板节点的情况下，每存在一个单模板节点，就将该单模板节点展开为与N个量子比特中的每个量子比特所分别对应的单校准节点，从而得到N个单校准节点。示例性地，由同一个单模板节点所展开得到的N个单校准节点，对应的校准过程相同，但是所校准的量子比特不同。
请参考图8，其示出了本申请一个实施例提供的量子芯片的量子比特校准图的示意图。
示例性地，根据图5示出的量子芯片的拓扑结构图，可知N＝4，故可将图4示出的单模板节点A展开为图8中的单校准节点A(q1)、A(q2)、A(q3)和A(q4)，以A(q1)为例，A(q1)表示针对量子比特q1执行单模板节点A表征的校准过程；可将图4示出的单模板节点B展开为图8中的单校准节点B(q1)、B(q2)、B(q3)和B(q4)，以B(q1)为例，B(q1)表示针对量子比特q1执行单模板节点B表征的校准过程。
2、在模版节点为耦合模板节点的情况下，根据结构数据，将耦合模板节点展开为量子比特校准图中的M个耦合校准节点，其中，M为N个量子比特中包含的量子比特组的数量，M为正整数，量子比特组包括存在耦合关系的Q个量子比特。
在一些实施例中，在模版节点为耦合模板节点的情况下，根据结构数据所指示的量子芯片的N个量子比特中的存在耦合关系的量子比特，分别展开该模板节点，得到M个耦合校准节点，每个耦合校准节点用于指示对于一组存在耦合关系的量子比特的一个校准过程。
具体来说，当至少两个模板节点中的第i个模板节点为耦合模板节点的情况下，将第i个模板节点展开为M个校准节点，每个校准节点用于对N个量子比特中的一个量子比特组执行第i个模板节点所表征的校准过程，i为正整数。其中，一个量子比特组中包括满足耦合关系的至少两个量子比特。在一些实施例中，量子芯片上的N个量子比特中存在M个量子比特组。在一些实施例中，上述第一关系为这里的耦合关系。在一些实施例中，结构数据还指示了N个量子比特中存在关系的量子比特。示例性地，该关系包括耦合关系。示例性地，直接从结构数据中确定存在关系的量子比特，并判定该关系是否为耦合关系。在该关系是耦合关系的情况下，将满足耦合关系的至少两个量子比特作为一个量子比特组，并对于一个量子比特组执行第i个模板节点所表征的校准过程。每个校准节点用于对N个量子比特中的一个量子比特组执行第i个模板节点所表征的校准过程，M个量子比特组对应M个校准节点。此时，该校准节点也称为耦合校准节点，该校准节点所校准的量子比特的数量为存在耦合关系的一个量子比特组中的量子比特的数量。
示例性地，对于至少两个模板节点中的每个模板节点，判断其是否属于耦合模板节点。在其属于耦合模板节点的情况下，每存在一个耦合模板节点，就获取N个量子比特中的M个量子比特组，将该耦合模板节点展开为与M个量子比特组中的每个量子比特组所分别对应的耦合校准节点，从而得到M个耦合校准节点。示例性地，由同一个耦合模板节点所展开得到的M个耦合校准节点，对应的校准过程相同，但是所校准的量子比特组不同。
示例性地，图4中的模板节点C和模板节点D均为耦合模板节点(Q＝2)。根据图5示出的量子芯片的拓扑结构图，又知4个量子比特中包含的量子比特组的数量为4，分别为包括q1和q2的量子比特组c1_2、包括q1和q3量子比特组c1_3、包括q2和q4的量子比特组c2_4、包括q3和q4的量子比特组c3_4。故可将图4示出的耦合模板节点C展开为图8中的耦合校准节点C(c1_2)、C(c1_3)、C(c2_4)和C(c3_4)，以C(c1_2)为例，C(c1_2)表示针对量子比特q1和q2执行耦合模板节点C表征的校准过程；可将图4示出的耦合模板节点D展开为图8中的耦合校准节点D(c1_2)、D(c1_3)、D(c2_4)和D(c3_4)，以D(c1_2)为例，D(c1_2)表示针对量子比特q1和q2执行耦合模板节点D表征的校准过程。
在上文实施例中，将单模板节点展开为单校准节点，将耦合模板节点展开为耦合校准节点，使得生成的量子比特校准图既能用于针对量子芯片执行单量子比特校准任务，也能用于针对量子芯片中相耦合的量子比特执行多量子比特校准任务，保障了量子比特校准图的完备性。
在一些实施例中，子步骤332包括：在模板节点为目标模板节点的情况下，根据结构数据，将该目标模板节点展开为至少两个通过第三有向边相连接的校准节点。目标模板节点所表征的校准过程在作用于不同量子比特时，受量子比特间的耦合关系影响。
在一些实施例中，目标模板节点所表征的校准过程在作用于不同量子比特时，受量子比特间的耦合关系影响是指目标模板节点所表征的校准过程针对不同量子比特(不同的单量子比特或不同的量子比特组)的执行顺序受量子比特间的耦合关系影响。
示例性地，目标模板节点所表征的校准过程用于校准量子比特的时序参数，时序参数是与量子芯片的工作时序有关的参数，对时序参数的校准需要根据量子比特间的耦合关系。考虑针对量子芯片中的不同量子比特或不同量子比特组的执行顺序，因此，上述目标模板节点所表征的校准过程受量子比特间的耦合关系影响。
示例性地，目标模板节点所表征的校准过程用于校准量子比特的串扰参数，串扰参数用于描述由于量子芯片中的量子比特耦合而形成的噪声，针对串扰参数的校准同样需要根据量子比特间的耦合关系，考虑针对量子芯片中的不同量子比特或不同量子比特组的执行顺序，因此，上述目标模板节点所表征的校准过程受量子比特间的耦合关系影响。
第三有向边用于指示第三有向边连接的两个校准节点所分别表征的校准过程无法并行执行。
示例性地，请参考图8，连接B(q1)和B(q2)的第三有向边用于指示B(q1)和B(q2)所分别表征的校准过程无法并行执行，连接B(q1)和B(q3)的第三有向边用于指示B(q1)和B(q3)所分别表征的校准过程无法并行执行，连接B(q3)和B(q4)的第三有向边用于指示B(q3)和B(q4)所分别表征的校准过程无法并行执行。在一些实施例中，如图8所示，连接B(q1)和B(q2)的第三有向边不仅用于指示B(q1)和B(q2)所分别表征的校准过程无法并行执行，还可以指示先执行B(q1)所表征的校准过程、再执行B(q2)所表征的校准过程，也即第三有向边用于指示第三有向边连接的两个校准节点所分别表征的校准过程串行执行。
在上文实施例中，将目标模板节点展开为多个通过第三有向边相连接的校准节点，从而在最终生成的量子比特校准图中，限定了由目标模板节点展开而来的部分校准节点无法并行执行，为目标模板节点所表征的校准过程设置了并行执行的约束，保障了根据量子比特校准图执行校准任务的正确性。
在一些实施例中，上述目标模板节点为单模板节点或耦合模板节点。
在一些实施例中，在目标模板节点为单模板节点的情况下，第三有向边连接的两个校准节点分别对应的量子比特存在耦合关系。
示例性地，请参考图8，B(q1)和B(q2)所分别对应的量子比特q1和q2存在如图4所示的耦合关系，B(q1)和B(q3)所分别对应的量子比特q1和q3存在如图4所示的耦合关系，B(q3)和B(q4)所分别对应的量子比特q3和q4存在如图4所示的耦合关系。
在一些实施例中，在目标模板节点为耦合模板节点的情况下，第三有向边连接的两个校准节点分别对应的Q个量子比特包含同一量子比特。
示例性地，第三有向边连接的一个校准节点对应图4中的q1和q2，第三有向边连接的另一个校准节点对应图4中的q1和q3。
在一些实施例中，根据结构数据，通过树搜索方法将目标模板节点展开为多个通过第三有向边相连接的校准节点。
在一些实施例中，树搜索方法包括BFS(Breath First Search，广度优先搜索)和DFS(Deep First Search，深度优先搜索)。
示例性地，对于图4示出的模板节点B，若根据图5示出的拓扑结构图，对其使用BFS方法，即可展开为图8中通过第三有向边连接的B(q1)、B(q2)、B(q3)和B(q4)，第三有向边指示的顺序即为BFS方法的搜索顺序，在该示例中，以拓扑结构图中的量子比特q1为BFS的起始搜索点，生成B(q1)，而后再按广度优先的原则，搜索与q1耦合的q2和q3，生成B(q2)和B(q3)。最后，再从q3搜索到q4，生成B(q4)。作为树搜索算法的起始搜索点的量子比特由技术人员按需设定，本申请对此不作限定。
在上文实施例中，第三有向边连接的两个校准节点分别对应的量子比特存在耦合关系，或者，第三有向边连接的两个校准节点分别对应的多个量子比特包含同一量子比特。即第三有向边连接的两个校准节点分别对应的量子比特存在物理上的直接关联关系，故通过上述方法，能够使得目标模板节点所表征的校准过程，在作用于量子芯片中的这些物理距离较为接近的量子比特(或量子比特组)时，被分开执行，可以避免由于同时针对相耦合的量子比特(或包含同一量子比特的两个量子比特组)执行标模板节点所表征的校准过程而导致校准结果出现偏差。
在一些实施例中，通过以下代码针对校准模板中的模板节点是针对单量子比特还是针对存在耦合关系的多个量子比特，以及，模板节点的展开方法：

子步骤334，将第一有向边展开为量子比特校准图中的至少一条第二有向边，第二有向边用于指示第二有向边连接的两个校准节点所分别表征的校准过程的执行顺序。
在一些实施例中，本申请实施例中的展开也可以理解为分裂，将一条第一有向边分裂成至少一条第二有向边。在一些实施例中，从一条第一有向边所展开得到的至少一条第二有向边，也可以认为是从该第一有向边分裂出的至少一条第二有向边。
在一些实施例中，每一条第二有向边均连接两个校准节点以生成量子比特校准图。
需要说明的是，由第二有向边所连接的两个校准节点与该第二有向边对应的第一有向边连接的两个模板节点是相对应的。示例性地，若第二有向边t由第一有向边r展开得到，第一有向边r连接的两个模板节点分别为模板节点j和模板节点k，则第二有向边t连接的两个校准节点分别由模板节点j和模板节点k展开得到。
另外，还需说明的是，第二有向边的方向与该第二有向边对应的第一有向边的方向也是相对应的。示例性地，若第二有向边t由第一有向边r展开得到，第一有向边r连接的两个模板节点分别为模板节点j和模板节点k，且第一有向边r从模板节点j指向模板节点k，则第二有向边t从由模板节点j展开得到的校准节点指向由模板节点k展开得到的校准节点。
在一些实施例中，子步骤334包括以下步骤至少之一：
1、在第一有向边连接的两个模板节点均为单模板节点的情况下，将第一有向边展开为量子比特校准图中的N条第二有向边，N条第二有向边中的每一条第二有向边连接与N个量子比特中同一量子比特对应的两个单校准节点。
两个单校准节点与N个量子比特中同一量子比特对应是指两个单校准节点分别表征的校准过程所针对的量子比特均为该量子比特。
示例性地，若第一有向边为图4中的ab，则可将第一有向边ab展开为图8中连接A(q1)和B(q1)、连接A(q2)和B(q2)、连接A(q3)和B(q3)、连接A(q4)和B(q4)的共4条第二有向边(由于A和B均被展开为了4个校准节点，故已知N＝4)，以连接A(q1)和B(q1)的第二有向边为例，该第二有向边连接的A(q1)和B(q1)均与图5中的量子比特q1相对应。
2、在第一有向边连接的两个模板节点分别为一个单模板节点和一个耦合模板节点的情况下，将第一有向边展开为量子比特校准图中的M×Q条第二有向边，M×Q条第二有向边中的每一条第二有向边连接与N个量子比特中同一量子比特对应的一个单校准节点和一个耦合校准节点。
单校准节点和耦合校准节点与N个量子比特中同一量子比特对应是指两个校准节点分别表征的校准过程所针对的量子比特均包含该量子比特。
示例性地，若第一有向边为图4中的ac(耦合模板节点C针对两个量子比特，Q＝2)，则可将第一有向边ac展开为图8中连接A(q1)和C(c1_2)、连接A(q1)和C(c1_3)、连接A(q2)和C(c1_2)、连接A(q2)和C(c2_4)、连接A(q3)和C(c1_3)、连接A(q3)和C(c3_4)、连接A(q4)和C(c3_4)、连接A(q4)和C(c2_4)的共8条第二有向边(由于耦合模板节点C被展开为了4个校准节点，故M＝4)，以连接A(q1)和C(c1_2)的第二有向边为例，该第二有向边连接的A(q1)和C(c1_2)均与图5中的量子比特q1相对应。
示例性地，若第一有向边为图4中的bd(耦合模板节点D针对两个量子比特，Q＝2)，则可将第一有向边bd展开为图8中连接B(q1)和D(c1_2)、连接B(q1)和D(c1_3)、连接B(q2)和D(c1_2)、连接B(q2)和D(c2_4)、连接B(q3)和D(c1_3)、连接B(q3)和D(c3_4)、连接B(q4)和D(c3_4)、连接B(q4)和D(c2_4)的共8条第二有向边(由于耦合模板节点D被展开为了4个校准节点，故M＝4)，以连接B(q1)和D(c1_2)的第二有向边为例，该第二有向边连接的B(q1)和D(c1_2)均与图5中的量子比特q1相对应。
3、在第一有向边连接的两个模板节点分别为第一耦合模板节点和第二耦合模板节点的情况下，将第一有向边展开为量子比特校准图中的P条第二有向边。
第一耦合模板节点用于表征针对存在耦合关系的Q1个量子比特的一种校准过程，第二耦合模板节点用于表征针对存在耦合关系的Q2个量子比特的一种校准过程，Q2为大于1且小于或等于Q1的整数，P为(N个量子比特中)各个第一量子比特组分别包含的第二量子比特组的数量之和，P为正整数。第一量子比特组包括上述N个量子比特中的Q1个存在耦合关系的量子比特，第二量子比特组包括上述N个量子比特中的Q2个存在耦合关系的量子比特，P条第二有向边中的每一条第二有向边连接与N个量子比特中同一第二量子比特组对应的两个耦合校准节点。
两个耦合校准节点与N个量子比特中同一第二量子比特组对应是指两个耦合校准节点分别表征的校准过程所针对的量子比特均包含该第二量子比特组中的量子比特。
示例性地，若第一有向边为图4中的cd，第二耦合模板节点为图4中的C，第一耦合模板节点为图4中的D(由于第二耦合模板节点C和第一耦合模板节点D均针对两个量子比特，故Q1＝Q2＝2)，则可将第一有向边cd展开为图8中连接C(c1_2)和D(c1_2)、连接C(c1_3)和D(c1_3)、连接C(c3_4)和D(c3_4)、连接C(c2_4)和D(c2_4)的共4条第二有向边(由于第一量子比特组和第二量子比特组相同，故P＝M＝4)，以连接C(c1_2)和D(c1_2)的第二有向边为例，该第二有向边连接的C(c1_2)和D(c1_2)均与第二量子比特组c1_2(即图5中的量子比特q1和q2)相对应。
示例性地，请参考图9，其示出了本申请一个实施例提供的量子比特校准图的生成过程的示意图。在图9示出的校准模板91中，第二耦合模板节点E用于表征针对存在耦合关系的两个量子比特的一种校准过程，即Q2＝2，第一耦合模板节点F用于表征针对存在耦合关系的三个量子比特的一种校准过程，即Q1＝3，在拓扑结构图92中，量子芯片包括量子比特q5、q6、q7和q8，其中，q5和q6存在耦合关系、q6和q7存在耦合关系、q7和q8存在耦合关系、q5、q6和q7存在耦合关系、q5、q7和q8存在耦合关系。在相应的量子比特校准图93中，第二耦合模板节点E被展开为了E(c5_6)、E(c6_7)、E(c7_8)共三个耦合校准节点，E(c5_6)表示针对量子比特q5和q6(即第二量子比特组(c5_6))执行第二耦合模板节点E表征的校准过程，E(c6_7)表示针对量子比特q6和q7(即第二量子比特组(c6_7))执行第第二耦合模板节点E表征的校准过程，E(c7_8)表示针对量子比特q7和q8(即第二量子比特组(c7_8))执行第第二耦合模板节点E表征的校准过程。第一耦合模板节点F被展开为了F(c5_6_7)、F(c5_7_8)共两个耦合校准节点，F(c5_6_7)表示针对量子比特q5、q6和q7执行第一耦合模板节点F表征的校准过程，F(c5_7_8)表示针对量子比特q5、q7和q8执行第一耦合模板节点F表征的校准过程。则可将第一有向边ef展开为图9中连接E(c5_6)和F(c5_6_7)、连接E(c6_7)和F(c5_6_7)、连接E(c7_8)和F(c5_7_8)的共3条第二有向边((c5_6_7)包含(c5_6)和(c6_7)，(c5_7_8)包含(c7_8)，即P＝3)。其中，E(c5_6)和F(c5_6_7)对应(c5_6)，E(c6_7)和F(c5_6_7)对应(c6_7)，E(c7_8)和F(c5_7_8)对应E(c7_8)。
在上文实施例的各种情况下，第二有向边所连接的两个校准节点均分别与量子芯片中的同一量子比特或同一量子比特组相对应，故采用上述方法展开得到的各条第二有向边，能够基于量子芯片中的各个量子比特的耦合情况，充分且准确地指示针对量子芯片中的各个量子比特、各个量子比特组执行不同校准过程的顺序。
在一些实施例中，根据结构数据，将校准模板中，每一个模板节点展开为至少一个校准节点，每一条第一有向边展开为至少一条第二有向边，从而得到量子芯片的量子比特校准图。
在上文实施例中，以校准模板为基础，根据量子芯片的结构数据，分别展开校准模板中的模板节点和第一有向边，从而将校准模板展开为了量子芯片的量子比特校准图。采用了倒置展开的方法，不以量子芯片的拓扑结构图为底层结构，而是以相对稳定的校准模板作为底层结构，保证了校准模板中的模板节点所表征的校准过程在作用于量子芯片中的量子比特时的一致性，并且，保证了量子比特校准图的底层结构的稳定性，该底层结构不会随着量子芯片的规模和拓扑结构变化而变化，有利于量子比特校准图的即时生成和优化。
在一些实施例中，通过以下代码生成量子芯片的量子比特校准图：
在一些实施例中，在生成量子比特校准图之后，按量子比特校准图中，各条第二有向边指示的执行顺序，执行各个校准节点分别表征的校准过程。
示例性地，请参考图8，按第二有向边指示的执行顺序，先执行由图4中的模板节点A展开而来的校准节点A(q1)、A(q2)、A(q3)和A(q4)所分别表征的校准过程，再执行由图4中的模板节点B展开而来的校准节点B(q1)、B(q2)、B(q3)和B(q4)所分别表征的校准过程，以及，由图4中的模板节点C展开而来的校准节点C(c1_2)、C(c1_3)、C(c3_4)和C(c2_4)所分别表征的校准过程。最后执行由图4中的模板节点D展开而来的校准节点D(c1_2)、D(c1_3)、D(c3_4)和D(c2_4)所分别表征的校准过程。
在上文实施例中，根据由第一有向边展开得到的第二有向边指示的执行顺序，执行各个校准节点分别表征的校准过程。在实现针对量子芯片的校准任务自动化执行的同时，保障了各个校准过程执行顺序的正确性。
在一些实施例中，量子比特校准图中，J个校准节点所分别表征的校准过程被并行执行，J个校准节点是由同一模板节点展开得到的，J为大于1的整数。
示例性地，请参考图8，由图4中的模板节点A展开而来的校准节点A(q1)、A(q2)、A(q3)和A(q4)所分别表征的校准过程可以被并行执行。由图4中的模板节点C展开而来的校准节点C(c1_2)、C(c1_3)、C(c3_4)和C(c2_4)所分别表征的校准过程可以被并行执行。以及，由图4中的模板节点D展开而来的校准节点D(c1_2)、D(c1_3)、D(c3_4)和D(c2_4)所分别表征的校准过程可以被并行执行。
在上文实施例中，通过设置由同一模板节点展开得到的J个校准节点被并行执行，可以提高针对量子芯片中的N个量子比特执行校准任务的效率，减少校准任务执行过程所需的时间。
在一些实施例中，量子比特校准图中，K个校准节点所分别表征的校准过程被并行执行。
K个校准节点是由同一目标模板节点展开得到的，且K个校准节点相互间隔的第三有向边的数量大于第一阈值。
示例性地，请参考图8，在由图4中的目标模板节点B展开而来的校准节点B(q1)、B(q2)、B(q3)和B(q4)中，B(q1)为最优先执行的校准节点，而B(q2)和B(q3)间隔的第三有向边的数量为2，若第一阈值为1，则B(q2)和B(q3)所分别表征的校准过程被并行执行。若第一阈值大于或等于2，则B(q2)和B(q3)所分别表征的校准过程不能被并行执行。
第一阈值是由技术人员根据目标模板节点所需校准的参数，以及，量子芯片中的各个器件(如量子比特和将量子比特相耦合的器件)的排布，按需求设定的，可以为1、2、3等，本申请对此不作限定。
由上文实施例可知，第三有向边连接的两个校准节点分别对应的量子比特存在物理上的直接关联关系，因此，两个校准节点间隔的第三有向边的数量可以用于表征两个校准节点分别对应的量子比特或量子比特组在量子芯片中的距离，或者说，在量子芯片中相互影响的程度。因此，通过上述方法，设置第一阈值，令由目标模板节点展开而来的校准节点有间隔地并行执行，既保障了校准任务的执行效率，也考虑了量子芯片的实际物理结构与排布，从而保证了执行校准任务的有效性。
下述为本申请装置实施例，可以用于执行本申请方法实施例。对于本申请装置实施例中未披露的细节，请参照本申请方法实施例。
请参考图10，其示出了本申请一个实施例提供的量子比特校准图的生成装置的框图。该装置具有实现上述量子比特校准图的生成方法的功能，所述功能可以由硬件实现，也可以由硬件执行相应的软件实现。该装置可以是计算机设备，也可以设置在计算机设备中。该装置1000可以包括：获取模块1010和生成模块1020。
获取模块1010，用于获取校准模板，所述校准模板包括至少两个模板节点和至少一条第一有向边，所述模板节点用于表征针对量子比特的一种校准过程，所述第一有向边用于指示所述第一有向边连接的两个模板节点所分别表征的校准过程的执行顺序。
获取模块1010，还用于获取量子芯片的结构数据，所述结构数据用于指示所述量子芯片包括的N个量子比特，N为大于1的整数。
生成模块1020，用于根据所述校准模板和所述结构数据，生成所述量子芯片的量子比特校准图，所述量子比特校准图用于图形化表示针对所述N个量子比特的校准任务。
在一些实施例中，所述生成模块1020包括：节点展开子模块、边展开子模块和生成子模块(图10中未示出)。
节点展开子模块，用于根据所述结构数据，将所述模板节点展开为所述量子比特校准图中的至少一个校准节点，所述校准节点用于表征针对所述N个量子比特中的至少一个量子比特的一个校准过程；
边展开子模块，用于将所述第一有向边展开为所述量子比特校准图中的至少一条第二有向边，所述第二有向边用于指示所述第二有向边连接的两个校准节点所分别表征的校准过程的执行顺序。
在一些实施例中，所述模板节点为单模板节点或耦合模板节点，所述单模板节点用于表征针对单个量子比特的一种校准过程，所述耦合模板节点用于表征针对存在耦合关系的Q个量子比特的一种校准过程，所述校准节点为单校准节点或耦合校准节点，所述单校准节点用于表征针对所述N个量子比特中的一个量子比特的一个校准过程，所述耦合校准节点用于表征针对所述N个量子比特中的存在耦合关系的Q个量子比特的一个校准过程，Q为大于1的整数。
节点展开子模块，用于在所述模版节点为所述单模板节点的情况下，根据所述结构数据，将所述单模板节点展开为所述量子比特校准图中的N个单校准节点；在所述模版节点为所述耦合模板节点的情况下，根据所述结构数据，将所述耦合模板节点展开为所述量子比特校准图中的M个耦合校准节点，其中，M为所述N个量子比特中包含的量子比特组的数量，所述M为正整数，所述量子比特组包括存在耦合关系的Q个量子比特。
在一些实施例中，边展开子模块，用于在所述第一有向边连接的两个模板节点均为所述单模板节点的情况下，则将所述第一有向边展开为所述量子比特校准图中的N条第二有向边，N条第二有向边中的每一条第二有向边连接与所述N个量子比特中同一量子比特对应的两个单校准节点；在所述第一有向边连接的两个模板节点分别为所述单模板节点和所述耦合模板节点的情况下，将所述第一有向边展开为所述量子比特校准图中的M×Q条第二有向边，M×Q条第二有向边中的每一条第二有向边连接与所述N个量子比特中同一量子比特对应的单校准节点和耦合校准节点；在所述第一有向边连接的两个模板节点分别为第一耦合模板节点和第二耦合模板节点的情况下，将所述第一有向边展开为所述量子比特校准图中的P条第二有向边，其中，所述第一耦合模板节点用于表征针对存在耦合关系的Q1个量子比特的一种校准过程，所述第二耦合模板节点用于表征针对存在耦合关系的Q2个量子比特的一种校准过程，Q2为大于1且小于或等于Q1的整数，P为各个第一量子比特组分别包含的第二量子比特组的数量之和，P为正整数，所述第一量子比特组包括所述N个量子比特中的存在耦合关系的Q1个量子比特，所述第二量子比特组包括所述N个量子比特中的存在耦合关系的Q2个量子比特，P条所述第二有向边中的每一条第二有向边连接与所述N个量子比特中同一第二量子比特组对应的两个耦合校准节点。
在一些实施例中，节点展开子模块，用于在所述模板节点为目标模板节点的情况下，根据所述结构数据，将所述目标模板节点展开为所述量子比特校准图中的至少两个通过第三有向边相连接的校准节点，所述目标模板节点所表征的校准过程在作用于不同量子比特时，受量子比特间的耦合关系影响，所述第三有向边用于指示所述第三有向边连接的两个校准节点所分别表征的校准过程无法并行执行。
在一些实施例中，所述目标模板节点为单模板节点或耦合模板节点，所述单模板节点用于表征针对单个量子比特的一种校准过程，所述耦合模板节点用于表征针对存在耦合关系的Q个量子比特的一种校准过程，Q为大于1的整数；在所述目标模板节点为所述单模板节点的情况下，所述第三有向边连接的两个校准节点分别对应的量子比特存在耦合关系；在所述目标模板节点为所述耦合模板节点的情况下，所述第三有向边连接的两个校准节点分别对应的Q个量子比特包含同一量子比特。
在一些实施例中，该装置1000还包括：执行模块(图10中未示出)。
执行模块，用于按所述量子比特校准图中，各条所述第二有向边指示的执行顺序，执行各个所述校准节点分别表征的校准过程。
在一些实施例中，J个校准节点所分别表征的校准过程被并行执行，所述J个校准节点是由同一模板节点展开得到的，所述J为大于1的整数。
在一些实施例中，K个校准节点所分别表征的校准过程被并行执行；所述K个校准节点是由同一目标模板节点展开得到的，且所述K个校准节点相互间隔的第三有向边的数量大于第一阈值；其中，所述目标模板节点所表征的校准过程在作用于不同量子比特时，受量子比特间的耦合关系影响，所述第三有向边用于指示所述第三有向边连接的两个校准节点所分别表征的校准过程无法并行执行。
需要说明的是，上述实施例提供的装置，在实现其功能时，仅以上述各功能模块的划分进行举例说明，实际应用中，可以根据需要而将上述功能分配由不同的功能模块完成，即将设备的内部结构划分成不同的功能模块，以完成以上描述的全部或者部分功能。另外，上述实施例提供的装置与方法实施例属于同一构思，其具体实现过程详见方法实施例，这里不再赘述。
请参考图11，其示例性示出了本申请一个实施例提供的计算机设备的结构框图。
通常，计算机设备1100包括有：处理器1101和存储器1102。
处理器1101可以包括一个或多个处理核心，比如4核心处理器、8核心处理器等。处理器1101可以采用DSP(Digital Signal Processing，数字信号处理)、FPGA(Field Programmable Gate Array，现场可编程门阵列)、PLA(Programmable Logic Array，可编程逻辑阵列)中的至少一种硬件形式来实现。处理器1101也可以包括主处理器和协处理器，主处理器是用于对在唤醒状态下的数据进行处理的处理器，也称CPU；协处理器是用于对在待机状态下的数据进行处理的低功耗处理器。在一些实施例中，处理器1101可以在集成有GPU(Graphics Processing Unit，图像处理器)，GPU用于负责显示屏所需要显示的内容的渲染和绘制。一些实施例中，处理器1101还可以包括AI(Artificial Intelligence，人工智能)处理器，该AI处理器用于处理有关机器学习的计算操作。
存储器1102可以包括一个或多个计算机可读存储介质，该计算机可读存储介质可以是有形的和非暂态的。存储器1102还可包括高速随机存取存储器，以及非易失性存储器，比如一个或多个磁盘存储设备、闪存存储设备。在一些实施例中，存储器1102中的非暂态的计算机可读存储介质存储有计算机程序，该计算机程序由处理器1101加载并执行以实现上述量子比特校准图的生成方法。
本领域技术人员可以理解，图11中示出的结构并不构成对计算机设备1100的限定，可以包括比图示更多或更少的组件，或者组合某些组件，或者采用不同的组件布置。
在一些实施例中，还提供了一种芯片产品，所述芯片产品包括可编程逻辑电路和/或计算机程序，当所述芯片产品运行时，用于实现上述量子比特校准图的生成方法。
在一些实施例中，还提供了一种计算机可读存储介质，所述存储介质中存储有计算机程序，所述计算机程序由处理器加载并执行以实现上述量子比特校准图的生成方法。
可选地，该计算机可读存储介质可以包括：ROM(Read-Only Memory，只读存储器)、RAM(Random-Access Memory，随机存储器)、SSD(Solid State Drives，固态硬盘)或光盘等。其中，随机存取记忆体可以包括ReRAM(Resistance Random Access Memory，电阻式随机存取记忆体)和DRAM(Dynamic Random Access Memory，动态随机存取存储器)。
在一些实施例中，还提供了一种计算机程序产品，所述计算机程序产品包括计算机程序，所述计算机程序存储在计算机可读存储介质中，处理器从所述计算机可读存储介质读取并执行所述计算机程序，以实现上述量子比特校准图的生成方法。
应当理解的是，在本文中提及的“多个”是指两个或两个以上。“和/或”，描述关联对象的关联关系，表示可以存在三种关系，例如，A和/或B，可以表示：单独存在A，同时存在A和B，单独存在B这三种情况。字符“/”一般表示前后关联对象是一种“或”的关系。另外，本文中描述的步骤编号，仅示例性示出了步骤间的一种可能的执行先后顺序，在一些其它实施例中，上述步骤也可以不按照编号顺序来执行，如两个不同编号的步骤同时执行，或者两个不同编号的步骤按照与图示相反的顺序执行，本申请实施例对此不作限定。
以上仅为本申请的示例性实施例，并不用以限制本申请，凡在本申请的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本申请的保护范围之内。

Claims (14)

  1. 一种量子比特校准图的生成方法，所述方法由计算机设备执行，所述方法包括：
    获取校准模板，所述校准模板包括至少两个模板节点和至少一条第一有向边，所述模板节点用于表征针对量子比特的一种校准过程，所述第一有向边用于指示所述第一有向边连接的两个模板节点所分别表征的校准过程的执行顺序；
    获取量子芯片的结构数据，所述结构数据用于指示所述量子芯片包括的N个量子比特，N为大于1的整数；
    根据所述校准模板和所述结构数据，生成所述量子芯片的量子比特校准图，所述量子比特校准图用于图形化表示针对所述N个量子比特的校准任务。
  2. 根据权利要求1所述的方法，其中，所述根据所述校准模板和所述结构数据，生成所述量子芯片的量子比特校准图，包括：
    根据所述结构数据，将所述模板节点展开为所述量子比特校准图中的至少一个校准节点，所述校准节点用于表征针对所述N个量子比特中的至少一个量子比特的一个校准过程；
    将所述第一有向边展开为所述量子比特校准图中的至少一条第二有向边，所述第二有向边用于指示所述第二有向边连接的两个校准节点所分别表征的校准过程的执行顺序。
  3. 根据权利要求2所述的方法，其中，所述结构数据还用于指示所述N个量子比特之间的耦合情况，所述模板节点为单模板节点或耦合模板节点，所述单模板节点用于表征针对单个量子比特的一种校准过程，所述耦合模板节点用于表征针对存在耦合关系的Q个量子比特的一种校准过程，所述校准节点为单校准节点或耦合校准节点，所述单校准节点用于表征针对所述N个量子比特中的一个量子比特的一个校准过程，所述耦合校准节点用于表征针对所述N个量子比特中的存在耦合关系的Q个量子比特的一个校准过程，Q为大于1的整数；
    所述根据所述结构数据，将所述模板节点展开为所述量子比特校准图中的至少一个校准节点，包括如下至少之一：
    在所述模版节点为所述单模板节点的情况下，根据所述结构数据，将所述单模板节点展开为所述量子比特校准图中的N个单校准节点；
    在所述模版节点为所述耦合模板节点的情况下，根据所述结构数据，将所述耦合模板节点展开为所述量子比特校准图中的M个耦合校准节点，其中，M为所述N个量子比特中包含的量子比特组的数量，M为正整数，所述量子比特组包括存在耦合关系的Q个量子比特。
  4. 根据权利要求3所述的方法，其中，所述将所述第一有向边展开为所述量子比特校准图中的至少一条第二有向边，包括如下至少之一：
    在所述第一有向边连接的两个模板节点均为所述单模板节点的情况下，将所述第一有向边展开为所述量子比特校准图中的N条第二有向边，N条第二有向边中的每一条第二有向边连接与所述N个量子比特中同一量子比特对应的两个单校准节点；
    在所述第一有向边连接的两个模板节点分别为所述单模板节点和所述耦合模板节点的情况下，将所述第一有向边展开为所述量子比特校准图中的M×Q条第二有向边，M×Q条第二有向边中的每一条第二有向边连接与所述N个量子比特中同一量子比特对应的一个单校准节点和一个耦合校准节点；
    在所述第一有向边连接的两个模板节点分别为第一耦合模板节点和第二耦合模板节点的情况下，将所述第一有向边展开为所述量子比特校准图中的P条第二有向边，其中，所述第一耦合模板节点用于表征针对存在耦合关系的Q1个量子比特的一种校准过程，所述第二耦合模板节点用于表征针对存在耦合关系的Q2个量子比特的一种校准过程，Q1为大于1的正整数，Q2为大于1且小于或等于Q1的整数，P为各个第一量子比特组分别包含的第二量子比特组的数量之和，P为正整数，所述第一量子比特组包括所述N个量子比特中的存在耦合关系的Q1个量子比特，所述第二量子比特组包括所述N个量子比特中的存在耦合关系的Q2个量子比特，P条第二有向边中的每一条第二有向边连接与所述N个量子比特中同一第二量子比特组对应的两个耦合校准节点。
  5. 根据权利要求2至4任一项所述的方法，其中，所述结构数据还用于指示所述N个量子比特之间的耦合情况，所述根据所述结构数据，将所述模板节点展开为所述量子比特校准图中的至少一个校准节点，包括：
    在所述模板节点为目标模板节点的情况下，根据所述结构数据，将所述目标模板节点展开为所述量子比特校准图中的至少两个通过第三有向边相连接的校准节点，所述目标模板节点所表征的校准过程在作用于不同量子比特时，受量子比特间的耦合关系影响，所述第三有向边用于指示所述第三有向边连接的两个校准节点所分别表征的校准过程无法并行执行。
  6. 根据权利要求5所述的方法，其中，所述目标模板节点为单模板节点或耦合模板节点，所述单模板节点用于表征针对单个量子比特的一种校准过程，所述耦合模板节点用于表征针对存在耦合关系的Q个量子比特的一种校准过程，所述Q为大于1的整数；
    在所述目标模板节点为所述单模板节点的情况下，所述第三有向边连接的两个校准节点分别对应的量子比特存在耦合关系；
    在所述目标模板节点为所述耦合模板节点的情况下，所述第三有向边连接的两个校准节点分别对应的Q个量子比特包含同一量子比特。
  7. 根据权利要求2至6任一项所述的方法，其中，所述方法还包括：
    按所述量子比特校准图中，各条所述第二有向边指示的执行顺序，执行各个所述校准节点分别表征的校准过程。
  8. 根据权利要求2至7任一项所述的方法，其中，J个校准节点所分别表征的校准过程被并行执行，所述J个校准节点是由同一模板节点展开得到的，所述J为大于1的整数。
  9. 根据权利要求2至8任一项所述的方法，其中，K个校准节点所分别表征的校准过程被并行执行；
    所述K个校准节点是由同一目标模板节点展开得到的，且所述K个校准节点相互间隔的第三有向边的数量大于第一阈值；
    其中，所述目标模板节点所表征的校准过程在作用于不同量子比特时，受量子比特间的耦合关系影响，所述第三有向边用于指示所述第三有向边连接的两个校准节点所分别表征的校准过程无法并行执行。
  10. 一种量子比特校准图的生成装置，所述装置包括：
    获取模块，用于获取校准模板，所述校准模板包括至少两个模板节点和至少一条第一有向边，所述模板节点用于表征针对量子比特的一种校准过程，所述第一有向边用于指示所述第一有向边连接的两个模板节点所表征的校准过程的执行顺序；
    所述获取模块，还用于获取量子芯片的结构数据，所述结构数据用于指示所述量子芯片包括的N个量子比特，N为大于1的整数；
    生成模块，用于根据所述校准模板和所述结构数据，生成所述量子芯片的量子比特校准图，所述量子比特校准图用于图形化表示针对所述N个量子比特的校准任务。
  11. 一种计算机设备，所述计算机设备包括处理器和存储器，所述存储器中存储有计算机程序，所述计算机程序由所述处理器加载并执行以实现如权利要求1至9任一项所述的方法。
  12. 一种芯片产品，所述芯片产品包括可编程逻辑电路和/或计算机程序，当所述芯片产品运行时，用于实现如权利要求1至9任一项所述的方法。
  13. 一种计算机可读存储介质，所述计算机可读存储介质中存储有计算机程序，所述计算机程序由处理器加载并执行以实现如权利要求1至9任一项所述的方法。
  14. 一种计算机程序产品，所述计算机程序产品包括计算机程序，所述计算机程序存储在计算机可读存储介质中，处理器从所述计算机可读存储介质读取并执行所述计算机程序，以实现如权利要求1至9任一项所述的方法。
PCT/CN2024/134115 2024-06-06 2024-11-25 量子比特校准图的生成方法、装置、设备及存储介质 Pending WO2025251547A1 (zh)

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CN115470922A (zh) * 2022-03-28 2022-12-13 合肥本源量子计算科技有限责任公司 量子比特校准方法及装置、量子控制系统、量子计算机
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CN115470920A (zh) * 2022-03-28 2022-12-13 合肥本源量子计算科技有限责任公司 量子比特校准方法以及装置、量子计算机
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