WO2025236563A1 - 一种半导体器件及其制造方法、电子设备 - Google Patents

一种半导体器件及其制造方法、电子设备

Info

Publication number
WO2025236563A1
WO2025236563A1 PCT/CN2024/129996 CN2024129996W WO2025236563A1 WO 2025236563 A1 WO2025236563 A1 WO 2025236563A1 CN 2024129996 W CN2024129996 W CN 2024129996W WO 2025236563 A1 WO2025236563 A1 WO 2025236563A1
Authority
WO
WIPO (PCT)
Prior art keywords
hole
layer
semiconductor
substrate
word line
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
PCT/CN2024/129996
Other languages
English (en)
French (fr)
Inventor
朱正勇
康卜文
赵超
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Beijing Superstring Academy of Memory Technology
Original Assignee
Beijing Superstring Academy of Memory Technology
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Beijing Superstring Academy of Memory Technology filed Critical Beijing Superstring Academy of Memory Technology
Publication of WO2025236563A1 publication Critical patent/WO2025236563A1/zh
Pending legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment

Definitions

  • This disclosure relates to, but is not limited to, device design and manufacturing in the field of semiconductor technology, and particularly to a semiconductor device and its manufacturing method, and electronic equipment.
  • This application provides a semiconductor device, including: multiple layers of memory cells stacked in a direction perpendicular to a substrate, a first word line extending in a direction perpendicular to the substrate through multiple layers of memory cells at the same location, a second word line extending in a direction perpendicular to the substrate through multiple layers of memory cells at the same location, and a third word line extending in a direction perpendicular to the substrate through multiple layers of memory cells at the same location.
  • the memory cell includes: a first transistor and a second transistor, the first transistor and the second transistor being distributed along a first direction parallel to the substrate; a second word line and a third word line being distributed along a second direction parallel to the substrate, the first direction and the second direction intersecting;
  • the first transistor includes: a first gate electrode, a second gate electrode, and a first semiconductor layer.
  • the first gate electrodes of memory cells at the same location in different layers extend along a direction perpendicular to the substrate and are spaced apart.
  • the first semiconductor layer partially surrounds the first gate electrode.
  • the second gate electrode is disposed on the side of the first semiconductor layer away from the first gate electrode.
  • the second gate electrode of the first transistor at the same location in different layers is part of the first word line.
  • the second transistor includes: a second semiconductor layer; a portion of the first gate electrode not surrounded by the first semiconductor layer connected to the second semiconductor layer; the second semiconductor layer partially surrounding the second word line; the third word line forming a plurality of first grooves spaced apart in a direction perpendicular to the substrate with openings facing the second word line, the second semiconductor layer being distributed on the bottom and sidewalls of the first grooves, and the second word line forming a plurality of protrusions facing the plurality of first grooves respectively.
  • the first semiconductor layer includes a first semiconductor sublayer and a second semiconductor sublayer disposed on the side of the first semiconductor sublayer away from the first gate electrode.
  • the first semiconductor sublayer partially surrounds the first gate electrode.
  • the doping concentration of the second semiconductor sublayer is greater than that of the first semiconductor sublayer.
  • the second semiconductor sublayer includes a first portion and a second portion disposed at intervals on the surface of the first semiconductor sublayer away from the first gate electrode.
  • the first word line is distributed in the region between the first portion and the second portion on the sidewall of the first semiconductor sublayer opposite to the first gate electrode.
  • the first transistor further includes a first electrode and a second electrode, the first electrode being connected to the first portion and the second electrode being connected to the second portion, the second portion surrounding the second electrode, and the second electrodes of the first transistors at the same location on different layers being connected to form an integral structure extending in a direction perpendicular to the substrate.
  • the first portions of the first transistors in the same column distributed along the second direction on the same layer are interconnected to form an integral structure, and the second portions of the first transistors in the same column distributed along the second direction on the same layer are separated from each other.
  • the first electrode connections of the first transistors in the same column distributed along the second direction form a first bit line extending along the second direction.
  • the second electrode and the first word line are disposed on the same side of the first portion, and on the same side of the first gate electrode.
  • the semiconductor device further includes an isolation layer that extends through multiple layers of the first transistor; first gate electrode portions at the same location in different layers surround the isolation layer and are sequentially distributed in different regions of the sidewalls of the isolation layer along a direction perpendicular to the substrate.
  • the first transistor further includes a first gate insulating layer disposed between the first gate electrode and the first semiconductor sublayer, and the first gate insulating layers of the first transistors at the same position in different layers are connected to form an integral structure extending in a direction perpendicular to the substrate.
  • the semiconductor device further includes:
  • An insulating layer and a conductive layer are alternately distributed from top to bottom along a direction perpendicular to the substrate;
  • the first hole has, from the outside to the inside, the first semiconductor sub-layer, the first gate insulating layer, the first gate electrode, and the isolation layer, and the isolation layer fills the first hole;
  • the second hole has a second gate insulating layer and the first word line distributed sequentially from the outside to the inside, and the first word line fills the second hole;
  • the third hole contains only signal lines, and the signal lines fill the third hole.
  • the second electrode of the first transistor at the same position in different layers is part of the signal lines.
  • the boundary near the first word line, the boundary near the second word line, and the boundary away from the second word line fall into the orthographic projection of the sub-hole of the first hole in the conductive layer onto the substrate, and the boundary away from the first word line falls on the boundary of the orthographic projection of the sub-hole of the first hole in the conductive layer onto the substrate.
  • the semiconductor device further includes: a fourth hole penetrating the insulating layer and the conductive layer, wherein the fourth hole is provided with the second semiconductor layer, the third gate insulating layer, and the second word line in sequence from the outside to the inside, the second word line filling the fourth hole, the sidewall of the fourth hole exposing the first gate electrode, and the boundary of the fourth hole in the sub-hole of the insulating layer near the first gate electrode and the boundary near the third word line falling into the orthogonal projection of the sub-hole of the fourth hole in the conductive layer on the substrate, and the boundary away from the first gate electrode and the boundary away from the third word line falling on the boundary of the sub-hole of the fourth hole in the conductive layer on the orthogonal projection of the sub-hole of the fourth hole on the substrate.
  • the semiconductor device further includes a second lateral groove disposed on the side of the second word line opposite to the first gate electrode and extending along a second direction, the second lateral groove communicating with the fourth hole.
  • the opening of the transverse groove is away from the second word line and the third word line, and the second semiconductor layer is also distributed on the side wall and bottom wall of the second transverse groove.
  • the second semiconductor layers of the second transistors distributed in the same column along the second direction are disconnected.
  • the semiconductor device further includes: a second bit line distributed in the second lateral groove where the second semiconductor layer is disposed and filling the second lateral groove.
  • the semiconductor device further includes: a fifth hole penetrating the insulating layer and the conductive layer, wherein a fourth gate insulating layer and the third word line are sequentially distributed from the outside to the inside of the fifth hole, and the third word line fills the fifth hole; and in the orthogonal projection of the sub-hole of the fifth hole in the conductive layer onto the substrate, the boundary of the fifth hole near the second bit line and the boundary of the fifth hole near the second word line fall into the orthogonal projection of the sub-hole of the fifth hole in the insulating layer onto the substrate, and the boundary away from the second bit line and the boundary away from the second word line fall on the boundary of the orthogonal projection of the sub-hole of the fifth hole in the insulating layer onto the substrate.
  • This disclosure provides a method for manufacturing a semiconductor device, including:
  • a substrate is provided, on which a stacked structure comprising alternating functional layers and sacrificial layers is formed, the stacked structure comprising a plurality of memory cell regions, the memory cell regions comprising a first transistor region and a second transistor region distributed along a first direction parallel to the substrate;
  • a first gate electrode and a first semiconductor layer are formed in the first transistor region, which are disposed in the functional layer.
  • a first word line is formed through each layer in a direction perpendicular to the substrate.
  • the first semiconductor layer partially surrounds the first gate electrode.
  • the first word line is disposed on the side of the first semiconductor layer away from the first gate electrode.
  • the first gate electrodes of memory cells at the same position in different layers are stacked and spaced apart in a direction perpendicular to the substrate.
  • the second gate electrode of the first transistor at the same position in different layers is part of the first word line.
  • a second word line, a third word line, and a second semiconductor layer are formed in the second transistor region; the first gate electrode is connected to the second semiconductor layer; the second semiconductor layer partially surrounds the second word line; the third word line has a plurality of first grooves with openings facing the second word line and spaced apart in a direction perpendicular to the substrate, the bottom wall and side wall of the first grooves are provided with the second semiconductor layer, and the second word line has a plurality of protrusions facing the plurality of first grooves respectively.
  • forming a stacked structure comprising alternating functional layers and sacrificial layers on the substrate includes:
  • a semiconductor thin film and a sacrificial layer thin film are sequentially deposited on the substrate to form a stacked structure comprising alternating semiconductor structural layers and sacrificial layers;
  • the stacked structure is patterned to form a T-shaped first trench penetrating each layer.
  • the first trench includes a first sub-trench extending along a first direction and a second sub-trench extending from the non-end of the first sub-trench along a second direction parallel to the substrate.
  • the memory cell region is included between adjacent first sub-trenches spaced apart along the second direction.
  • the first transistor region and the second transistor region are respectively disposed on both sides of the second sub-trench. The first direction and the second direction intersect.
  • a first hole is formed in the first transistor region near a first sub-trench of a first trench, penetrating the stacked structure in a direction perpendicular to the substrate.
  • the sidewalls of the first hole expose the first sub-trench.
  • the sacrificial layer is removed by etching through the first hole and replaced with an insulating layer.
  • forming a first gate electrode and a first semiconductor layer disposed in the functional layer in the first transistor region, and forming a first word line penetrating each layer along a direction perpendicular to the substrate includes:
  • the semiconductor structure layer is etched along a direction parallel to the substrate based on the first hole; a plurality of first semiconductor sub-layers, a first gate insulating layer, a plurality of gate electrodes, and an isolation layer are formed within the first hole; the plurality of first gate electrodes are etched along...
  • the plurality of first semiconductor sublayers are spaced apart perpendicular to the substrate direction, partially surrounding the first gate electrode and spaced apart along the direction perpendicular to the substrate direction, the first gate insulating layer is disposed between the first semiconductor sublayers and the first gate electrode, the first gate electrode partially surrounds the isolation layer, and the isolation layer fills the first hole;
  • a second via is formed in a first sub-trench near another first trench in the first transistor region, penetrating the stacked structure in a direction perpendicular to the substrate. Based on the second via, the semiconductor structure layer is etched in a direction parallel to the substrate to expose the first semiconductor sub-layer. A second gate insulating layer and a first word line filling the second via are sequentially formed in the second via. The first via and the second via divide the semiconductor structure layer of the first transistor region into a second semiconductor sub-layer comprising a separate first portion and a second portion.
  • the method further includes:
  • a third hole is formed between the second hole and the second sub-trench in the first transistor region, penetrating the stacked structure in a direction perpendicular to the substrate.
  • the sidewalls of the third hole expose a second portion of the second semiconductor sublayer.
  • a signal line is formed in the third hole, filling the third hole and contacting the second portion of the second semiconductor sublayer.
  • forming a second word line, a third word line, and a second semiconductor layer in the second transistor region includes:
  • a fourth hole is formed in the second transistor region, penetrating the stacked structure in a direction perpendicular to the substrate. Based on the fourth hole, the semiconductor structure layer, the first semiconductor sublayer, and the first gate insulating layer are etched in a direction parallel to the substrate to expose the first gate electrode, forming a lateral groove. A second semiconductor layer, a third gate insulating layer, and a second word line filling the fourth hole are formed sequentially in the fourth hole, and the second semiconductor layer is formed on the bottom wall and sidewall of the lateral groove.
  • a fifth hole is formed in the second transistor region through the stacked structure in a direction perpendicular to the substrate.
  • the fifth hole and the fourth hole are distributed in a second direction.
  • the semiconductor structure layer and the insulating layer are etched in a direction parallel to the substrate to expose the third gate insulating layer and the second semiconductor layer.
  • a fourth gate insulating layer and a third word line filling the fifth hole are sequentially formed in the fifth hole.
  • it also includes:
  • a second trench is formed between adjacent first transistor regions along a first direction, extending through each layer; the second trench extends along a second direction; the semiconductor structure layer is laterally etched within the second trench without exposing the first semiconductor sublayer, forming a first lateral trench; a first bit line is formed within the first lateral trench to fill the first lateral trench.
  • it also includes:
  • a third trench extending in the second direction through each layer is formed between adjacent second transistor regions along the first direction; the semiconductor structure layer is laterally etched in the third trench to form a second lateral trench, and the second lateral trench communicates with the fourth via.
  • the second semiconductor layer is also formed on the inner wall of the second transverse trench; a second bit line is formed in the second transverse trench where the second semiconductor layer is formed to fill the second transverse trench.
  • This disclosure provides an electronic device, including any of the semiconductor devices described above, or a semiconductor device formed according to the manufacturing method of any of the semiconductor devices described above.
  • Figure 1A is a top view of a semiconductor device provided in some embodiments;
  • Figure 1B is a cross-sectional view perpendicular to the substrate along the AA' direction in Figure 1A;
  • Figure 1C is a cross-sectional view perpendicular to the substrate along the BB' direction in Figure 1A;
  • Figure 1D is a cross-sectional view perpendicular to the substrate along the CC' direction in Figure 1A;
  • Figure 1E is a cross-sectional view perpendicular to the substrate along the DD' direction in Figure 1A;
  • Figure 1F is a cross-sectional view parallel to the substrate along the FF' direction in Figure 1B;
  • Figure 1G is an equivalent circuit diagram of a semiconductor device provided in an exemplary embodiment.
  • Figure 2A is a top view of the stacked structure provided in some embodiments
  • Figure 2B is a cross-sectional view perpendicular to the substrate along the AA’ direction in Figure 2A.
  • Figure 3A is a top view of the first trench and the first insulating layer after formation according to some embodiments, and Figure 3B is a cross-sectional view perpendicular to the substrate along the EE' direction in Figure 3A;
  • Figure 4A is a top view of the first initial hole after it has been formed according to some embodiments
  • Figure 4B is a cross-sectional view perpendicular to the substrate along the AA’ direction in Figure 4A.
  • Figure 5A is a top view of the second insulating layer after formation according to some embodiments
  • Figure 5B is a cross-sectional view perpendicular to the substrate along the AA’ direction in Figure 5A.
  • Figure 6A is a top view of the first initial hole after exposure according to some embodiments, and Figure 6B is a cross-sectional view perpendicular to the substrate along the AA' direction in Figure 6A;
  • Figure 7A is a top view of the first groove after it has been formed according to some embodiments
  • Figure 7B is a cross-sectional view perpendicular to the substrate along the AA' direction in Figure 7A.
  • Figure 8A is a top view of the first semiconductor structure layer after formation according to some embodiments
  • Figure 8B is a cross-sectional view perpendicular to the substrate along the AA' direction in Figure 8A.
  • Figure 9A is a top view of the first semiconductor sublayer after formation according to some embodiments
  • Figure 9B is a cross-sectional view perpendicular to the substrate along the AA' direction in Figure 9A.
  • Figure 10A is a top view of the first conductive layer and the first gate insulating layer after formation according to some embodiments
  • Figure 10B is a cross-sectional view perpendicular to the substrate along the AA’ direction in Figure 10A.
  • Figure 11A is a top view of the first gate electrode after formation according to some embodiments
  • Figure 11B is a cross-sectional view perpendicular to the substrate along the AA' direction in Figure 11A.
  • Figure 12A is a top view of the second initial hole and the third groove provided in some embodiments;
  • Figure 12B is a cross-sectional view perpendicular to the substrate along the BB’ direction in Figure 12A; and
  • Figure 12C is a cross-sectional view perpendicular to the substrate along the CC’ direction in Figure 12A.
  • Figure 13A is a top view of the second gate insulating layer and the first word line after formation according to some embodiments;
  • Figure 13B is a cross-sectional view perpendicular to the substrate along the BB’ direction in Figure 13A; and
  • Figure 13C is a cross-sectional view perpendicular to the substrate along the CC’ direction in Figure 13A.
  • Figure 14A is a top view of the third hole after it has been formed according to some embodiments
  • Figure 14B is a cross-sectional view perpendicular to the substrate along the BB' direction in Figure 14A.
  • Figure 15A is a top view of some embodiments after forming signal lines
  • Figure 15B is a cross-sectional view perpendicular to the substrate along the BB' direction in Figure 15A.
  • Figure 16A is a top view of the second trench after it has been formed according to some embodiments
  • Figure 16B is a cross-sectional view perpendicular to the substrate along the BB' direction in Figure 16A.
  • Figure 17A is a top view of the first line layer after formation according to some embodiments
  • Figure 17B is a cross-sectional view perpendicular to the substrate along the BB' direction in Figure 17A.
  • Figure 18A is a top view of the first line and the fourth insulating layer after forming according to some embodiments
  • Figure 18B is a cross-sectional view perpendicular to the substrate along the BB' direction in Figure 18A.
  • Figure 19A is a top view of the fourth initial hole and the third trench after forming according to some embodiments;
  • Figure 19B is a cross-sectional view perpendicular to the substrate along the AA’ direction in Figure 19A; and
  • Figure 19C is a cross-sectional view perpendicular to the substrate along the DD’ direction in Figure 19A.
  • Figure 20A is a top view of the fifth groove after it has been formed according to some embodiments;
  • Figure 20B is a cross-sectional view perpendicular to the substrate along the AA’ direction in Figure 20A; and
  • Figure 20C is a cross-sectional view perpendicular to the substrate along the DD’ direction in Figure 20A.
  • Figure 21A is a top view of the third semiconductor structure layer after formation according to some embodiments;
  • Figure 21B is a cross-sectional view perpendicular to the substrate along the AA’ direction in Figure 21A; and
  • Figure 21C is a cross-sectional view perpendicular to the substrate along the DD’ direction in Figure 21A.
  • Figure 22A is a top view of the second semiconductor layer after formation according to some embodiments;
  • Figure 22B is a cross-sectional view perpendicular to the substrate along the AA’ direction in Figure 22A; and
  • Figure 22C is a cross-sectional view perpendicular to the substrate along the DD’ direction in Figure 22A.
  • Figure 23A is a top view of the formation of the sixth groove according to some embodiments, and Figure 23B is a cross-sectional view perpendicular to the substrate along the AA’ direction in Figure 23A;
  • Figure 24A is a top view of the second bit line layer after formation according to some embodiments
  • Figure 24B is a cross-sectional view perpendicular to the substrate along the AA’ direction in Figure 24A.
  • Figure 25A is a top view of the second bit line after formation according to some embodiments
  • Figure 25B is a cross-sectional view perpendicular to the substrate along the AA’ direction in Figure 25A.
  • Figure 26A is a top view of the second word line and the third gate insulating layer provided in some embodiments;
  • Figure 26B is a cross-sectional view perpendicular to the substrate along the AA’ direction in Figure 26A; and
  • Figure 26C is a cross-sectional view perpendicular to the substrate along the DD’ direction in Figure 26A.
  • Figure 27A is a top view of the fifth initial hole after it has been formed according to some embodiments
  • Figure 27B is a cross-sectional view perpendicular to the substrate along the BB’ direction in Figure 27A
  • Figure 27C is a cross-sectional view perpendicular to the substrate along the DD’ direction in Figure 27A.
  • connection should be interpreted broadly. For example, they can refer to physical or signal connections, contact or integral connections; direct connections, indirect connections via intermediate components, or internal communication between two components. Those skilled in the art will understand the specific meaning of these terms in this disclosure according to the specific circumstances.
  • a transistor is a device that includes at least three terminals: a gate electrode, a drain electrode, and a source electrode.
  • a transistor has a channel region between the drain electrode (drain electrode terminal, drain region, or drain electrode) and the source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode.
  • the channel region refers to the region through which current primarily flows.
  • the first electrode may be the drain electrode and the second electrode may be the source electrode, or vice versa.
  • the functions of the "source electrode” and the “drain electrode” are sometimes interchanged. Therefore, in this disclosure, the "source electrode” and the “drain electrode” can be interchanged.
  • connection includes the situation where constituent elements are connected together by a component having some electrical function.
  • component having some electrical function There are no particular limitations on the “component having some electrical function,” as long as it enables the transmission and reception of electrical signals between the connected constituent elements.
  • component having some electrical function include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other components with various functions.
  • parallel means approximately parallel or nearly parallel, for example, two straight lines forming an angle of -10° or more and less than 10°, and therefore also includes angles of -5° or more and less than 5°.
  • perpendicular means approximately perpendicular, for example, two straight lines forming an angle of 80° or more and less than 100°, and therefore also includes angles of 85° or more and less than 95°.
  • a and B are an integral structure
  • an integral structure can refer to a structure without obvious boundaries such as discontinuities or gaps in its microstructure.
  • an integral structure is formed by patterning interconnected membrane layers on a single membrane layer.
  • a and B may be formed using the same material as a single membrane layer and simultaneously created through the same patterning process, resulting in a structure with interconnected relationships.
  • the orthographic projection of B is within the range of the orthographic projection of A
  • the boundary of the orthographic projection of B falls within the boundary range of the orthographic projection of A, or the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B.
  • Figure 1A is a top view of a semiconductor device provided in some embodiments;
  • Figure 1B is a cross-sectional view perpendicular to substrate 1 along the AA' direction in Figure 1A;
  • Figure 1C is a cross-sectional view perpendicular to substrate 1 along the BB' direction in Figure 1A;
  • Figure 1D is a cross-sectional view perpendicular to substrate 1 along the DD' direction in Figure 1A;
  • Figure 1E is a cross-sectional view perpendicular to substrate 1 along the DD' direction in Figure 1A;
  • Figure 1F is a cross-sectional view parallel to substrate 1 along the FF' direction in Figure 1B.
  • embodiments of this disclosure provide a semiconductor device including a multilayer memory cell array vertically stacked on a substrate 1, wherein the multilayer memory cell array may be distributed along a third direction Z.
  • the third direction Z may be perpendicular to the substrate 1.
  • the memory cell array may include multiple first bit lines 31, multiple second bit lines 32, multiple first word lines 40a, multiple second word lines 40b, multiple third word lines 40c, and multiple memory cells.
  • Each memory cell array may include multiple memory cells distributed along a first direction X parallel to the substrate 1 and a second direction Y parallel to the substrate 1.
  • the first direction X and the second direction Y may intersect.
  • the first direction X and the second direction Y may be perpendicular. Every two columns of memory cells form a group.
  • the first bit line 31 can be a conductive line extending along the second direction Y.
  • the second bit line 32 can be a conductive line extending along the second direction Y.
  • Multiple first bit lines 31 of the same memory cell array can be spaced apart from each other, and the multiple first bit lines 31 of the same memory cell array can be distributed at intervals along the first direction X.
  • Multiple second bit lines 32 of the same memory cell array can be spaced apart from each other, and the multiple second bit lines 32 of the same memory cell array can be distributed at intervals along the first direction X.
  • First bit lines 31 of different memory cell arrays can be stacked on the substrate 1, with first bit lines 31 at the same position in different layers spaced apart from each other.
  • Second bit lines 32 of different memory cell arrays can be stacked on the substrate 1, with second bit lines 32 at the same position in different layers spaced apart from each other.
  • Each column of storage cells distributed along the second direction Y is connected to the same first bit line 31 and the same second bit line 32.
  • the two second bit lines 32 connected to the two columns of storage cells in the same group are respectively disposed between the two first bit lines 31 connected to the two columns of storage cells in the same group.
  • the memory cell may include a first transistor and a second transistor.
  • the first transistor and the second transistor in the same memory cell may be distributed along a first direction X.
  • the first word line 40a, the second word line 40b, and the third word line 40c can extend along the third direction Z.
  • Multiple memory cells stacked vertically at the same position on different layers share a first word line 40a, a second word line 40b, and a third word line 40c. Different memory cells on the same layer correspond to different first word lines 40a, different second word lines 40b, and different third word lines 40c.
  • the following description uses a semiconductor device comprising multiple vertically stacked memory cells in the same location as an example, with 2T0C memory cells as an example.
  • a semiconductor device which may include:
  • the memory cell may include a first transistor and a second transistor.
  • the first transistor may include a first gate electrode 26a, a second gate electrode 26b, a first electrode 51 and a second electrode 52, and a first semiconductor layer 23a.
  • the second transistor may include a third gate electrode 26c, a fourth gate electrode 26d, a third electrode 53 and a fourth electrode 54, and a second semiconductor layer 23b.
  • the second semiconductor layer 23b partially surrounds the second word line 40b.
  • the third word line 40c forms a plurality of first grooves spaced apart in a direction perpendicular to the substrate 1, with openings facing the second word line 40b.
  • the second semiconductor layer 23b is distributed on the bottom and sidewalls of the first grooves.
  • the second word line 40b forms a plurality of protrusions facing the plurality of first grooves.
  • the solution provided in this embodiment controls the second transistor of the corresponding memory cell through dual word lines, which can realize the selection of the corresponding memory cell in the memory array without setting a separate selection transistor, thus simplifying the structure and manufacturing process of the peripheral selection circuit of the memory array.
  • the first gate electrode 26a may extend in a direction perpendicular to the substrate 1.
  • the first gate electrode 26a may form a groove with its opening direction opposite to the first word line 40a.
  • the groove formed by the first gate electrode 26a may include a bottom wall extending in a direction perpendicular to the substrate 1 and two side walls extending in a direction perpendicular to the substrate 1.
  • the first gate electrodes 26a of memory cells at the same position in different layers extend in a direction perpendicular to the substrate 1 and are spaced apart.
  • the first gate electrode 26a may include a bottom wall extending parallel to the first direction X and perpendicular to the substrate 1, and two side walls extending parallel to the second direction Y and perpendicular to the substrate 1.
  • the first semiconductor layer 23a may include a first semiconductor sublayer 231 and a second semiconductor sublayer 232.
  • the first semiconductor sublayer 231 may extend in a direction perpendicular to the substrate 1, as shown in FIG1F.
  • the first semiconductor sublayer 231 may be distributed on the outer wall (i.e. the outer surface of the groove) of the groove formed by the first gate electrode 26a, and partially surround the first gate electrode 26a.
  • the second semiconductor sublayer 232 is disposed on the side of the first semiconductor sublayer 231 away from the first gate electrode 26a.
  • the doping concentration of the second semiconductor sublayer 232 is greater than that of the first semiconductor sublayer 231.
  • the second semiconductor sublayer 232 may be included on the surface of the first semiconductor sublayer 231 away from the first gate electrode 26a.
  • the first portion 2321 and the second portion 2322 are spaced apart on the surface.
  • the high-doped sublayer is placed on the outer wall of the low-doped sublayer, which facilitates the early formation of the low-doped and high-doped sublayers respectively, avoiding additional and more complex doping operations during the semiconductor device fabrication process and simplifying the process.
  • the second semiconductor sublayer 232 may be a heavily doped semiconductor film layer
  • the first semiconductor sublayer 231 may be a lightly doped or undoped semiconductor film layer, thereby facilitating the use of the first semiconductor sublayer 231 as the channel region of the first transistor, and the two parts of the second semiconductor sublayer 232 as the source contact region and drain contact region of the second transistor, respectively, and in contact with the source electrode and drain electrode.
  • the height of the first portion 2321 of the second semiconductor sublayer 232 along the direction perpendicular to the substrate 1 may be the same as or approximately the same as the height of the second portion 2322 of the second semiconductor sublayer 232 along the direction perpendicular to the substrate 1.
  • the first electrode 51 is connected to the first portion 2321 of the second semiconductor sublayer 232, and the first electrode 51 is disposed on the side of the first portion 2321 away from the first gate electrode 26a.
  • the second semiconductor sublayer 232 may extend along the second direction Y. This approach facilitates obtaining the second semiconductor sublayer 232 by stacking semiconductor films with high doping concentrations and etching the semiconductor films, without the need to dope different semiconductor layers.
  • the first portions 2321 of the second semiconductor sublayers 232 of the first transistors in the same column distributed along the second direction Y of the same layer can be connected to form an integral structure.
  • This integral structure can extend along the second direction Y.
  • the embodiments of this disclosure are not limited thereto; the first portions 2321 of the second semiconductor sublayers 232 of the transistors in the same column distributed along the second direction Y of the same layer can be separated from each other.
  • the second portion 2322 of the second semiconductor sublayer 232 of the first transistors in the same column distributed along the second direction Y can be separated from each other.
  • the first bit line 31 may be a strip electrode parallel to the substrate 1, a portion of which may be the first electrode 51 of the first transistor.
  • the sidewall of the strip electrode is connected to the first portion 2321 of the second semiconductor sublayer 232.
  • the first bit line 31 may have an integrally designed branch connected to the first portion 2321 of the second semiconductor sublayer 232, wherein the extension direction of the branch intersects the extension direction of the first bit line 31, such as being approximately perpendicular.
  • the branch may be the first electrode 51 of the first transistor.
  • the branch can be multiple branches on one sidewall of the first line 31, and each branch is connected to the first part 2321 of the second semiconductor sublayer 232 of the first transistor.
  • a first gate insulating layer 24a extending in a direction perpendicular to the substrate 1 is disposed between the first semiconductor sublayer 231 and the first gate electrode 26a.
  • the first gate insulating layers 24a of multiple first transistors at the same location on different layers can be connected to form a single structure.
  • the solution provided in this embodiment facilitates the one-time formation of the first gate insulating layers 24a of multiple first transistors, thus simplifying the process.
  • the first gate electrodes 26a of a plurality of first transistors at the same location on different layers are spaced apart from each other, for example, physically disconnected.
  • the semiconductor device may further include an isolation layer 13 extending through a plurality of first transistors in a direction perpendicular to the substrate 1.
  • the first gate electrode 26a may partially surround the isolation layer 13.
  • the plurality of first gate electrodes 26a of the plurality of first transistors at the same position in different layers partially surround different regions of the isolation layer 13. That is, the plurality of first gate electrodes 26a of the plurality of first transistors at the same position in different layers are sequentially distributed in different regions of the sidewall of the isolation layer 13 in a direction perpendicular to the substrate 1.
  • the first gate insulating layer 24a partially surrounds the isolation layer 13, and the first semiconductor sublayer 231 partially surrounds the isolation layer 13.
  • an isolation layer 13 is adjacent to a first sub-trench, and a first gate electrode 26a partially surrounds the isolation layer 13 but does not surround the isolation layer 13 on the side facing the adjacent first sub-trench; that is, the first gate electrode 26a surrounds three sidewalls of the isolation layer 13; a first gate insulating layer 24a surrounds the isolation layer 13 and has a gap only on the side facing the second transistor region to expose the first gate electrode 26a; a first semiconductor sub-layer 231 is distributed on the outer sidewall of the first gate electrode 26a and has a gap on the side facing the second transistor to expose the first gate electrode 26a.
  • the portion of the first gate electrode 26a not surrounded by the first semiconductor layer 23a is connected to the second semiconductor layer 23b.
  • the second semiconductor layer 23b and the first semiconductor sub-layer 231 are separated by the first gate insulating layer 24a.
  • the second electrode 52 is connected to a second portion 2322 of the second semiconductor sublayer 232, and the second portion 2322 may surround the second electrode 52.
  • the second portion 2322 may completely surround the second electrode 52, or partially surround the second electrode 52, that is, the cross-section of the second portion 2322 parallel to the substrate 1 may be a closed loop or an open loop.
  • the second portion 2322 occupies a smaller area, which can reduce the device area.
  • the second gate electrode 26b may be part of the first word line 40a, the second gate electrode 26b of the first transistor at the same position in different layers may be part of the same first word line 40a, and the second gate electrodes 26a of the first transistor at the same position in different layers may be connected to form a first word line 40a with an integral structure.
  • the first word line 40a may be distributed in the region between the first portion 2321 and the second portion 2322 on the sidewall of the first semiconductor sublayer 231 on the side opposite to the first gate electrode 26a.
  • the second electrode 52 and the first word line 40a may be disposed on the same side of the first portion 2321, and on the same side of the first gate electrode 26a.
  • the third gate electrode 26c may be part of the second word line 40b, and the third gate electrode 26c of the second transistors at the same location on different layers may be part of the same second word line 40b.
  • the third gate electrodes 26c of the second transistors at the same location on different layers may be connected to form a second word line 40b with an integral structure.
  • the fourth gate electrode 26d may be part of the third word line 40c, and the fourth gate electrode 26d of the second transistors at the same location on different layers may be part of the same third word line 40c.
  • the fourth gate electrodes 26d of the second transistors at the same location on different layers may be connected to form a third word line 40c with an integrated structure.
  • the first electrode 51 may be connected to the first bit line 31, or the first electrode 51 may be a portion of the first bit line 31.
  • the first electrodes 51 of the first transistors of the same column of the same memory cell array may be connected to the same first bit line 31. That is, the first electrodes 51 of the first transistors of the same column distributed along the second direction Y are connected to form a first bit line 31 extending along the second direction Y.
  • the first electrodes 51 of the first transistors of adjacent columns of the same memory cell array may be connected to different first bit lines 31.
  • the fourth electrode 54 may be connected to the second bit line 32, or the fourth electrode 54 may be a portion of the second bit line 32.
  • the fourth electrodes 54 of the second transistors of the same column of the same memory cell array may be connected to the same second bit line 32. That is, the fourth electrodes 54 of the second transistors of the same column distributed along the second direction Y are connected to form a second bit line 32 extending along the second direction Y.
  • the fourth electrodes 54 of the second transistors of adjacent columns of the same memory cell array may be connected to different second bit lines 32.
  • the first gate electrode 26a may be connected to the third electrode 53, or the first gate electrode 26a and the third electrode 53 may share the same electrode.
  • the second electrodes 52 of the first transistors at the same location on different layers can be connected.
  • the semiconductor device may also include a signal line 52' extending in a direction perpendicular to the substrate 1, wherein the second electrodes 52 at the same location on different layers are connected to form an integral structure of the signal line 52'.
  • the semiconductor device may include a T-shaped first layer extending through multiple layers along a direction perpendicular to substrate 1.
  • a trench T1 may include a first sub-trench extending along a first direction X and a second sub-trench extending from the non-ends of the first sub-trench along a second direction Y parallel to the substrate 1. Adjacent first sub-trenches spaced apart along the second direction Y define a memory cell region. The two sides of the second sub-trench in the memory cell region are respectively referred to as a first transistor region and a second transistor region, and the first transistor region and the second transistor region are connected and not completely separated by the second sub-trench.
  • a first insulating layer 11 may be filled in the first trench T1.
  • a first gate electrode 26a, a first word line 40a, and a signal line 52' may be disposed in the first transistor region.
  • a third word line 40c may be disposed in the second transistor region.
  • a second semiconductor layer 23b may be disposed in the second transistor region and extend from the second transistor region to the first transistor region to connect with the first gate electrode 26a.
  • the second word line 40b may be disposed in the second transistor region and extend to the first transistor region.
  • the first word line 40a, signal line 52', and third word line 40c can be distributed along the first direction X, and the first gate electrode 26a and second word line 40b can also be distributed along the first direction X. This arrangement allows the first word line 40a, signal line 52', and third word line 40c to be distributed along the first direction X while ensuring the connection between the first gate electrode 26a and the second semiconductor layer 23b, achieving a compact layout and reducing the device area.
  • the semiconductor device may further include:
  • An insulating layer and a conductive layer are alternately distributed from top to bottom along a direction perpendicular to the substrate 1;
  • the conductive layer may include a first semiconductor layer 23a, a first gate electrode 26a, a second semiconductor layer 23b, a first bit line 31, and a second bit line 32;
  • the first hole is provided with the first semiconductor sub-layer 231, the first gate insulating layer 24a, the first gate electrode 26a, and the isolation layer 13 in sequence from the outside to the inside, and the isolation layer 13 fills the first hole;
  • the second hole has a second gate insulating layer 24b and a first word line 40a distributed sequentially from the outside to the inside, and the first word line 40a fills the second hole;
  • the third hole contains only signal lines 52', and the signal lines 52' fill the third hole.
  • the boundary of the first hole near the first word line 40a, the boundary near the second word line 40b, and the boundary away from the second word line 40b fall within the orthographic projection of the first hole in the conductive layer onto the substrate 1, and the boundary away from the first word line 40a falls on the boundary of the orthographic projection of the first hole in the conductive layer onto the substrate 1. That is, one sidewall of the first hole exposes the first insulating layer 11 located in the first sub-trench, and the first hole extends linearly toward the boundary of the first sub-trench in a direction perpendicular to the substrate 1.
  • the solution provided in this embodiment can minimize the size of the first transistor region along the second direction Y, thereby reducing the device area.
  • the aperture of the second hole located in the insulating layer may be smaller than the aperture of the second hole located in the conductive layer.
  • the diameter of the sub-hole of the third hole located in the insulating layer can be equal to the diameter of the sub-hole of the third hole located in the conductive layer.
  • the solution provided in this embodiment can form the third hole in one step, simplifying the process.
  • the semiconductor device may further include: a fourth hole penetrating the insulating layer and the conductive layer, wherein the fourth hole is provided with a second semiconductor layer 23b, a third gate insulating layer 24c, and a second word line 40b distributed sequentially from the outside to the inside, the second word line 40b filling the fourth hole, the sidewall of the fourth hole exposing the first gate electrode 26a, and the boundaries of the fourth hole near the first gate electrode 26a and near the third word line 40c in the orthogonal projection of the fourth hole in the insulating layer falling within the orthogonal projection of the fourth hole in the conductive layer on the substrate 1, and the boundaries away from the first gate electrode 26a and away from the third word line 40c falling on the boundaries of the fourth hole in the orthogonal projection of the fourth hole in the conductive layer on the substrate 1.
  • the sidewall of the fourth hole away from the first gate electrode 26a extends linearly in the insulating layer and the conductive layer in a direction perpendicular to the substrate 1.
  • one sidewall of the fourth hole exposes the first insulating layer 11 located in the first sub-trench, and the fourth hole faces the first sub-trench.
  • the sidewalls i.e., the sidewalls facing away from the third word line 40c
  • the semiconductor device may further include a second lateral groove (refer to the subsequent sixth groove V6) disposed on the side of the second word line 40b opposite to the first gate electrode 26a and extending along the second direction Y.
  • the second lateral groove communicates with the fourth hole, and the opening of the second lateral groove faces away from the second word line 40b and the third word line 40c.
  • the second semiconductor layer 23b is also distributed on the sidewalls and bottom wall of the second lateral groove.
  • a second bit line 32 is distributed in and fills the second lateral groove, thereby allowing the second bit line 32 to connect with the second semiconductor layer 23b distributed on the bottom wall and sidewalls of the second lateral groove.
  • the second semiconductor layers 23b of the second transistors in the same column distributed along the second direction Y are disconnected. As shown in FIG1F, the second semiconductor layers 23b are distributed in a portion of the sidewall of the second hole facing the adjacent first sub-trench, thereby disconnecting the second semiconductor layers 23b of adjacent second transistors along the second direction Y.
  • the semiconductor device may further include: a fifth hole penetrating the insulating layer and the conductive layer, wherein a fourth gate insulating layer 24d and a third word line 40c are sequentially distributed from the outside to the inside of the fifth hole, and the third word line 40c fills the fifth hole; and in the orthographic projection of the sub-hole of the fifth hole in the conductive layer onto the substrate 1, the boundaries of the fifth hole near the second bit line 32 and the boundaries near the second word line 40b fall within the orthographic projection of the sub-hole of the fifth hole in the insulating layer onto the substrate 1, and the boundaries away from the second bit line 32 and the boundaries away from the second word line 40b fall on the boundaries of the sub-hole of the fifth hole in the insulating layer onto the substrate 1.
  • the sidewall of the fifth hole away from the second bit line 32 extends linearly in the insulating layer and the conductive layer in a direction perpendicular to the substrate 1.
  • the sidewall of the fifth hole away from the second word line 40b extends linearly in the insulating layer and the conductive layer in a direction perpendicular to the substrate 1.
  • Figure 1G is an equivalent circuit diagram of a memory cell of a semiconductor device provided in an exemplary embodiment.
  • the memory cell may include a first transistor T1 and a second transistor T2.
  • the first electrode 51 of the first transistor T1 is connected to the first bit line 31
  • the second electrode 52 is connected to the reference voltage terminal Vrefn
  • the second gate electrode 26b is connected to the first word line 40a
  • the first gate electrode 26a is connected to the third electrode 53 of the second transistor T2.
  • the fourth electrode 54 of the second transistor T2 is connected to the second bit line 32, the third gate electrode 26c (to distinguish it from the first gate electrode 26a and the second gate electrode 26b of the first transistor, this does not mean that the second transistor T2 has three gate electrodes; the same applies to the fourth gate electrode 26d) is connected to the second word line 40b, and the fourth gate electrode 26d is connected to the third word line 40c.
  • the memory cell may also include a memory node SN, which may include the first gate electrode 26a of the first transistor T1.
  • the first transistor T1 can be a read transistor
  • the second transistor T2 can be a write transistor
  • the first bit line 31 can be a read bit line RBL
  • the second bit line 32 can be a write bit line WBL
  • the first word line 40a can be a read word line
  • the second word line 40b can be a first write word line WWL1
  • the third word line 40c can be a second write word line WWL2.
  • the second transistor T2 is turned on when both the first write word line WWL1 and the second write word line WWL2 are loaded with an activation signal
  • the second transistor T2 is turned off when at least one of the first write word line WWL1 and the second write word line WWL2 is loaded with a deactivation signal.
  • the second transistor T2 when both the first write line WWL1 and the second write line WWL2 are loaded with high-level signals (i.e., when both the third gate electrode 26c and the fourth gate electrode 26d of the second transistor T2 are loaded with high-level signals), the second transistor T2 is turned on. When at least one of the first write line WWL1 and the second write line WWL2 is loaded with a low-level signal, the second transistor T2 is turned off.
  • the second transistor T2 when the first transistor T1 and the second transistor T2 are P-type transistors, when both the first write line WWL1 and the second write line WWL2 are loaded with low-level signals, the second transistor T2 is turned on; when at least one of the first write line WWL1 and the second write line WWL2 is loaded with a high-level signal, the second transistor T2 is turned off.
  • second word lines 40b distributed along the first direction X in the same row can be connected together, i.e., connected to a first common word line; third word lines 40c distributed along the second direction Y in the same column can be connected together, i.e., connected to a second common word line; or, second word lines 40b distributed along the second direction Y in the same column can be connected together, i.e., connected to a first common word line; third word lines 40c distributed along the first direction X in the same row can be connected together, i.e., connected to a second common word line.
  • a vertical column of memory cells i.e., a group of memory cells at the same position in different layers
  • the scheme provided in this embodiment does not require setting selection transistors for the first common word line and the second common word line to select memory cells in a vertical column.
  • the process steps of manufacturing selection transistors can be eliminated, and the number of word line drivers is smaller.
  • the number of word line drivers remains unchanged as the number of stacked layers increases.
  • the circuit control logic is simple.
  • the film layer can be processed by patterning and photolithography.
  • the "patterning process” includes film deposition, photoresist coating, mask exposure, development, etching, and photoresist stripping, which are mature manufacturing processes in related technologies.
  • the "photolithography process” in this embodiment includes film coating, mask exposure, and development, which are mature manufacturing processes in related technologies.
  • Deposition can employ known processes such as sputtering, evaporation, and chemical vapor deposition; coating can employ known coating processes; and etching can employ known methods, without specific limitations.
  • thin film refers to a thin film made of a certain material on a substrate using a deposition or coating process. If the "thin film” does not require patterning or photolithography during the entire manufacturing process, it can also be called a “layer”. If the "thin film” requires patterning or photolithography during the entire manufacturing process, it is called a “thin film” before the patterning process and a “layer” after the patterning process. The "layer” after the patterning or photolithography process contains at least one "pattern”.
  • the manufacturing process of the semiconductor device may include:
  • the formation of the stacked structure may include: providing a substrate 1, and alternately depositing a first semiconductor thin film and a sacrificial layer thin film on the substrate 1 to form a stacked structure including a plurality of alternately arranged second semiconductor structure layers 232' and sacrificial layers 10;
  • the stacked structure includes a plurality of alternately arranged second semiconductor structure layers 232' and sacrificial layers 10, and a hard mask layer 9 disposed on the side of the topmost sacrificial layer 10 facing away from the substrate 1, the hard mask layer 9 covering the sacrificial layer 10, as shown in Figures 2A and 2B.
  • Figure 2A is a top view of the stacked structure after formation according to some embodiments
  • Figure 2B is a cross-sectional view perpendicular to the substrate 1 along the AA' direction in Figure 2A.
  • the AA' direction may be parallel to the first direction X.
  • substrate 1 may be a conventional silicon substrate or other bulk substrate including a semiconductor material layer.
  • the first semiconductor thin film may be a heavily doped semiconductor film layer, and the second semiconductor structure layer 232' may subsequently form a second semiconductor sublayer 232.
  • the sacrificial layer film can be a semiconductor material, such as SiGe.
  • a semiconductor material facilitates the epitaxial growth of the first semiconductor film.
  • the sacrificial layer film will subsequently be replaced with an insulating film.
  • the hard mask layer 9 includes, but is not limited to, at least one of the following: carbon, polycrystalline silicon, silicon oxide, etc.
  • the stacked structure shown in Figure 2B includes three second semiconductor structure layers 232' and three sacrificial layers 10. This is only an example. In other embodiments, the stacked structure may include more or fewer alternating layers of second semiconductor structure layers 232' and sacrificial layers 10.
  • the plurality of stacked structures are etched to form a plurality of first trenches T1 penetrating the stacked structures.
  • the plurality of first trenches T1 are spaced apart along a first direction X and a second direction Y.
  • a memory cell region is defined between every two adjacent first trenches T1 along the second direction Y.
  • the first trenches T1 can be T-shaped trenches.
  • Each T-shaped trench can include a first sub-trench extending in a straight line along the first direction X and a second sub-trench extending along the second direction Y from the middle of the first sub-trench.
  • the middle portion is not strictly evenly divided but is a position between the two ends of the first sub-trench.
  • a first insulating film is deposited and smoothed within each first trench T1 to form a first insulating layer 11 filling the first trench T1; the first insulating layer 11 may be flush with the hard mask layer 9.
  • Figures 3A and 3B where Figure 3A is a top view of the first trench T1 and the first insulating layer 11 after formation according to some embodiments, and Figure 3B is a cross-sectional view perpendicular to the substrate 1 along the EE' direction in Figure 3A.
  • the EE' direction may be parallel to the first direction X.
  • the first insulating layer 11 can isolate multiple subsequently formed memory cells.
  • the first insulating film may be a low-K dielectric layer, including but not limited to silicon oxide, such as silicon dioxide ( SiO2 ).
  • the stacked structure is etched from the top layer to the bottom layer using dry etching (etching stops on the substrate 1) to form a first initial hole K1.
  • the diameter of the first initial hole K1 is the same as the diameter of the second sub-hole in the second semiconductor structure layer 232' and the diameter of the first sub-hole in the sacrificial layer 10, as shown in Figures 4A and 4B.
  • Figure 4A is a top view after the formation of the first initial hole K1 provided in some embodiments
  • Figure 4B is a cross-sectional view perpendicular to the substrate 1 along the AA' direction in Figure 4A.
  • One sidewall of the first initial hole K1 exposes the first insulating layer 11 in a straight sub-trench (i.e., the first sub-trench) adjacent to the first initial hole K1 in the T-shaped trench (i.e., the first trench T1).
  • the remaining sidewalls of the first initial hole K1 do not expose the first insulating layer 11; that is, the remaining sidewalls expose the second semiconductor structure layer 232', the sacrificial layer 10, and the hard mask layer 9.
  • the first initial hole K1 is located in the first transistor region on one side of the sub-trench (i.e., the second sub-trench) extending along the second direction Y of the T-shaped trench.
  • the orthographic projection of the first initial hole K1 onto the substrate 1 is, for example, square. However, it is not limited to this and can be other shapes.
  • the sacrificial layer 10 is removed by lateral etching based on the first initial hole K1;
  • a second insulating film is deposited on the substrate 1 where the aforementioned structure is formed, forming a second insulating layer 12 that fills the area where the first initial hole K1 and the original sacrificial layer 10 are located, as shown in Figures 5A and 5B.
  • Figure 5A is a top view of the second insulating layer 12 after its formation, as provided in some embodiments, and Figure 5B is a cross-sectional view perpendicular to the substrate 1 along the AA' direction in Figure 5A.
  • the second insulating layer 12 can isolate memory cells from different layers.
  • the second insulating layer 12 may be a film layer with an etching selectivity ratio to the first insulating layer 11, such as SiN.
  • the second insulating layer 12 in the first initial hole K1 is removed by etching along a direction perpendicular to the substrate 1, exposing the first initial hole K1, as shown in Figures 6A and 6B.
  • Figure 6A is a top view of the first initial hole K1 after exposure according to some embodiments
  • Figure 6B is a cross-sectional view perpendicular to the substrate 1 along the AA' direction in Figure 6A.
  • the second semiconductor structure layer 232' is laterally etched (i.e., along a direction parallel to the substrate 1) to form a first lateral groove V1, such that the orthogonal projection of the sub-hole of the first hole located in the second insulating layer 12 onto the substrate 1 falls within the orthogonal projection of the sub-hole located in the second semiconductor structure layer 232' onto the substrate 1, as shown in Figure 7A and As shown in Figure 7B, where Figure 7A is a top view of the first groove V1 formed according to some embodiments, and Figure 7B is a cross-sectional view perpendicular to the substrate 1 along the AA' direction in Figure 7A.
  • the aforementioned first hole includes a first initial hole K1 and a first groove V1.
  • one of the two sidewalls spaced apart along the first direction X exposes the second semiconductor structure layer 232', and a portion of the other sidewall exposes the second semiconductor structure layer 232' while the other portion exposes the first insulating layer 11.
  • one of the two sidewalls exposes the first insulating layer 11 and the other exposes the second semiconductor structure layer 232'. That is, when etching laterally along the second direction Y, a portion of the second semiconductor structure layer 232' in that direction is etched away, and the first insulating layer 11 is not exposed.
  • the etching reaches the sub-groove (i.e., the second sub-groove) extending along the second direction Y of the T-shaped trench.
  • a second semiconductor thin film is deposited on the substrate 1 on which the aforementioned structure is formed to form a first semiconductor structure layer 231' that fills the first hole, as shown in Figures 8A and 8B.
  • Figure 8A is a top view of the first semiconductor structure layer 231' after its formation, as provided in some embodiments, and Figure 8B is a cross-sectional view perpendicular to the substrate 1 along the AA' direction in Figure 8A.
  • the first semiconductor structure layer 231' can be a lightly doped or undoped semiconductor material.
  • the deposition of the second semiconductor thin film may be an epitaxial growth of the second semiconductor thin film.
  • the material of the second semiconductor thin film may be silicon or polycrystalline silicon with a band gap of less than 1.65 eV, or it may be a wide band gap material, such as a metal oxide material with a band gap of greater than 1.65 eV.
  • the material of the metal oxide semiconductor layer or channel may include metal oxides of at least one of the following metals: indium, gallium, zinc, tin, tungsten, magnesium, zirconium, aluminum, hafnium, etc.
  • the metal oxide may also contain compounds of other elements, such as nitrogen (N) and silicon (Si); it may also contain trace amounts of other doping elements.
  • the material of the metal oxide semiconductor layer or channel may include one or more of the following: indium gallium zinc oxide (InGaZnO), indium zinc oxide (InZnO), indium gallium oxide (InGaO), indium tin oxide (InSnO), indium gallium tin oxide (InGaSnO), indium gallium zinc tin oxide (InGaZnSnO), indium oxide (InO), tin oxide (SnO), zinc tin oxide (ZnSnO, ZTO), indium aluminum zinc gold oxide (InAlZnO), zinc oxide (ZnO), indium gallium silicon oxide (InGaSiO), and indium tungsten oxide (InWO4).
  • InGaZnO indium gallium zinc oxide
  • InGaO indium gallium oxide
  • InSnO indium tin oxide
  • InGaSnO indium gallium zinc tin oxide
  • ZnSnO zinc tin oxide
  • ZTO zinc tin oxide
  • TiO titanium oxide
  • ZnON zinc oxynitride
  • zinc magnesium oxide MgZnO
  • ZrInZnO zirconium indium zinc oxide
  • HfInZnO hafnium indium zinc oxide
  • SnInZnO tin indium zinc oxide
  • AlSnInZnO aluminum tin indium zinc oxide
  • SiInZnO aluminum zinc tin oxide
  • GaZnSnO gallium zinc tin oxide
  • ZrZnSnO zirconium zinc tin oxide
  • the metal oxide material is IGZO
  • the leakage current of the transistor is less than or equal to 10 ⁇ 15 A, which can improve the performance of dynamic memory.
  • the first semiconductor structure layer 231' in the first hole is etched away except for the area where the first groove V1 is located. That is, the first semiconductor structure layer 231' in the first initial hole K1 is etched away, leaving only the first semiconductor structure layer 231' located in the first groove V1. This makes the first semiconductor structure layer 231' divided into multiple parts located in different layers.
  • the first semiconductor structure layer 231' is laterally etched to form a second groove V2, retaining a portion of the first semiconductor structure layer 231'.
  • the retained first semiconductor structure layer 231' is the first semiconductor sublayer 231 of the multiple transistors.
  • Figures 9A and 9B where Figure 9A illustrates the formation of the first semiconductor sublayer 231 provided in some embodiments.
  • Figure 9B is a top view of the conductor sublayer 231 and a cross-sectional view perpendicular to the substrate 1 along the AA' direction in Figure 9A.
  • the first semiconductor sublayer 231 comprises two independent parts, which are separated by the first insulating layer 11 in the first trench T1. This prevents the first semiconductor sublayer 231 and the second semiconductor layer 23b from connecting when the second semiconductor layer 23b is subsequently formed.
  • the area shown by the dashed line in Figure 9A is the outer boundary of the second groove V2.
  • a first gate insulating film and a first gate electrode film are sequentially deposited on the substrate 1 on which the aforementioned structure is formed to form a first gate insulating layer 24a and a first conductive layer 26a’.
  • the first conductive layer 26a’ fills the first initial hole K1 and the second groove V2, as shown in Figures 10A and 10B.
  • Figure 10A is a top view after the formation of the first conductive layer 26a’ and the first gate insulating layer 24a according to some embodiments
  • Figure 10B is a cross-sectional view perpendicular to the substrate 1 along the AA’ direction in Figure 10A.
  • the first gate insulating layer 24a covers the bottom wall and side wall of the first initial hole K1 and the second groove V2.
  • the material of the first gate insulating layer 24a may comprise one or more high-K dielectric materials. In some embodiments, it may include one or more oxides of hafnium, aluminum, lanthanum, zirconium, etc. Exemplary examples include, but are not limited to, at least one of the following: hafnium oxide ( HfO2 ), aluminum oxide ( Al2O3 ), hafnium aluminum oxide ( HfAlO ), hafnium lanthanum oxide (HfLaO), zirconium oxide ( ZrO2 ), etc.
  • the materials of the subsequent second gate insulating layer 24b, third gate insulating layer 24c, and fourth gate insulating layer 24d are similar and will not be described further.
  • the first gate electrode thin film may be one or more of the following different types of materials:
  • it contains metals such as tungsten, aluminum, titanium, copper, nickel, platinum, ruthenium, molybdenum, gold, iridium, rhodium, tantalum, and cobalt; it can also be a metal alloy containing these metals.
  • metal oxides can be metal oxides, metal nitrides, metal silicides, metal carbides, etc., such as highly conductive metal oxide materials like indium tin oxide (ITO), indium zinc oxide (IZO), indium oxide (InO), and aluminum-doped zinc oxide (AZO); or metal nitride materials like titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), and titanium aluminum nitride (TiAlN).
  • ITO indium tin oxide
  • IZO indium zinc oxide
  • InO indium oxide
  • AZO aluminum-doped zinc oxide
  • metal nitride materials like titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), and titanium aluminum nitride (TiAlN).
  • the first conductive layer 26a' in the first initial hole K1 is removed by etching, while the first conductive layer 26a' located in the plurality of second grooves V2 is retained.
  • the first conductive layer 26a' in each second groove V2 is the first gate electrode 26a of a first transistor.
  • the first gate electrodes 26a of the first transistors at the same position in different layers are disconnected.
  • the first gate electrode 26a is also multiplexed as the third electrode 53 of the second transistor, and the storage node SN includes the first gate electrode 26a.
  • Figure 11A is a top view after the formation of the first gate electrode 26a according to some embodiments
  • Figure 11B is a cross-sectional view perpendicular to the substrate 1 along the AA’ direction in Figure 11A.
  • the isolation layer 13 may be a low-K dielectric layer, including but not limited to silicon oxide, such as silicon dioxide ( SiO2 ).
  • the stacked structure is etched from the top layer to the bottom layer using dry etching (etching stops on substrate 1) to form...
  • the second initial hole K2 is located near the first trench T1 that is far from the first initial hole K1 among two adjacent first trenches T1 along the second direction Y, and the sidewall of the second initial hole K2 does not expose the first insulating layer 11.
  • the second initial hole K2 and the first initial hole K1 are located on the same side of the sub-trench (i.e. the second sub-trench) extending along the second direction Y of the first trench T1.
  • Figure 12A is a top view of the second initial hole K2 and the third groove V3 after formation according to some embodiments;
  • Figure 12B is a cross-sectional view perpendicular to the substrate 1 along the BB' direction in Figure 12A;
  • Figure 12C is a cross-sectional view perpendicular to the substrate 1 along the CC' direction in Figure 12A.
  • the third groove V3 has two sidewalls spaced apart along the second direction Y, one sidewall exposing the first insulating layer 11 located in the I-shaped sub-trench, and the other sidewall exposing the first semiconductor layer 231; two sidewalls spaced apart along the first direction X expose the second semiconductor structure layer 232'. Lateral etching is performed to expose the first semiconductor layer 231, so that the subsequently formed first word line 40a can control the first transistor.
  • the aforementioned second hole includes the second initial hole K2 and the third groove V3.
  • the orthographic projection of the second initial hole K2 onto the substrate 1 is, for example, square. However, it is not limited to this and can be other shapes.
  • a second gate insulating film and a second gate electrode film are sequentially deposited on the substrate 1 forming the aforementioned structure to form a second gate insulating layer 24b and a first word line 40a.
  • the second gate insulating layer 24b covers the bottom wall and sidewall of the second initial hole K2 and the third groove V3, and the first word line 40a fills the second initial hole K2 and the third groove V3, as shown in Figures 13A, 13B, and 13C.
  • Figure 13A is a top view of the second gate insulating layer 24b and the first word line 40a after formation according to some embodiments;
  • Figure 13B is a cross-sectional view perpendicular to the substrate 1 along the BB' direction in Figure 13A; and
  • Figure 13C is a cross-sectional view perpendicular to the substrate 1 along the CC' direction in Figure 13A.
  • the second gate electrode 26b of the first transistor at the same location in different layers is a part of the first word line 40a.
  • the stacked structure is etched from top to bottom using dry etching (etching stops on substrate 1) to form a third hole K3.
  • the third hole K3 is disposed between the second initial hole K2 and the sub-trench extending along the second direction Y of the first trench T1, and between the first initial hole K1 and the line-shaped sub-trench of the first trench T1.
  • the sidewall of the third hole K3 extending along the first direction X and away from the first initial hole K1 can expose the first insulating layer 11 located in the line-shaped sub-trench of the first trench T1.
  • the remaining sidewalls can expose the second semiconductor structure layer 232', but do not expose the second gate insulating layer 24b, the first semiconductor sub-layer 231, and the first insulating layer 11 located in the sub-trench extending along the second direction Y of the first trench T1.
  • Figures 14A and 14B where Figure 14A is a top view after the formation of the third hole K3 according to some embodiments, and Figure 14B is a cross-sectional view perpendicular to substrate 1 along the BB' direction in Figure 14A.
  • the orthographic projection of the third hole K3 onto the substrate 1 is, for example, square. However, it is not limited to this and can be other shapes.
  • the second semiconductor structure layer 232' exposed on the sidewall of the third hole K3 is metallized to form a metal silicide to reduce the contact resistance between the subsequently formed signal line 52' and the second semiconductor structure layer 232'.
  • a first conductive thin film is deposited to form a signal line 52' filling the third hole K3.
  • the second electrode 52 of the first transistor at the same position in a different layer is a part of the signal line 52'.
  • Figures 15A and 15B where Figure 15A is a top view after forming the signal line 52' according to some embodiments, and Figure 15B is a cross-sectional view perpendicular to the substrate 1 along the BB' direction in Figure 15A.
  • the second semiconductor structure layer 232' surrounding the signal line 52' is the second portion 2322 of the second semiconductor sublayer 232, with a gap between the first portion 2321 and the second portion 2322.
  • the stacked structure is etched from top to bottom to form a second trench T2 that runs through the stacked structure.
  • the second trench T2 extends along a second direction Y.
  • a set of memory cells is defined between adjacent second trenches T2 along a first direction X.
  • Each set of memory cells includes two columns of memory cells, as shown in Figures 16A and 16B.
  • Figure 16A is a top view after the second trench T2 is formed according to some embodiments
  • Figure 16B is a cross-sectional view perpendicular to the substrate 1 along the BB' direction in Figure 16A.
  • the second semiconductor structure layer 232' is etched laterally, but not completely etched away (the second gate insulating layer 24b is not exposed), forming a fourth trench V4.
  • the fourth trench V4 extends along the second direction Y.
  • the second semiconductor structure layer 232' located on the side of the first semiconductor sublayer 231 facing the second trench V2 serves as the first part 2321 of the second semiconductor sublayer 232.
  • the fourth trench V4 is a lateral trench extending along the second direction Y.
  • the second semiconductor sublayer 232 is subjected to metal silicide treatment to form a metal silicide, so as to reduce the contact resistance between the second semiconductor sublayer 232 and the first first line layer 31' to be formed;
  • a second conductive thin film is deposited to form a first line layer 31', which fills the second trench T2 and the fourth groove V4; as shown in Figures 17A and 17B, wherein Figure 17A is a top view after the formation of the first line layer 31' provided in some embodiments, and Figure 17B is a cross-sectional view perpendicular to the substrate 1 along the BB' direction in Figure 17A.
  • the first line layer 31' in the second trench T2 is removed by etching, while the first line layer 31' in the fourth groove V4 is retained. At this time, the first line layer 31' is divided into multiple first lines 31 located in different layers, and the multiple first lines 31 are disconnected from each other.
  • a fourth insulating film is deposited to form a fourth insulating layer 14 that fills the second trench T2.
  • the fourth insulating layer 14 separates different groups of memory cells, as shown in Figures 18A and 18B.
  • Figure 18A is a top view after the formation of the first line 31 and the fourth insulating layer 14 according to some embodiments.
  • Figure 18B is a cross-sectional view perpendicular to the substrate 1 along the BB' direction in Figure 18A.
  • the fourth insulating layer 14 may be a low-K dielectric layer, including but not limited to silicon oxide, such as silicon dioxide ( SiO2 ).
  • Figure 19A is a top view after forming the fourth initial hole K4 and the third trench T3 according to some embodiments.
  • Figure 19B is a cross-sectional view perpendicular to the substrate 1 along the AA’ direction in Figure 19A.
  • Figure 19C is a cross-sectional view perpendicular to the substrate 1 along the DD’ direction in Figure 19A.
  • the third trench T3 extends along the second direction Y, and the third trench T3 is spaced between two columns of storage cells in the same group.
  • the fourth initial hole K4 is located on the side of the sub-trench extending along the second direction Y of the first initial hole K1 towards the first trench T1, and the fourth initial hole K4 and the first initial hole K1 are close to the same straight trench (i.e., the first sub-trench) of the first trench T1, and one sidewall of the fourth initial hole K4 exposes the first insulating layer 11 in the straight sub-trench of the adjacent first trench T1.
  • the orthographic projection of the fourth initial hole K4 onto the substrate 1 is, for example, square. However, it is not limited to this and can be other shapes.
  • the second semiconductor structure layer 232', the first semiconductor sub-layer 231, and the first gate insulating layer 24a are laterally etched to form a fifth trench V5.
  • the sidewall of the fifth trench V5 exposes the first gate electrode 26a so that the first gate electrode 26a can be connected to the subsequently formed second semiconductor layer 23b.
  • the fourth initial hole K4 and the third trench T3 are connected, and the sidewall of the fifth trench V5 exposes the sidewall of the first insulating layer 11 in the first sub-trench facing the third trench T3.
  • Figure 20A is a top view after the formation of the fifth trench V5 according to some embodiments
  • Figure 20B is a cross-sectional view perpendicular to the substrate 1 along the AA' direction in Figure 20A
  • Figure 20C is a cross-sectional view perpendicular to the substrate 1 along the DD' direction in Figure 20A.
  • a third semiconductor thin film and a fifth insulating thin film are sequentially deposited on the substrate 1 on which the aforementioned structure is formed to form a third semiconductor structure layer 23b’ and a fifth insulating layer 15;
  • the third semiconductor structure layer 23b’ covers the sidewalls and bottom walls of the fourth initial hole K4 and the third trench T3, and covers the inner wall (sidewalls and bottom wall) of the fifth groove V5;
  • the fifth insulating layer 15 fills the fourth initial hole K4, the third trench T3 and the fifth groove V5; as shown in Figures 21A, 21B and 21C, wherein Figure 21A is a top view after the formation of the third semiconductor structure layer 23b’ according to some embodiments, Figure 21B is a cross-sectional view perpendicular to the substrate 1 along the AA’ direction in Figure 21A, and Figure 21C is a cross-sectional view perpendicular to the substrate 1 along the DD’ direction in Figure 21A.
  • the fifth insulating film may be a low-K dielectric layer, including but not limited to silicon oxide, such as silicon dioxide ( SiO2 ).
  • Etching removes the third semiconductor structure layer 23b’ and the fifth insulating layer 15 in the fourth initial hole K4 and the third trench T3, while retaining the third semiconductor structure layer 23b’ and the fifth insulating layer 15 in the fifth groove V5.
  • This divides the third semiconductor structure layer 23b’ into multiple portions located in different layers, each portion being the second semiconductor layer 23b of a second transistor, thereby disconnecting the second semiconductor layers 23b of the second transistors at the same position in different layers.
  • FIG. 22A is a top view after the formation of the second semiconductor layer 23b according to some embodiments
  • Figure 22B is a cross-sectional view perpendicular to the substrate 1 along the AA’ direction in Figure 22A
  • Figure 22C is a cross-sectional view perpendicular to the substrate 1 along the DD’ direction in Figure 22A.
  • the sixth insulating film may be a film layer that has an etching selectivity ratio with the fifth insulating layer, including but not limited to SiN.
  • the sixth insulating layer 16 in the third trench T3 is removed by etching
  • the fifth insulating layer 15 is laterally etched to form the sixth groove V6; the sixth groove V6 exposes the sixth insulating layer 16 located in the fourth initial hole K4; as shown in Figures 23A and 23B, wherein Figure 23A is a top view after the formation of the sixth groove V6 provided in some embodiments, and Figure 23B is a cross-sectional view perpendicular to the substrate 1 along the AA’ direction in Figure 23A.
  • the sixth groove V6 can be a part of the fifth groove V5, and the part of the fifth groove V5 other than the sixth groove V6 is called the seventh groove V7.
  • a third conductive thin film is deposited to form a second bit line layer 32', which fills the third trench T3 and the sixth groove V6; as shown in Figures 24A and 24B, wherein Figure 24A is a top view after the formation of the second bit line layer 32' provided in some embodiments, and Figure 24B is a cross-sectional view perpendicular to the substrate 1 along the AA' direction in Figure 24A.
  • the second bit line layer 32' in the third trench T3 is removed by etching, while the second bit line layer 32' in the sixth groove V6 is retained. At this time, the second bit line layer 32' is divided into multiple second bit lines 32 located in different layers, and these multiple second bit lines 32 are disconnected from each other.
  • a seventh insulating film is deposited to form a seventh insulating layer 17 that fills the third trench T3.
  • the seventh insulating layer 17 spacees two columns of memory cells in the same group, as shown in Figures 25A and 25B.
  • Figure 25A is a top view after the formation of the second bit line 32 provided in some embodiments
  • Figure 25B is a cross-sectional view perpendicular to the substrate 1 along the AA’ direction in Figure 25A.
  • the seventh insulating film may be a low-K dielectric layer, including but not limited to silicon oxide, such as silicon dioxide ( SiO2 ).
  • the sixth insulating layer 16 in the fourth initial hole K4 is removed by etching, and the fifth insulating layer 15 in the seventh groove V7 is removed by lateral etching based on the fourth initial hole K4.
  • a third gate insulating film and a third gate electrode film are sequentially deposited on the substrate 1 on which the aforementioned structure is formed, forming a third gate insulating layer 24c and a second word line 40b.
  • the third gate insulating layer 24c covers the bottom wall and sidewalls of the fourth initial hole K4, as well as the bottom wall and sidewalls of the seventh groove V7.
  • the third gate electrode film fills the fourth initial hole K4 and the seventh groove V7, as shown in Figures 26A, 26B, and 26C.
  • Figure 26A is a top view after forming the second word line 40b and the third gate insulating layer 24c according to some embodiments.
  • Figure 26B is a cross-sectional view perpendicular to the substrate 1 along the AA' direction in Figure 26A.
  • Figure 26C is a cross-sectional view perpendicular to the substrate 1 along the DD' direction in Figure 26A.
  • the aforementioned fourth hole may include the fourth initial hole K4 and the seventh groove V7.
  • the stacked structure is etched from the top layer to the bottom layer using dry etching (etching stops on the substrate 1) to form a fifth initial hole K5; the fifth initial hole K5 and the third hole K3 are respectively disposed on both sides of the second sub-trench extending along the second direction Y of the first trench T1; the sidewall of the fifth initial hole K5 exposes the second semiconductor structure layer 232' and the second semiconductor layer 23b; and the fifth initial hole K5 is close to the first trench T1 of the two first trenches T1 that define the memory cell where the fifth initial hole K5 is located, away from the fourth initial hole K4. For example, in two first trenches T1 that are adjacent along the second direction Y, the fourth initial hole K4 is close to one of the first trenches T1, and the fifth initial hole K5 is close to the other first trench T1.
  • the second semiconductor structure layer 232' and the second insulating layer 12 are laterally etched to form region V8.
  • the bottom wall of region V8 exposes the first insulating layer 11 and the seventh insulating layer 17. That is, the second semiconductor structure layer 232' is etched laterally along the first direction X and the second direction Y to expose the first insulating layer 11; the second insulating layer 12 is etched laterally along the first direction X to expose the first insulating layer 11 and the seventh insulating layer 17; and the second insulating layer 12 is etched laterally along the second direction Y to expose the first insulating layer 11 and the third gate insulating layer 24c, as shown in Figures 27A, 27B, and 27C.
  • Figure 27A is a top view after forming the fifth initial hole K5 according to some embodiments;
  • Figure 27B is a cross-sectional view perpendicular to the substrate 1 along the BB' direction in Figure 27A; and
  • Figure 27C is a cross-sectional view perpendicular to the substrate 1 along the DD' direction in Figure 27A.
  • the aforementioned fifth hole includes the fifth initial hole K5 and region V8.
  • the orthographic projection of the fifth initial hole K5 onto the substrate 1 is, for example, square. However, it is not limited to this and can be other shapes.
  • a fourth gate insulating film and a fourth gate electrode film are sequentially deposited on the substrate 1 on which the aforementioned structure is formed to form the fourth gate.
  • the fourth gate insulating layer 24d and the third word line 40c; the fourth gate insulating layer 24d covers the bottom wall and side wall of the fifth initial hole K5, and the bottom wall and side wall of the region V8, and the fourth gate electrode film fills the fifth initial hole K5 and the region V8, as shown in Figures 1A, 1B, 1C, 1D, 1E and 1F.
  • the disclosure also provides an electronic device, including the semiconductor device described in any of the foregoing embodiments, or a semiconductor device formed by the manufacturing method of the semiconductor device described in any of the foregoing embodiments.
  • the electronic device may be a storage device, a smartphone, a computer, a tablet computer, an artificial intelligence device, a wearable device, or a power bank, etc.
  • the storage device may include memory in a computer, etc., and is not limited thereto.

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Semiconductor Memories (AREA)

Abstract

一种半导体器件及其制造方法、电子设备，涉及半导体技术领域，包括：多层存储单元、贯穿多层的第一字线(40a)、第二字线(40b)和第三字线(40c)；第二字线(40b)和第三字线(40c)沿第二方向分布，存储单元包括沿第一方向分布的第一晶体管和第二晶体管；第一晶体管包括部分环绕第一栅电极(26a)的第一半导体层(23a)和设置在第一半导体层(23a)背离第一栅电极(26a)一侧的第二栅电极(26b)；不同层相同位置的第一栅电极(26a)垂直延伸且间隔分布；第一栅电极(26a)未被第一半导体层(23a)环绕的部分区域与第二晶体管的第二半导体层(23b)连接；第三字线(40c)形成有开口朝向第二字线(40b)的间隔分布的多个第一凹槽，第一凹槽分布有第二半导体层(23b)，第二字线(40b)形成有朝向第一凹槽的凸起。

Description

一种半导体器件及其制造方法、电子设备
本申请要求于2024年5月15日提交的、申请号为202410606499.4、发明名称为“一种半导体器件及其制造方法、电子设备”的中国专利申请的优先权，其内容应理解为通过引用的方式并入本申请中。
技术领域
本公开实施例涉及但不限于半导体技术领域的器件设计及其制造，尤指一种半导体器件及其制造方法、电子设备。
背景技术
随着集成电路技术的发展，器件的关键尺寸日益缩小，单个芯片所包含的器件种类及数量随之增加，使得工艺生产中的任何微小差异都可能对器件性能造成影响。
为了尽可能降低产品的成本，人们希望在有限的衬底上做出尽可能多的器件单元。自从摩尔定律问世以来，业界提出了各种半导体结构设计和工艺优化，以满足人们对当前产品的需求。
发明内容
以下是对本文详细描述的主题的概述。本概述并非是为了限制权利要求的保护范围。
本申请提供了一种半导体器件，包括：多层沿垂直于衬底的方向堆叠的存储单元、贯穿多层相同位置的所述存储单元的沿垂直于衬底方向延伸的第一字线、贯穿多层相同位置的所述存储单元的沿垂直于衬底方向延伸的第二字线和贯穿多层相同位置的所述存储单元的沿垂直于衬底方向延伸的第三字线；
所述存储单元包括：第一晶体管和第二晶体管，所述第一晶体管和第二晶体管沿平行于所述衬底的第一方向分布；所述第二字线和第三字线沿平行于所述衬底的第二方向分布，所述第一方向和所述第二方向交叉；
所述第一晶体管包括：第一栅电极、第二栅电极和第一半导体层，不同层相同位置的存储单元的所述第一栅电极沿垂直于所述衬底的方向延伸且间隔分布；所述第一半导体层部分环绕所述第一栅电极；所述第二栅电极设置在所述第一半导体层背离所述第一栅电极一侧，不同层相同位置的第一晶体管的第二栅电极为所述第一字线的一部分；
所述第二晶体管包括：第二半导体层；所述第一栅电极未被所述第一半导体层环绕的部分区域与所述第二半导体层连接；所述第二半导体层部分环绕所述第二字线；所述第三字线形成有开口朝向所述第二字线的沿垂直于衬底方向间隔分布的多个第一凹槽，所述第一凹槽的底壁和侧壁分布有所述第二半导体层，所述第二字线形成有分别朝向多个所述第一凹槽的多个凸起。
在一些实施例中，所述第一半导体层包括第一半导体子层和设置在所述第一半导体子层背离所述第一栅电极一侧的第二半导体子层，所述第一半导体子层部分环绕所述第一栅电极，所述第二半导体子层的掺杂浓度大于所述第一半导体子层的掺杂浓度，所述第二半导体子层包括在所述第一半导体子层背离所述第一栅电极的表面上间隔设置的第一部分和第二部分。
在一些实施例中，所述第一字线分布在所述第一半导体子层背离所述第一栅电极一侧的侧壁上所述第一部分和所述第二部分之间的区域。
在一些实施例中，所述第一晶体管还包括第一电极和第二电极，所述第一电极连接所述第一部分，所述第二电极连接所述第二部分，所述第二部分环绕所述第二电极，不同层相同位置的第一晶体管的第二电极连接形成沿垂直于衬底方向延伸的一体式结构。
在一些实施例中，同层沿所述第二方向分布的同一列的所述第一晶体管的所述第一部分相互连接形成一体式结构，同层沿所述第二方向分布的同一列的所述第一晶体管的所述第二部分相互分离。
在一些实施例中，沿所述第二方向分布的同一列的所述第一晶体管的所述第一电极连接形成沿所述第二方向延伸的第一位线。
在一些实施例中，所述第二电极和所述第一字线设置在所述第一部分的同侧，以及，设置在所述第一栅电极的同侧。
在一些实施例中，所述半导体器件还包括贯穿多层所述第一晶体管的隔离层；不同层相同位置的第一栅电极部分环绕所述隔离层且沿垂直于衬底方向依次分布在所述隔离层的侧壁的不同区域。
在一些实施例中，所述第一晶体管还包括设置在所述第一栅电极和所述第一半导体子层之间的第一栅极绝缘层，不同层相同位置的第一晶体管的第一栅极绝缘层连接形成沿垂直于衬底方向延伸的一体式结构。
在一些实施例中，所述半导体器件还包括：
沿着垂直所述衬底的方向从上至下依次交替分布的绝缘层和导电层；
贯穿所述绝缘层和所述导电层的第一孔、第二孔、第三孔；
所述第一孔从外到内依次分布有所述第一半导体子层、所述第一栅极绝缘层、所述第一栅电极、所述隔离层，且所述隔离层填充所述第一孔；
所述第二孔从外到内依次分布有第二栅极绝缘层、所述第一字线，且所述第一字线填充所述第二孔；
所述第三孔中仅分布有信号线，且所述信号线填充所述第三孔，不同层相同位置的第一晶体管的第二电极为所述信号线的一部分。
在一些实施例中，所述第一孔在所述绝缘层的子孔在所述衬底的正投影中，靠近所述第一字线的边界、靠近所述第二字线的边界、背离所述第二字线的边界落入所述第一孔在所述导电层的子孔在所述衬底的正投影内，背离所述第一字线的边界落在所述第一孔在所述导电层的子孔在所述衬底的正投影的边界上。
在一些实施例中，所述半导体器件还包括：贯穿所述绝缘层和所述导电层的第四孔，且所述第四孔从外到内依次分布有所述第二半导体层、第三栅极绝缘层、第二字线，所述第二字线填充所述第四孔，所述第四孔的侧壁暴露所述第一栅电极，且所述第四孔在所述绝缘层的子孔在所述衬底的正投影中，靠近所述第一栅电极的边界和靠近所述第三字线的边界落入所述第四孔在所述导电层的子孔在所述衬底的正投影内，背离所述第一栅电极的边界和背离所述第三字线的边界落在所述第四孔在所述导电层的子孔在所述衬底的正投影的边界上。
在一些实施例中，所述半导体器件还包括，设置在所述第二字线背离所述第一栅电极一侧且沿第二方向延伸的第二横向凹槽，所述第二横向凹槽与所述第四孔连通，所述第二 横向凹槽的开口背离所述第二字线和所述第三字线，所述第二半导体层还分布在所述第二横向凹槽的侧壁和底壁。
在一些实施例中，沿所述第二方向分布的同一列的第二晶体管的第二半导体层之间断开。
在一些实施例中，所述半导体器件还包括：分布在设置有所述第二半导体层的所述第二横向凹槽中且填充所述第二横向凹槽的第二位线。
在一些实施例中，所述半导体器件还包括：贯穿所述绝缘层和所述导电层的第五孔，且所述第五孔从外到内依次分布有第四栅极绝缘层和所述第三字线，所述第三字线填充所述第五孔；且所述第五孔在所述导电层的子孔在所述衬底的正投影中，靠近所述第二位线的边界和靠近所述第二字线的边界落入所述第五孔在所述绝缘层的子孔在所述衬底的正投影内，背离所述第二位线的边界和背离所述第二字线的边界落在所述第五孔在所述绝缘层的子孔在所述衬底的正投影的边界上。
本公开实施例提供一种半导体器件的制造方法，包括：
提供衬底，在所述衬底上形成包括交替设置的功能层和牺牲层的堆叠结构，所述堆叠结构包括多个存储单元区，所述存储单元区包括沿平行于衬底的第一方向分布的第一晶体管区和第二晶体管区；
在所述第一晶体管区形成设置在所述功能层的第一栅电极和第一半导体层，以及，形成沿垂直于衬底方向贯穿每层的第一字线，所述第一半导体层部分环绕所述第一栅电极，所述第一字线设置在所述第一半导体层背离所述第一栅电极一侧，不同层相同位置的存储单元的所述第一栅电极沿垂直于所述衬底的方向堆叠且间隔分布，不同层相同位置的第一晶体管的第二栅电极为所述第一字线的一部分；
在所述第二晶体管区形成第二字线、第三字线和第二半导体层；所述第一栅电极与所述第二半导体层连接；所述第二半导体层部分环绕所述第二字线；所述第三字线形成有开口朝向所述第二字线的沿垂直于衬底方向间隔分布的多个第一凹槽，所述第一凹槽的底壁和侧壁分布有所述第二半导体层，所述第二字线形成有分别朝向多个所述第一凹槽的多个凸起。
在一些实施例中，在所述衬底上形成包括交替设置的功能层和牺牲层的堆叠结构包括：
在所述衬底上依次沉积半导体薄膜和牺牲层薄膜，形成包括交替设置的半导体结构层和牺牲层的堆叠结构；
对所述堆叠结构进行构图，形成贯穿每层的T形的第一沟槽，所述第一沟槽包括沿第一方向延伸的第一子沟槽和由所述第一子沟槽的非端部沿平行于所述衬底的第二方向延伸的第二子沟槽；沿第二方向间隔分布的相邻的第一子沟槽之间包括所述存储单元区，所述第一晶体管区和所述第二晶体管区分别设置在所述第二子沟槽两侧；所述第一方向和所述第二方向交叉；
在所述第一晶体管区靠近一个第一沟槽的第一子沟槽处形成沿垂直于所述衬底的方向上贯穿所述堆叠结构的第一孔，所述第一孔的侧壁暴露所述第一子沟槽，通过所述第一孔刻蚀去除所述牺牲层，并将所述牺牲层替换为绝缘层。
在一些实施例中，在所述第一晶体管区形成设置在所述功能层的第一栅电极和第一半导体层，以及，形成沿垂直于衬底方向贯穿每层的第一字线包括：
基于所述第一孔沿平行于所述衬底的方向刻蚀所述半导体结构层；在所述第一孔内形成多个第一半导体子层、第一栅极绝缘层、多个栅电极和隔离层；所述多个第一栅电极沿 垂直于衬底方向间隔分布，所述多个第一半导体子层部分环绕所述第一栅电极且沿垂直于衬底方向间隔分布，所述第一栅极绝缘层设置在所述第一半导体子层和所述第一栅电极之间，所述第一栅电极部分环绕所述隔离层，所述隔离层填充所述第一孔；
在所述第一晶体管区靠近另一个第一沟槽的第一子沟槽处形成沿垂直于所述衬底的方向上贯穿所述堆叠结构的第二孔，基于所述第二孔沿平行于所述衬底的方向刻蚀所述半导体结构层以暴露所述第一半导体子层，在所述第二孔内依次形成第二栅极绝缘层和填充所述第二孔的第一字线；所述第一孔和所述第二孔将所述第一晶体管区的半导体结构层间隔为包括独立的第一部分和第二部分的第二半导体子层；
所述方法还包括：
在所述第一晶体管区内所述第二孔和所述第二子沟槽之间形成沿垂直于所述衬底的方向上贯穿所述堆叠结构的第三孔，所述第三孔的侧壁暴露所述第二半导体子层的第二部分，在所述第三孔内形成填充所述第三孔且与所述第二半导体子层的第二部分接触的信号线。
在一些实施例中，在所述第二晶体管区形成第二字线、第三字线和第二半导体层包括：
在所述第二晶体管区形成沿垂直于所述衬底的方向上贯穿所述堆叠结构的第四孔，基于所述第四孔沿平行于所述衬底的方向刻蚀所述半导体结构层、所述第一半导体子层、所述第一栅极绝缘层以暴露所述第一栅电极，形成横向凹槽；在所述依次第四孔内依次形成第二半导体层、第三栅极绝缘层和填充所述第四孔的第二字线，且所述第二半导体层形成在所述横向凹槽的底壁和侧壁；
在所述第二晶体管区形成沿垂直于所述衬底的方向上贯穿所述堆叠结构的第五孔，所述第五孔与所述第四孔沿第二方向分布，基于所述第五孔沿平行于所述衬底的方向刻蚀所述半导体结构层、所述绝缘层以暴露所述第三栅极绝缘层和所述第二半导体层，在所述第五孔内依次形成第四栅极绝缘层和填充所述第五孔的第三字线。
在一些实施例中，还包括：
在沿第一方向相邻的第一晶体管区之间形成贯穿每层的第二沟槽，所述第二沟槽沿第二方向延伸；在所述第二沟槽内横向刻蚀所述半导体结构层且不暴露所述第一半导体子层，形成第一横向沟槽，在所述第一横向沟槽内形成填充所述第一横向沟槽的第一位线。
在一些实施例中，还包括：
在沿第一方向相邻的第二晶体管区之间形成贯穿每层的沿第二方向延伸的第三沟槽；在所述第三沟槽内横向刻蚀所述半导体结构层，形成第二横向沟槽，且所述第二横向沟槽与所述第四孔连通；
在所述第四孔内形成所述第二半导体层时，还在所述第二横向沟槽的内壁上形成所述第二半导体层；在形成有所述第二半导体层的所述第二横向沟槽内形成填充所述第二横向沟槽的第二位线。
本公开实施例提供一种电子设备，包括上述任一所述的半导体器件，或者，根据上述任一所述的半导体器件的制造方法形成的半导体器件。
本申请的其它特征和优点将在随后的说明书中阐述，并且，部分地从说明书中变得显而易见，或者通过实施本申请而了解。本申请的其他优点可通过在说明书以及附图中所描述的方案来实现和获得。
在阅读并理解了附图和详细描述后，可以明白其他方面。
附图概述
附图用来提供对本申请技术方案的理解，并且构成说明书的一部分，与本申请的实施例一起用于解释本申请的技术方案，并不构成对本申请技术方案的限制。
图1A为一些实施例提供的半导体器件的俯视图，图1B为沿图1A中AA’方向的垂直于衬底的截面图，图1C为沿图1A中BB’方向的垂直于衬底的截面图，图1D为沿图1A中CC’方向的垂直于衬底的截面图，图1E为沿图1A中DD’方向的垂直于衬底的截面图，图1F为沿图1B中FF’方向的平行于衬底的截面图；图1G为一示例性实施例提供的半导体器件的等效电路图；
图2A为一些实施例提供的形成堆叠结构后的俯视图，图2B为沿图2A中AA’方向的垂直于衬底的截面图；
图3A为一些实施例提供的形成第一沟槽和第一绝缘层后的俯视图，图3B为沿图3A中EE’方向的垂直于衬底的截面图；
图4A为一些实施例提供的形成第一初始孔后的俯视图，图4B为沿图4A中AA’方向的垂直于衬底的截面图；
图5A为一些实施例提供的形成第二绝缘层后的俯视图，图5B为沿图5A中AA’方向的垂直于衬底的截面图；
图6A为一些实施例提供的暴露第一初始孔后的俯视图，图6B为沿图6A中AA’方向的垂直于衬底的截面图；
图7A为一些实施例提供的形成第一凹槽后的俯视图，图7B为沿图7A中AA’方向的垂直于衬底的截面图；
图8A为一些实施例提供的形成第一半导体结构层后的俯视图，图8B为沿图8A中AA’方向的垂直于衬底的截面图；
图9A为一些实施例提供的形成第一半导体子层后的俯视图，图9B为沿图9A中AA’方向的垂直于衬底的截面图；
图10A为一些实施例提供的形成第一导电层和第一栅极绝缘层后的俯视图，图10B为沿图10A中AA’方向的垂直于衬底的截面图；
图11A为一些实施例提供的形成第一栅电极后的俯视图，图11B为沿图11A中AA’方向的垂直于衬底的截面图；
图12A为一些实施例提供的形成第二初始孔和第三凹槽后的俯视图，图12B为沿图12A中BB’方向的垂直于衬底的截面图，图12C为沿图12A中CC’方向的垂直于衬底的截面图；
图13A为一些实施例提供的形成第二栅极绝缘层和第一字线后的俯视图，图13B为沿图13A中BB’方向的垂直于衬底的截面图，图13C为沿图13A中CC’方向的垂直于衬底的截面图；
图14A为一些实施例提供的形成第三孔后的俯视图，图14B为沿图14A中BB’方向的垂直于衬底的截面图；
图15A为一些实施例提供的形成信号线后的俯视图，图15B为沿图15A中BB’方向的垂直于衬底的截面图；
图16A为一些实施例提供的形成第二沟槽后的俯视图，图16B为沿图16A中BB’方向的垂直于衬底的截面图；
图17A为一些实施例提供的形成第一位线层后的俯视图，图17B为沿图17A中BB’方向的垂直于衬底的截面图；
图18A为一些实施例提供的形成第一位线和第四绝缘层后的俯视图，图18B为沿图18A中BB’方向的垂直于衬底的截面图；
图19A为一些实施例提供的形成第四初始孔和第三沟槽后的俯视图，图19B为沿图19A中AA’方向的垂直于衬底的截面图，图19C为沿图19A中DD’方向的垂直于衬底的截面图；
图20A为一些实施例提供的形成第五凹槽后的俯视图，图20B为沿图20A中AA’方向的垂直于衬底的截面图，图20C为沿图20A中DD’方向的垂直于衬底的截面图；
图21A为一些实施例提供的形成第三半导体结构层后的俯视图，图21B为沿图21A中AA’方向的垂直于衬底的截面图，图21C为沿图21A中DD’方向的垂直于衬底的截面图；
图22A为一些实施例提供的形成第二半导体层后的俯视图，图22B为沿图22A中AA’方向的垂直于衬底的截面图，图22C为沿图22A中DD’方向的垂直于衬底的截面图；
图23A为一些实施例提供的形成第六凹槽后的俯视图，图23B为沿图23A中AA’方向的垂直于衬底的截面图；
图24A为一些实施例提供的形成第二位线层后的俯视图，图24B为沿图24A中AA’方向的垂直于衬底的截面图；
图25A为一些实施例提供的形成第二位线后的俯视图，图25B为沿图25A中AA’方向的垂直于衬底的截面图；
图26A为一些实施例提供的形成第二字线和第三栅极绝缘层后的俯视图，图26B为沿图26A中AA’方向的垂直于衬底的截面图，图26C为沿图26A中DD’方向的垂直于衬底的截面图；
图27A为一些实施例提供的形成第五初始孔后的俯视图，图27B为沿图27A中BB’方向的垂直于衬底的截面图，图27C为沿图27A中DD’方向的垂直于衬底的截面图。
详述
下文中将结合附图对本公开实施例进行详细说明。在不冲突的情况下，本公开实施例及实施例中的特征可以相互任意组合。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。
本公开的实施方式并不一定限定附图所示尺寸，附图中各部件的形状和大小不反映真实比例。此外，附图示意性地示出了理想的例子，本公开的实施方式不局限于附图所示的形状或数值。
本公开中的“第一”、“第二”、“第三”等序数词是为了避免构成要素的混同而设置，并不表示任何顺序、数量或者重要性。
在本公开中，为了方便起见，使用“中部”、“上”、“下”、“前”、“后”、“竖直”、“水平”、 “顶”、“底”、“内”、“外”等指示方位或位置关系的词句以参照附图说明构成要素的位置关系，仅是为了便于描述本说明书和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本公开的限制。构成要素的位置关系根据描述各构成要素的方向适当地改变。因此，不局限于在公开中说明的词句，根据情况可以适当地更换。
在本公开中，除非另有明确的规定和限定，术语“安装”、“相连”、“连接”应做广义理解。例如，可以是物理连接或信号连接，可以是接触连接或一体地连接；可以是直接相连，或通过中间件间接相连，或两个元件内部的连通。对于本领域的普通技术人员而言，可以根据具体情况理解上述术语在本公开中的具体含义。
在本公开中，晶体管是指至少包括栅电极、漏电极以及源电极这三个端子的元件。晶体管在漏电极(漏电极端子、漏区域或漏电极)与源电极(源电极端子、源区域或源电极)之间具有沟道区域，并且电流能够流过漏电极、沟道区域以及源电极。在本公开中，沟道区域是指电流主要流过的区域。
在本公开中，可以是第一电极为漏电极、第二电极为源电极，或者可以是第一电极为源电极、第二电极为漏电极。在使用极性相反的晶体管的情况或电路工作中的电流方向变化的情况等下，“源电极”及“漏电极”的功能有时互相调换。因此，在本公开中，“源电极”和“漏电极”可以互相调换。
在本公开中，“连接”包括构成要素通过具有某种电作用的元件连接在一起的情况。“具有某种电作用的元件”只要可以进行连接的构成要素间的电信号的授受，就对其没有特别的限制。“具有某种电作用的元件”的例子不仅包括电极和布线，而且还包括晶体管等开关元件、电阻器、电感器、电容器、其它具有各种功能的元件等。
在本公开中，“平行”是指大约平行或几乎平行，比如，两条直线形成的角度为-10°以上且10°以下的状态，因此，也包括该角度为-5°以上且5°以下的状态。另外，“垂直”是指大约垂直，比如，两条直线形成的角度为80°以上且100°以下的状态，因此，也包括85°以上且95°以下的角度的状态。
本公开实施例中的“A和B为一体式结构”可以是指在微观结构上无明显的断层或间隙等明显的分界界面。一般地，在一个膜层上图案化形成连接的膜层为一体式。比如A和B使用相同的材料成一个膜层并通过同一次图案化工艺同时形成具有连接关系的结构。
本公开实施例中“B的正投影位于A的正投影的范围之内”，是指B的正投影的边界落入A的正投影的边界范围内，或者A的正投影的边界与B的正投影的边界重叠。
图1A为一些实施例提供的半导体器件俯视图，图1B为沿图1A中AA’方向的垂直于衬底1的截面图；图1C为沿图1A中BB’方向的垂直于衬底1的截面图，图1D为沿图1A中DD’方向的垂直于衬底1的截面图，图1E为沿图1A中DD’方向的垂直于衬底1的截面图，图1F为沿图1B中FF’方向的平行于衬底1的截面图。如图1A至图1F所示，本公开实施例提供一种半导体器件，包括在衬底1上垂直堆叠的多层存储单元阵列，所述多层存储单元阵列可以沿第三方向Z分布。所述第三方向Z可以垂直于所述衬底1。
所述存储单元阵列可以包括多条第一位线31、多条第二位线32、多条第一字线40a、多条第二字线40b、多条第三字线40c和多个存储单元。每个所述存储单元阵列可以包括沿平行于所述衬底1的第一方向X和平行于所述衬底1的第二方向Y阵列分布的多个存储单元。所述第一方向X和第二方向Y可以交叉。在一些实施例中，所述第一方向X和第二方向Y可以垂直。每两列存储单元作为一组。
如图1B和图1C所示，所述第一位线31可以是沿第二方向Y延伸的导电线。所述 第二位线32可以是沿第二方向Y延伸的导电线。同一存储单元阵列的多条第一位线31可以彼此间隔，同一存储单元阵列的所述多条第一位线31可以沿第一方向X间隔分布。同一存储单元阵列的多条第二位线32可以彼此间隔，同一存储单元阵列的所述多条第二位线32可以沿第一方向X间隔分布。不同存储单元阵列的第一位线31可以堆叠设置在衬底1上，不同层相同位置的第一位线31彼此间隔。不同存储单元阵列的第二位线32可以堆叠设置在衬底1上，不同层相同位置的第二位线32彼此间隔。
沿第二方向Y分布的每列存储单元连接到同一第一位线31和同一第二位线32，与同一组的两列存储单元分别连接的两条第二位线32设置在与该组的两列存储单元分别连接的两条第一位线31之间。
所述存储单元可以包括第一晶体管和第二晶体管。同一存储单元的第一晶体管和第二晶体管可以沿第一方向X分布。
所述第一字线40a、第二字线40b、第三字线40c可以沿第三方向Z延伸，不同层相同位置在垂直方向堆叠的多个存储单元共用一条所述第一字线40a，共用一条所述第二字线40b，以及，共用一条所述第三字线40c；同层的不同存储单元对应不同的第一字线40a，以及，对应不同的第二字线40b，以及，对应不同的第三字线40c。
下面以包括相同位置的多个垂直堆叠的存储单元的半导体器件为例进行说明，且以存储单元为2T0C为例说明。
如图1A至1F所示，本公开实施例提供一种半导体器件，所述半导体器件可以包括：
衬底1，设置在衬底1上的至少一个存储单元，所述存储单元可以包括第一晶体管和第二晶体管，所述第一晶体管可以包括第一栅电极26a、第二栅电极26b、第一电极51和第二电极52、第一半导体层23a。所述第二晶体管可以包括第三栅电极26c、第四栅电极26d、第三电极53和第四电极54、第二半导体层23b。所述第二半导体层23b部分环绕所述第二字线40b；所述第三字线40c形成有开口朝向所述第二字线40b的沿垂直于衬底1方向间隔分布的多个第一凹槽，所述第一凹槽的底壁和侧壁分布有所述第二半导体层23b，所述第二字线40b形成有分别朝向多个所述第一凹槽的多个凸起。
本实施例提供的方案，通过双字线控制选通对应的存储单元的第二晶体管，可以无需单独设置选通晶体管即可实现存储阵列中对应的存储单元的选通，可以简化存储阵列外围选通电路结构及制作工艺。
所述第一栅电极26a可以沿垂直于衬底1方向延伸，所述第一栅电极26a可以形成开口方向背离所述第一字线40a的凹槽，第一栅电极26a形成的凹槽可以包括沿垂直于衬底1方向延伸的底壁和沿垂直于衬底1方向延伸的两个侧壁。不同层相同位置的存储单元的所述第一栅电极26a沿垂直于所述衬底1的方向延伸且间隔分布。
比如，第一栅电极26a可以包括沿平行于第一方向X延伸且垂直于衬底1的一个底壁，和沿平行于第二方向Y延伸且垂直于衬底1的两个侧壁。
所述第一半导体层23a可以包括第一半导体子层231和第二半导体子层232，所述第一半导体子层231可以沿垂直于衬底1方向延伸，如图1F所示，所述第一半导体子层231可以分布在所述第一栅电极26a形成的凹槽的外侧壁(即凹槽的外表面)，且部分环绕所述第一栅电极26a。
所述第二半导体子层232设置在所述第一半导体子层231背离所述第一栅电极26a一侧，所述第二半导体子层232的掺杂浓度大于所述第一半导体子层231的掺杂浓度，所述第二半导体子层232可以包括在所述第一半导体子层231背离所述第一栅电极26a的表 面上间隔设置的第一部分2321和第二部分2322。上述方案，将高掺杂浓度的子层设置在低掺杂浓度的子层外侧壁，便于分别提前形成低掺杂浓度的子层和高掺杂浓度的子层，避免了在半导体器件制作过程中进行额外的较为复杂的掺杂操作，简化了工艺。
其中，所述第二半导体子层232可以是重掺杂的半导体膜层，所述第一半导体子层231可以是轻掺杂或者未掺杂的半导体膜层，从而便于将第一半导体子层231作为第一晶体管的沟道区域，将第二半导体子层232的两部分分别作为第二晶体管的源接触区域和漏接触区域，分别与源电极和漏电极接触。
在一些实施例中，所述第二半导体子层232的第一部分2321沿垂直于衬底1方向的高度可以和所述第二半导体子层232的第二部分2322沿垂直于衬底1方向的高度相同或大致相同。
所述第一电极51与所述第二半导体子层232的第一部分2321连接，所述第一电极51设置在所述第一部分2321背离所述第一栅电极26a一侧。
在一些实施例中，所述第二半导体子层232可以沿第二方向Y延伸。该方案便于通过堆叠掺杂浓度高的半导体膜层，刻蚀该半导体膜层得到所述第二半导体子层232，无需对不同层的半导体层进行掺杂。
在一些实施例中，如图1F所示，同层的沿第二方向Y方向分布的同一列的第一晶体管的第二半导体子层232的第一部分2321可以连接形成一体式结构。该一体式结构可以沿第二方向Y延伸。但本公开实施例不限于此，同层的沿第二方向Y方向分布的同一列的晶体管的第二半导体子层232的第一部分2321可以相互分离。
在一些实施例中，如图1F所示，同层的沿第二方向Y方向分布的同一列的第一晶体管的第二半导体子层232的第二部分2322可以相互分离。
在一些实施例中，所述第一位线31可以为平行于衬底1的条状电极，所述条状电极的一部分可以是第一晶体管的第一电极51，所述条状电极的侧壁与所述第二半导体子层232的第一部分2321连接，或者，第一位线31可以具有一体式设计的分支，所述分支与所述第二半导体子层232的第一部分2321连接，其中，所述分支的延伸方向与所述第一位线31的延伸方向交叉，如大约垂直，所述分支可以是第一晶体管的第一电极51。
所述分支可以是在第一位线31的一个侧壁上的多个分支，每个分支对应连接一个第一晶体管的所述第二半导体子层232的第一部分2321。
在一些实施例中，所述第一半导体子层231和所述第一栅电极26a之间设置有沿垂直于所述衬底1方向延伸的第一栅极绝缘层24a。
在一些实施例中，不同层相同位置的多个第一晶体管的第一栅极绝缘层24a可以连接形成一体式结构。本实施例提供的方案，便于一次性形成多个第一晶体管的第一栅极绝缘层24a，可以简化工艺。
在一些实施例中，不同层相同位置的多个第一晶体管的第一栅电极26a彼此之间间隔设置，比如，物理上断开。
在一些实施例中，如图1A、图1B、图1F所示，所述半导体器件还可以包括沿垂直于衬底1方向延伸贯穿多个第一晶体管的隔离层13，所述第一栅电极26a可以部分环绕所述隔离层13，不同层相同位置的多个第一晶体管的多个第一栅电极26a部分环绕所述隔离层13的不同区域，即不同层相同位置的多个第一晶体管的多个第一栅电极26a沿垂直于衬底1方向依次分布在所述隔离层13的侧壁的不同区域，所述第一栅极绝缘层24a部分环绕所述隔离层13，所述第一半导体子层231部分环绕所述隔离层13。
在一些实施例中，如图1F所示，隔离层13靠近一个第一子沟槽，第一栅电极26a部分环绕隔离层13，且不环绕所述隔离层13朝向所靠近的第一子沟槽一侧，即，第一栅电极26a环绕隔离层13的三个侧壁；第一栅极绝缘层24a环绕所述隔离层13且仅在朝向第二晶体管区一侧存在缺口，以暴露所述第一栅电极26a；第一半导体子层231分布在第一栅电极26a的外侧壁且在朝向所述第二晶体管一侧存在缺口，以暴露所述第一栅电极26a。第一栅电极26a未被所述第一半导体层23a环绕的部分区域与所述第二半导体层23b连接。第二半导体层23b和第一半导体子层231之间被第一栅极绝缘层24a间隔。
在一些实施例中，所述第二电极52与所述第二半导体子层232的第二部分2322连接，所述第二部分2322可以环绕所述第二电极52。在一些实施例中，所述第二部分2322可以全环绕所述第二电极52，或者部分环绕所述第二电极52，即第二部分2322平行于衬底1的截面可以是闭环或者开环。所述第二部分2322部分环绕所述第二电极52时，第二部分2322占用的面积更小，可以减小器件面积。
在一些实施例中，所述第二栅电极26b可以是第一字线40a的一部分，不同层相同位置的第一晶体管的第二栅电极26b可以为同一第一字线40a的一部分，不同层相同位置的第一晶体管的第二栅电极26a可以连接形成一体式结构的第一字线40a。
在一些实施例中，所述第一字线40a可以分布在所述第一半导体子层231背离所述第一栅电极26a一侧的侧壁上所述第一部分2321和所述第二部分2322之间的区域。
在一些实施例中，所述第二电极52和所述第一字线40a可以设置在所述第一部分2321的同侧，以及，设置在所述第一栅电极26a的同侧。
在一些实施例中，所述第三栅电极26c可以是第二字线40b的一部分，不同层相同位置的第二晶体管的第三栅电极26c可以为同一第二字线40b的一部分。不同层相同位置的第二晶体管的第三栅电极26c可以连接形成一体式结构的第二字线40b。
在一些实施例中，所述第四栅电极26d可以是第三字线40c的一部分，不同层相同位置的第二晶体管的第四栅电极26d可以为同一第三字线40c的一部分。不同层相同位置的第二晶体管的第四栅电极26d可以连接形成一体式结构的第三字线40c。
在一些实施例中，所述第一电极51可以连接到第一位线31，或者，所述第一电极51可以是第一位线31的一部分。同一存储单元阵列的同一列的存储单元的第一晶体管的第一电极51可以连接到同一第一位线31。即，沿所述第二方向Y分布的同一列的所述第一晶体管的所述第一电极51连接形成沿所述第二方向Y延伸的第一位线31。同一存储单元阵列的相邻列的存储单元的第一晶体管的所述第一电极51可以连接到不同第一位线31。
在一些实施例中，所述第四电极54可以连接到第二位线32，或者，所述第四电极54可以是第二位线32的一部分。同一存储单元阵列的同一列的存储单元的第二晶体管的第四电极54可以连接到同一第二位线32。即，沿所述第二方向Y分布的同一列的所述第二晶体管的所述第四电极54连接形成沿所述第二方向Y延伸的第二位线32。同一存储单元阵列的相邻列的存储单元的第二晶体管的所述第四电极54可以连接到不同第二位线32。
在一些实施例中，所述第一栅电极26a可以连接到第三电极53，或者，第一栅电极26a和第三电极53复用同一电极。
不同层相同位置的第一晶体管的第二电极52可以连接。所述半导体器件还可以包括沿垂直于衬底1方向延伸的信号线52’，不同层相同位置的第二电极52连接形成一体式结构的所述信号线52’。
在一些实施例中，所述半导体器件可以包括沿垂直于衬底1方向贯穿多层的T形第 一沟槽T1，所述第一沟槽T1可以包括沿第一方向X延伸的第一子沟槽和由所述第一子沟槽的非端部沿平行于所述衬底1的第二方向Y延伸的第二子沟槽；沿第二方向Y间隔分布的相邻的第一子沟槽之限定一个存储单元区，存储单元区中所述第二子沟槽的两侧分别称为第一晶体管区和第二晶体管区，且第一晶体管区和第二晶体管区之间连通，未被第二子沟槽完全隔断。第一沟槽T1中可以填充第一绝缘层11。所述第一栅电极26a、所述第一字线40a、所述信号线52’可以设置在第一晶体管区，所述第三字线40c可以设置在第二晶体管区，所述第二半导体层23b可以设置在第二晶体管区，且从第二晶体管区延伸到第一晶体管区与所述第一栅电极26a连接，所述第二字线40b可以设置在第二晶体管区，且延伸到第一晶体管区。第一字线40a、信号线52’和第三字线40c可以沿第一方向X分布，第一栅电极26a、第二字线40b可以沿第一方向X分布。该排布方式可以在满足第一栅电极26a和第二半导体层23b连接的情况下，第一字线40a、信号线52’和第三字线40c沿第一方向X分布，尽量紧凑布局，减小器件面积。
在一些实施例中，所述半导体器件还可以包括：
沿着垂直所述衬底1的方向从上至下依次交替分布的绝缘层和导电层；所述导电层可以包括第一半导体层23a、第一栅电极26a、第二半导体层23b、第一位线31；第二位线32；
贯穿所述绝缘层和所述导电层的第一孔、第二孔、第三孔；
所述第一孔从外到内依次分布有所述第一半导体子层231、所述第一栅极绝缘层24a、所述第一栅电极26a、所述隔离层13，且所述隔离层13填充所述第一孔；
所述第二孔从外到内依次分布有第二栅极绝缘层24b、所述第一字线40a，且所述第一字线40a填充所述第二孔；
所述第三孔中仅分布有信号线52’，且所述信号线52’填充所述第三孔。
在一些实施例中，所述第一孔在所述绝缘层的子孔在所述衬底1的正投影中，靠近所述第一字线40a的边界、靠近所述第二字线40b的边界、背离所述第二字线40b的边界落入所述第一孔在所述导电层的子孔在所述衬底1的正投影内，背离所述第一字线40a的边界落在所述第一孔在所述导电层的子孔在所述衬底1的正投影的边界上。即，第一孔的一个侧壁暴露位于第一子沟槽的第一绝缘层11，第一孔朝向该第一子沟槽的边界沿垂直于衬底1的方向直线延伸。本实施例提供的方案，可以使得第一晶体管区沿第二方向Y的尺寸尽量减小，减小器件面积。
在一些实施例中，所述第二孔位于所述绝缘层的子孔的孔径可以小于所述第二孔位于所述导电层的子孔的孔径。
在一些实施例中，所述第三孔位于所述绝缘层的子孔的孔径可以等于所述第三孔位于所述导电层的子孔的孔径。本实施例提供的方案，可以一次性形成第三孔，工艺简单。
在一些实施例中，所述半导体器件还可以包括：贯穿所述绝缘层和所述导电层的第四孔，且所述第四孔从外到内依次分布有所述第二半导体层23b、第三栅极绝缘层24c、第二字线40b，所述第二字线40b填充所述第四孔，所述第四孔的侧壁暴露所述第一栅电极26a，且所述第四孔在所述绝缘层的子孔在所述衬底1的正投影中，靠近所述第一栅电极26a的边界和靠近所述第三字线40c的边界落入所述第四孔在所述导电层的子孔在所述衬底1的正投影内，背离所述第一栅电极26a的边界和背离所述第三字线40c的边界落在所述第四孔在所述导电层的子孔在所述衬底1的正投影的边界上。如图1B所示，第四孔背离第一栅电极26a的侧壁在绝缘层和导电层沿垂直于衬底1的方向直线延伸。如图1E所示，第四孔的一个侧壁暴露位于第一子沟槽的第一绝缘层11，第四孔朝向该第一子沟槽 的侧壁(即背离第三字线40c的侧壁)在绝缘层和导电层沿垂直于衬底1的方向直线延伸。本实施例提供的方案，可以使得第二晶体管区沿第二方向Y的尺寸尽量减小，减小器件面积。
在一些实施例中，如图1B和图1C所示，所述半导体器件还可以包括，设置在所述第二字线40b背离所述第一栅电极26a一侧且沿第二方向Y延伸的第二横向凹槽(参考后续的第六凹槽V6)，所述第二横向凹槽与所述第四孔连通，所述第二横向凹槽的开口背离所述第二字线40b和所述第三字线40c，所述第二半导体层23b还分布在所述第二横向凹槽的侧壁和底壁。第二位线32分布在所述第二横向凹槽且填充所述第二横向凹槽，从而，第二位线32可以与分布在所述第二横向凹槽的底壁和侧壁的第二半导体层23b连接。
在一些实施例中，沿所述第二方向Y分布的同一列的第二晶体管的第二半导体层23b之间断开。如图1F所示，第二半导体层23b分布在第二孔朝向所邻近的第一子沟槽的侧壁的部分区域，从而沿第二方向Y相邻的第二晶体管的第二半导体层23b之间断开。
在一些实施例中，所述半导体器件还可以包括：贯穿所述绝缘层和所述导电层的第五孔，且所述第五孔从外到内依次分布有第四栅极绝缘层24d、第三字线40c，所述第三字线40c填充所述第五孔；且所述第五孔在所述导电层的子孔在所述衬底1的正投影中，靠近所述第二位线32的边界和靠近所述第二字线40b的边界落入所述第五孔在所述绝缘层的子孔在所述衬底1的正投影内，背离所述第二位线32的边界和背离所述第二字线40b的边界落在所述第五孔在所述绝缘层的子孔在所述衬底1的正投影的边界上。如图1C所示，第五孔背离第二位线32的侧壁在绝缘层和导电层沿垂直于衬底1的方向直线延伸。如图1E所示，第五孔背离第二字线40b的侧壁在绝缘层和导电层沿垂直于衬底1的方向直线延伸。
图1G为一示例性实施例提供的半导体器件的存储单元的等效电路示意图。如图1G所示，所述存储单元可以包括第一晶体管T1和第二晶体管T2，所述第一晶体管T1的第一电极51连接第一位线31，第二电极52连接参考电压端Vrefn，第二栅电极26b连接第一字线40a，第一栅电极26a连接第二晶体管T2的第三电极53；第二晶体管T2的第四电极54连接第二位线32，第三栅电极26c(为了和第一晶体管的第一栅电极26a和第二栅电极26b区分，不代表第二晶体管T2有三个栅电极，后续第四栅电极26d类似)连接第二字线40b，第四栅电极26d连接第三字线40c。所述存储单元还可以包括存储节点SN，所述存储节点SN可以包含所述第一晶体管T1的第一栅电极26a。
在一些实施例中，所述第一晶体管T1可以是读晶体管，所述第二晶体管T2可以是写晶体管，所述第一位线31可以是读位线RBL，所述第二位线32可以是写位线WBL，所述第一字线40a可以是读字线，所述第二字线40b可以是第一写字线WWL1，所述第三字线40c可以是第二写字线WWL2。该电路中，所述第一写字线WWL1和第二写字线WWL2均加载激活信号时，第二晶体管T2开启，所述第一写字线WWL1和第二写字线WWL2至少之一加载非激活信号时，第二晶体管T2关断。
以第一晶体管T1和第二晶体管T2为N型晶体管为例。所述第一写字线WWL1和第二写字线WWL2均加载高电平信号时，即第二晶体管T2的第三栅电极26c和第四栅电极26d均加载高电平信号时，第二晶体管T2开启。所述第一写字线WWL1和第二写字线WWL2至少之一加载低电平信号时，第二晶体管T2关断。在另一示例性实施例中，所述第一晶体管T1和第二晶体管T2为P型晶体管时，所述第一写字线WWL1和第二写字线WWL2均加载低电平信号时，第二晶体管T2导通，所述第一写字线WWL1和第二写字线WWL2至少之一加载高电平信号时，所述第二晶体管T2关断。
在一些实施例中，沿第一方向X分布的同一行的第二字线40b可以连接在一起，即连接到一条第一公共字线，沿第二方Y分布的同一列的第三字线40c可以连接在一起，即，连接到一条第二公共字线；或者，沿第二方向Y分布的同一列的第二字线40b可以连接在一起，即连接到一条第一公共字线，沿第一方向X分布的同一行的第三字线40c可以连接在一起，即，连接到一条第二公共字线。该方案中，通过激活一条第一公共字线和一条第二公共字线，可以实现选中一垂直列的存储单元(即不同层相同位置的一组存储单元)，本实施例提供的方案，无需为第一公共字线和第二公共字线设置选通晶体管，即可实现选中一垂直列的存储单元，相比为第一公共字线、第二公共字线分布设置选通晶体管的方案，可以省去制造选通晶体管的工艺步骤，且字线驱动器的数量较少，且随着堆叠层数的增多，字线驱动器的数量不变，另外，电路控制逻辑简单。
下面通过本实施例半导体器件的制造过程进一步说明本实施例的技术方案。本实施例中可以通过构图工艺和光刻工艺对膜层进行处理。所说的“构图工艺”包括沉积膜层、涂覆光刻胶、掩模曝光、显影、刻蚀、剥离光刻胶等处理，是相关技术中成熟的制造工艺。本实施例中所说的“光刻工艺”包括涂覆膜层、掩模曝光和显影，是相关技术中成熟的制造工艺。沉积可采用溅射、蒸镀、化学气相沉积等已知工艺，涂覆可采用已知的涂覆工艺，刻蚀可采用已知的方法，在此不做具体的限定。在本实施例的描述中，需要理解的是，“薄膜”是指将某一种材料在基底上利用沉积或涂覆工艺制造出的一层薄膜。若在整个制造过程当中该“薄膜”无需构图工艺或光刻工艺，则该“薄膜”还可以称为“层”。若在整个制造过程当中该“薄膜”还需构图工艺或光刻工艺，则在构图工艺前称为“薄膜”，构图工艺后称为“层”。经过构图工艺或光刻工艺后的“层”中包含至少一个“图案”。
在一示例性实施例中，所述半导体器件的制造过程可以包括：
1)形成堆叠结构；
所述形成堆叠结构可以包括：提供衬底1，在所述衬底1上交替沉积第一半导体薄膜和牺牲层薄膜，形成包括多个交替设置的第二半导体结构层232’和牺牲层10的堆叠结构；
沉积硬掩膜薄膜，形成硬掩膜层9。此时，所述堆叠结构包括多个交替设置的第二半导体结构层232’和牺牲层10，以及，设置在最顶层的牺牲层10背离衬底1一侧的硬掩膜层9，所述硬掩膜层9覆盖所述牺牲层10，如图2A和图2B所示。图2A为一些实施例提供的形成堆叠结构后的俯视图，图2B为沿图2A中AA’方向的垂直于衬底1的截面图。所述AA’方向可以平行于所述第一方向X。
在一些实施例中，衬底1可以是常规的硅衬底或包括半导体材料层的其他体衬底。
在一些实施例中，所述第一半导体薄膜可以是重掺杂的半导体膜层，后续该第二半导体结构层232’可以形成第二半导体子层232。
在一些实施例中，所述牺牲层薄膜可以是半导体材料，比如SiGe等。此处使用半导体材料是便于进行第一半导体薄膜的外延生长。后续会将牺牲层薄膜替换为绝缘薄膜。
在一些实施例中，所述硬掩膜层9包括但不限于以下至少之一：碳、多晶硅、硅氧化物等。
图2B中示出的堆叠结构包括三层第二半导体结构层232’和三层牺牲层10，仅为示例，在其他实施例中，所述叠层结构可以包括更多或更少层交替设置的第二半导体结构层232’和牺牲层10。
2)形成第一沟槽T1和第一绝缘层11；
刻蚀所述多个堆叠结构，形成贯穿所述堆叠结构的多个第一沟槽T1；所述多个第一沟槽T1沿第一方向X和第二方向Y间隔分布，每两个沿第二方向Y相邻的第一沟槽T1之间定义出一个存储单元区域，其中所述第一沟槽T1可以为T字形沟槽；所述T字形沟槽可以包含第一方向X延伸的一字形的第一子沟槽以及由第一子沟槽的中部沿第二方向Y延伸的第二子沟槽。此处中部非严格的中间均分的位置，为第一子沟槽两端之间的一个位置。
在每个第一沟槽T1内沉积第一绝缘薄膜并磨平，形成填充所述第一沟槽T1的第一绝缘层11；所述第一绝缘层11可以和硬掩膜层9齐平。如图3A和图3B所示，其中，图3A为一些实施例提供的形成第一沟槽T1和第一绝缘层11后的俯视图，图3B为沿图3A中EE’方向的垂直于衬底1的截面图。所述EE’方向可以平行于所述第一方向X。所述第一绝缘层11可以对后续形成的多个存储单元进行隔离。
在一些实施例中，所述第一绝缘薄膜可以是low-K介质层，包括但不限于硅氧化物，比如二氧化硅(SiO2)等。
3)形成第一初始孔K1；
利用干法刻蚀对所述堆叠结构从顶层至底层进行刻蚀(刻蚀停止在衬底1上)，形成第一初始孔K1，此时，第一初始孔K1在第二半导体结构层232’的第二子孔和在牺牲层10的第一子孔的孔径一致，如图4A和图4B所示，其中，图4A为一些实施例提供的形成第一初始孔K1后的俯视图，图4B为沿图4A中AA’方向的垂直于衬底1的截面图。
所述第一初始孔K1的一个侧壁暴露与所述第一初始孔K1相邻的位于所述T字形沟槽(即第一沟槽T1)的一字形子沟槽(即第一子沟槽)中的所述第一绝缘层11。所述第一初始孔K1的其余侧壁不暴露所述第一绝缘层11，即其余侧壁暴露第二半导体结构层232’、牺牲层10和硬掩膜层9。且沿第一方向X，所述第一初始孔K1位于所述T字形沟槽的沿第二方向Y延伸的子沟槽(即第二子沟槽)的一侧的第一晶体管区。
在一些实施例中，所述第一初始孔K1在衬底1的正投影比如为方形。但不限于此，可以是其他形状。
4)形成第二绝缘层12；
基于所述第一初始孔K1横向刻蚀去除所述牺牲层10；
在形成前述结构的衬底1上沉积第二绝缘薄膜，形成填充所述第一初始孔K1和原所述牺牲层10所在区域的第二绝缘层12，如图5A和图5B所示，其中，图5A为一些实施例提供的形成第二绝缘层12后的俯视图，图5B为沿图5A中AA’方向的垂直于衬底1的截面图。所述第二绝缘层12可以对不同层的存储单元进行隔离。
在一些实施例中，所述第二绝缘层12可以是和第一绝缘层11存在刻蚀选择比的膜层，比如SiN等。
5)暴露第一初始孔K1；
沿垂直于衬底1方向刻蚀去除第一初始孔K1中的第二绝缘层12，暴露所述第一初始孔K1，如图6A和图6B所示，其中，图6A为一些实施例提供的暴露第一初始孔K1后的俯视图，图6B为沿图6A中AA’方向的垂直于衬底1的截面图。
6)形成第一凹槽V1；
基于所述第一初始孔K1横向刻蚀(即沿平行于衬底1的方向)所述第二半导体结构层232’，形成横向的第一凹槽V1，使得第一孔位于第二绝缘层12的子孔在所述衬底1的正投影落入位于第二半导体结构层232’的子孔在所述衬底1的正投影内，如图7A和 图7B所示，其中，图7A为一些实施例提供的形成第一凹槽V1后的俯视图，图7B为沿图7A中AA’方向的垂直于衬底1的截面图。前述的第一孔包括第一初始孔K1和第一凹槽V1。
参考图7A中环绕第一初始孔K1的虚线所示的区域，即为第一凹槽V1的外边界，其中沿第一方向X间隔分布的两个侧壁中，一个侧壁暴露第二半导体结构层232’，另一个侧壁的一部分暴露第二半导体结构层232’，另一部分暴露第一绝缘层11，沿第二方向Y间隔分布的两个侧壁中，两个侧壁其中一个暴露第一绝缘层11，另一个暴露第二半导体结构层232’，即沿第二方向Y横向刻蚀时，刻蚀掉该方向的部分第二半导体结构层232’，不暴露第一绝缘层11，沿第一方向X横向刻蚀时，刻蚀到T字形沟槽的沿第二方向Y延伸的子沟槽(即第二子沟槽)处。
7)形成第一半导体结构层231’；
在形成前述结构的衬底1上沉积第二半导体薄膜，形成填充所述第一孔的第一半导体结构层231’，如图8A和图8B所示，其中，图8A为一些实施例提供的形成第一半导体结构层231’后的俯视图，图8B为沿图8A中AA’方向的垂直于衬底1的截面图。
所述第一半导体结构层231’可以为轻掺杂或未掺杂的半导体材料。
在一些实施例中，所述沉积第二半导体薄膜可以是外延生长第二半导体薄膜。
在本公开的示例性实施例中，所述第二半导体薄膜的材料可以为带隙小于1.65eV的硅或多晶硅等材料，或者，可以是宽带隙材料，比如带隙大于1.65eV的金属氧化物材料。
举例来说，金属氧化物半导体层或沟道的材料可包括如下金属中的至少之一的金属氧化物：铟、镓、锌、锡、钨、镁、锆、铝、铪等材料。当然，该金属氧化物中也不排除含有其他元素的化合物，比如，N、Si等元素；也不排除含有其他少量掺杂元素。
一些实施例中，金属氧化物半导体层或沟道的材料可以包含以下中的一或多者：铟镓锌氧化物(InGaZnO)、氧化铟锌(InZnO)、氧化铟镓(InGaO)、氧化铟锡(InSnO)、氧化铟镓锡(InGaSnO)、氧化铟镓锌锡(InGaZnSnO)、氧化铟(InO)、氧化锡(SnO)、氧化锌锡(ZnSnO，ZTO)、氧化铟铝锌金(InAlZnO)、氧化锌(ZnO)、铟镓硅氧化物(InGaSiO)、氧化铟钨(InWO，IWO)、氧化钛(TiO)、氮氧化锌(ZnON)、氧化镁锌(MgZnO)、锆铟锌氧化物(ZrInZnO)、铪铟锌氧化物(HfInZnO)、锡铟锌氧化物(SnInZnO)、铝锡铟锌氧化物(AlSnInZnO)、硅铟锌氧化物(SiInZnO)、铝锌锡氧化物(AlZnSnO)、镓锌锡氧化物(GaZnSnO)、锆锌锡氧化物(ZrZnSnO)等材料，只要保证晶体管的漏电流能满足要求即可，具体可根据实际情况进行调整。
这些材料的带隙较宽，具有较低的漏电流，比如，当金属氧化物材料为IGZO时，晶体管的漏电流小于或者等于10-15A，由此可以改善动态存储器的工作性能。
上述金属氧化物半导体层或沟道的材料仅强调材料的元素类型，不强调材料中原子占比以及材料的膜质。
8)形成第一半导体子层231；
刻蚀去除第一孔中除第一凹槽V1所在区域外的第一半导体结构层231’，即，刻蚀去除第一初始孔K1中的第一半导体结构层231’，仅保留位于第一凹槽V1中的第一半导体结构层231’；使得第一半导体结构层231’分割为多个分别位于不同层的部分；
基于所述第一初始孔K1横向刻蚀所述第一半导体结构层231’，形成第二凹槽V2，保留部分第一半导体结构层231’，保留的第一半导体结构层231’即为多个晶体管的第一半导体子层231。如图9A和图9B所示，其中，图9A为一些实施例提供的形成第一半 导体子层231后的俯视图，图9B为沿图9A中AA’方向的垂直于衬底1的截面图。参考图9A，此时，第一半导体子层231包括独立的两部分，这两部分被第一沟槽T1中的第一绝缘层11隔断。后续形成第二半导体层23b时，可以避免第一半导体子层231和第二半导体层23b连接。
参考图9A中虚线示出的区域即为第二凹槽V2的外边界。
9)形成第一导电层26a’和第一栅极绝缘层24a；
在形成前述结构的衬底1上依次沉积第一栅绝缘薄膜和第一栅电极薄膜，形成第一栅极绝缘层24a和第一导电层26a’；所述第一导电层26a’填充所述第一初始孔K1和第二凹槽V2，如图10A和图10B所示，其中，图10A为一些实施例提供的形成第一导电层26a’和第一栅极绝缘层24a后的俯视图，图10B为沿图10A中AA’方向的垂直于衬底1的截面图。
所述第一栅极绝缘层24a覆盖所述第一初始孔K1和第二凹槽V2的底壁和侧壁。
在一些实施例中，所述第一栅极绝缘层24a的材料可以包含一层或多层High-K介质材料。一些实施例中，可以包括铪、铝、镧、锆等一个或多个的氧化物。示例性的，比如，可以包括但不限于以下至少之一：氧化铪(HfO2)、氧化铝(Al2O3)，铪铝氧化物(HfAlO)，铪镧氧化物(HfLaO)、锆的氧化物(ZrO2)等高K材料。后续第二栅极绝缘层24b、第三栅极绝缘层24c和第四栅极绝缘层24d材料类似，不再赘述。
在一些实施例中，所述第一栅电极薄膜可以是如下不同类型材料中的一种或多种：
比如，含有钨、铝、钛、铜、镍、铂、钌、钼、金、铱、铑、钽、钴等金属；可以是含有前述提到的这些金属中的金属合金；
或者，可以是金属氧化物、金属氮化物、金属硅化物、金属碳化物等，如铟锡氧化物(ITO)、铟锌氧化物(IZO)、铟的氧化物(InO)、掺铝氧化锌(Aluminum doped Zinc Oxide，AZO)等导电性较高的金属氧化物材料；比如，氮化钛(TiN)、氮化钽(TaN)、氮化钨(WN)、氮化钛铝(TiAlN)等金属氮化物材料；
或者，可以是多晶硅材料、导电掺杂半导体材料等，比如，导电掺杂后的硅、导电掺杂后的锗、导电掺杂后的硅锗等；体现导电性的其他材料等。
后续第二栅电极薄膜、第三栅电极薄膜、第四栅电极薄膜、第一导电薄膜、第二导电薄膜、第三导电薄膜材料类似，不再赘述。
10)形成第一栅电极26a；
刻蚀去除第一初始孔K1中的第一导电层26a’，保留位于多个第二凹槽V2中的第一导电层26a’，每个第二凹槽V2中的第一导电层26a’即为一个第一晶体管的第一栅电极26a；不同层相同位置的第一晶体管的第一栅电极26a之间断开。所述第一栅电极26a还复用为第二晶体管的第三电极53，存储节点SN包括所述第一栅电极26a。
沉积第三绝缘薄膜，形成隔离层13，所述隔离层13填充所述第一初始孔K1，如图11A和图11B所示，其中，图11A为一些实施例提供的形成第一栅电极26a后的俯视图，图11B为沿图11A中AA’方向的垂直于衬底1的截面图。
在一些实施例中，所述隔离层13可以是low-K介质层，包括但不限于硅氧化物，比如二氧化硅(SiO2)等。
11)形成第二初始孔K2和第三凹槽V3；
利用干法刻蚀对所述堆叠结构从顶层至底层进行刻蚀(刻蚀停止在衬底1上)，形成 第二初始孔K2，所述第二初始孔K2靠近沿第二方向Y相邻的两个第一沟槽T1中远离所述第一初始孔K1的第一沟槽T1，且所述第二初始孔K2的侧壁不暴露所述第一绝缘层11，所述第二初始孔K2与所述第一初始孔K1位于所述第一沟槽T1的沿第二方向Y延伸的子沟槽(即第二子沟槽)的同侧。
基于所述第二初始孔K2横向刻蚀所述第二半导体结构层232’，形成第三凹槽V3，如图12A、图12B和图12C所示，其中，图12A为一些实施例提供的形成第二初始孔K2和第三凹槽V3后的俯视图，图12B为沿图12A中BB’方向的垂直于衬底1的截面图，图12C为沿图12A中CC’方向的垂直于衬底1的截面图。所述第三凹槽V3沿第二方向Y间隔分布的两个侧壁，其中一个侧壁暴露所述位于所述一字形子沟槽中的第一绝缘层11，另一个侧壁暴露所述第一半导体层231；沿第一方向X间隔分布的两个侧壁暴露所述第二半导体结构层232’。横向刻蚀是为了暴露出第一半导体层231，使得后续形成的第一字线40a能控制第一晶体管。前述的第二孔包括所述第二初始孔K2和第三凹槽V3。
在一些实施例中，所述第二初始孔K2在衬底1的正投影比如为方形。但不限于此，可以是其他形状。
12)形成第二栅极绝缘层24b和第一字线40a；
在形成前述结构的衬底1上依次沉积第二栅绝缘薄膜和第二栅电极薄膜，形成第二栅极绝缘层24b和第一字线40a；所述第二栅极绝缘层24b覆盖所述第二初始孔K2和第三凹槽V3的底壁和侧壁，所述第一字线40a填充所述第二初始孔K2和第三凹槽V3，如图13A、图13B和图13C所示，其中，图13A为一些实施例提供的形成第二栅极绝缘层24b和第一字线40a后的俯视图，图13B为沿图13A中BB’方向的垂直于衬底1的截面图，图13C为沿图13A中CC’方向的垂直于衬底1的截面图。不同层同一位置的第一晶体管的第二栅电极26b为所述第一字线40a的一部分。
13)形成第三孔K3；
利用干法刻蚀对所述堆叠结构从顶层至底层进行刻蚀(刻蚀停止在衬底1上)，形成第三孔K3，所述第三孔K3设置在所述第二初始孔K2和所述第一沟槽T1的沿第二方向Y延伸的子沟槽之间，以及，设置在所述第一初始孔K1和所述第一沟槽T1的一字形子沟槽之间，第三孔K3的沿第一方向X延伸且远离所述第一初始孔K1的侧壁可以暴露位于所述第一沟槽T1的一字形子沟槽中的第一绝缘层11，其余侧壁可以暴露所述第二半导体结构层232’，且不暴露所述第二栅极绝缘层24b、所述第一半导体子层231，以及，位于所述第一沟槽T1的沿第二方向Y延伸的子沟槽中的第一绝缘层11。如图14A和图14B所示，其中，图14A为一些实施例提供的形成第三孔K3后的俯视图，图14B为沿图14A中BB’方向的垂直于衬底1的截面图。
在一些实施例中，所述第三孔K3在衬底1的正投影比如为方形。但不限于此，可以是其他形状。
14)形成信号线52’；
对第三孔K3侧壁暴露出的第二半导体结构层232’进行金属硅化，形成金属硅化物以降低后续形成的信号线52’与第二半导体结构层232’之间的接触电阻；
沉积第一导电薄膜，形成填充所述第三孔K3的信号线52’，不同层相同位置的所述第一晶体管的第二电极52为所述信号线52’的一部分。如图15A和图15B所示，其中，图15A为一些实施例提供的形成信号线52’后的俯视图，图15B为沿图15A中BB’方向的垂直于衬底1的截面图。环绕信号线52’的第二半导体结构层232’即为第二半导体子层232的第二部分2322，第一部分2321和第二部分2322之间间隔。
15)形成第二沟槽T2；
从顶层至底层刻蚀所述堆叠结构，形成贯穿所述堆叠结构的第二沟槽T2，所述第二沟槽T2沿第二方向Y延伸，沿第一方向X相邻的第二沟槽T2之间限定一组存储单元，每组存储单元包括两列存储单元，如图16A和图16B所示，其中，图16A为一些实施例提供的形成第二沟槽T2后的俯视图，图16B为沿图16A中BB’方向的垂直于衬底1的截面图。
16)形成第四凹槽V4和第一位线层31’；
基于所述第二沟槽T2横向刻蚀所述第二半导体结构层232’，且未完全刻蚀掉所述第二半导体结构层232’(不暴露第二栅极绝缘层24b)，形成第四凹槽V4，所述第四凹槽V4沿第二方向Y延伸，此时，位于第一半导体子层231朝向所述第二凹槽V2一侧的第二半导体结构层232’即作为第二半导体子层232的第一部分2321。第四凹槽V4为沿第二方向Y延伸的横向沟槽；
对所述第二半导体子层232进行金属硅化处理，形成金属硅化物，以便降低第二半导体子层232与待形成的第一位线层31’之间的接触电阻；
沉积第二导电薄膜，形成第一位线层31’，所述第一位线层31’填充所述第二沟槽T2和所述第四凹槽V4；如图17A和图17B所示，其中，图17A为一些实施例提供的形成第一位线层31’后的俯视图，图17B为沿图17A中BB’方向的垂直于衬底1的截面图。
17)形成第一位线31和第四绝缘层14；
刻蚀去除所述第二沟槽T2中的第一位线层31’，保留位于所述第四凹槽V4中的第一位线层31’，此时，第一位线层31’被分割为位于不同层的多条第一位线31，该多条第一位线31之间断开；
沉积第四绝缘薄膜，形成填充所述第二沟槽T2的第四绝缘层14，所述第四绝缘层14对不同组的存储单元进行间隔，如图18A和图18B所示，其中，图18A为一些实施例提供的形成第一位线31和第四绝缘层14后的俯视图，图18B为沿图18A中BB’方向的垂直于衬底1的截面图。
在一些实施例中，所述第四绝缘层14可以是low-K介质层，包括但不限于硅氧化物，比如二氧化硅(SiO2)等。
18)形成第四初始孔K4和第三沟槽T3；
利用干法刻蚀对所述堆叠结构从顶层至底层进行刻蚀(刻蚀停止在衬底1上)，形成第四初始孔K4和第三沟槽T3，如图19A、图19B和图19C所示，其中，图19A为一些实施例提供的形成第四初始孔K4和第三沟槽T3后的俯视图，图19B为沿图19A中AA’方向的垂直于衬底1的截面图，图19C为沿图19A中DD’方向的垂直于衬底1的截面图。
所述第三沟槽T3沿第二方向Y延伸，所述第三沟槽T3间隔同一组内的两列存储单元。所述第四初始孔K4位于所述第一初始孔K1朝向所述第一沟槽T1的沿第二方向Y延伸的子沟槽一侧，且所述第四初始孔K4与所述第一初始孔K1靠近同一第一沟槽T1的一字形沟槽(即第一子沟槽)，且所述第四初始孔K4的一个侧壁暴露所靠近的第一沟槽T1的一字形子沟槽中的第一绝缘层11。
在一些实施例中，所述第四初始孔K4在衬底1的正投影比如为方形。但不限于此，可以是其他形状。
19)形成第五凹槽V5；
基于所述第四初始孔K4和第三沟槽T3横向刻蚀所述第二半导体结构层232’、所述第一半导体子层231、所述第一栅极绝缘层24a，形成第五凹槽V5，所述第五凹槽V5的侧壁暴露出所述第一栅电极26a，以便第一栅电极26a与后续形成的第二半导体层23b连接，且横向刻蚀后，第四初始孔K4和第三沟槽T3连通，且第五凹槽V5的侧壁暴露出所述第一子沟槽中的第一绝缘层11朝向所述第三沟槽T3一侧的侧壁；如图20A、图20B和图20C所示，其中，图20A为一些实施例提供的形成第五凹槽V5后的俯视图，图20B为沿图20A中AA’方向的垂直于衬底1的截面图，图20C为沿图20A中DD’方向的垂直于衬底1的截面图。
20)形成第三半导体结构层23b’；
在形成前述结构的衬底1上依次沉积第三半导体薄膜和第五绝缘薄膜，形成第三半导体结构层23b’和第五绝缘层15；所述第三半导体结构层23b’覆盖所述第四初始孔K4和第三沟槽T3的侧壁和底壁，以及，覆盖所述第五凹槽V5的内壁(侧壁和底壁)，所述第五绝缘层15填充所述第四初始孔K4、所述第三沟槽T3和所述第五凹槽V5；如图21A、图21B和图21C所示，其中，图21A为一些实施例提供的形成第三半导体结构层23b’后的俯视图，图21B为沿图21A中AA’方向的垂直于衬底1的截面图，图21C为沿图21A中DD’方向的垂直于衬底1的截面图。
在一些实施例中，所述第五绝缘薄膜可以是low-K介质层，包括但不限于硅氧化物，比如二氧化硅(SiO2)等。
21)形成第二半导体层23b；
刻蚀去除所述第四初始孔K4和第三沟槽T3中的第三半导体结构层23b’和第五绝缘层15，保留所述第五凹槽V5中的第三半导体结构层23b’和第五绝缘层15，使得第三半导体结构层23b’分割为多个分别位于不同层的部分，每个部分为一个第二晶体管的第二半导体层23b，从而不同层相同位置的第二晶体管的第二半导体层23b之间断开；
沉积第六绝缘薄膜，形成第六绝缘层16，所述第六绝缘层16填充所述第四初始孔K4和第三沟槽T3，如图22A、图22B和图22C所示，其中，图22A为一些实施例提供的形成第二半导体层23b后的俯视图，图22B为沿图22A中AA’方向的垂直于衬底1的截面图，图22C为沿图22A中DD’方向的垂直于衬底1的截面图。
在一些实施例中，所述第六绝缘薄膜可以是和第五绝缘层存在刻蚀选择比的膜层，包括但不限于SiN等。
22)形成第六凹槽V6；
刻蚀去除所述第三沟槽T3中的第六绝缘层16；
基于所述第三沟槽T3横向刻蚀所述第五绝缘层15，形成第六凹槽V6；所述第六凹槽V6暴露位于所述第四初始孔K4中的第六绝缘层16；如图23A和图23B所示，其中，图23A为一些实施例提供的形成第六凹槽V6后的俯视图，图23B为沿图23A中AA’方向的垂直于衬底1的截面图。
所述第六凹槽V6可以为第五凹槽V5的一部分，第五凹槽V5除第六凹槽V6外的部分称为第七凹槽V7。
23)形成第二位线层32’；
沉积第三导电薄膜，形成第二位线层32’，所述第二位线层32’填充所述第三沟槽T3和所述第六凹槽V6；如图24A和图24B所示，其中，图24A为一些实施例提供的形成第二位线层32’后的俯视图，图24B为沿图24A中AA’方向的垂直于衬底1的截面图。
24)形成第二位线32；
刻蚀去除所述第三沟槽T3中的第二位线层32’，保留位于所述第六凹槽V6中的第二位线层32’，此时，第二位线层32’被分割为位于不同层的多条第二位线32，该多条第二位线32之间断开；
沉积第七绝缘薄膜，形成填充所述第三沟槽T3的第七绝缘层17，所述第七绝缘层17对同一组的两列存储单元进行间隔，如图25A和图25B所示，其中，图25A为一些实施例提供的形成第二位线32后的俯视图，图25B为沿图25A中AA’方向的垂直于衬底1的截面图。
在一些实施中，所述第七绝缘薄膜可以是low-K介质层，包括但不限于硅氧化物，比如二氧化硅(SiO2)等。
25)形成第二字线40b和第三栅极绝缘层24c；
刻蚀去除所述第四初始孔K4中的第六绝缘层16，基于所述第四初始孔K4横向刻蚀去除所述第七凹槽V7中的第五绝缘层15；
在形成前述结构的衬底1上依次沉积第三栅绝缘薄膜和第三栅电极薄膜，形成第三栅极绝缘层24c和第二字线40b；所述第三栅极绝缘层24c覆盖所述第四初始孔K4的底壁和侧壁，以及，所述第七凹槽V7的底壁和侧壁，所述第三栅电极薄膜填充所述第四初始孔K4和第七凹槽V7，如图26A、图26B和图26C所示，其中，图26A为一些实施例提供的形成第二字线40b和第三栅极绝缘层24c后的俯视图，图26B为沿图26A中AA’方向的垂直于衬底1的截面图，图26C为沿图26A中DD’方向的垂直于衬底1的截面图。前述第四孔可以包括第四初始孔K4和第七凹槽V7。
26)形成第五初始孔K5；
利用干法刻蚀对所述堆叠结构从顶层至底层进行刻蚀(刻蚀停止在衬底1上)，形成第五初始孔K5；所述第五初始孔K5与第三孔K3分别设置在第一沟槽T1的沿第二方向Y延伸的第二子沟槽的两侧；所述第五初始孔K5的侧壁暴露所述第二半导体结构层232’和所述第二半导体层23b；且所述第五初始孔K5靠近限定所述第五初始孔K5所在的存储单元的两个第一沟槽T1中远离所述第四初始孔K4的第一沟槽T1，比如，两个沿第二方向Y相邻的第一沟槽T1，第四初始孔K4靠近其中一个第一沟槽T1，第五初始孔K5靠近另一个第一沟槽T1。
基于所述第五初始孔K5横向刻蚀所述第二半导体结构层232’和所述第二绝缘层12，形成区域V8，所述区域V8的底壁暴露所述第一绝缘层11和所述第七绝缘层17，即，沿第一方向X和第二方向Y横向刻蚀所述第二半导体结构层232’，暴露所述第一绝缘层11；沿第一方向X横向刻蚀所述第二绝缘层12，暴露所述第一绝缘层11和所述第七绝缘层17，沿第二方向Y横向刻蚀所述第二绝缘层12，暴露所述第一绝缘层11和所述第三栅极绝缘层24c，如图27A、图27B和图27C所示，其中，图27A为一些实施例提供的形成第五初始孔K5后的俯视图，图27B为沿图27A中BB’方向的垂直于衬底1的截面图，图27C为沿图27A中DD’方向的垂直于衬底1的截面图。前述第五孔包括第五初始孔K5和区域V8。
在一些实施例中，所述第五初始孔K5在衬底1的正投影比如为方形。但不限于此，可以是其他形状。
27)形成第三字线40c和第四栅极绝缘层24d；
在形成前述结构的衬底1上依次沉积第四栅绝缘薄膜和第四栅电极薄膜，形成第四栅 极绝缘层24d和第三字线40c；所述第四栅极绝缘层24d覆盖所述第五初始孔K5的底壁和侧壁，以及，所述区域V8的底壁和侧壁，所述第四栅电极薄膜填充所述第五初始孔K5和区域V8，如图1A、图1B、图1C、图1D、图1E和图1F所示。
本公开实施例还提供了一种电子设备，包括前述任一实施例所述的半导体器件，或者，前述任一实施例所述的半导体器件的制造方法形成的半导体器件。所述电子设备可以为：存储装置、智能电话、计算机、平板电脑、人工智能设备、可穿戴设备或移动电源等。存储装置可以包括计算机中的内存等，此处不作限定。
虽然本发明所揭露的实施方式如上，但所述的内容仅为便于理解本发明而采用的实施方式，并非用以限定本发明。任何本发明所属领域内的技术人员，在不脱离本发明所揭露的精神和范围的前提下，可以在实施的形式及细节上进行任何的修改与变化，但本发明的专利保护范围，仍须以所附的权利要求书所界定的范围为准。

Claims (23)

  1. 一种半导体器件，包括：多层沿垂直于衬底的方向堆叠的存储单元、贯穿多层相同位置的所述存储单元的沿垂直于衬底方向延伸的第一字线、贯穿多层相同位置的所述存储单元的沿垂直于衬底方向延伸的第二字线和贯穿多层相同位置的所述存储单元的沿垂直于衬底方向延伸的第三字线；
    所述存储单元包括：第一晶体管和第二晶体管，所述第一晶体管和第二晶体管沿平行于所述衬底的第一方向分布；所述第二字线和第三字线沿平行于所述衬底的第二方向分布，所述第一方向和所述第二方向交叉；
    所述第一晶体管包括：第一栅电极、第二栅电极和第一半导体层；不同层相同位置的存储单元的所述第一栅电极沿垂直于所述衬底的方向延伸且间隔分布；所述第一半导体层部分环绕所述第一栅电极；所述第二栅电极设置在所述第一半导体层背离所述第一栅电极一侧，不同层相同位置的第一晶体管的第二栅电极为所述第一字线的一部分；
    所述第二晶体管包括：第二半导体层；所述第一栅电极未被所述第一半导体层环绕的部分区域与所述第二半导体层连接；所述第二半导体层部分环绕所述第二字线；所述第三字线形成有开口朝向所述第二字线的沿垂直于衬底方向间隔分布的多个第一凹槽，所述第一凹槽的底壁和侧壁分布有所述第二半导体层，所述第二字线形成有分别朝向多个所述第一凹槽的多个凸起。
  2. 根据权利要求1所述的半导体器件，其中，所述第一半导体层包括第一半导体子层和设置在所述第一半导体子层背离所述第一栅电极一侧的第二半导体子层，所述第一半导体子层部分环绕所述第一栅电极，所述第二半导体子层的掺杂浓度大于所述第一半导体子层的掺杂浓度，所述第二半导体子层包括在所述第一半导体子层背离所述第一栅电极的表面上间隔设置的第一部分和第二部分。
  3. 根据权利要求2所述的半导体器件，其中，所述第一字线分布在所述第一半导体子层背离所述第一栅电极一侧的侧壁上所述第一部分和所述第二部分之间的区域。
  4. 根据权利要求2所述的半导体器件，其中，所述第一晶体管还包括第一电极和第二电极，所述第一电极连接所述第一部分，所述第二电极连接所述第二部分，所述第二部分环绕所述第二电极，不同层相同位置的第一晶体管的第二电极连接形成沿垂直于衬底方向延伸的一体式结构。
  5. 根据权利要求4所述的半导体器件，其中，同层沿所述第二方向分布的同一列的所述第一晶体管的所述第一部分相互连接形成一体式结构，同层沿所述第二方向分布的同一列的所述第一晶体管的所述第二部分相互分离。
  6. 根据权利要求5所述的半导体器件，其中，沿所述第二方向分布的同一列的所述第一晶体管的所述第一电极连接形成沿所述第二方向延伸的第一位线。
  7. 根据权利要求4所述的半导体器件，其中，所述第二电极和所述第一字线设置在所述第一部分的同侧，以及，设置在所述第一栅电极的同侧。
  8. 根据权利要求2所述的半导体器件，其中，所述半导体器件还包括贯穿多层所述第一晶体管的隔离层；不同层相同位置的第一栅电极部分环绕所述隔离层且沿垂直于衬底方向依次分布在所述隔离层的侧壁的不同区域。
  9. 根据权利要求8所述的半导体器件，其中，所述第一晶体管还包括设置在所述第一栅电极和所述第一半导体子层之间的第一栅极绝缘层，不同层相同位置的第一晶体管的 第一栅极绝缘层连接形成沿垂直于衬底方向延伸的一体式结构。
  10. 根据权利要求9所述的半导体器件，其中，所述半导体器件还包括：
    沿着垂直所述衬底的方向从上至下依次交替分布的绝缘层和导电层；
    贯穿所述绝缘层和所述导电层的第一孔、第二孔、第三孔；
    所述第一孔从外到内依次分布有所述第一半导体子层、所述第一栅极绝缘层、所述第一栅电极、所述隔离层，且所述隔离层填充所述第一孔；
    所述第二孔从外到内依次分布有第二栅极绝缘层、所述第一字线，且所述第一字线填充所述第二孔；
    所述第三孔中仅分布有信号线，且所述信号线填充所述第三孔，不同层相同位置的第一晶体管的第二电极为所述信号线的一部分。
  11. 根据权利要求10所述的半导体器件，其中，所述第一孔在所述绝缘层的子孔在所述衬底的正投影中，靠近所述第一字线的边界、靠近所述第二字线的边界、背离所述第二字线的边界落入所述第一孔在所述导电层的子孔在所述衬底的正投影内，背离所述第一字线的边界落在所述第一孔在所述导电层的子孔在所述衬底的正投影的边界上。
  12. 根据权利要求10所述的半导体器件，其中，所述半导体器件还包括：贯穿所述绝缘层和所述导电层的第四孔，且所述第四孔从外到内依次分布有所述第二半导体层、第三栅极绝缘层、第二字线，所述第二字线填充所述第四孔，所述第四孔的侧壁暴露所述第一栅电极，且所述第四孔在所述绝缘层的子孔在所述衬底的正投影中，靠近所述第一栅电极的边界和靠近所述第三字线的边界落入所述第四孔在所述导电层的子孔在所述衬底的正投影内，背离所述第一栅电极的边界和背离所述第三字线的边界落在所述第四孔在所述导电层的子孔在所述衬底的正投影的边界上。
  13. 根据权利要求12所述的半导体器件，其中，所述半导体器件还包括，设置在所述第二字线背离所述第一栅电极一侧且沿所述第二方向延伸的第二横向凹槽，所述第二横向凹槽与所述第四孔连通，所述第二横向凹槽的开口背离所述第二字线和所述第三字线，所述第二半导体层还分布在所述第二横向凹槽的侧壁和底壁。
  14. 根据权利要求13所述的半导体器件，其中，沿所述第二方向分布的同一列的第二晶体管的第二半导体层之间断开。
  15. 根据权利要求13所述的半导体器件，其中，所述半导体器件还包括：分布在设置有所述第二半导体层的所述第二横向凹槽中且填充所述第二横向凹槽的第二位线。
  16. 根据权利要求15所述的半导体器件，其中，所述半导体器件还包括：贯穿所述绝缘层和所述导电层的第五孔，且所述第五孔从外到内依次分布有第四栅极绝缘层和所述第三字线，所述第三字线填充所述第五孔；且所述第五孔在所述导电层的子孔在所述衬底的正投影中，靠近所述第二位线的边界和靠近所述第二字线的边界落入所述第五孔在所述绝缘层的子孔在所述衬底的正投影内，背离所述第二位线的边界和背离所述第二字线的边界落在所述第五孔在所述绝缘层的子孔在所述衬底的正投影的边界上。
  17. 一种半导体器件的制造方法，包括：
    提供衬底，在所述衬底上形成包括交替设置的功能层和牺牲层的堆叠结构，所述堆叠结构包括多个存储单元区，所述存储单元区包括沿平行于衬底的第一方向分布的第一晶体管区和第二晶体管区；
    在所述第一晶体管区形成设置在所述功能层的第一栅电极和第一半导体层，以及，形 成沿垂直于衬底方向贯穿每层的第一字线，所述第一半导体层部分环绕所述第一栅电极，所述第一字线设置在所述第一半导体层背离所述第一栅电极一侧，不同层相同位置的存储单元的所述第一栅电极沿垂直于所述衬底的方向堆叠且间隔分布，不同层相同位置的第一晶体管的第二栅电极为所述第一字线的一部分；
    在所述第二晶体管区形成第二字线、第三字线和第二半导体层；所述第一栅电极与所述第二半导体层连接；所述第二半导体层部分环绕所述第二字线；所述第三字线形成有开口朝向所述第二字线的沿垂直于衬底方向间隔分布的多个第一凹槽，所述第一凹槽的底壁和侧壁分布有所述第二半导体层，所述第二字线形成有分别朝向多个所述第一凹槽的多个凸起。
  18. 根据权利要求17所述的半导体器件的制造方法，其中，在所述衬底上形成包括交替设置的功能层和牺牲层的堆叠结构包括：
    在所述衬底上依次沉积半导体薄膜和牺牲层薄膜，形成包括交替设置的半导体结构层和牺牲层的堆叠结构；
    对所述堆叠结构进行构图，形成贯穿每层的T形的第一沟槽，所述第一沟槽包括沿第一方向延伸的第一子沟槽和由所述第一子沟槽的非端部沿平行于所述衬底的第二方向延伸的第二子沟槽；沿第二方向间隔分布的相邻的第一子沟槽之间包括所述存储单元区，所述第一晶体管区和所述第二晶体管区分别设置在所述第二子沟槽两侧；所述第一方向和所述第二方向交叉；
    在所述第一晶体管区靠近一个第一沟槽的第一子沟槽处形成沿垂直于所述衬底的方向上贯穿所述堆叠结构的第一孔，所述第一孔的侧壁暴露所述第一子沟槽，通过所述第一孔刻蚀去除所述牺牲层，并将所述牺牲层替换为绝缘层。
  19. 根据权利要求18所述的半导体器件的制造方法，其中，在所述第一晶体管区形成设置在所述功能层的第一栅电极和第一半导体层，以及，形成沿垂直于衬底方向贯穿每层的第一字线包括：
    基于所述第一孔沿平行于所述衬底的方向刻蚀所述半导体结构层；在所述第一孔内形成多个第一半导体子层、第一栅极绝缘层、多个栅电极和隔离层；所述多个第一栅电极沿垂直于衬底方向间隔分布，所述多个第一半导体子层部分环绕所述第一栅电极且沿垂直于衬底方向间隔分布，所述第一栅极绝缘层设置在所述第一半导体子层和所述第一栅电极之间，所述第一栅电极部分环绕所述隔离层，所述隔离层填充所述第一孔；
    在所述第一晶体管区靠近另一个第一沟槽的第一子沟槽处形成沿垂直于所述衬底的方向上贯穿所述堆叠结构的第二孔，基于所述第二孔沿平行于所述衬底的方向刻蚀所述半导体结构层以暴露所述第一半导体子层，在所述第二孔内依次形成第二栅极绝缘层和填充所述第二孔的第一字线；所述第一孔和所述第二孔将所述第一晶体管区的半导体结构层间隔为包括独立的第一部分和第二部分的第二半导体子层；
    所述方法还包括：
    在所述第一晶体管区内所述第二孔和所述第二子沟槽之间形成沿垂直于所述衬底的方向上贯穿所述堆叠结构的第三孔，所述第三孔的侧壁暴露所述第二半导体子层的第二部分，在所述第三孔内形成填充所述第三孔且与所述第二半导体子层的第二部分接触的信号线。
  20. 根据权利要求19所述的半导体器件的制造方法，其中，在所述第二晶体管区形成第二字线、第三字线和第二半导体层包括：
    在所述第二晶体管区形成沿垂直于所述衬底的方向上贯穿所述堆叠结构的第四孔，基于所述第四孔沿平行于所述衬底的方向刻蚀所述半导体结构层、所述第一半导体子层、所述第一栅极绝缘层以暴露所述第一栅电极，形成横向凹槽；在所述第四孔内依次形成第二半导体层、第三栅极绝缘层和填充所述第四孔的第二字线，且所述第二半导体层形成在所述横向凹槽的底壁和侧壁；
    在所述第二晶体管区形成沿垂直于所述衬底的方向上贯穿所述堆叠结构的第五孔，所述第五孔与所述第四孔沿第二方向分布，基于所述第五孔沿平行于所述衬底的方向刻蚀所述半导体结构层、所述绝缘层以暴露所述第三栅极绝缘层和所述第二半导体层，在所述第五孔内依次形成第四栅极绝缘层和填充所述第五孔的第三字线。
  21. 根据权利要求19所述的半导体器件的制造方法，还包括：
    在沿第一方向相邻的第一晶体管区之间形成贯穿每层的第二沟槽，所述第二沟槽沿第二方向延伸；在所述第二沟槽内横向刻蚀所述半导体结构层且不暴露所述第一半导体子层，形成第一横向沟槽，在所述第一横向沟槽内形成填充所述第一横向沟槽的第一位线。
  22. 根据权利要求20所述的半导体器件的制造方法，还包括：
    在沿第一方向相邻的第二晶体管区之间形成贯穿每层的沿第二方向延伸的第三沟槽；在所述第三沟槽内横向刻蚀所述半导体结构层，形成第二横向沟槽，且所述第二横向沟槽与所述第四孔连通；
    在所述第四孔内形成所述第二半导体层时，还在所述第二横向沟槽的内壁上形成所述第二半导体层；在形成有所述第二半导体层的所述第二横向沟槽内形成填充所述第二横向沟槽的第二位线。
  23. 一种电子设备，包括如权利要求1至16任一所述的半导体器件，或者，根据权利要求17至22任一所述的半导体器件的制造方法形成的半导体器件。
PCT/CN2024/129996 2024-05-15 2024-11-05 一种半导体器件及其制造方法、电子设备 Pending WO2025236563A1 (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN202410606499.4A CN118201358B (zh) 2024-05-15 2024-05-15 一种半导体器件及其制造方法、电子设备
CN202410606499.4 2024-05-15

Publications (1)

Publication Number Publication Date
WO2025236563A1 true WO2025236563A1 (zh) 2025-11-20

Family

ID=91406783

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2024/129996 Pending WO2025236563A1 (zh) 2024-05-15 2024-11-05 一种半导体器件及其制造方法、电子设备

Country Status (2)

Country Link
CN (1) CN118201358B (zh)
WO (1) WO2025236563A1 (zh)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN118201358B (zh) * 2024-05-15 2024-07-16 北京超弦存储器研究院 一种半导体器件及其制造方法、电子设备

Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115346987A (zh) * 2022-10-18 2022-11-15 北京超弦存储器研究院 一种存储单元、3d存储器及其制备方法、电子设备
US20220383953A1 (en) * 2021-05-27 2022-12-01 Sunrise Memory Corporation Three-dimensional memory structure fabricated using repeated active stack sections
CN116193862A (zh) * 2022-10-18 2023-05-30 北京超弦存储器研究院 存储单元、存储器和电子设备
CN116648061A (zh) * 2023-06-09 2023-08-25 长鑫存储技术有限公司 存储单元、存储阵列及存储阵列的形成方法
US20230337438A1 (en) * 2022-04-19 2023-10-19 Samsung Electronics Co., Ltd. Semiconductor devices and data storage systems including the same
CN117222222A (zh) * 2022-05-31 2023-12-12 长鑫存储技术有限公司 半导体结构及其制作方法
CN117615572A (zh) * 2022-08-22 2024-02-27 细美事有限公司 半导体设备及制造半导体设备的方法
CN117715419A (zh) * 2024-02-06 2024-03-15 北京超弦存储器研究院 存储单元、存储器、存储器的制备方法、芯片及电子设备
CN117835693A (zh) * 2022-09-27 2024-04-05 华为技术有限公司 一种存储阵列、存储器及电子设备
CN118201358A (zh) * 2024-05-15 2024-06-14 北京超弦存储器研究院 一种半导体器件及其制造方法、电子设备

Patent Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20220383953A1 (en) * 2021-05-27 2022-12-01 Sunrise Memory Corporation Three-dimensional memory structure fabricated using repeated active stack sections
US20230337438A1 (en) * 2022-04-19 2023-10-19 Samsung Electronics Co., Ltd. Semiconductor devices and data storage systems including the same
CN117222222A (zh) * 2022-05-31 2023-12-12 长鑫存储技术有限公司 半导体结构及其制作方法
CN117615572A (zh) * 2022-08-22 2024-02-27 细美事有限公司 半导体设备及制造半导体设备的方法
CN117835693A (zh) * 2022-09-27 2024-04-05 华为技术有限公司 一种存储阵列、存储器及电子设备
CN115346987A (zh) * 2022-10-18 2022-11-15 北京超弦存储器研究院 一种存储单元、3d存储器及其制备方法、电子设备
CN116193862A (zh) * 2022-10-18 2023-05-30 北京超弦存储器研究院 存储单元、存储器和电子设备
CN116648061A (zh) * 2023-06-09 2023-08-25 长鑫存储技术有限公司 存储单元、存储阵列及存储阵列的形成方法
CN117715419A (zh) * 2024-02-06 2024-03-15 北京超弦存储器研究院 存储单元、存储器、存储器的制备方法、芯片及电子设备
CN118201358A (zh) * 2024-05-15 2024-06-14 北京超弦存储器研究院 一种半导体器件及其制造方法、电子设备

Also Published As

Publication number Publication date
CN118201358A (zh) 2024-06-14
CN118201358B (zh) 2024-07-16

Similar Documents

Publication Publication Date Title
WO2025030798A9 (zh) 半导体器件及其制造方法、电子设备
WO2024164470A1 (zh) 3d堆叠的半导体器件及其制造方法、3d存储器、电子设备
WO2024192874A1 (zh) 晶体管、3d堆叠的半导体器件及其制造方法、电子设备
KR20260010454A (ko) 3차원 메모리 및 그 제조 방법, 전자 장비
WO2025241407A1 (zh) 一种半导体器件及其制造方法、电子设备
WO2025060315A1 (zh) 半导体器件及其制造方法、电子设备
WO2025039539A1 (zh) 半导体器件及其制造方法、电子设备
WO2025030893A1 (zh) 半导体器件及其制造方法、电子设备
CN118317603B (zh) 半导体器件及其制造方法、电子设备
WO2025030892A1 (zh) 半导体器件及其制造方法、电子设备
WO2025236563A1 (zh) 一种半导体器件及其制造方法、电子设备
WO2025227605A1 (zh) 一种半导体器件及其制造方法、电子设备
CN121057196A (zh) 一种半导体器件及其制造方法、电子设备、访问方法
WO2025130187A9 (zh) 一种半导体器件及其制造方法、电子设备
WO2024159668A1 (zh) 3d堆叠的半导体器件、阵列及其制造方法、电子设备
CN119922905A (zh) 一种半导体器件及其制造方法、电子设备
WO2025130193A1 (zh) 一种半导体器件及其制造方法、电子设备
CN119922906B (zh) 一种半导体器件及其制造方法、电子设备
WO2026020615A1 (zh) 一种半导体器件及其制造方法、电子设备
US12238918B1 (en) Semiconductor device, manufacturing method therefor, and electronic device
US12328861B2 (en) Semiconductor device, manufacturing method therefor, and electronic equipment
WO2026020608A1 (zh) 一种半导体器件及其制造方法、电子设备
WO2026020609A1 (zh) 一种半导体器件及其制造方法、电子设备
WO2026020616A1 (zh) 一种半导体器件及其制造方法、电子设备
WO2025035767A1 (zh) 一种半导体器件及其制造方法、电子设备

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 24938571

Country of ref document: EP

Kind code of ref document: A1