WO2025236199A1

WO2025236199A1 - Sharing of spare lanes across chiplet i/o interface circuits

Info

Publication number: WO2025236199A1
Application number: PCT/CN2024/093307
Authority: WO
Inventors: Nehal Patel; Ramon A. MANGASER; Chao Yuan; Nooreen SAMNANI
Original assignee: ATI Technologies ULC; AMD Products China Co Ltd; Advanced Micro Devices Inc
Current assignee: ATI Technologies ULC; AMD Products China Co Ltd; Advanced Micro Devices Inc
Priority date: 2024-05-15
Filing date: 2024-05-15
Publication date: 2025-11-20
Anticipated expiration: 2026-11-15

Abstract

A chiplet can include a first interface circuit including first lanes, the first lanes including a particular first lane operable to selectively route one or more inputs of the particular first lane to a first output terminal of the particular first lane, and a second interface circuit including second lanes, the second lanes including a particular second lane operable to selectively route one or more inputs of the particular second lane to a second output terminal of the particular second lane. An output port of the particular first lane can be coupled to an input port of the particular second lane via an interconnect between the first and second interface circuits.

Description

SHARING OF SPARE LANES ACROSS CHIPLET I/O INTERFACE CIRCUITS

BACKGROUND

A recent trend in chip design is a system architecture that includes multiple “chiplets” in a package. A system of multiple chiplets offers modularity and flexibility in manufacturing. In a multi-chiplet system, data are transferred between chiplets through communication channels that connect the chiplets’ input-output interfaces.

BRIEF DESCRIPTION OF THE DRAWINGS

The accompanying drawings illustrate a number of example implementations and are a part of the specification. Together with the following description, these drawings demonstrate and explain various principles of the present disclosure.

FIG. 1A is a block diagram of an example of a multi-chiplet system with a 2.5D layout.

FIG. 1B is a block diagram of an example of a multi-chiplet system with a 3D layout.

FIG. 2A is a block diagram of an example of a chiplet.

FIG. 2B is a block diagram of an example of an input-output (I/O) interface system.

FIG. 2C is a block diagram of an example of an I/O interface unit.

FIG. 2D is a block diagram of an example of interconnected I/O interface units.

FIG. 3A is a block diagram of an example of interconnected I/O interface units with spare lanes.

FIG. 3B is a diagram of an example of a repair shift pattern for the I/O interface units of FIG. 3A.

FIG. 3C is a block diagram of an example of a repaired configuration of the I/O interface units of FIG. 3A.

FIG. 3D is a diagram of an example of a repair shift pattern for the repaired configuration of the I/O interface units of FIG. 3C.

FIG. 4A is a block diagram of another example of interconnected I/O interface units with spare lanes.

FIG. 4B is a diagram of an example of a repair shift pattern for the I/O interface units of FIG. 4A.

FIG. 4C is a block diagram of an example of a repaired configuration of the I/O interface units of FIG. 4A.

FIG. 4D is a diagram of an example of a repair shift pattern for the repaired configuration of the I/O interface units of FIG. 4C.

FIG. 5A is a block diagram of an example of an I/O interface unit with spare lanes.

FIG. 5B is a diagram of an example of a repair shift pattern for the I/O interface unit of FIG. 5A.

FIG. 5C is a block diagram of an example of a repaired configuration of the I/O interface unit of FIG. 5A.

FIG. 5D is a diagram of an example of a repair shift pattern for the repaired configuration of the I/O interface unit of FIG. 5C.

FIG. 6 is a block diagram of an example of a multi-chiplet system with spare lane sharing across I/O interface units.

FIG. 7A is a block diagram of an example of interconnected chiplets with spare lane share across I/O interface units.

FIG. 7B is a diagram of an example of a repair shift pattern for two I/O interface units of FIG. 7A with spare lane sharing.

FIG. 7C is a block diagram of an example of a repaired configuration of two I/O interface units of FIG. 7A with spare lane sharing.

FIG. 7D is a diagram of an example of a repair shift pattern for the repaired configuration of the I/O interface units of FIG. 7C.

FIG. 8 is a flowchart of an example an automated method for repairing a multi-chiplet system with spare lane sharing.

FIG. 9A is a block diagram of an example of an electronic design automation (EDA) tool.

FIG. 9B is a flowchart of an example of a method for manufacturing a chiplet with spare lane sharing.

FIG. 10 is a block diagram of an example of a computing device.

Throughout the drawings, identical reference characters and descriptions indicate similar, but not necessarily identical, elements. While the examples described herein are susceptible to various modifications and alternative forms, specific implementations have been shown by way of example in the drawings and will be described in detail herein. However, the example implementations described herein are not intended to be limited to the particular forms disclosed. Rather, the present disclosure covers all modifications, equivalents, and alternatives falling within the scope of the appended claims.

DETAILED DESCRIPTION OF EXAMPLE IMPLEMENTATIONS

The I/O interface system of a chiplet can be organized as a collection of I/O interface units, each having one or more data lanes. Data lanes on different I/O interface units of different chiplets can be coupled to a common interconnect to form a communication channel. The number of interconnects between chiplets in a multi-chiplet system is already large (e.g., tens of thousands of wires connected between chiplets within an advanced package) and rapidly increasing. Faulty die-to-die interconnects are common.

In some chiplets, an interface unit can have one or more spare lanes that can be used as substitutes for faulty lanes, thereby repairing the interface unit. In particular, some chiplets have one or two spare lanes per interface unit. However, ifthe number of faulty lanes (e.g., lanes coupled to defective communication channels) in an individual interface unit exceeds the number of spare lanes in the interface unit, this approach to I/O interface repair fails, and the multi-chip system is discarded. In some cases, some of the system’s chiplets can be harvested for reuse before the system is discarded, but the cost of discarding the package and any non-harvested chiplets remains high.

One possible solution to the problem of faulty lanes in chiplets is to increase the number of spare lanes in each interface unit. However, adding spare lanes on high-speed I/O interface units can reduce the speed of the I/O interface system, because scaling up each lane’s circuity to accommodate the additional spare lanes can increase the latency along the interface unit’s critical path.

The inventors have recognized and appreciated that chiplet interface repair can be made more robust by sharing spare lanes between interface units (e.g., physically or logically adjacent interface units) on a chiplet. For example, if a spare lane is not available to repair a faulty lane in a first interface unit, a spare lane of a second interface unit can be used to replace the faulty lane of the first interface unit. Sharing of spare lanes across interface units increases the repairability of faulty lanes by more efficiently using spare lanes, and thereby increases package yield without significantly increasing communication latency.

Sharing of spare lanes across interface units can be used to increase the repairability of faulty lanes without increasing the number of spare lanes on a chiplet and, therefore, without increasing the number of pins (or ‘bumps’ ) on the chiplet die. Thus, sharing of spare lanes across interface units can be added to newer versions of a chiplet while maintaining backward compatibility with older versions of the chiplet.

Sharing of spare lanes between interface units on a chiplet can be configured during package testing to address faulty lanes detected during the manufacturing process. In some examples, sharing of spare lanes can be reconfigured automatically and dynamically by controllers of the interface units as new faulty lanes are detected after the manufacturing process is complete (e.g., when the multi-chiplet system is in use) . Such reconfiguration of the interface units may be referred to herein as “soft repair. ”

This disclosure provides, with reference to FIGS. 1-7D and 10, detailed descriptions of example systems and devices for spare lane sharing across interface units of a chiplet. Detailed descriptions of related methods are provided in connection with FIGS. 8-9B.

In some aspects, the techniques described herein relate to a chiplet including: a first interface circuit including a plurality of first lanes, the plurality of first lanes including a particular first lane, the particular first lane operable to selectively route one or more inputs of the particular first lane to a first output terminal of the particular first lane; and a second interface circuit including a plurality of second lanes, the plurality of second lanes including a particular second lane, the particular second lane operable to selectively route one or more inputs of the particular second lane to a second output terminal of the particular second lane; wherein an output port of the particular first lane is coupled to an input port of the particular second lane via an interconnect between the first and second interface circuits.

In some aspects, the techniques described herein relate to a chiplet, wherein each first lane in the plurality of first lanes includes a first routing circuit operable to selectively route one or more inputs of the respective first lane to the first output terminal of the respective first lane, and wherein first interface circuit includes a first controller configured to control operation of the first routing circuits.

In some aspects, the techniques described herein relate to a chiplet, wherein each of the first routing circuits includes a respective multiplexer.

In some aspects, the techniques described herein relate to a chiplet, wherein each second lane in the plurality of second lanes includes a second routing circuit operable to selectively route one or more inputs of the respective second lane to an output terminal of the respective second lane, and wherein the second interface circuit includes a second controller configured to control operation of the second routing circuits.

In some aspects, the techniques described herein relate to a chiplet, wherein the particular second lane includes a particular second routing circuit of the second routing circuits, and wherein the particular second routing circuit is configured to selectively route the one or more inputs of the particular second lane to the second output terminal of the particular second lane.

In some aspects, the techniques described herein relate to a chiplet, wherein the plurality of first lanes includes one or more first data lanes and one or more first spare lanes, and wherein the plurality of second lanes includes one or more second data lanes and one or more second spare lanes.

In some aspects, the techniques described herein relate to a chiplet, wherein the particular first lane is a first data lane of the first interface circuit, and wherein the particular second lane is a second spare lane of the second interface circuit.

In some aspects, the techniques described herein relate to a chiplet, wherein the chiplet is a first chiplet disposed over a substrate of a multi-chiplet system and coupled to a second chiplet disposed over the substrate.

In some aspects, the techniques described herein relate to a chiplet, wherein each first lane in the plurality of first lanes of the first interface circuit of the first chiplet is coupled to a respective lane of a plurality of lanes of a interface circuit of the second chiplet, thereby forming a plurality of communication channels between the first and second chiplets.

In some aspects, the techniques described herein relate to a chiplet, wherein the first controller of first interface circuit of the first chiplet is configured to communicate with a controller of the interface circuit of the second chiplet to identify one or more communication channels in the plurality of communication channels as faulty.

In some aspects, the techniques described herein relate to a chiplet, wherein the first interface circuit is an instantiation of a macro cell, and the second interface circuit is an instantiation of the macro cell.

In some aspects, the techniques described herein relate to a controller-implemented method including: detecting a plurality of defective communication channels between a first plurality of interface circuits of a first chiplet of a multi-chiplet system and a second plurality of interface circuits of a second chiplet of the multi-chiplet system, wherein the first plurality of interface circuits includes a first interface circuit and a second interface circuit; and repairing the first plurality of interface circuits, including configuring a spare lane of the second interface circuit to route data between a data lane of the first interface circuit and a corresponding interface circuit in the second plurality of interface circuits.

In some aspects, the techniques described herein relate to a method, wherein: the plurality of defective communication channels includes a plurality of data lanes of the first plurality of interface circuits, wherein a number DU of defective communication channels associated with the first interface circuit is greater than a number SU of spare lanes in the first interface circuit, and wherein a total number DT of defective communication channels associated with the first plurality of interface circuits is less than or equal to a total number ST of spare lanes in the first plurality of interface circuits, and repairing the first plurality of interface circuits includes configuring a plurality of spare lanes of the first plurality of interface circuits to route data between a plurality of data lanes of the first plurality of interface circuits and the second plurality of interface circuits.

In some aspects, the techniques described herein relate to a method, wherein configuring a plurality of spare lanes of the first plurality of interface circuits to route data between a plurality of data lanes of the first plurality of interface circuits and the second plurality of interface circuits includes providing a plurality of control signals to a plurality of routing circuits of the plurality of spare lanes.

In some aspects, the techniques described herein relate to a method, wherein configuring the spare lane of the second interface circuit to route data between the data lane of the first interface circuit and the corresponding interface circuit in the second plurality of interface circuits includes configuring the spare lane to route data between the data lane of the first interface circuit and an output terminal of the spare lane of the second interface circuit via an interconnect coupling a first port of the first interface circuit and a second port of the second interface circuit.

In some aspects, the techniques described herein relate to a method, further including: detecting a plurality of defective communication channels between a third plurality of interface circuits of the first chiplet of the multi-chiplet system and a fourth plurality of interface circuits of a third chiplet of the multi-chiplet system, wherein a total number of defective communication channels associated with the third plurality of interface circuits is greater than a total number of spare lanes in the third plurality of interface circuits; and generating an alert indicating that the multi-chiplet system is unable to repair the plurality of defective communication channels between the first chiplet and the third chiplet.

In some aspects, the techniques described herein relate to a method, wherein detecting the plurality of defective communication channels between the first plurality of interface circuits of the first chiplet and the second plurality of interface circuits of the second chiplet includes: for each communication channel of a plurality of communication channels between the first plurality of interface circuits and the second plurality of interface circuits, transmitting a sequence of bits from a transmission lane of the respective communication channel to a reception lane of the respective communication channel via an interconnect coupling an output terminal of the transmission lane to an input terminal of the reception lane; and comparing a sequence of bits received by the reception lane to the sequence of bits transmitted by the transmission lane.

In some aspects, the techniques described herein relate to a chiplet manufacturing method, including: generating a representation of a physical implementation of a chiplet from a description of the chiplet, wherein the description of the chiplet includes a description of a plurality of interface circuits, wherein generating, the representation of the chiplet includes adding, to the representation of the chiplet, a plurality of macro cells implementing the plurality of interface circuits, wherein the plurality of macro cells includes a first macro cell and a second macro cell, wherein the first macro cell includes a first plurality of lanes including a first lane, wherein the second macro cell includes a second plurality of lanes including a second lane, wherein the first lane includes an output port, and wherein the second lane includes an input port; and manufacturing the chiplet based on the generated representation of the chiplet, wherein manufacturing the chiplet includes fabricating the chiplet using an integrated circuit fabrication process, wherein fabricating the chiplet includes fabricating an interconnect coupling the output port of the first lane of the first macro cell to the input port of the second lane of the second macro cell.

In some aspects, the techniques described herein relate to a method, wherein the interconnect is routed through one or more layers of the chiplet.

In some aspects, the techniques described herein relate to a method, wherein the chiplet is disposed over an interposer, the interposer is disposed over a substrate, and the chiplet is coupled to a second chiplet disposed over the interposer via an interconnect routed through the interposer and/or the substrate.

In some aspects, the techniques described herein relate to a method, wherein the representation of the chiplet includes a circuit schematic or an integrated circuit layout.

FIG. 1A illustrates an example of a multi-chiplet system 100 with a 2.5D layout. Multi-chiplet systems are sometimes described as “multi-chiplet modules, ” “hybrid integrated circuits, ” or “advanced packages. ” In the example of FIG. 1A, multi-chiplet system 100 includes chiplets 110 (e.g., chiplets 110a–110n) disposed on an interposer 120, which is disposed on a package substrate 130. The multi-chiplet system 100 also includes package-level pins 140 and chiplet interconnects 150. The chiplet interconnects 150 can be routed through the interposer 120 or through the interposer 120 and the package substrate 130. In some examples, the chiplets 110 can communication with each other via the interconnects 150 using any suitable communication standard or protocol including, without limitation, Universal Chiplet Interconnect Express (UCIe) , bunch of wires (BoW) , Open High Bandwidth Interconnect (OpenHBI) , the Optical Internetworking Forum (OIF) Extra Short Reach (XSR) , etc.

FIG. 1B illustrates an example of a multi-chiplet system with a 3D layout. In the example of FIG. 1B, multi-chiplet system 101 includes chiplets 111 (e.g., 111a–115a, 111b, 111n–115n) disposed on an interposer 121, which is disposed on a package substrate 131. The system 101 also includes chiplets 112-115 disposed on or over the chiplets 111. The multi-chiplet system 101 also includes package-level pins 141 and chiplet interconnects 151. The chiplet interconnects 151 can be routed through the chiplets 111-115, the interposer 121, and/or the package substrate 130. In some examples, the chiplets 111-115 can communication with each other via the interconnects 151 using any suitable communication standard or protocol.

FIG. 2A shows an example of a chiplet 200. In some examples, a chiplet is a discrete unpackaged die that can be assembled into a package with other chiplets. In some examples, achiplet 200 includes a functional unit 202 and an I/O interface system 204. Some non-limiting examples of types of chiplets include compute chiplets, memory chiplets, I/O chiplets, and fabric chiplets. In a compute chiplet, the functional unit 202 can include a processor (e.g., CPU core, GPU core, etc. ) . Some non-limiting examples of processors are described herein with reference to FIG. 10. In a memory chiplet, the functional unit 202 can include a memory module (e.g., DRAM, HBM, etc. ) or other computer-readable storage medium. Some examples of computer-readable storage media are described herein with reference to FIG. 10. In an I/O chiplet, the functional unit 202 can include an I/O interface that facilitates communication with other chiplets, peripheral devices, and/or other computing devices. In a fabric chiplet, the functional unit 202 can include a data transfer fabric (e.g., high-speed and/or high-bandwidth fabric) to facilitate communication between chiplets within a package or between other computing devices.

FIG. 2B shows an example of an input-output (I/O) interface system 210. An I/O interface system 210 can include one or more I/O interface units 212 (e.g., “I/O interface circuits” or “interface circuits” 212a–212n) .

FIG. 2C shows example of an I/O interface unit 220. The interface unit 220 can include a controller 222, one or more data lanes 224, and one or more spare lanes 226. In some examples, the controller 222 implements a communication protocol by processing data in one or more protocol layers and by controlling transmission of signals via the lane hardware. In some examples, the controller 222 can test the data lanes and spare lanes to detect defects. In some examples, the controller 222 can configure circuits within the lanes to route signals between the controller, the I/O terminals of the lanes, and/or the I/O ports of the interface unit 220.

A lane (224, 226) (e.g., communication lane) can transmit data to a device external from the chiplet 200 via an I/O terminal (e.g., a pin or bump coupled to an off-die interconnect) and/or receive data from a device external to the chiplet 200 via an I/O terminal. In some examples, in addition to transmitting data to and/or receiving data from an external device via an I/O terminal, a lane can transmit data to and/or receive data from other on-chiplet components via one or more I/O ports. In some examples, an I/O port includes circuitry (e.g., a buffer, latch, amplifier, etc. ) configured to transmit and/or receive data via an interconnect. In some examples, an I/O port is an interconnect used to transmit and/or receive data.

In some examples, a lane can be a transmission lane or a reception lane. A transmission lane can include a circuit operable to transmit data (e.g., a sequence of bits) via an output terminal. A reception lane can include a circuit operable to receive data (e.g., a sequence of bits) via an input terminal. In some examples, a lane (224, 226) can be a transceiver lane with circuitry operable to transmit and receive data via an I/O terminal.

In some examples, a transmission lane includes a routing component (e.g., “routing circuit” ) that can selectively route one more inputs of the lane to an output terminal of the lane. Selectively routing an input of the lane to an output terminal of the lane can include routing data received at an input port of the lane to the output terminal of the lane, and/or coupling the input port to the output terminal. Any suitable routing component can be used including, without limitation, a multiplexer, a multiway switch, etc. In some examples, the interface unit’s controller 222 can control the routing operations of the transmission lanes’ routing components (e.g., by providing suitable control signals to the routing components) .

In some examples, a reception lane includes a routing component that can selectively route one more inputs of the lane to an output port of the lane. Selectively routing an input of the lane to an output terminal of the lane can include routing data received at an input port or input terminal of the lane to the output port, and/or coupling the input port (or input terminal) to the output port. Any suitable routing component can be used including, without limitation, amultiplexer, a multiway switch, etc. In some examples, the interface unit’s controller 222 can control the routing operations of the reception lanes’ routing components (e.g., by providing suitable control signals to the routing components) .

A data lane 224 can be configured to transmit or receive data via an I/O terminal. Spare lanes can be used to replace faulty data lanes (e.g., defective data lanes and/or data lanes coupled to defective communication channels) , thereby facilitating repair of an interface unit 212 or interface system 204. An interface unit 220 can include any suitable number of data lanes (e.g., 8, 16, 32, 64, any integer between 1 and 256 or greater) and any suitable number of spare lanes (e.g., 1, 2, 3, 4, more than 4) .

In some examples, an interface unit 220 is synthesized and/or laid out during a chiplet fabrication process by instantiating a “cell” (e.g., a standard cell or macro cell) . Integrated circuits are often designed and fabricated by first preparing a schematic diagram or hardware description language (HDL) specification of a logical circuit in which functional elements are interconnected to perform a logical function. For example, with standard cell technology, the schematic diagram or HDL specification is synthesized into standard cells of a specific cell library. Each cell can correspond to a logical function unit, which can be implemented by one or more transistors optimized for the cell. The cells in the cell library can be defined by cell definitions. Each cell library definition can include a cell layout definition and cell characteristics. The cell layout definition can include a predetermined layout pattern for the transistors in the cell, geometry data for the cell’s transistors, and cell routing data.

These cells can correspond to low-level functions (e.g., logical “AND” and “OR” gates) or higher-level functions (e.g., phase-locked loops, memories, or central processing units (CPUs) ) . The higher-level cells are often referred to as “macro cells. ” A macro cell can include fully custom logic, one or more lower-level cells, and/or one or more higher-level cells. A hard macro cell includes a predefined layout pattern of pre-placed logical components within the cell, geometry data for these pre-placed components and routing data for routing the interconnections between the components. A hard macro cell can be selected from a cell library or other database and instantiated as a single unit within the overall layout pattern of an integrated circuit design. In some examples, an interface unit 220 is synthesized and/or laid out during a chiplet fabrication process by instantiating a hard macro cell from a cell library.

In the example of FIG. 2C, each interface unit 220 includes a controller 222 that configures and controls the lanes (224, 226) of the interface unit. In some examples, two or more interface units 220 share a controller external to those interface units (e.g., external to the macro cells for the interface units) .

FIG. 2D shows of an example of interconnected interface units on two chiplets (230, 260) . In the example FIG. 2D, chiplet 230 includes a first interface unit, which includes a controller 240, transmission lanes 250 (e.g., transmission lanes 250a–250b) , and reception lanes 255 (e.g., reception lanes 255a–255b) . The controller 240 can implement one or more layers of a communication protocol. For example, the controller 240 can implement a protocol layer 242, an adapter layer 244, and/or a physical layer 246. Any suitable protocol layer 242 can be used (e.g., CXL, PCIE, AXI, streaming, raw, custom, etc. ) . The adapter layer 244 can perform any suitable functions (e.g., multiplexing, cyclic redundancy check (CRC) , retry, etc. ) . The physical layer can perform any suitable functions (e.g., link training, lane repair, clocking, electrical control, etc. ) . Likewise, chiplet 260 includes a second interface unit, which includes a controller 270, transmission lanes 280 (e.g., transmission lanes 280a–280b) , and reception lanes 285 (e.g., reception lanes 285a–285b) . The controller 270 can implement one or more layers of a communication protocol (e.g., a protocol layer 242, an adapter layer 244, and/or a physical layer 246) .

FIG. 3A shows an example of interconnected interface units (300, 350) each having one spare lane and capable of selective, unidirectional shift of data inputs by one lane. Interface unit 300 can be disposed on a first chiplet and can replace a single faulty data lane (e.g., data lane 320a–320p) with a spare lane 330. Interface unit 350 can be disposed on a second chiplet and can replace a single faulty data lane (e.g., data lane 370a–370p) with a spare lane 380. Thus, the interface units (300, 350) can be configured to reroute their data inputs such that the spare lane substitutes for a faulty data lane, effectively repairing a single faulty communication channel between the interface units.

In the example of FIG. 3A, the interface unit 300 includes a controller 310 (e.g., controller 222 or 240) , multiple data transmission lanes 320 (e.g., data lanes 320a–320p) , and a spare transmission lane 330. Each data transmission lane 320 is provided with a data input 322 (e.g., data inputs 322a–322p) and a test input 324 (e.g., test inputs 324a–324p) . The data input 322 can be provided, for example, by the controller 310 or by a functional unit of the chiplet. The test input 324 can be provided, for example, by a pattern generator, which can be implemented by the controller 310. Each data transmission lane 320 can include an input multiplexer (MUX) 326, a lane repair multiplexer 327, an amplifier 328, and a package pin (or bump) 329. Other implementations of the data transmission lanes are possible. In some examples, the multiplexer 327a is omitted from data transmission lane 320a, and the output of the input multiplexer 326a is coupled directly to the input of the amplifier 328.

The spare transmission lane 330 is provided with a test input 334. The test input 334 can be provided, for example, by a pattern generator, which can be implemented by the controller 310. The spare transmission lane 330 can include an input multiplexer 336, a lane repair multiplexer 337, an amplifier 338, and a package pin (or bump) 339. Other implementations of the spare transmission lane are possible. In some examples, the input multiplexer 336 is omitted and the test input 334 is coupled directly to an input of the lane repair multiplexer 337.

In the example of FIG. 3A, the lane repair multiplexers 327 (e.g., multiplexers 327a–327p) and multiplexer 337 of the interface unit 300 are connected by repair interconnect 340 (e.g., repair interconnects 340a–340p) in a single-lane, unidirectional shift (right shift) configuration. In some examples, controller 310 can configure the lane repair multiplexers (e.g., by providing suitable input selection control signals to the lane repair multiplexers) to selectively reroute the lane inputs such that the spare transmission lane 330 effectively replaces one of the data transmission lanes 320.

In some examples, the architecture of interface unit 350 is the inverse of the architecture of interface unit 300. For example, the interface unit 350 can include a controller 360 (e.g., controller 222 or 240) , multiple data reception lanes 370, and a spare reception lane 380. Each data reception lane 370 can be coupled to a counterpart data transmission lane 320 by an interconnect, through which the data lane 370 can receive data transmitted by the counterpart data lane 320. The input of the data lane 370 can be received via a package pin (or bump) 379, amplified by an amplifier 378, and provided as input to a lane repair multiplexer 377. The output of the lane repair multiplexer 377 can be demultiplexed into data output 372 (e.g., data outputs 372a–327p) or test output 374 (e.g., test outputs 374a–374p) by a demultiplexer (DEMUX) 376. The data output 372 can be provided to the controller 360 or to a functional unit of the chiplet. The test output 374 can be provided, for example, to a pattern checker, which can compare the data pattern of the test output 374 to the data pattern of the test input 324 to determine whether the communication channel formed by the counterpart lanes 320 and 370 is defective. In some examples, the pattern checker is implemented by the controller 360. Other implementations of the data lanes 370 are possible.

The spare reception lane 380 can be coupled to a counterpart spare transmission lane 330 by an interconnect, through which the spare reception lane 380 can receive data transmitted by the counterpart spare transmission lane 330. The input of the spare reception lane 380 can be received via a package pin (or bump) 389, amplified by an amplifier 388, and provided as input to a lane repair multiplexer 387. The output of the lane repair multiplexer 387 can be demultiplexed into data output 382 or test output 384 by a demultiplexer (DEMUX) 386. The data output 382 can be provided to the controller 360 or to a functional unit of the chiplet. The test output 384 can be provided, for example, to a pattern checker, which can compare the data pattern of the test output 384 to the data pattern of the test input 334 to determine whether the communication channel formed by the counterpart spare lanes 330 and 380 is defective. In some examples, the pattern checker is implemented by the controller 360. Other implementations of the spare reception lanes 380 are possible. In some examples, the lane repair multiplexer 387 is omitted from spare reception lane 380, and the output of the amplifier 388 is coupled directly to the input of the DEMUX 386.

In the example of FIG. 3A, the lane repair multiplexers 377 and 387 of the interface unit 350 are connected by repair interconnect 390 (e.g., repair interconnects 390a–390p) in a single-lane, unidirectional shift (left shift) configuration. In some examples, controller 360 can configure the lane repair multiplexers (e.g., by providing suitable input selection control signals to the lane repair multiplexers) to selectively reroute the lane inputs such that the spare reception lane 380 effectively replaces one of the data reception lanes 370.

FIG. 3B shows an example of a repair shift pattern for the interface unit 300 of FIG. 3A. In the example of FIG. 3B, the interface unit 300 has a 16-bit data width (e.g., 16 bits, labeled Bit 0–Bit 15, transmitted over 16 data transmission lanes 370) . Bit 0 can be the data input 322a of data lane 320a, and Bit 15 can be the input data 322p of data lane 320p. The spare lane 330 is represented in FIG. 3B by the notation “SL. ”

FIG. 3C shows an example of a repaired configuration of the interface units (300, 350) of FIG. 3A. FIG. 3D shows an example of a repair shift pattern for the repaired configuration of FIG. 3C. In the example of FIGS. 3C and 3D, the communication channel formed by data lanes 320c and 370c (nominally intended for transmission of Bit 2) is faulty. In this case, repair multiplexers of data lanes 320d–320p and spare lane 330 reroute (right shift) Bits 2-15 from lanes 320c–320p (respectively) to lanes 320d–320p and 330 (respectively) . Bits 0-1 are transmitted by lanes 320a–320b without rerouting. In interface unit 350, the repair routing is the inverse of the above-described repair routing for interface unit 300. Bits 0 and 1 are received in data lanes 370a and 370b, respectively, without rerouting. Bits 2-15 are received in lanes 370d– 370p and 380, respectively, and rerouted (left shifted) into data lanes 370c–370p. Thus, the spare lanes (330, 380) can act as substitutes for the faulty lanes (320c, 370c) , thereby facilitating repair of the interface units (300, 350) .

When spare lanes are not shared between interface units within an I/O interface system, lane repair for the chiplet can fail ifthe number of faulty lanes in any interface unit exceeds the number of spare lanes in that interface unit. For example, in an interface unit with a single spare lane and no lane spare lane sharing, a short fault between two data lanes can be irreparable because a single spare lane is insufficient to reroute the data of the two faulty data lanes. Thus, expanding the interface units to include two or more spare lanes can further increase the units’ resilience to faulty lanes.

FIG. 4A shows an example of interconnected interface units (400, 450) each having two spare lanes and capable of selective, unidirectional shift of data inputs by a maximum distance of two lanes. Interface unit 400 can be disposed on a first chiplet and can replace two faulty data lanes (e.g., data lanes 420a–420p) with spare lanes (e.g., spare lanes 430a, 430b) . Interface unit 450 can be disposed on a second chiplet and can replace two faulty data lanes 470 with spare lanes 480. Thus, the interface units (400, 450) can be configured to reroute their data inputs such that the spare lanes (430, 480) substitute for two faulty data lanes (420, 470) , effectively repairing two faulty communication channel between the interface units.

In the example of FIG. 4A, the interface unit 400 includes a controller 410 (e.g., controller 222 or 240) , multiple data transmission lanes 420, and two spare transmission lanes 430. Each data transmission lane 420 is provided with a data input 422 (e.g., data inputs 422a–422p) and a test input 424 (e.g., test inputs 424a–424p) . The data input 422 can be provided, for example, by the controller 410 or by a functional unit of the chiplet. The test input 424 can be provided, for example, by a pattern generator, which can be implemented by the controller 410. Each data transmission lane 420 can include an input multiplexer (MUX) 426, a lane repair multiplexer427 (e.g., multiplexers 427a–427p) , an amplifier, and a package pin (or bump) . Other implementations of the data transmission lanes are possible. In some examples, the multiplexer427a is omitted from data transmission lane 420a, and the output of the input multiplexer426 is coupled directly to the input of the lane’s amplifier.

Each of the spare transmission lanes 430 is provided with a test input 434 (e.g., test input 434a, 434b) . Each test input 434 can be provided, for example, by a pattern generator, which can be implemented by the controller 410. A spare transmission lane 430 can include an input multiplexer436, a lane repair multiplexer437, an amplifier, and a package pin (or bump) . Other implementations of the spare transmission lanes are possible. In some examples, the input multiplexer436 is omitted and the test input 434 is coupled directly to an input of the lane repair multiplexer437.

In the example of FIG. 4A, the lane repair multiplexers 427 and 437 of the interface unit 400 are connected by repair interconnect 440 (e.g., repair interconnects 440a–440p) in a unidirectional shift (right shift) configuration with a maximum shift distance of two lanes. In some examples, controller410 can configure the lane repair multiplexers (e.g., by providing suitable input selection control signals to the lane repair multiplexers) to selectively reroute the lane inputs such that the spare transmission lanes 430 effectively replace two of the data transmission lanes 420.

In some examples, the architecture of interface unit 450 is the inverse of the architecture of interface unit 400. For example, the interface unit 450 can include a controller 460 (e.g., controller 222 or 240) , multiple data reception lanes 470 (e.g., data reception lanes 470a–470p) , and spare reception lanes 480 (e.g., spare reception lanes 480a, 480b) . Each data reception lane 470 can be coupled to a counterpart data transmission lane 420 by an interconnect, through which the data lane 470 can receive data transmitted by the counterpart data lane 420. The input of the data lane 470 can be received via a package pin (or bump) , amplified by an amplifier, and provided as input to a lane repair multiplexer 477. The output of the lane repair multiplexer477 can be demultiplexed into data output 472 (e.g., data output 472a–472p) or test output 474 (e.g., test output 474a–474p) by a demultiplexer (DEMUX) . The data output 472 can be provided to the controller460 or to a functional unit of the chiplet. The test output 474 can be provided, for example, to a pattern checker, which can compare the data pattern of the test output 474 to the data pattern of the test input 424 to determine whether the communication channel formed by the counterpart lanes 420 and 470 is defective. In some examples, the pattern checker is implemented by the controller 460. Other implementations of the data reception lanes 470 are possible.

The spare reception lane 480 can be coupled to a counterpart spare transmission lane 430 by an interconnect, through which the spare reception lane 480 can receive data transmitted by the counterpart spare transmission lane 430. The input of the spare reception lane 480 can be received via a package pin (or bump) , amplified by an amplifier, and provided as input to a lane repair multiplexer 487. The output of the lane repair multiplexer 487 can be demultiplexed into data output 482 or test output484 by a DEMUX. The data output 482 can be provided to the controller460 or to a functional unit of the chiplet. The test output 484 can be provided, for example, to a pattern checker. In some examples, the pattern checker is implemented by the controller460. Other implementations of the spare reception lanes 480 are possible. In some examples, the lane repair multiplexer 487 is omitted from spare reception lane 480b, and the output of the lane’s amplifier is coupled directly to the input of the DEMUX.

In the example of FIG. 4A, the lane repair multiplexers 477 (e.g., lane repair multiplexer 477a) and the lane repair multiplexers 487 (e.g., lane repair multiplexer 487a, 487b) of the interface unit 450 are connected by repair interconnect 490 (e.g., repair interconnect 490b–490p) in a unidirectional shift (left shift) configuration with a maximum shift distance of two lanes. In some examples, controller 460 can configure the lane repair multiplexers (e.g., by providing suitable input selection control signals to the lane repair multiplexers) to selectively reroute the lane inputs such that the spare reception lanes 480 effectively replace two of the data reception lanes 470.

FIG. 4B shows an example of a repair shift pattern for the interface unit 400 of FIG. 4A. In the example of FIG. 4B, the interface unit 400 has a 16-bit data width (e.g., 16 bits, labeled Bit 0–Bit 15, transmitted over 16 data transmission lanes 470) . Bit 0 can be the data input 422a of data lane 420a, and Bit 15 can be the data input 422p of data lane 420p. The spare lanes 430a and430b are represented in FIG. 4B by the notation “SL1” and “SL2, ” respectively.

FIG. 4C shows an example of a repaired configuration of the interface units (400, 450) of FIG. 4A. FIG. 4D shows an example of a repair shift pattern for the repaired configuration of FIG. 4C. In the example of FIGS. 4C and4D, the communication channel formed by data lanes 420b and 470b (nominally intended for transmission of Bit 1) and the communication channel formed by data lanes 420d and 470d (nominally intended for transmission of Bit 3) are faulty. In this case, the lane repair multiplexer of data lane 420c reroutes (right shifts) Bit 1 from lanes 420b to lane 420c, and the repair multiplexers of data lanes 420e–420p and spare lanes 430a–430b reroute (right shift) Bits 2-15 from lanes 420c–420p to lanes 420e–420p and spare lanes 430a–430b, respectively. Bit 0 is transmitted by lane 420a without rerouting. In interface unit 450, the repair routing is the inverse of the above-described repair routing for interface unit 400. Thus, the spare lanes (430, 480) can act as substitutes for the faulty lanes (420b/470b and 420d /470d) , thereby facilitating repair of the interface units (400, 450) .

FIG. 5A shows an example of an interface unit 500 having two spare lanes 530 and capable of selective, bidirectional shift of data inputs by a maximum distance of one lane. Interface unit 500 can replace two faulty data lanes 520 with spare lanes 530. Thus, interface unit 500 can be configured to reroute data inputs such that the spare lanes 530 substitute for two faulty data lanes 520, effectively repairing two faulty data lanes. In the example of FIG 5A, interface unit 500 can be disposed on a first chiplet and coupled (e.g., by inter-chiplet interconnects) to a second interface unit (not shown) disposed on a second chiplet.

In the example of FIG. 5A, the interface unit 500 includes a controller 510 (e.g., controller 222 or 240) , multiple data transmission lanes 520 (e.g., data transmission lanes 520a–520p) , and two spare transmission lanes 530 (e.g., data transmission lanes 530a, 530b) . Each data transmission lane 520 is provided with a data input 522 (e.g., data input 522a–522p) and a test input 524 (e.g., test input 524a–524p) . The data input 522 can be provided, for example, by the controller 510 or by a functional unit of the chiplet. The test input 524 can be provided, for example, by a pattern generator. Each data transmission lane 520 can include an input multiplexer 526 and a lane repair multiplexer 527. Other implementations of the data transmission lanes are possible.

Each of the spare transmission lanes 530 is provided with a test input 534. Each test input 534 can be provided, for example, by a pattern generator. A spare transmission lane 530 can include an input multiplexer 536 and a lane repair multiplexer 537. Other implementations of the spare transmission lanes are possible. In some examples, the input multiplexer 536 is omitted and the test input 534 is coupled directly to an input of the lane repair multiplexer 537.

In the example of FIG. 5A, the lane repair multiplexers 527 and 537 of the interface unit 500 are connected by repair interconnect 540 (e.g., repair interconnect 540a–540c) in a bidirectional shift configuration with a maximum shift distance of one lane in either direction. In some examples, controller 510 can configure the lane repair multiplexers (e.g., by providing suitable input selection control signals to the lane repair multiplexers) to selectively reroute the lane inputs such that the spare transmission lanes 530 effectively replace two of the data transmission lanes 520.

FIG. 5B shows an example of a repair shift pattern for the interface unit 500 of FIG. 5A. In the example of FIG. 5B, the interface unit 500 has a 16-bit data width (e.g., 16 bits, labeled Bit 0–Bit 15, transmitted over 16 data transmission lanes 520) . Bit 0 can be the data input 522a of data lane 520a, and Bit 15 can be the data input 522p of data lane 520p. The spare lanes 530a and 530b are represented in FIG. 5B by the notation “SL1” and “SL2, ” respectively.

FIG. 5C shows an example of a repaired configuration of the interface unit 500 of FIG. 5A. FIG. 5D shows an example of a repair shift pattern for the repaired configuration of FIG. 5C. In the example of FIGS. 5C and 5D, data lanes 520b and 520d (nominally intended for transmission of Bits 1 and 3, respectively) are faulty. In this case, the repair multiplexers of lanes 530a and 520a reroute (left shift) Bits 0 and 1 from lanes 520a and 520b to lanes 530a and 520a, respectively. In addition, the repair multiplexers of data lanes 520e–520p and spare lane 530b reroute (right shift) Bits 3-15 from lanes 520d–520p to lanes 520e–520p and 530b, respectively. Bit 2 is transmitted by lane 520c without rerouting. Thus, the spare lanes 530 can act as substitutes for the faulty lanes (520b, 520d) , thereby facilitating repair of the interface unit 500.

FIG. 6 shows an example of a multi-chiplet system 600 with spare lane sharing across I/O interface units. In the example of FIG. 6, the multi-chiplet system 600 includes chiplets 610 and 630. Chiplet 610 includes a functional unit 612 and I/O interface system 620. The I/O interface system 620 includes multiple interface units 622 (e.g., interface units 622a–622p) . One or more subsets of the interface units 622 (e.g., physically and/or logically adjacent pairs of interface units 622) are coupled by interconnects 624 (e.g., interconnects 624a, 624b) . In some examples, the interface units 622 coupled by an interconnect 624 can use the interconnect 624 to implement spare lane sharing. For example, interface units 622a and 622b coupled by an interconnect 624a can use the interconnect 624a to shift data from a lane of interface unit 622a to a lane of interface unit 622b or vice-versa.

Chiplet 630 includes functional unit 632 and I/O interface system 640. I/O interface system 640 includes multiple interface units 642 (e.g., interface units 642a–642p) . One or more subsets of the interface units 642 (e.g., logically or physically adjacent pairs of interface units) are coupled by interconnects 644 (e.g., interconnects 644a, 644b) . In some examples, the interface units 642 coupled by an interconnect 644 can use the interconnect 644 to implement spare lane sharing. For example, interface units 642a and 642b coupled by an interconnect 644a can use the interconnect 644a to shift data from a lane of interface unit 642a to a lane of interface unit 642b or vice-versa. In the example of FIG. 6, each interface unit 622 on chiplet 610 is coupled to a corresponding interface unit 642 on chiplet 630 by one or more interconnects 650.

Assuming a set of N interface units on a chiplet are coupled for spare lane sharing and each of the interface units has M spare lanes, up to N*M faulty lanes within the N interface units can be repaired using spare lane sharing. In the example of FIG. 6, all of the interface units 622 in I/O interface system 620 are arranged and coupled serially (e.g., in a daisy chain topology) , with physically adjacent interface units 622 being directly coupled to each other. (In this context, two interface units 622 are ‘directly coupled’ to each other if at least one of the interface units is able to reroute data from one or more of its lanes into one or more lanes of the other interface unit without routing that data through a third interface unit, even if the hardware used to directly couple the two interface units includes components other than or in addition to a simple interconnect. ) In some examples, distinct subsets of the interface units 622 are daisy-chained. In some examples, some or all of the interface units 622 are connected in a ring topology for lane sharing. Other topographical arrangements and couplings of the interface units 622 for purposes of lane sharing are possible.

FIG. 7A shows an example of a multi-chiplet system in which spare lanes are shared across interface units within each chiplet’s I/O interface system. In the example of FIG. 7A, the multi-chiplet system includes chiplets 700 and 701. The I/O interface system of chiplet 700 includes interface units 702 and 704. The I/O interface system of chiplet 701 includes interface units 706 and 708.

In some examples, interface unit 702 supports spare lane sharing with bidirectional shift of up to two lanes in either direction and two spare lanes. Interface unit 702 can include a controller 710, data transmission lanes 720a–720p, and two spare transmission lanes 730a and 730b. Each data transmission lane includes a data input 722 (e.g., data inputs 722a–722p) , a test input 724 (e.g., test inputs 724a–724p) , and a lane repair multiplexer 727 (e.g., multiplexers 727a–727p) . Each spare transmission lane 730 includes a test input 734 (e.g., test inputs 734a–734p) and a lane repair multiplexer 737 (e.g., multiplexers 737a, 737b) .

In the example of FIG. 7A, the selected input 733a of data lane 720a is coupled to a lane sharing output 751a of the interface unit 702, which can be coupled to a lane sharing input of another interface unit IFUx (not shown) on the chiplet 700. Likewise, the input 733a of spare lane 730a is optionally coupled to a lane sharing output 752a of the interface unit 702, which can be coupled to another lane sharing input of interface unit IFUx. Likewise, the interface unit 702 has a lane sharing input 753a coupled to the lane repair multiplexer 737a of spare lane 730a. Optionally, the interface unit 702 has another lane sharing input 754a coupled to the lane repair multiplexers 737a and 727a of spare lane 730a and data lane 720a, respectively.

In the example of FIG. 7A, the selected input of data lane 720p is coupled to a lane sharing output 758a of the interface unit 702. The selected input of spare lane 730b is optionally coupled to another lane sharing output 757a of the interface unit 702. Likewise, the interface unit 702 has a lane sharing input 756a coupled to the lane repair multiplexer 737b of spare lane 730b. Optionally, the interface unit 702 has another lane sharing input 755a coupled to the lane repair multiplexers 737b and 727p of spare lane 730b and data lane 720p, respectively.

In some examples, interface unit 704 also supports spare lane sharing with bidirectional shift of up to two lanes in either direction and two spare lanes. Interface unit 702 can include a controller 740, data transmission lanes 742a–742p, and two spare transmission lanes 744a and 744b. Each data lane can include a data input, a test input, and a lane repair multiplexer. The selected input of data lane 742a can be coupled to a lane sharing output 752b of the interface unit 704, which can be coupled to lane sharing input 756a of interface unit 702. The selected input of spare lane 744a is optionally coupled to another lane sharing output 751b of interface unit 704, which can be coupled to input 755a of interface unit 702. Likewise, the interface unit 704 has a lane sharing input 754b coupled to the lane repair multiplexer of spare lane 744a. Lane sharing input 754b of interface unit 704 can be coupled to lane sharing output 758a of interface unit 702. Optionally, the interface unit 704 has another lane sharing input 753b coupled to the lane repair multiplexers of spare lane 744a and data lane 742a. Lane sharing input 753b of interface unit 704 can be coupled to lane sharing output 757a of interface unit 702.

In some examples, interface units 706 and 708 of chiplet 701 also support spare lane sharing with bidirectional shift of up to two lanes in either direction and two spare lanes. Interface unit 706 can include a controller 760, data reception lanes 762a–762p, and two spare reception lanes 764a and 764b. The data reception lanes 762a–762p can be coupled to the corresponding data transmission lanes 720a–720p of interface unit 702 by interconnects. Interface unit 708 can include a controller 780, data reception lanes 782a–782p, and two spare reception lanes 784a and 784b. The data reception lanes 782a–782p can be coupled to the corresponding data transmission lanes 742a–742p of interface unit 704 by interconnects. The reception lanes can perform the inverse function (and can have inverse schematics) of the respective transmission lanes to which they are coupled. Like transmission interface units 702 and 704, each of reception interface units 706 and 708 provides one or more lane sharing inputs and/or lane sharing outputs configured to be coupled to the corresponding lane sharing output (s) and/or input (s) of other interface units on chiplet 701 to facilitate spare lane sharing.

In some examples, the controllers of the interface units cooperate (e.g., communicate) with each other to establish repair recipes and configure the lane repair multiplexers to implement those repair recipes, as described in further detail below with reference to Fig. 8. A repair recipe can be a configuration of a set of interface units that repairs one or more (e.g., all) the faulty lanes in those interface units.

In the example of FIG. 7A, each interface unit has a dedicated controller. In some examples, two or more (e.g., all) interface units in an I/O interface system can share a controller, which may be disposed outside macro cells that implement those interface units.

FIG. 7B shows an example of a repair shift pattern for interface units 702 and 704 of FIG. 7A, which are coupled for spare lane sharing. In the example of FIG. 7B, the interface unit 702 has a 16-bit data width (e.g., 16 bits, labeled Bit 0x–Bit 15x, transmitted over 16 data transmission lanes 720) . Bit 0x can be the data input 722a of data lane 720a, and Bit 15x can be the data input 722p of data lane 720p. The spare lanes 730a and 730b of interface unit 702 are represented in FIG. 7B by the notation “SL1x” and “SL2x, ” respectively. Also, in the example of FIG. 7B, the interface unit 704 has a 16-bit data width (e.g., 16 bits, labeled Bit 0y–Bit 15y, transmitted over 16 data transmission lanes 742) . Bit 0y can be the input data of data lane 742a, and Bit 15y can be the input data of data lane 742p. The spare lanes 744a and 744b of interface unit 704 are represented in FIG. 7B by the notation “SL1y” and “SL2y, ” respectively.

FIG. 7C shows an example of a repaired configuration of the interface units 702 and 704 of FIG. 7A with spare lane sharing. FIG. 7D shows an example of a repair shift pattern for the repaired configuration of FIG. 7C. In the example of FIGS. 7C and 7D, data lanes 720c, 720d, and 720e (nominally intended for transmission of Bits 2x, 3x, and 4x, respectively) are faulty. In this case, the repair multiplexers of lanes 730a, 720a, and 720b reroute (left shift) Bits 0x-2x from lanes 720a-720c to lanes 730a and 720a–720b, respectively. In addition, the repair multiplexers of data lanes 720f–720p, spare lane 730b, and spare lane 744 (of interface unit 704) reroute (right shift) Bits 3x–15x from lanes 720d–720p to lanes 720f–720p, 730b, and 744a, respectively. Thus, the spare lanes 730a and 730b of interface unit 702 and the spare lane 744a of interfance unit 704 can act as substitutes for the faulty lanes (720c–720e) of interface unit 702, thereby facilitating repair of the interface unit 702.

In the example of FIGS. 7C and 7D, data lane 742d (nominally intended for transmission of Bit 4y) is faulty. In this case, the repair multiplexers of lanes 742d–742p and 744b reroute (right shift) Bits 4y–15y from lanes 742d–742p to lanes 742e–742p and 744b, respectively. Bits 0y–3y are transmitted from lanes 742a–742c, respectively, without rerouting.

FIG. 8 shows an example of an automated method 800 for repairing a multi-chiplet system with spare lane sharing. In some examples, the automated repair method 800 is used during a manufacturing process (e.g., during post-silicon testing of a multi-chiplet system) to detect defective communication channels and repair the communication interfaces between chiplets. In some examples, the automated repair method 800 is used during operation of the multi-chiplet system to dynamically detect new defects in communication channels and automatically repair those defects.

In some examples, the method 800 is performed by the controller (s) of one or more I/O interface systems of one or more chiplets of the multi-chiplet system. For example, the method 800 can be performed by the controller (s) of a set of interface units of a chiplet in the multi-chiplet system. In some examples, the controller (s) performing the method 800 interact (e.g., communicate) with the controller (s) of other interface unit (s) in the multi-chiplet system to carry out the method 800.

At step 810 of the automated repair method, defective communication channels between interface units of a first chiplet of a multi-chiplet system and interface units of a second chiplet of the multi-chiplet system are detected. The defective channels may be detected using any suitable technique. In some examples, the controllers of the lanes of the interface units coupled to each other to form communication channels between a pair (or set) of chiplets interact (e.g., communicate) to test those communication channels. For example, for each communication channel between the interface units of the first chiplet and the interface units of the second chiplet, the controller of the channel’s transmission lane can transmit a pattern (e.g., sequence of bits) from the transmission lane to the channel’s reception lane via an interconnect coupling the I/O terminals of the transmission and reception lanes, and the controller of the reception lane can compare the received pattern (e.g., sequence of bits) to the transmitted pattern. If the patterns do not match, the channel can be retested or classified as defective (e.g., by the controllers) . This detection process can be performed for each communication channel coupling any two chiplets in the multi-chip system.

At step 820 of the automated repair method, the interface units of the first chiplet that are included in the collective communication channel between the first and second chiplets can be repaired (e.g., by the controller (s) of the interface units of the first chiplet) . Repairing a set of interface units of a chiplet can include configuring spare lanes of that set of interface units to route data between data lanes of those interface units and the corresponding interface units of the second chiplet, such that the interface units of the first chiplet bypass the defective communication channels between the first and second chiplets. In some examples, configuring spare lanes of a set of interface units of a first chiplet to route data between data lanes of those interface units and interface units of a second chiplet includes providing control signals to routing components of the spare lanes.

In some examples, repairing a set of interface units of a chiplet can include configuring a spare lane of an interface unit U₂ in the set of interface units of the chiplet to route data between a data lane of another interface unit U₁ in the set of interface units and a corresponding interface unit of the second chiplet. In some examples, configuring the spare lane of interface unit U₂ to route data between the data lane of the interface unit U₁ and the corresponding interface unit of the second chiplet includes configuring the spare lane of U₂ to route data between the data lane of U₁ and an output terminal of the spare lane via an interconnect coupling a first port of U₁ and a second port of U₂.

In some examples, step 820 of the automated repair method further includes repairing the interface units of the second chiplet that are included in the collective communication channel between the first and second chiplets (e.g., by the controller (s) of the interface units of the second chiplet) , such that the defective, individual communication channels between the first and second chiplets are bypassed and the nominal aggregate communication bandwidth between the first and second chiplets is restored.

In some examples, before performing step 820, the controller (s) of the interface units included in the communication channel between the first and second chiplets may assess whether the chiplets are able to automatically repair the defective communication channels. For example, the controllers may assess whether a total number D_T of defective communication channels between the first and second chiplets is less than or equal to a total number S_T of spare lanes in the interface units that form the collective communication channel between the first and second chiplets. If so, the controllers may determine that the collective communication channel between the first and second chiplets is repairable. If a number D_U of defective communication channels associated with a particular interface unit is greater than a number S_U of spare lanes in that interface unit, the controllers may determine that spare lane sharing can be used to repair that interface unit.

Alternatively, ifthe total number D_T of defective communication channels between the first and second chiplets is greater than a total number S_T of spare lanes in the interface units that form the collective communication channel between the first and second chiplets, the controllers can determine that the chiplets are unable to repair the defects in the collective communication channel between the chiplets, even if spare lane sharing is used. In this case, the first and/or second chiplet can generate an alert indicating that the multi-chiplet system is unable to repair the defective communication channels between the chiplets. In this case, a manufacturer or operator of the multi-chiplet chip can discard the multi-chip system, attempt to harvest one or more functioning chiplets from the multi-chiplet system, and/or attempt to manually repair the defective communication channels.

In a multi-chiplet system in which multiple pairs (or sets) of chiplets are communicatively coupled (e.g., directly communicatively coupled) to each other via their interface units, the repair method 800 can be carried out for each pair (or set) of coupled chiplets.

Still referring to step 820, repairing the interface units of a chiplet (e.g., configuring the interface units to share spare lanes to bypass defective data lanes) can include determining the routing path (e.g., repair shift pattern) for each of the affected interface units. In some examples, a centralized processor can determine the routing paths for all of the affected interface units based on the defective communication channels, the number and location of the spare lanes within each interface unit, and the routing capabilities (e.g., shift-left/shift-right/bidirectional shift by up to K lanes) of each interface unit. The controllers of the affected interface units can then configure the routing components of those interface units to implement the determined routing path. Alternatively, a distributed technique for determining the routing paths of the affected interface units can be used.

FIG. 9A shows an example of an electronic design automation (EDA) tool. In some examples, an electronic design automation (EDA) tool can facilitate design, simulation, verification, and/or manufacturing of chiplets or multi-chiplet systems. In general, EDA tools are used to design, simulate, verify, and/or prepare for manufacturing of electronic systems (e.g., integrated circuits, printed circuit boards, etc. ) .

As shown in FIG. 9A, some examples of an EDA tool 900 can include one or more facilities, for example, a design facility 910, a verification facility 920, and/or a manufacturing facility 930. In some examples, the design facility 910 can perform one or more design steps, including, without limitation, a system design step, a logic design step, a circuit synthesis step, afloor planning step, and/or a physical implementation step. In the system design step, the design facility 910 can receive (e.g., from a user) a description of the functionality to be implemented by the system, and can perform hardware-software architecture partitioning of the described functionality. Examples ofEDA software tools from Synopsys, Inc. that can be used to perform the system design step include Model Architect, Saber, System Studio, and products.

In the logic design step, the design facility 910 can obtain a high-level logical description of the system (e.g., a description of the system in a hardware design language (HDL) , including, but not limited to Verilog or VHDL) . In some examples, the design facility 910 generates the logical description of the system (or portions thereof) based on the functional description of the system. In some examples, the design facility 910 receives the logical description of the system (or portions thereof) from a user. Examples ofEDA software tools from Synopsys, Inc. that can be used to perform the logic design step include VCS, VERA, Magellan, Formality, ESP and LEDA products.

In the synthesis step, the design facility 910 can translate the high-level logical description of the system into a circuit schematic, which can be represented by a netlist or any other suitable description of a circuit’s components and connections therebetween. In some examples, this synthesis step can include selection of one or more library cells (e.g., standard cells or macro cells) to perform logic functions specified in the high-level logical description of the circuit. In some examples, the schematic can be customized for a particular IC technology (e.g., the IC technology that will be used to implement the system) . Examples of EDA software tools from Synopsys, Inc. that can be used to perform the synthesis step include Design Physical Compiler, DFT Compiler, Power Compiler, FPGA Compiler, TetraMAX, andproducts.

In the floor planning step, the design facility 910 can generate a floor plan for an IC that will implement the system or a portion thereof. Examples ofEDA tools from Synopsys, Inc. that can be used to perform the floor planning step include Astro and Custom Designer products.

In the physical implementation step, the design facility 910 can generate a representation of a physical implementation of the system (e.g., a physical layout of the components of the system on an IC) . Generating the representation of the system’s physical implementation can include “placing” the circuit’s components (e.g., determining positions on the IC for the circuit’s components) and routing the circuit’s connections (e.g., determining the positions on the IC of the electrical conductors coupling the circuit’s components) . In some examples, this physical implementation step can include selection of one or more library cells to implement circuit components included in the circuit schematic. Examples ofEDA tools from Synopsys, Inc. that can be used to perform the physical implementation step include the Astro, IC Compiler, and Custom Designer products.

Returning to FIG. 9A, in some examples the verification facility 920 can perform one or more verification steps, including, without limitation, a simulation step, a functional verification step, a schematic verification (e.g., netlist verification) step, a transistor-level verification step, afloor plan verification step, and/or a physical verification step. In the simulation step, the verification facility 920 can simulate the operation of a representation of the system (e.g., a high-level logical description, circuit schematic, floor plan, or layout of the system) .

In the functional verification step, the verification facility 920 checks the high-level logical description of the system for functional accuracy. For example, the verification facility 920 can simulate the operation of the high-level logical description of the circuit in response to particular inputs to determine whether the logical description of the circuit produces correct outputs in response to the inputs. Examples ofEDA tools from Synopsys, Inc. that can be used at the functional verification step include VCS, VERA, Magellan, Formality, ESP and LEDA products.

In the schematic verification step, the verification facility 920 checks the system schematic (e.g., the system netlist) for compliance with applicable timing constraints and for correspondence with the high-level logical description of the circuit. Examples ofEDA tools from Synopsys, Inc. that can be used at the verification step include Formality, PrimeTime, and VCS products.

In the transistor-level verification step, the verification facility 920 checks a transistor-level representation of the system for compliance with applicable timing constraints and for correspondence with the high-level logical description of the circuit. Examples ofEDA tools from Synopsys, Inc. that can be used at the transistor-level verification step include AstroRail, PrimeRail, PrimeTime, and Star-RCXT products.

In the floor plan verification step, the verification facility 920 checks the floor plan of the system for compliance with applicable constraints (e.g., timing, top-level routing, etc. ) .

In the physical verification step, the verification facility 920 checks the representation of the physical implementation of the system (e.g., a physical layout of the system components on an IC) for compliance with manufacturing constraints, electrical constraints, lithographic constraints, and/or schematic constraints. The Hercules product from Synopsys, Inc., is an example of an EDA tool that can be used at the physical verification step.

Returning to FIG. 9A, the manufacturing facility 930 can be operable to perform one or more steps to prepare for manufacturing the system, including, without limitation, a tape-out step and/or a resolution enhancement step. In the tape-out step, the manufacturing facility 930 generates tape-out data to be used (e.g., after lithographic enhancements are applied) for production of masks for lithographic fabrication of ICs that implement the system. Examples of EDA tools from Synopsys, Inc. that can be used at the tape-out step include the IC Compiler and Custom Designer families of tools.

In the resolution enhancement step, the manufacturing facility 930 can perform geometric manipulations of the system’s physical layout to improve manufacturability of the IC. Examples of EDA software products from Synopsys, Inc. that can be used at this resolution enhancement step include Proteus, ProteusAF, and PSMGen tools.

In some examples, an EDA tool can perform an EDA method including one or more (e.g., all) of the above-described design, verification, and/or manufacturing steps in any suitable order. In some examples, one or more of the design, verification, and/or manufacturing steps can be performed iteratively (e.g., until the tool determines that the system satisfies particular constraints and/or passes particular tests) .

In some examples, one or more EDA tools can be used to design, verify, and/or fabricate a multi-chiplet system 100, a chiplet 200, or portions thereof. For example, an EDA tool can be used to synthesize a circuit schematic of a chiplet (or portions thereof) (e.g., based on a logical description of the chiplet or portions thereof) . In some examples, the synthesized schematic can include an I/O interface system 620 of a chiplet. As another example, an EDA tool can generate a representation of a physical implementation of the system (e.g., a physical layout of the components of the system on an IC) , including the I/O interface system 620 of a chiplet. As another example, an EDA tool can generate lithographic masks suitable for fabricating the physical implementation of the chiplet 200 or multi-chiplet system 100. In some examples, these lithographic masks can be used with one or more process technologies to fabricate an IC that implements the chiplet 200 or multi-chiplet system 100. Any suitable process technology (e.g., semiconductor process technology) can be used to fabricate the IC.

FIG. 9B shows an example of a method 950 for manufacturing a chiplet with spare lane sharing. The manufacturing method 950 may be performed, for example, by an EDA tool. In step 952 of the manufacturing method 950, a representation of a physical implementation of a chiplet is generated from a description of the chiplet. The description of the chiplet can include a description of two or more I/O interface units. The representation of the chiplet can include a circuit schematic or an integrated circuit layout. Generating the representation of the chiplet can include adding, to the representation of the chiplet, two or more macro cells implementing the interface units. Each of two of the macro cells cell can include two or more lanes.

In step 954 of the manufacturing method 950, the chiplet is manufactured based on the generated representation of the chiplet. Manufacturing the chiplet can include fabricating the chiplet using an integrated circuit fabrication process. Fabricating the chiplet can include fabricating an interconnect coupling an output port of a first lane of a first one of the macro cells to an input port of a second lane of a second one of the macro cells. In some examples, the interconnect is routed through one or more layers of the chiplet. In some examples, the manufactured chiplet is disposed over an interposer, the interposer is disposed over a substrate, and the fabricated chiplet is coupled to a second chiplet disposed over the interposer via an interconnect routed through the interposer and/or the substrate.

Further Examples

Techniques operating according to the principles described herein may be implemented in any suitable manner. Included in the discussion above are flow charts showing the steps and acts of various processes that can be used to repair the I/O interface system of a chiplet or manufacture a chiplet capable of sharing spare lanes between interface units of the I/O interface system. The processing and decision blocks of the flow charts above represent steps and acts that may be included in algorithms that carry out these various processes. Algorithms derived from these processes may be implemented as software integrated with and directing the operation of one or more single-or multi-purpose processors, may be implemented as functionally-equivalent circuits such as a Digital Signal Processing (DSP) circuit, Field Programmable Gate Array (FPGA) , or an Application-Specific Integrated Circuit (ASIC) , or may be implemented in any other suitable manner. It should be appreciated that the flow charts included herein do not depict the syntax or operation of any particular circuit or of any particular programming language or type of programming language. Rather, the flow charts illustrate the functional information one of ordinary skill in the art may use to fabricate circuits or to implement computer software algorithms to perform the processing of a particular apparatus carrying out the types of techniques described herein. It should also be appreciated that, unless otherwise indicated herein, the particular sequence of steps and/or acts described in each flow chart is merely illustrative of the algorithms that may be implemented and can be varied in implementations and embodiments of the principles described herein.

Accordingly, in some embodiments, the techniques described herein may be embodied in computer-executable instructions implemented as software, including as application software, system software, firmware, middleware, embedded code, or any other suitable type of software. Such computer-executable instructions may be written using any of a number of suitable programming languages and/or programming or scripting tools, and also may be compiled as executable machine language code or intermediate code that is executed on a framework or virtual machine.

When techniques described herein are embodied as computer-executable instructions, these computer-executable instructions may be implemented in any suitable manner, including as a number of functional facilities, each providing one or more operations to complete execution of algorithms operating according to these techniques. A “functional facility, ” however instantiated, is a structural component of a computer system that, when integrated with and executed by one or more computers, causes the one or more computers to perform a specific operational role. Afunctional facility may be a portion of or an entire software element. For example, a functional facility may be implemented as a function of a process, or as a discrete process, or as any other suitable unit of processing. Iftechniques described herein are implemented as multiple functional facilities, each functional facility may be implemented in its own way; all need not be implemented the same way. Additionally, these functional facilities may be executed in parallel and/or serially, as appropriate, and may pass information between one another using a shared memory on the computer (s) on which they are executing, using a message passing protocol, or in any other suitable way.

Generally, functional facilities include routines, programs, objects, components, data structures, etc. that perform particular tasks or implement particular abstract data types. Typically, the functionality of the functional facilities may be combined or distributed as desired in the systems in which they operate. In some implementations, one or more functional facilities carrying out techniques herein may together form a complete software package. These functional facilities may, in alternative embodiments, be adapted to interact with other, unrelated functional facilities and/or processes, to implement a software program application.

Some exemplary functional facilities have been described herein for carrying out one or more tasks. It should be appreciated, though, that the functional facilities and division of tasks described is merely illustrative of the type of functional facilities that may implement the exemplary techniques described herein, and that embodiments are not limited to being implemented in any specific number, division, or type of functional facilities. In some implementations, all functionality may be implemented in a single functional facility. It should also be appreciated that, in some implementations, some of the functional facilities described herein may be implemented together with or separately from others (i.e., as a single unit or separate units) , or some of the se functional facilities may not be implemented.

Computer-executable instructions implementing the techniques described herein (when implemented as one or more functional facilities or in any other manner) may, in some embodiments, be encoded on one or more computer-readable media to provide functionality to the media. Computer-readable media include magnetic media such as a hard disk drive, optical media such as a Compact Disk (CD) or a Digital Versatile Disk (DVD) , a persistent or non-persistent solid-state memory (e.g., Flash memory, Magnetic RAM, etc. ) , or any other suitable storage media. Such a computer-readable medium may be implemented in any suitable manner, including as computer-readable storage media 1006 of FIG. 10 described below (i.e., as a portion of a computing device 1000) or as a stand-alone, separate storage medium. As used herein, “computer-readable media” (also called “computer-readable storage media” ) refers to tangible storage media. Tangible storage media are non-transitory and have at least one physical, structural component. In a “computer-readable medium, ” as used herein, at least one physical, structural component has at least one physical property that may be altered in some way during a process of creating the medium with embedded information, a process of recording information thereon, or any other process of encoding the medium with information. For example, amagnetization state of a portion of a physical structure of a computer-readable medium may be altered during a recording process.

In some, but not all, implementations in which the techniques may be embodied as computer-executable instructions, these instructions may be executed on one or more suitable computing device (s) operating in any suitable computer system, including the exemplary computer system of FIG. 6, or one or more computing devices (or one or more processors (e.g., controllers) of one or more computing devices) may be programmed to execute the computer-executable instructions. A computing device or processor may be programmed to execute instructions when the instructions are stored in a manner accessible to the computing device/processor, such as in a local memory (e.g., an on-chip cache or instruction register, acomputer-readable storage medium accessible via a bus, a computer-readable storage medium accessible via one or more networks and accessible by the device/processor, etc. ) . Functional facilities that comprise these computer-executable instructions may be integrated with and direct the operation of a single multi-purpose programmable digital computer apparatus, a coordinated system of two or more multi-purpose computer apparatuses sharing processing power andjointly carrying out the techniques described herein, a single computer apparatus or coordinated system of computer apparatuses (co-located or geographically distributed) dedicated to executing the techniques described herein, one or more Field-Programmable Gate Arrays (FPGAs) for carrying out the techniques described herein, or any other suitable system.

FIG. 10 illustrates one exemplary implementation of a computing device in the form of a computing device 1000 that may be used in a system implementing the techniques described herein, although others are possible. It should be appreciated that FIG. 10 is intended neither to be a depiction of necessary components for a computing device to operate in accordance with the principles described herein, nor a comprehensive depiction.

Computing device 1000 may comprise at least one processor 1002, a network adapter 1004, and computer-readable storage media 1006. Computing device 1000 may be, for example, a desktop or laptop personal computer, a personal digital assistant (PDA) , a smart mobile phone, a server, a wireless access point or other networking element, or any other suitable computing device [pick appropriate devices for this invention] . Network adapter 1004 may be any suitable hardware and/or software to enable the computing device 1000 to communicate wired and/or wirelessly with any other suitable computing device over any suitable computing network. The computing network may include wireless access points, switches, routers, gateways, and/or other networking equipment as well as any suitable wired and/or wireless communication medium or media for exchanging data between two or more computers, including the Internet. Computer-readable media 1006 may be adapted to store data to be processed and/or instructions to be executed by one or more processors 1002. Processor 1002 enables processing of data and execution of instructions. The data and instructions may be stored on the computer-readable storage media 1006.

The data and instructions stored on computer-readable storage media 1006 may comprise computer-executable instructions implementing techniques which operate according to the principles described herein. In the example of FIG. 10, computer-readable storage media 1006 stores computer-executable instructions implementing various facilities and storing various information as described above. In some examples, computer-readable storage media 1006 may store facilities 910-930 of an EDA tool 900. In some examples, computer-readable storage media 1006 may store a repair facility capable of performing the repair method 800.

While not illustrated in FIG. 10, a computing device may additionally have one or more components and peripherals, including input and output devices. These devices can be used, among other things, to present a user interface. Examples of output devices that can be used to provide a user interface include printers or display screens for visual presentation of output and speakers or other sound generating devices for audible presentation of output. Examples of input devices that can be used for a user interface include keyboards, and pointing devices, such as mice, touch pads, and digitizing tablets. As another example, a computing device may receive input information through speech recognition or in other audible format.

Embodiments have been described where the techniques are implemented in circuitry and/or computer-executable instructions. It should be appreciated that some embodiments may be in the form of a method, of which at least one example has been provided. The acts performed as part of the method may be ordered in any suitable way. Accordingly, embodiments may be constructed in which acts are performed in an order different than illustrated, which may include performing some acts simultaneously, even though shown as sequential acts in illustrative embodiments.

Various aspects of the embodiments described above may be used alone, in combination, or in a variety of arrangements not specifically discussed in the embodiments described in the foregoing and is therefore not limited in its application to the details and arrangement of components set forth in the foregoing description or illustrated in the drawings. For example, aspects described in one embodiment may be combined in any manner with aspects described in other embodiments.

Use of ordinal terms such as “first, ” “second, ” “third, ” etc., in the claims to modify a claim element does not by itselfconnote any priority, precedence, or order of one claim element over another or the temporal order in which acts of a method are performed, but are used merely as labels to distinguish one claim element having a certain name from another element having a same name (but for use of the ordinal term) to distinguish the claim elements.

Also, the phraseology and terminology used herein is for the purpose of description and should not be regarded as limiting. The use of “including, ” “comprising, ” “having, ” “containing, ” “involving, ” and variations thereof herein, is meant to encompass the items listed thereafter and equivalents thereof as well as additional items.

The word “exemplary” is used herein to mean serving as an example, instance, or illustration. Any embodiment, implementation, process, feature, etc. described herein as exemplary should therefore be understood to be an illustrative example and should not be understood to be a preferred or advantageous example unless otherwise indicated.

The phrase “and/or, ” as used in the specification and in the claims, should be understood to mean “either or both” of the elements so conjoined, i.e., elements that are conjunctively present in some cases and disjunctively present in other cases. Multiple elements listed with “and/or” should be construed in the same fashion, i.e., “one or more” of the elements so conjoined. Other elements can optionally be present other than the elements specifically identified by the “and/or” clause, whether related or unrelated to those elements specifically identified. Thus, as a non-limiting example, a reference to “A and/or B” , when used in conjunction with open-ended language such as “comprising” can refer, in one embodiment, to A only (optionally including elements other than B) ; in another embodiment, to B only (optionally including elements other than A) ; in yet another embodiment, to both A and B (optionally including other elements) ; etc.

Unless otherwise noted, the terms “connected to” and “coupled to” (and their derivatives) , as used in the specification and claims, are to be construed as permitting both direct and indirect (i.e., via other elements or components) connection.

Having thus described several aspects of at least one embodiment, it is to be appreciated that various alterations, modifications, and improvements will readily occur to those skilled in the art. Such alterations, modifications, and improvements are intended to be part of this disclosure, and are intended to be within the spirit and scope of the principles described herein. Accordingly,the foregoing description and drawings are by way of example only.

Claims

A chiplet comprising:

a first interface circuit including a plurality of first lanes, the plurality of first lanes including a particular first lane, the particular first lane operable to selectively route one or more inputs of the particular first lane to a first output terminal of the particular first lane; and

a second interface circuit including a plurality of second lanes, the plurality of second lanes including a particular second lane, the particular second lane operable to selectively route one or more inputs of the particular second lane to a second output terminal of the particular second lane,

wherein an output port of the particular first lane is coupled to an input port of the particular second lane via an interconnect between the first and second interface circuits.
The chiplet of claim 1, wherein each first lane in the plurality of first lanes includes a first routing circuit operable to selectively route one or more inputs of the respective first lane to the first output terminal of the respective first lane, and wherein first interface circuit includes a first controller configured to control operation of the first routing circuits.
The chiplet of claim 2, wherein each of the first routing circuits includes a respective multiplexer.
The chiplet of claim 2, wherein each second lane in the plurality of second lanes includes a second routing circuit operable to selectively route one or more inputs of the respective second lane to an output terminal of the respective second lane, and wherein the second interface circuit includes a second controller configured to control operation of the second routing circuits.
The chiplet of claim 4, wherein the particular second lane includes a particular second routing circuit of the second routing circuits, and wherein the particular second routing circuit is configured to selectively route the one or more inputs of the particular second lane to the second output terminal of the particular second lane.
The chiplet of claim 1, wherein the plurality of first lanes includes one or more first data lanes and one or more first spare lanes, and wherein the plurality of second lanes includes one or more second data lanes and one or more second spare lanes.
The chiplet of claim 6, wherein the particular first lane is a first data lane of the first interface circuit, and wherein the particular second lane is a second spare lane of the second interface circuit.
The chiplet of claim 2, wherein the chiplet is a first chiplet disposed over a substrate of a multi-chiplet system and coupled to a second chiplet disposed over the substrate.
The chiplet of claim 8, wherein each first lane in the plurality of first lanes of the first interface circuit of the first chiplet is coupled to a respective lane of a plurality of lanes of a interface circuit of the second chiplet, thereby forming a plurality of communication channels between the first and second chiplets.
The chiplet of claim 9, wherein the first controller of first interface circuit of the first chiplet is configured to communicate with a controller of the interface circuit of the second chiplet to identify one or more communication channels in the plurality of communication channels as faulty.
The chiplet of claim 1, wherein the first interface circuit is an instantiation of a macro cell, and the second interface circuit is an instantiation of the macro cell.
A controller-implemented method comprising:

detecting a plurality of defective communication channels between a first plurality of interface circuits of a first chiplet of a multi-chiplet system and a second plurality of interface circuits of a second chiplet of the multi-chiplet system, wherein the first plurality of interface circuits includes a first interface circuit and a second interface circuit; and

repairing the first plurality of interface circuits, including configuring a spare lane of the second interface circuit to route data between a data lane of the first interface circuit and a corresponding interface circuit in the second plurality of interface circuits.
The method of claim 12, wherein:

the plurality of defective communication channels includes a plurality of data lanes of the first plurality of interface circuits, wherein a number D_U of defective communication channels associated with the first interface circuit is greater than a number S_U of spare lanes in the first interface circuit, and wherein a total number D_T of defective communication channels associated with the first plurality of interface circuits is less than or equal to a total number S_T of spare lanes in the first plurality of interface circuits, and

repairing the first plurality of interface circuits includes configuring a plurality of spare lanes of the first plurality of interface circuits to route data between a plurality of data lanes of the first plurality of interface circuits and the second plurality of interface circuits.
The method of claim 13, wherein configuring a plurality of spare lanes of the first plurality of interface circuits to route data between a plurality of data lanes of the first plurality of interface circuits and the second plurality of interface circuits includes providing a plurality of control signals to a plurality of routing circuits of the plurality of spare lanes.
The method of claim 12, wherein configuring the spare lane of the second interface circuit to route data between the data lane of the first interface circuit and the corresponding interface circuit in the second plurality of interface circuits includes configuring the spare lane to route data between the data lane of the first interface circuit and an output terminal of the spare lane of the second interface circuit via an interconnect coupling a first port of the first interface circuit and a second port of the second interface circuit.
The method of claim 12, further comprising:

detecting a plurality of defective communication channels between a third plurality of interface circuits of the first chiplet of the multi-chiplet system and a fourth plurality of interface circuits of a third chiplet of the multi-chiplet system, wherein a total number of defective communication channels associated with the third plurality of interface circuits is greater than a total number of spare lanes in the third plurality of interface circuits; and

generating an alert indicating that the multi-chiplet system is unable to repair the plurality of defective communication channels between the first chiplet and the third chiplet.
The method of claim 12, wherein detecting the plurality of defective communication channels between the first plurality of interface circuits of the first chiplet and the second plurality of interface circuits of the second chiplet includes:

for each communication channel of a plurality of communication channels between the first plurality of interface circuits and the second plurality of interface circuits,

transmitting a sequence of bits from a transmission lane of the respective communication channel to a reception lane of the respective communication channel via an interconnect coupling an output terminal of the transmission lane to an input terminal of the reception lane; and

comparing a sequence of bits received by the reception lane to the sequence of bits transmitted by the transmission lane.
A chiplet manufacturing method, comprising:

generating a representation of a physical implementation of a chiplet from a description of the chiplet, wherein the description of the chiplet includes a description of a plurality of interface circuits, wherein generating, the representation of the chiplet includes adding, to the representation of the chiplet, a plurality of macro cells implementing the plurality of interface circuits, wherein the plurality of macro cells includes a first macro cell and a second macro cell, wherein the first macro cell includes a first plurality of lanes including a first lane, wherein the second macro cell includes a second plurality of lanes including a second lane, wherein the first lane includes an output port, and wherein the second lane includes an input port; and

manufacturing the chiplet based on the generated representation of the chiplet, wherein manufacturing the chiplet includes fabricating the chiplet using an integrated circuit fabrication process, wherein fabricating the chiplet includes fabricating an interconnect coupling the output port of the first lane of the first macro cell to the input port of the second lane of the second macro cell.
The method of claim 18, wherein the interconnect is routed through one or more layers of the chiplet.
The method of claim 19, wherein the chiplet is disposed over an interposer, the interposer is disposed over a substrate, and the chiplet is coupled to a second chiplet disposed over the interposer via an interconnect routed through the interposer and/or the substrate.
The method of claim 18, wherein the representation of the chiplet includes a circuit schematic or an integrated circuit layout.