WO2025221237A1 - Early-life failure detection in reserve memory - Google Patents

Early-life failure detection in reserve memory

Info

Publication number
WO2025221237A1
WO2025221237A1 PCT/US2024/024629 US2024024629W WO2025221237A1 WO 2025221237 A1 WO2025221237 A1 WO 2025221237A1 US 2024024629 W US2024024629 W US 2024024629W WO 2025221237 A1 WO2025221237 A1 WO 2025221237A1
Authority
WO
WIPO (PCT)
Prior art keywords
memory
reserve
test
array
die
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
PCT/US2024/024629
Other languages
French (fr)
Inventor
Mayank Parasrampuria
Akhil YADA
Bhaskar Narayana Talatam
Rakesh Kumar Kinger
Prachi Sinha
Shivam TULSYAN
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Google LLC
Original Assignee
Google LLC
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Google LLC filed Critical Google LLC
Priority to PCT/US2024/024629 priority Critical patent/WO2025221237A1/en
Priority to TW114113471A priority patent/TW202542919A/en
Publication of WO2025221237A1 publication Critical patent/WO2025221237A1/en
Pending legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/18—Address generation devices; Devices for accessing memories, e.g. details of addressing circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/18—Address generation devices; Devices for accessing memories, e.g. details of addressing circuits
    • G11C29/24—Accessing extra cells, e.g. dummy cells or redundant cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/44—Indication or identification of errors, e.g. for repair
    • G11C29/4401—Indication or identification of errors, e.g. for repair for self repair
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/46—Test trigger logic
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C2029/0403—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals during or with feedback to manufacture
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/18—Address generation devices; Devices for accessing memories, e.g. details of addressing circuits
    • G11C2029/1802—Address decoder
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/18—Address generation devices; Devices for accessing memories, e.g. details of addressing circuits
    • G11C2029/1806—Address conversion or mapping, i.e. logical to physical address
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/36—Data generation devices, e.g. data inverters
    • G11C2029/3602—Pattern generator
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/38—Response verification devices
    • G11C29/40—Response verification devices using compression techniques
    • G11C2029/4002—Comparison of products, i.e. test results of chips or with golden chip
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C2029/4402—Internal storage of test result, quality data, chip identification, repair information
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/50—Marginal testing, e.g. race, voltage or current testing
    • G11C2029/5002—Characteristic
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/50—Marginal testing, e.g. race, voltage or current testing
    • G11C2029/5004—Voltage
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/10—Test algorithms, e.g. memory scan [MScan] algorithms; Test patterns, e.g. checkerboard patterns 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G11C29/78—Masking faults in memories by using spares or by reconfiguring using programmable devices
    • G11C29/781—Masking faults in memories by using spares or by reconfiguring using programmable devices combined in a redundant decoder
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G11C29/78—Masking faults in memories by using spares or by reconfiguring using programmable devices
    • G11C29/785—Masking faults in memories by using spares or by reconfiguring using programmable devices with redundancy programming schemes
    • G11C29/789—Masking faults in memories by using spares or by reconfiguring using programmable devices with redundancy programming schemes using non-volatile cells or latches

Definitions

  • RAM random access memory
  • the die includes a memory’ array, a reserve-memory access circuit (RMA circuit), and a controller.
  • the memory array includes a plurality of main memory elements and at least one reserve memory' element.
  • Each main memory' element includes a group of memory’ cells.
  • the reserve memory element includes another group of memory' cells substantially similar in structure to at least one of the main memory' elements of the plurality, and suitable as a memory replace for the at least one of the main memory’ elements of the plurality.
  • the RMA circuit is communicatively coupled w'ith the plurality of main memory elements and the at least one reserve memory element.
  • the RMA circuit is configured to cause the die to temporarily swap a memory’ address of a selected main memory element with an address of the at least one reserve memory’ element.
  • An addressable portion of the memory’ array now temporarily comprises the reserve memory element and the remaining plurality of mam memory elements. That is, responsive to the swapping of the memory address, the addressable portion of the memory’ array temporarily comprises the reserve memory’ element and the remaining plurality of main memory elements.
  • the controller is configured to generate test patterns for the memory array. Additionally, the controller is configured to run a memory stress test on the addressable portion of the memory array. The memory stress test may be run using the generated test patterns.
  • the die includes a memory array with a plurality of main memory elements and at least one reserve memory' element.
  • Each main memory element includes a group of memory cells that are. by default, live memory cells at initial manufacture.
  • the reserve memory element includes another group of memory' cells substantially similar in structure to a main memory' element of the plurality', and suitable as a memory' replacement for the main memory element of the plurality.
  • the die also includes a built-in self-repair (BISR) module with a controller and a reserve-memory access (RMA) circuit.
  • the controller is configured to determine test patterns for the memory array and to detect memory element fault information for the memory array.
  • the reserve-memory access (RMA) circuit is configured to select between two alternative modes of test operations: a main- element test mode and a reserve-element test mode.
  • a main-element test mode the reserve memory element is in a state of not being addressable for testing by the controller.
  • the reserveelement test mode the reserve memory element is in a state of being addressable for testing by the controller.
  • the method includes activating main memory elements of a memory array and at least one reserve memory element of the memory’ array.
  • the at least one reserve memory element includes a group of memory cells that are similar in structure to at least one main memory' element of the main memory elements and suitable as a memory' replacement for the at least one main memory element.
  • the method also includes writing, to the main memory elements and the at least one reserve memory element, a golden test pattern to result in a stored test pattern in the memory array.
  • the method additionally includes determining a faulty memory element within the memory' array by comparing the stored test pattern with the golden test pattern.
  • aspects described below also include a system with means for performing early -life failure detection in reserve memory.
  • FIG. 1A illustrates an example production process for memory' in w'hich detection for early -life failure in reserve memory' may be employed
  • FIG. IB illustrates an example implementation of a product in which may be deployed a die that supports early-life failure detection in reserve memory
  • FIG. 1C illustrates an example die that supports early -life failure detection of reserve memory
  • FIG. ID illustrates stress tests that can be performed while applying aspects of early lifefailure detection in reserve memory
  • FIG. 2 illustrates an example die with a built-in self-repair (BISR) module capable of performing aspects of early-life failure detection in reserve memory';
  • BISR built-in self-repair
  • FIG. 3A illustrates an example die with an enhanced BIST module capable of performing aspects of early-life failure detection in reserve memory';
  • FIG. 3B illustrates an example implementation of a reserve-memory 7 access (RMA) circuit that performs aspects of early-life failure detection in reserve memory 7 ;
  • RMA reserve-memory 7 access
  • FIG. 4 illustrates an example logic table for a reserve-memory access (RMA) circuit that performs aspects of early -life failure detection in reserve memory;
  • RMA reserve-memory access
  • FIG. 5A illustrates an example method of testing and repairing a die
  • FIG. 5B illustrates an example full-span memory array in three successive stages during testing and repairing according to FIG. 5A;
  • FIG. 5C illustrates an example of a full-span memory array after application of the example testing and repairing according to FIG. 5 A;
  • FIG. 6 illustrates an example method for performing aspects of early -life failure detection in reserve memory
  • FIG. 7 illustrates another example method for performing aspects of early-life failure detection in reserve memory.
  • Memory can be extremely compact with electrically-sensitive components. During the manufacturing process, microchips are tested extensively in order to weed out (throw out) dies that are identified as failing. This ensures such flawed components are never used in consumer and business devices.
  • Discarding dies can be w asteful.
  • One way to address this problem is to enhance the die via reserve memory locations.
  • An in-factory test can be used to identify the faulty regions within a main memory of the die. If a small segment of the main memory is determined to have failed during manufacture, it can be replaced at the factory 7 with the reserve memory before the die is integrated within a product.
  • a problem arises with existing factory testing procedures. With current procedures, the reserve memory is sometimes not tested at all. To the extent that some reserve memory is partially tested, the reserve memory 7 may not be stress-tested to the same extent as the main memory. This means that potentially flawed/vulnerable reserve memory may be present on a die that is put into use in an electronic device in the field. If and when such reserve memory is later called into service in the field (during an automated, in-service self-repair), there is an elevated risk of overall memory 7 failure.
  • FIG. 1A is an illustration of an example manufacturing process 100 (also called “fabrication” or “production”) for dies 102 (or dice 102) in which detection of early-life failure in reserve memory may be employed.
  • a die 102 can be implemented with any suitable memory 7 including, but not limited to, random-access memory, dynamic random-access memory 7 (DRAM), synchronous DRAM, three-dimensional (3D) stacked DRAM, double-data-rate (DDR) memory , low-power double-data-rate (LPDDR) memory (e.g.. LPDDR DRAM or LPDDR SDRAM), or static random-access memory (SRAM).
  • the die 102 can also be referred to as a system-on-chip (SoC) or a chip.
  • SoC system-on-chip
  • the die 102 can be implemented within a memory 7 device or a memory module. Some memory 7 devices can include multiple dies 102.
  • FIG. 1A is a hybrid figure that interleaves method steps and tangible elements of the manufacturing process 100.
  • the process 100 begins with highly purified silicon wafers 104, typically round and flat, that are blank (that is, have no other structural form(s) or materials deposited on them).
  • the silicon wafers 104 form the substrate for integrated circuit manufacture.
  • other substrates materials such as gallium arsenide, may be employed.
  • the “first” step 106 is actually dozens or even hundreds of steps, depending on how they are characterized for descriptive purposes.
  • the steps may involve photolithography, etching various kinds of structures on the silicon wafers, and depositing numerous chemical elements (semiconductors, metals, and insulators) in highly specific, extremely dense, microscopic patterns.
  • the details of this processing step 106 are outside the scope of this document, and are not essential to understanding the present system and method.
  • the result of processing step 106 is the patterned wafer 108.
  • the patterned wafer 108 will now contain literally billions of microscopic electronic components such as transistor, resistors, and capacitors, suitably connected with conductive metals to implement the present technology, namely a die 102.
  • the patterned wafer 108 can contain hundreds of dies 102, all still structurally connected on the silicon wafer 104.
  • the “squares” illustrated for the patterned wafer 108 are each a die 102.
  • the cut-off squares on the edges of the wafer 108 are partial/incomplete dies 102, and are disposed of during the manufacturing process 100.
  • a dicing and packaging step 110 entails slicing the dies 102 into separate dies, and possibly mounting them on a suitable packaging material (not illustrated).
  • the packing material may be partly ceramic or plastic or other non-conducting materials, and also provide for electrical connections to the dies 102.
  • each memory-die-as-integrated- with- packaging is still referred to simply as a die 102.
  • the result of the dicing and packaging step 1 10 may be a collection 112 of dozens, hundreds, or even thousands of individual, untested dies 102.
  • the structure of a die 102 is discussed in some detail further below in this document.
  • the structure includes many millions of microscopic — and potentially fragile — electronic components (transistors, capacitors, etc ).
  • some microscopic components may be imperfectly formed. This may result in portions of the die 102 that either do not work right out of the factory; or which may be prone to short-term failure once they are put into use with electricity running through them in the field.
  • the testing process may entail mounting each single die 102 on a die test bed 116, which can drive patterns of electrical signals through the die 102.
  • the electrical patterns may be generated (wholly or partly) by an external testing device (ETD) 118, which is coupled to the die test bed 116 via a communicative coupling 120, as further shown in FIG. 2.
  • ETD external testing device
  • the ETD 118 can be a specialized computer.
  • the results of testing may be three-fold: Some dies 102 may be found to be working flawlessly. Other dies 102 may be found to have some defects, but can still be repaired internally at the factory. This is discussed further below in this document. Still other dies 102 may be found to be failed beyond repair, and are disposed of at the factory before ever reaching a consumer.
  • the aggregate result of the testing may be a collection 122 of multiple tested and functional die 102. Improved systems and methods of testing at the factory are the subject of much of this document.
  • the dies 102 can be used in further device manufacture. This may be done in part at the same factory where the dies 102 are produced, though likely on different production lines; or the dies 102 may be shipped to other factories for incorporation into products.
  • the dies 102 are first arranged and mounted into ranks to form a module 126.
  • a module 126 For example, eight or nine dies 102 are arranged in one row, or sixteen or eighteen dies 102 are arranged in two rows on a circuit board to form the module 126.
  • the module 126 can be a dual in-line memory module (DIMM).
  • DIMM dual in-line memory module
  • the module 126 can plug into the motherboard of a product 128 such as a computer or a cell phone. This is discussed further with FIG. IB.
  • FIG. IB illustrates an example implementation of a product 128 which may be deployed with the die 102 that is factory -produced using the techniques for early -life failure detection in reserve memory.
  • the product 128 is illustrated with various non-limiting example devices including a desktop computer 128-1, a tablet 128-2, a laptop 128-3, a television 128-4, a computing watch 128-5.
  • Other devices not illustrated in the figure may also be a product 128, such as a home sendee device, a smart speaker, a smart thermostat, a baby monitor, a Wi-FiTM router, a drone, a trackpad, a drawing pad, a netbook, an electronic reader, a home automation and control system, a wall display, a home appliance, automotive control systems, medical testing or medical treatment devices, security systems, defense systems, factory or industrial monitoring/control devices, drones, aviation systems, or any other electronic device.
  • a home sendee device such as a smart speaker, a smart thermostat, a baby monitor, a Wi-FiTM router, a drone, a trackpad, a drawing pad, a netbook, an electronic reader, a home automation and control system, a wall display, a home appliance, automotive control systems, medical testing or medical treatment devices, security systems, defense systems, factory or industrial monitoring/control devices, drones, aviation systems, or any other electronic device.
  • the product 128 can include a host device 130, one or more computer processors 132, and a computer-readable medium 134. Elements of the host device 130 (not illustrated in the figure) may include a motherboard for mounting electronic components.
  • the product 128 can optionally include a cabinet, casing, or other physical structure that may provide both for mounting electronic components and control interfaces, and also provide other functionalities as well.
  • One or more peripherals such as keyboard, mice, buttons, display screens, touch screen displays, ports, and other such elements, may provide for user interface(s) and/or communications with networks or other electronic devices.
  • the product 128 can be the result of the host device 130 combined with a chosen group of peripherals that best meets the product requirements.
  • the computer processor 132 (also known as a microprocessor or a central processing unit (CPU) can access data that is stored on the at least one computer-readable medium 134.
  • the computer-readable medium 134 provides storage of program software and program data.
  • Applications and/or an operating system embodied as computer- readable instructions on the computer-readable medium 134 can be executed by the computer processor 132 to provide numerous types of functionalities well known in the arts.
  • Fixed or variable program data may also be stored in and/or read from the computer-readable medium 134.
  • the computer-readable medium 134 may implemented using the module 126 with one or more dies 102.
  • the module 126 is implemented as dual in-line memory modules (DIMM) or other types of memory cards, which in turn are configured with DRAM.
  • the computer-readable medium 134 can also include other types of memory that are not illustrated.
  • Other ty pes of memory' can include, without limitation: static random access memory' (SRAM), a solid state drive (SSD), a hard disk drive (HDD), optical memories, holographic memories, and other types of memory known in the art or to be developed.
  • the die 102 may be configured to include main memory and reserve memory.
  • the main memory 7 is composed of main memory' elements 136.
  • the reserve memory is composed of one or more reserve memory' elements 138.
  • the reserve memory' element 138 is similar in structure to a main memory element 136. In this way, the reserve memory element 138 can be a suitable replacement for the main memory element 136.
  • Example structures of the reserve memory' element 138 and the main memory element 136 can include a row or a column, as further described with respect to FIG. 1C.
  • the reserve memory (also referred to in the art as “backup memory ’ “redundant memory,” or “spare memory”) is defined as memory that is not by default available (or addressable) for use as storage as the memory 7 , but — if and when a portion of the main memory 7 fails — the reserve memory' may be called into use as a replacement for the failed portion of the main memory'.
  • This memory replacement (or memory swap) can occur if the main memory begins to fail over time or prior to field use if memory problems are identified at the factory during testing in step 114 (see FIG. 1 A above).
  • the reserve memory e.g., the one or more reserve memory’ elements 138
  • the reserve memory' may in particular be factory -tested according to the systems and methods described further herein. Die Structure
  • FIG. 1C is an illustration of an example die 102 with multiple banks 140.
  • the die 102 may be capable of performing aspects of early-life failure detection of reserve memory.
  • a die 102 may have multiple banks 140, and each bank 140 may have multiple full-span memory- arrays 142.
  • each bank 140 is considered to have one full-span memory' array 142.
  • the full-span memory array 142 may also have sub-arrays (not shown).
  • bank includes not only the full-span memory array 142 of storage cells, but also the associated electronics local to the array, including: a memory address router 144 (MAR 144) (also known in the art as a “memory wrapper”), a row' address decoder 146 (RAD 146), sense amplifiers 148, a column multipl exor/demulti plexor (MUX/DEMUX) 150 (all these elements are discussed further below ), and a built-in self-repair (BISR) module 152.
  • MAR 144 also known in the art as a “memory wrapper”
  • RAD 146 row' address decoder
  • sense amplifiers 148 sense amplifiers 148
  • MUX/DEMUX column multipl exor/demulti plexor
  • MUX/DEMUX built-in self-repair
  • the basic building block of the die 102 is a cell 154 (e.g., a memory cell or a storage cell).
  • Each cell 154 consists of fundamental electrical components, such as a capacitor and a transistor (not illustrated), and stores a single bit of data.
  • a single bit is either a ‘1‘ or a ‘O’, represented as a presence of an electric charge such as one volt, or a zero voltage, respectively.
  • the transistor is used to charge or discharge the capacitor.
  • a charged capacitor is typically representative of a ‘ 1 ’, while a discharged capacitor is typically representative of a ‘0.’
  • cells 154 are organized into a rectangular array of main rows 156 and main columns 158, fonning a main memory array 160.
  • the main rows 156 and the main columns 158 are example representations of the main memory elements 136.
  • the computer processor 132 of the product 128 accesses a chunk of the main memory array 160, it activates the main row' 156 containing the cells 154 storing the desired data; reads the desired data; and transfers it to the computer processor 132.
  • FIG. 1C depicts an example of athirty-two row (156) by sixteen column (158) bit-oriented main memory array 160, which has an accompanying, additional four additional reserve rows 162 and four additional reserve columns 164.
  • the reserve row's 162 and the reserve columns 164 are example representations of reserve memory' elements 138.
  • the collection of reserve row s 162 and reserve columns 164 can referred to as reserve (or redundant) memory.
  • a reserve memory’ element 138 is a group of cells 154 that is substantially similar (e.g., substantially identical) in structure and/or storage capabilities to any one of the main memory’ elements 136 (any one of the main rows 156 or main columns 158), and suitable as a memory replacement for the any one of the main memory elements 136.
  • the reserve rows 162 are parallel to and immediately adjacent to the main rows 156; and the reserve columns 164 are similarly parallel to and immediately adjacent to the main columns 158.
  • the functional main memory' array 160 available for storage is thirty -two rows by sixteen columns; but the full-span memory' array 142 of cells (which includes the main memory' array 160 and the reserve rows/columns 162/164) is thirty -six rows by twenty columns.
  • a main row 156 and/or a main column 158 may be any of '‘live” (operating effectively) or “defective” (live-but-not-properly functioning, or taken out of service due to defects). Whether it is “live” or “defective”, structurally a main row 156 is still a row, and a main column 158 is similarly still a column.
  • the reference numbers do not distinguish “live” from “defective.” That is, there are “main rows 156”, “live main rows 156”, and “defective main rows 156”; and similarly there are “main columns 158”, “live main columns 158”, and “defective main columns 158.” The distinction is identified via the adjectives “live” and “defective”, but not via the reference numbers.
  • Reserve rows 162 and reserve columns 164 are structurally distinct from the main rows 156 and the main columns 158 respectively.
  • the reserve memory elements 138 are by default not active (that is, not addressable for writing or reading). During testing and/or normal operation, the reserve memory elements 138 can be dormant (e.g., not addressable) or live (addressable and put into use to temporarily or permanently replace a main memory element 136). Note that reserve rows 162 and reserve columns 164 may be referred to collectively as "reserve memory.”
  • full-span memory arrays 142 may have many higher numbers of rows and columns.
  • the reserve rows 164 and reserve columns 164 of a 8,192 x 65,536 array are structurally additional rows and columns in the full-span memory array 142. That is, the reserve rows 162 and reserve columns 164 are generally placed adjacent to the main rows 156 and the main columns 158.
  • the reserve rows 162 and/or the reserve columns 164 are placed between main rows 156 and/or main columns 158, respectively.
  • memory swapping see FIGs. 5B and 5C
  • the number of addressable rows/columns at any one time remains fixed at 65,536 x 8,192. This is because when a live main row 156 is defective and therefore deactivated, it is replaced by a reserve row 162; and similarly for columns.
  • FIG. 1C is for example only, and not limiting.
  • the reserve rows/columns 162/164 may be placed elsewhere on the bank 140, that is, not adjacent to the main rows/columns 156/158.
  • a dormant reserve row 162 is allocated to replace a live main row 156, which is defective, then the row address of the defective main row 156 is called a row repair address (RRA). Then a decoder (not illustrated) decodes the RRA into control signals for switching row multiplexers to skip the defective main row 156 once a row address enable (RAE) signal is asserted. The RRA is mapped, via the multiplexers, to the address of a designated reserve row 162.
  • the reconfiguration of a main column 158, which is defective, and a dormant reserve column 164 is performed in a similar way: give a column repair address (CRA); map the CRA to the address of a reserve column 164; and assert a column address enable signal (CAE) to repair the defective main column 158 using the reserve column 164 (which goes from dormant to live).
  • CRA column repair address
  • CAE column address enable signal
  • the row and column multiplexers are not illustrated in the figure, but are an internal element of the memory’ address router 144.
  • the memoiy bank 140 also includes a variety of essential electronic components, only some of which are illustrated in the figure. These include a row address decoder 146 and column multiplexer/demultiplexer (MUX/DEMUX) 150, which together sene to select individual cells 154 or groups of cells in the main memory array 160 or the full -span memory array 142.
  • the memory bank 140 can also include sense amplifiers 148 (or an array of sense amplifiers), which detects the ‘0’ value or ‘1 ’ value in a specific cell 154.
  • the memory’ bank 140 can include the physical address reconfiguration mechanism, or router, already referred to above as the memoiy address router 144.
  • the full-span memory array 142 also includes the one or more resene columns 164 and/or one or more reserve rows 162.
  • rows and columns with the lives cells 154 are designated to store bits (‘ 1 ’s or ‘0’s) in their cells.
  • all the live cells 154 together are referred to synonymously as the “main memory array’' 160 or the “live array” 160.
  • the cells of the reserve column(s) 164 and reserve row(s) 162 are designated, by default, to normally not store anything, and so are initially dormant (e.g., not addressable). If not called into use at some point, they remain dormant.
  • These reserve memory elements 138 are present precisely for the purpose their name suggests: they are reserved or backup memory in case one or more “live'’ cells 154 turn into “unlive” cells 154 - that is, in case of cell failure leading to a defective cell.
  • Reserve rows and columns 162 and 164 may be thought of colloquially as “spare” rows or columns; though unlike, for example, spare tires, a spare row or spare column is not physically moved around to replace a defective “tire.”
  • the memory address router 144 is one element among others of the specialized electronics, which can be used to configure the bank 140 for repair. When a faulty live cell 154 is detected, the memory’ address router 144 can be programmed to turn the entire main row 156 or entire main column 158 containing the cell 154 to an “inactive” state. The memory address router 144 further swaps the now inactive main row 156 or main column 158 for a previously dormant reserve row’ 162 or column 164.
  • the BISR module 152 works in conjunction with the memory’ address router 144 to effect testing and repair of the banks 140.
  • the BISR module 152 is discussed further below in conjunction with FIGs. 2, 3A, 3B, and other figures.
  • FIG. ID provides plots of two different types of memory stress tests, which may be applied to a bank 140 during the testing step 114 in FIG. 1 A.
  • Example stress tests depicted in FIG. ID include a static stress test 168 and a dynamic stress test 170. These two types of stress tests 168, 170 are examples only, and other tests are known in the art or may be envisioned. It will be noted that a stress test may be applied more than once during manufacture, and may be applied in varied environmental conditions. For example, either or both stress tests 168, 170 may be run at normal room temperatures, or when the die 102 is exposed to elevated temperatures, and/or when the die 102 is exposed to reduced (chilled temperatures). Such environmental variations simulate real-world conditions that the die may be exposed in the course of normal field operations. Varied environmental pressures or other environmental variations, such as vibrations, may also be applied during stress testing.
  • a die 102 is normally operated with a supply voltage set at a nominal voltage 172 (or at a nominal voltage level).
  • the supply voltage can be referred to in the art as VDD (or sometimes Vdd or VDD), and this voltage is provided to the memory cells 154.
  • Stress testing may in some implementations entail operating the die 102 at a higher voltage than the nominal voltage 172. This higher voltage is referred to as a test voltage 174 (or an elevated voltage). In example stress tests, the test voltage 174 can be significantly larger than the nominal voltage 172.
  • the static stress test 168 is graphically illustrated at the top of FIG. ID.
  • the static stress test 168 adjusts the supply voltage between the nominal voltage 172 and the test voltage 174.
  • a pattern 176 is written to the live memory' array 160.
  • the pattern 176 can be designed to test for particular types of failures, including those associated with a stuck-at fault (SAF), a transition fault (TF), leakage, or short circuits between cells 154.
  • Example patterns 176 can include a checkerboard pattern 178 (alternating 0’s and l’s) or an inverted checkerboard pattern 180 (alternating l’s and 0’s), which are further explained with respect to FIG. 5B.
  • the test voltage 174 may, for example, be 1.5 times larger than the nominal voltage 172.
  • the dynamic stress test 170 is graphically illustrated at the bottom of FIG. ID. Similar to the static stress test 168, the dynamic stress test 170 adjusts the supply voltage between the nominal voltage 172 and the test voltage 174. In contrast to the static stress test 168, the dynamic stress test 170 writes the pattern 176 to the live memory array 160 during the time period that the supply voltage is set at the test voltage 174.
  • the cells 154 of the die 102 are pushed well-bey ond their nonnal operating conditions (that is, well above their normal operating voltages). If attempts to write data to, or read data from, a cell 154 pass before stress testing these cells 154 but fail after stress testing, the main row 156 or main column 158 containing the cell 154 may be identified as defective. This determination may be made by the built-in selfrepair module 152, which is further described in FIG. 2.
  • FIG. 2 illustrates memory testing and repair elements 200, namely an example die 102 with an example BISR module 152, which may also be referred to as a “reconfiguration circuit,” according to methods of early-life failure detection during manufacture.
  • a die 102 with such a configuration, including both the reserve memory element(s) 138 and the BISR module 152, may be called a repairable die.
  • the BISR module 152 may appear as external to the die 102. However, this is simply an “exploded” view 7 of the BISR module 152, for purposes of illustration only. This is indicated by the dotted lines in the figure that indicate the BISR module 152 as a module which, in this particular example illustration, is situated on a lower-left comer of the die 102. The lower left location on the die is example only, and is not limiting. It will therefore also be understood that the connections between the BISR module 152 and a repair port 202 and between the BISR module 152 and the memory 7 address router 144 are actually internal connections of the die 102, and specifically of the memory bank 140.
  • the die 102 may' have multiple BISR modules 152, as indicated by the shadowing of the “small” BISR module 152 on the die 102 in the figure. There may, for example, be one BISR module 152 for each memory bank 140. In some implementations, each BISR module 152 may be incorporated directly into the silicon “real estate” space of its corresponding memory bank 140 (this configuration is not illustrated in the figure).
  • FIG. 2 also illustrates the ETD 118, which may be communicatively coupled 120 to the BISR module 152 of the die 102.
  • the coupling 120 may be via a wired or wireless connection.
  • the coupling 120 may further be via the die test bed 116. which is not shown in FIG. 2 but is illustrated in FIG. 1A.
  • the ETD 118 may be a dedicated, specialized controller, or may be a general purpose computer that runs softw are.
  • the software can configure the on-board processor to run tests on the die 102. Either way, the ETD 1 18 will include its own processor 204, memory 206, and all other hardware elements required to perform its tasks.
  • the purposes of the ETD 118 may be to provide control signals that initiate or direct the operations of the BISR module 152.
  • the ETD 118 may also provide specialized or custom bit patterns for memory testing, as well as possibly regulate other external environmental conditions for testing (for example, the room temperature).
  • the details of operations of the ETD 1 18 will not be covered in this document. But it will be understood that various control or operational signals, indicated below as being received by the BISR module 152, may be generated by the ETD 118.
  • the BISR module 152 may have several internal sub-modules, including a built-in selftest (BIST) controller 208, a built-in repair analysis (BIRA) engine 210, a long-term, programmable, updateable memory (LTPUM) 212, and a built-in self-repair (BISR) register 214.
  • the long-term, programmable, updateable memory (LTPUM) 212 may alternatively be referred to simply as a memory.
  • the BIST controller 208 may generate binary test patterns for the die 102 under test. If-and-when a fault is detected in an active main memory element 136 by the BIST controller 208, the fault information is sent to the BIRA engine 210 for further processing. Note that both of the BIST controller 208 and the ETD 118, alone or in combination, may be referred to as “test pattern generators” and/or “test pattern controllers.”
  • the tests administered by the BIST controller 208 may be entirely built-in and self-initiated; or may be directed, controlled, and/or initiated to varying degrees by the ETD 118.
  • the BIST controller 208 may include an address-and-data-generator-and- comparator (ADGC) 216, which: generates target addresses for testing; generates “golden” test patterns 218 (or a golden test data pattern) for sending to the bank 140; and compares returned data (test data out 220 (TDO 220)) against the original golden test pattern 218 to identify memory' faults.
  • ADGC address-and-data-generator-and- comparator
  • golden test patterns 218 may be stored long-term in registers or other small memory' regions of static random access memory' (SRAM) or read-only memory' (ROM), or otherwise hard-coded into circuity, to ensure the stability and reliability of the golden test data.
  • SRAM static random access memory
  • ROM read-only memory
  • the BIRA engine 210 collects the fault information 222 sent from the BIST controller 208, and allocates reserve memory elements 138 (that is, it allocates reserve rows/columns 162/164) to replace the live-but-faulty main rows/columns 156/158. This allocation is done according to both the fault information 222 (which is generated by the BIST controller 208), and according to some designated, pre-coded reserve analysis algorithm(s) employed by the BIRA engine 210.
  • the allocated redundancies map the failed main memory' addresses to reserve memory addresses, and are known as repair signatures 224.
  • the established repair signatures 224 are stored in the short- term, during a testing process, in a BIRA register 226.
  • the LTPUM 212 stores established repair signatures 224 for long-term, permanent use - including permanent storage during power-down on the entire product 128, which contains the die 102.
  • the LTPUM 212 may be updatable on multiple occasions (as the die 102 may be subject to successive memory failures/repairs over its lifetime).
  • the repair signatures 224 of the LTPUM 212 are used upon system boot-up to restore any previously made repairs to the die 102.
  • other components can be coupled between the LTPUM 212 and the BISR register 214.
  • a control circuit or a decoder can interpret (e.g., decode) the information stored within the LTPUM 212 and put it in a format that is usable by other components for the repair operation.
  • LTPUM 212 includes a fuse array. While a fuse array is a known and commonly used fonn of such memory 7 , other ty pes of LTPUM 212 may be employed as well. When a fuse is blown in the fuse array, or other permanent-storage binary element is set in an LTPUM 212, this may be referred to as a "fuse event/’
  • a “blowing” or setting of a fuse is a onetime only process; that is, a fuse event, once done cannot be undone. However, enough fuses can be included in the fuse array to allow for progressive programming (successive fuse-blowing) over time, for any anticipated number of repairs. The ultimate result of a fuse event is to permanently disconnect those main elements 136 that are flagged as having faulty bits, and replace them with appropriate redundant elements 138.
  • the BISR register 214 sen es as a kind of way-station or transportation interface for repair signatures 224, and possibly for other internal data and signals, to be transported between: the BIST controller 208. the BIRA engine 210, the LTPUM 212. and other interface elements of the die 102. These other elements may include the memory 7 address router 144 (which configures memory pathway re-mappings in the banks 140), and the repair port 202, which may receive address and enable signals 228 and test patterns 176 (e.g., the golden test pattern 218).
  • the BISR register 214 may actually have multiple internal registers to manage and route data flow.
  • the BISR register 214 is coupled to a reserve-memory access circuit, which is further described with respect to FIG. 3A.
  • the repair port 202 of the die 102 may receive a variety 7 of signals pertaining to testing and repairing the die 102. These may include the address and enable signals 228 alluded to above, and/or various test patterns 176, and other signals and control commands, which may facilitate a memory testing process. These are generally apart from the repair signatures 224, which are received by the memory address router 144.
  • the BISR module 152 performs memory testing and repair during the manufacturing process 100 to improve the process yield.
  • the BIST controller 208 tests the live memory array 160.
  • the BIST controller 208 generates golden test patterns 218 for banks 140 on the die 102 and compares test responses (e.g., the TDO 220) with the golden test patern 218 for identifying the fault sites.
  • Test responses e.g., the TDO 220
  • “Golden” test data is defined as test data that is stored via hardware memory elements with extremely high reliability, so the golden test patern is a known, reliable reference for memory testing.
  • the fault information of the die 102 is sent to the B1RA engine 210 and collected in the memory fault storing logic of the BIRA engine 210.
  • a reserve analyzer (a processor or processing unit of the BIRA engine 210, not illustrated) determines the memoiy repair solution autonomously. That is, the BIRA engine 210 allocates redundancies (replacements of defective main memory elements 136 with reserve memory elements 138) according to various algorithms known or to be invented.
  • the established repair signatures 224 are programmed (or "blown") into the LTPUM 212 for permanent storage.
  • the repair signatures 224 may also be transmitted to the memory address router 144 for immediate implementation.
  • the repair signatures 224 are loaded (via intermediary circuits) from the LTPUM 212 into the memory 7 address routers 144 (specifically, into repair registers of the address routers, not illustrated in the figures).
  • the memory 7 address routers 144 are thereby configured to ensure that proper swapping occurs in the banks 140; that is, a reserve memory element 138 is suitably employed to replace a main memory element 136 that was previously identified as defective.
  • the reserve memory in other dies that do not perform early -life failure detection in reserve memory may not be fully tested, or even tested at all. during the manufacturing process. This is because the testing process, as described above, only tests live cells 154. The cells of reserve memory elements 138 do not become live until if/ when they have been swapped into use. Therefore, they are only partially tested or not tested at all during factory 7 testing according to the above methods. As such, potentially vulnerable reserve memory elements 138 may become part of a product 128 in the field, where such vulnerable reserve memory elements 138 may introduce instability . To address this, the BISR module 152 includes additional circuitry that enables the reserve memory element 138 to be temporarily addressable for testing, as further described with respect to FIG. 3A.
  • FIG. 3A illustrates enhanced memory testing and repair 300 that is performed using a reserve-memory access (RMA) circuit 302 (RMA circuit 302) of the built-in self-repair module 152.
  • the reserve-memory access (RMA) circuit 302 enables techniques for thorough, testing of reserve memory elements 138.
  • the BISR module 152 as a whole, including the RMA circuit 302 is illustrated in an exploded view, and is actually an onboard module of either the individual banks 140 or at least the die 102.
  • some of the signals, components, and/or connections shown in FIG. 2 are not shown explicitly in FIG. 3 A due to space constraints, it is to be understood that the BISR module 152 of FIG.
  • FIG. 3 A is similar to the BISR module 152 of FIG. 2.
  • the BISR module 152 shown in FIG. 3A differs from the BISR module 152 shown in FIG. 2 in that the RMA circuit 302 is explicitly depicted in the BISR module 152 of FIG. 3 A.
  • the RMA circuit 302 is integrated into the BISR module 152.
  • the RMA circuit 302 may be a separate module on the die 102 that is suitably communicatively coupled with other elements of the BISR module 152 (those the same as or similar to the BISR module 152 as illustrated in FIG. 2 above).
  • the purpose and function of the RMA circuit 302 is to enable reserve memory' elements 138 to be temporarily swapped for live main memory elements 136, so that the reserve memory elements 138 can be subject to testing (e.g., during the manufacturing process 100 of FIG. 1A or during other built-in self-tests). During the temporary syvap, it can be determined if one or more selected, reserve memory elements 138 — now made temporarily live in response to the swapping — can function properly.
  • the RMA circuit 302 is shoyvn in block form in FIG. 3A. As suggested in the figure by the shadowing of the RMA circuit 302, more than one RMA circuit 302 may be employed. For example, in one implementation, each RMA circuit 302 may be associated with a specific reserve memory element 138 or a specific set of reserve memory elements 138. This is discussed further beloyv. [0075] As shown in FIG. 3A, in one implementation, any one RMA circuit 302 is communicatively coupled with the ETD 118 and/or the BIST controller 208; with the BISR register 214; and with the memory address router 144.
  • the RMA circuit 302 is coupled between the BISR register 214 and the memory address router 144 so that it can utilize the existing repair architecture of the die 102 and provide a temporary repair signature 304 to enable one or more reserve memory elements 138 to be temporarily addressable fortesting. More specifically, the temporary' repair signature 304 acts like a typical repair signature 224 and causes the die 102 to make one or more reserve memory' elements 138 live while suppressing (e.g., deactivating) a matching number of main memory elements 136.
  • other components in the die 102 that are downstream from the RMA circuit 302 and perform aspects of the repair operation may be unaw are of whether the information passed from the BISR module 152 represents an established repair signature 224 (e.g., provided by the LTPUM 212) or a temporary' repair signature 304.
  • the RMA circuit 302 is designed in a manner that supports testing of the main memory' elements, testing of the reserve memory' elements, and repair operations. In a situation in which the die 102 has yet to be repaired and the die 102 is undergoing testing, the RMA circuit 302 can selectively cause a reserve memory' element 138 to be addressable or not addressable for the test. To support testing of the reserve memory element 138, the RMA circuit 302 passes the temporary’ repair signature 304, which specifies an address of a predetermined main memory element 136 for swapping in the repair memory element 138. To support testing of the main memory' elements 136, the RMA circuit 302 passes a null signal or an ’’empty’" signal that indicates that no repair is to be made. During normal operation, the RMA circuit 302 supports the repair operations by passing the repair signature 224 to the memory address router 144.
  • the RMA circuit 302 allows the repair signature 224 to be passed and the temporarily-swapped reserve memory' elements 138 can be restored to reserve status (for possible future use in the field), or may be marked as “failed” if appropriate.
  • the RMA circuit 302 can be understood as being configured to select between two alternative modes of test operations of the BISR module 152: (A) a main-element test mode, w'herein no reserve memory' element 138 is targeted for testing by the BIST controller 208; and (B) a reserve-element test mode, where a current reserve memory element(s) 138 is targeted for testing by the BIST controller 208. This process is further described w'ith respect to FIG. 5A.
  • the die 102 and in particular the bank 140 marks the defective reserve memory' element 138 as “bad”, so it is not utilized in future repairs. Stated generally, the die 102 maintains a persistent stored indication of flawed reserve memory elements 138, so they are not used for repair in the field. In various implementations of the present system and method this may be done in any number of ways.
  • the BISR module 152 may have a flawed reserve-memory (FRM) register 306, possibly in the form of a write-once read-many (WORM) memory that may be used to store suitable on- chip identification/identifiers for the defective reserve memory elements 138.
  • FFM flawed reserve-memory
  • WORM write-once read-many
  • defective reserve memory elements 138 may be more directly identified or marked proximately to the defective row/column.
  • each reserve memory elements 138 may have an adjacent extra bit or register (not shown in the figures) that may be a write-once bit/register for permanent storage.
  • the write-once bit/register may be set for example to one (‘1’) by default to identify a valid reserve memory elements 138, but set to zero CO’) if needed to identify that the reserve memory elements 138 is flawed or damaged.
  • FIG. 3A Some signals depicted in FIG. 3A are further described with respect to FIG. 3B. These signals include the expose redundant elements (ERE) signal 308 (ERE signal 308) and the repair enable signal (RES) 310 (RES 310).
  • ERP expose redundant elements
  • RES repair enable signal
  • An example implementation of the RMA circuit 302 is further described with respect to FIG. 3B.
  • FIG. 3B illustrates internal elements of an example RMA circuit 302.
  • the purpose and function of the RMA circuit 302 is discussed immediately above. It will be noted that both the hardw are wiring and the internal signals needed to enable such function could be implemented with a variety of different circuits and with a variety of possible components. Therefore it is emphasized that the configuration shown in FIG. 3B (and discussed in detail immediately below) is only one example possibility 7 among others that may be envisioned and that fall within the scope of the appended claims.
  • the RMA circuit 302 contains: a stress-test (ST) register 312; a multiplexer 314; and an (optional) AND gate 316 (indicated with a dashed border). The functions of these elements, and their interoperations, are described immediately below 7 . It will be noted that the BISR module 152 also contains an optional NOT gate 318 (indicated w ith a dashed border). In an implementation, the NOT gate 318 may not be part of the RAIA circuit 302; in an alternative implementation, the NOT gate 318 may be part of the RMA circuit 302. The NOT gate 318 is discussed further below.
  • the ST register 312 may store the temporary' repair signature 304. Although the term “stress-test” register 312 is associated with the “stress test”, generally speaking the ST register 312 can be used to enable testing of reserve memory elements 138 for any type of test that is performed prior to integration within the product 128 or any type of built-in self-test performed in the field. [0084]
  • the temporary' repair signature 304 may in various implementations: (i) be hard-coded into the ST register 312 (in ROM or reprogrammable memory), (ii) be obtained from the ETD 118 (see previous FIGs. 2 and 3A), and/or (hi) be obtained from the BIST controller 208.
  • the ST register 312 can store additional information, such as stress-test code bits that provide any necessary, ancillary' signaling that is required to implement the swap.
  • a stress-test code bit may indicate, via communication with the either the memory' address router 144 or the repair port 202, that the swap is in fact only temporary’ (and so should not be burned into the LTPLJM 212).
  • each RMA circuit 302 is associated with or coupled with one reserve memory' element 138 (or possibly with a set or group of reserve memory elements 138). This association or coupling establishes that the associated reserve memory elements 138 is to be tested when its specific RMA circuit 302 provides the temporary' repair signature 304.
  • the temporary repair signature 304 may be used to store the address of the main memory element 136 that is to be temporarily swapped with the reserve memory element 138 associated with the RMA circuit 302.
  • a plurality of respective RMA circuits 302 may each be communicatively coupled with a respective different reserve memory' element 138 so that each RMA circuit 302 is configured to store a respective different temporary' repair signature 304 indicative of an address (or addresses) of a different respective selected main memory element(s) 136.
  • the ST register 312 may store an associated ‘n’ temporary repair signatures 304 associated with ‘n’ addresses of main memory elements 136 for respective swappings.
  • the RMA circuit 302 may be associated with all of the reserve memory elements 138, or with a large cluster for reserve memory element 138.
  • a RMA circuit 302 may be associated with all the reserve rows 162 or with all the reserve columns 164.
  • the temporary' repair signature 304 may be a digital code, possibly a compressed code, that operationally reflects the row/column structure of the banks 140 employed on the die 102.
  • the digital code may be reflective of the organization, locations, and or electrical access routes (addresses, etc.) of the reserve memory elements 138 in relation to the main memory elements 136 on the dies 102.
  • the temporary repair signature 304 may vary among RMA circuits 302 on the same die 102.
  • the temporary repair signature 304 may be ⁇ 1 'bl. 8'b0 ⁇ .
  • a SynopsisTM N7 die from Synopsis, Inc.TM
  • the temporary repair signature 304 may be ⁇ 1’bl , 11 ’b0 ⁇ .
  • the details of how a temporary repair signature 304 (compressed or not) may indicate locations, arrangements, or addresses of reserve memory 7 elements 138 are beyond the scope of this document. Numerous possible systems or methods of such encoding may be employed, consistent with the appended claims.
  • the addresses of the main memory elements 136 to be temporarily swapped may be determined in a number of ways.
  • the RMA circuit 302 may have an RMA microcontroller and firmware, or hard-coded RMA logic (neither illustrated in the figure), to select the memory elements for swapping. The selection may be made by the BIST controller 208 or the ETD 118.
  • stress-test code bits may not be required.
  • the equivalent signals which may be associated with stress-test code bits may instead be embedded in or integrated with the temporary repair signature 304.
  • Either or both of the repair port 202 or the memory address router 144 may have associated logic that may recognize suitable signals or codes indicative that only a temporary swap is being made.
  • the temporary 7 repair signature 304 in the ST register 312 may be employed to program the registers of the memory address router 144 to temporarily "swap ouf' selected main memory elements 136. and simultaneously to temporarily “swap into” live mode one or more reserve memory elements 138.
  • the swap being temporary, it may also be later reversed (immediately after testing, for example), which would: (i) restore the affected, default main memory element(s) 136 to their live mode of operation, and (ii) restore the affected reserve memory element(s) 138 to a dormant status.
  • the RMA circuit 302’s multiplexer (MUX) 314 is configured to receive as input both the temporary repair signature 304 via data path 320, and also to receive in parallel the repair signature 224 from the BISR register 214 via data path 322. At any given moment of use, the MUX 314 will be configured to transmit one of (i) the temporary repair signature 304, or (ii) the repair signature 224 (e.g., the established repair signature) via the data path 324 to the memory address router 144. Other implementations are also possible in which the data path 324 also passes the output of the MUX 314 to any of the repair port 202 of the die 102, the BIST controller 208, or the BIRA engine 210.
  • MUX multiplexer
  • the temporary repair signature 304 Upon transmitting of the temporary repair signature 304, one or more banks 140 of the die 102 are configured to test the reserve memory elements 138 of the die 102.
  • the temporary' repair signature 304 indicates which among the main memory elements 136 are to be swapped for the testing, while the test pattern 176 provided by the BIST controller 208 may convey a variety’ of parameters pertaining to the stress test duration, timing, voltages, and/or patterns.
  • one or more banks 140 of the die 102 are configured — typically in the field, during use of the product 128 — to repair the bank(s) 140, where the repair signature 224 indicates which among the reserve memory’ element(s) 138 is to be substituted for a dysfunctional main memory element(s) 136.
  • An input test control signal (TCS) 326 to the MUX 314 determines the choice between a MUX output of the temporary’ repair signature 304 or a MUX output of the repair signature 224. For example, an input signal value of ‘U to the MUX 314 may select for the temporary repair signature 304, while an input signal value of ‘0’ may select for the repair signature 224.
  • the TCS 326 to the MUX 314 may come from a single source, such as the BIST controller 208. In such an implementation, the AND gate 316 is not employed. [0095] In the implementation shown in FIG. 3B, the TCS 326 to the MUX 314 comes from the AND gate 316.
  • the AND gate 316 may receive two control signals.
  • a first control signal can be the expose reserve elements (ERE) signal 308, which is received via signal path 328. This signal may be from a factory-controlled die testing process in step 114 of FIG. 1A.
  • the ERE signal 308 is provided by an off-chip source, such as the ETD 118.
  • the ERE signal 308 is provided by an on-chip source, such as the BIST controller 208. In general, the ERE signal 308 indicates whether or not testing of the reserve memory elements 138 is requested.
  • the RES 310 from the BISR register 214 is first passed through the NOT gate 318 before reaching the signal path 330 to the AND gate 316.
  • the effect is that when an actual repair of the die 102 is intended (so the RES 310 is asserted high), the input to the AND gate 316 is low and MUX 314 outputs the repair signature 224.
  • the RES 310 is asserted low (‘0’).
  • the NOT gate 318 turns the low RES 310 to a high ('! ’) value for transmission over the signal path 330 to the AND gate 316.
  • the AND gate 316 output signal e.g., the TCS 326) is high.
  • the MUX 314 selects for the temporary repair signature 304, and a test (e.g., the statis stress test 168 or the dynamic stress test 170) can be performed on the reserve memory elements 138 and the remaining (non-swapped) main memory’ elements 136.
  • the BISR register 214 or other elements may have an entirely separate repair disable signal line, making the NOT gate 318 superfluous.
  • the configuration discussed above requires two asserted inputs 328 and 330 to select for the temporary’ repair signature 304 via the MUX 314.
  • only one input may be required to initiate testing, in which case the AND gate 316 may be superfluous.
  • a function of the RMA circuit 302 is to enable reserve memory elements 138 to be temporarily swapped for main memory elements 136 of the live memory array 160, so that the reserve memory elements 138 can be subject to testing, including stress testing during manufacturing.
  • the RMA circuit 302 may also provide for, or help provide for, switching betw een a permanent repair mode and a reserve-element testing mode.
  • the RMA circuit 302 may employ the ST register 312.
  • the ST register 312 may maintain and provide for the temporary repair signature 304, such as to enable the die 102 to test the reserve memory elements 138.
  • the RMA circuit 302 may also employ the MUX 314 to select between repair mode operations and a resen e-element testing mode.
  • the RMA circuit 302 may be configured to put the die 102 into a reserve-element test mode to identify possibly flawed or error-prone reserve memory elements 138.
  • the RMA circuit 302 can also be configured to put the die 102 into a main-element test mode to identify possibly flawed or error-prone main memory elements 136.
  • the identifying of the flawed or error-prone elements can be performed by the BIST controller 208 or the ETD 118, or via both in combination.
  • control circuitry of the die 102 may be used to program the LTPUM 212.
  • An impact of the RMA circuit 302 for testing and normal operations is further described with respect to FIG. 4.
  • FIG. 4 illustrates an example logic table. Table 2 (400), for the RMA circuit 302.
  • the RMA circuit 302 may receive two inputs, the ERE signal 308 and the RES 310 (or a version thereof, such as an inverted version of the RES 310).
  • the RMA circuit 302 may receive the RES 310 and then internally invert the signal (that is, apply a logical NOT operation). The latter implementation is actually illustrated in FIG. 3B.
  • the ERE signal 308 (which is again a short-hand for “expose redundant elements” signal) may be received either from the ETD 118, or may be received from the BIST controller 208 of the die 102 or another component of the die 102.
  • the ERE signal 308, as its name suggests, is specifically applied to signal to the RMA circuit 302 that reserve memory elements 138 are desired/intended to be tested.
  • the RES 310 (which is again short-hand for “repair enable” signal) may be routed to the RMA circuit 302 by way of (for example) the BISR register 214.
  • the RES 310 can be provided by the ETD 118 and/or the BIST controller 208.
  • the RES 310 may either comprise or be reflective of a portion of the repair signature 224.
  • the RES 310 may indicate that a reserve memory element 138 has already been swapped into use (e.g., a repair operation has already been established). If the repair operation has already been established, then the reserve memory element 138 may have already been tested.
  • the RES 310 enables the previously- established repair signature 224 to be passed to the die 102.
  • the repair signature 224 may not be populated or may be considered empty (e g., void of data or invalid). This can be the case prior to completion of the die testing and repair 114 step in FIG. 1A. This can also be the case if there are currently no main memory' elements 136 identified as defective. If the repair signature 224 is empty, the die 102 is considered to have no defective main memory' elements 136 or is considered to have no main memory' elements 136 that have been identified as being defective. As such, the die 102 does not swap any of the active main memory elements 136 with the reserve memory elements 138.
  • the assertion of the ERE signal 308 is a “do-not-care” (DNC) situation.
  • the NOT RES 310 causes the RMA circuit 302 to output the repair signature 224 regardless of whether the ERE signal 308 is asserted to ‘ 1 ' or ‘0.’
  • the RMA circuit 302 outputs the “empty” repair signature 224.
  • the main memory elements 136 remain addressable and the reserve memory element 138 associated with the RMA circuit 302 remains in a non-addressable state (e.g., remain dormant). For testing, this means that the main memory elements 136 can be tested. For normal operations, this means that the main memory' element 136 are utilized for read and/or write operations.
  • the BIST controller 208 and/or the ETD 118 set the ERE signal 308 to ‘0’ during testing to enable testing of the main memory elements 136.
  • the ERE signal 308 can be set to ’0’ by default.
  • the RMA circuit 302 outputs the temporary 7 repair signature 304.
  • the reserve memory' element 138 associated with the RMA circuit 302 is utilized as a replacement for the main memory element 136 specified in the temporary repair signature 304.
  • the reserve memory element 138 transitions from a non-addressable state (e.g., the dormant state) to an addressable state (e.g., a live state).
  • a non-addressable state e.g., the dormant state
  • an addressable state e.g., a live state.
  • the reserve memory' element 138 can be tested to perform aspects of early -life failure detection in reserve memory.
  • the particular circuit architecture for the RMA circuit 302 above (FIG. 3B) is example only. Any circuit design that can implement the logic of Table 1 (400), and which can be suitably integrated with a BISR module 152 or made interoperable with a BISR module 152, falls within the scope of the current disclosure and the appended claims. Although the above examples are described with respect to a single RMA circuit 302 that is associated with a single reserve memory element 138, the operations described above can be similar applied to multiple RMA circuits 302 and/or an RMA circuit that is associated with multiple reserve memory' elements 138.
  • FIG. 5A illustrates an example method 500 for performing early-life failure detection in reserve memory.
  • the method 500 can also be referred to as enhanced stress testing.
  • the method 500 ensures the reserve memory elements 138 are subject to substantial and robust testing 114 during the manufacturing process 100.
  • the example method 500 may be executed by instruction control via the BIST controller 208 and/or the ETD 118.
  • Either or both of the BIST controller 208 and/or the ETD 118 may include a computer-readable storage medium comprising computer-executable instructions that, alone or in combination, execute some aspect of the method.
  • the computer- readable storage medium may for example comprise hard-coded instruction sets (fixed logic circuitry), firmware, or read-only memory with program code to be executed by microcontrollers of the BIST controller 208 and/or the ETD 118.
  • a bank 140 can have a full-span memory array 142 including both the main memory array 160 and any unused reserve memory elements 138. However, at any one time, it is only possible to access the main memory' array 160, which is a subset of the full-span memory' array 142. The main memory array 160 does not include unused (e.g., still dormant) reserve memory elements 138. The method 500 effectively overcomes this limitation for testing purposes.
  • Method 500 is discussed concurrently with reference to FIG. 5B, which illustrates an example full-span memory' array 142 in three successive stages during testing 114. It will be noted that the full-span memory array 142 of FIG. 5B is illustrated with only one reserve row 162 and one reserve column 164. The number of reserv e rows 162 and reserve columns 164 is for example only, and more could be employed (as in FIG. 1C), consistent with the general principles and operations of example method 500. In the example described below, the RES 310 is assumed to be ‘0,’ meaning that a repair has yet to be established.
  • the die 102 operates in accordance with a reserve-element test mode.
  • the ERE signal 308 is asserted to ‘ 1 ’ by the BIST controller 208 and/or the ETD 118, as indicated at 504.
  • this causes the RMA circuit 302 output the temporary' repair signature 304.
  • the temporary repair signature 304 causes the die 102 to swap a designated reserve memory element 138 with a main memon' element 136 associated with the temporary repair signature 304.
  • a reserve memory' element 138 becomes enabled (e.g., addressable or live), and so becomes effectively a part of the main memory array 160.
  • the BISR module 152 As part of the reserve-element test mode, the BISR module 152 generates a first pattern 176 for writing to the main memory array 1 0. For example, the BIST controller 208 and/or the ETD 118 may generate or provide the first pattern 176. Because the reserve memory' element 138 has been temporarily included in the main memory array 160, the first pattern 176 is written to the memory elements that include the reserve memory element 138.
  • the first pattern 176 can be the checkerboard pattern 178 or the inverse checkerboard pattern 180.
  • the result of this step is intended to be a transition from the full-span memory array 142 shown at 514 to the main memory' array 160 shown at 516.
  • the reserve memory element represents the reserve column 164.
  • the main memory' element 136 associated with the temporary repair signature 304 is the left-most main column 158.
  • a pattern of data is written to the reserve column 164 and the remaining main memory elements 136 (e.g., the main memory' elements 136 that do not include the main column 158 associated with the temporary repair signature 304).
  • the swapped-out main column 158 of the default main memory array 160 which in the figure happens to be the left-most or first column — has no bits impressed on it by the write operation.
  • step 502 implements aspects of early -life failure detection in reserve memory.
  • the method can optionally proceed to step 508.
  • the step 508 can be used to perform aspects of stress testing, as described with respect to FIG. ID.
  • step 508 the die 102 operates in accordance with a main-element test mode.
  • the ERE signal 308 is asserted to ‘0’ by the BIST controller 208 and/or the ETD 118, as indicated at 510.
  • this causes the RMA circuit 302 to output the repair signature 224, which is ‘‘empty” at this stage.
  • the die 102 “un-sw'aps” the tw'o previously-swapped elements. More specifically, the reserve column 164 returns to a dormant, non-addressable state and the main column 158 returns to alive, addressable state.
  • the reserve memory element 138 is again a reserve memory element, and the main memory element 136 specified in the temporary repair signature 304 is restored to its status as a member of the main memory’ array 160.
  • the result is that the main memory 7 element 136, which was effectively hidden from writing during step 506, may now have data written to it.
  • the BISR module 152 As part of the main-element test mode, the BISR module 152 generates a second pattern 176 for writing to the main memory array 160.
  • the BIST controller 208 and/or the ETD 118 may generate or provide the second pattern 176.
  • the result of step 512 is intended to be a transition from the main memory array 160 at 516 to the inclusive test array (ITA) 518 at 520.
  • ITA inclusive test array
  • steps 502 and 508 The effective net result of steps 502 and 508 is that the first test pattern 176 and the second test pattern 176, written consecutively, form a logical test pattern for writing to the inclusive testing array (ITA) 518.
  • the ITA 518 covers or spans all elements of the default main memoij' array 160 and the reserve column 164.
  • This logical golden test pattern 218 is imprinted upon the series of electronic signalings, which drives the write operation.
  • test patern is ‘‘intended” to be writen, or that a “logical test pattern” is formed for writing. What is meant by this is the following:
  • the BIST controller 208 generates (or stores or accesses) one or more so-called “golden test patem(s)” 218, such as a checkboard patern 178 or an inverse checkerboard pattern 180 that is intended as a template for what should be writen to the full-span memory array 142. Further, suitable write operation(s) are performed to write that patern to the memory
  • the test pattern illustrated in FIG. 5B (and specifically at 520) is an idealized/logical golden test pattern as it would occur (to be written to and read from) an inclusive test array 518 that had no flawed cells at all. Stated another way. the final test pattern illustrated may be considered as the golden test pattern 218. Many newly produced, real-world dies 102 will have flawed cells, and the golden test pattern 218 would not be flawlessly imprinted at first. However, post-stress-testing and especially post-repair, it is presumed and intended that all the live memory elements 136 and/or 138 are now fully reliable, and so the die 102 will flawlessly store and retrieve the golden test patterns 218 (as well as any other data written to memory).
  • the steps 502 and 508 can be used to perform aspects of a stress test, the details of this test are discussed above in conjunction with FIG. ID.
  • the ADGC 216 of the BIST controller 208 compares the data with the golden test pattern 218 to identify’ flaws in the inclusive test array 518, which includes potential flaws or vulnerabilities in the reserve column 164.
  • steps 502 and 504 can be performed multiple times for different logical test patterns and/or for different ty pes of stress tests. For example, to perform a first static stress test 168 with the logical golden test pattern representing the checkerboard pattern 178, steps 502 and 508 can be performed with the first pattern 176 representing the checkerboard pattern 178 and the second pattern 176 representing the inverted checkerboard pattern 180. To perform a second static stress test 168 with the logical golden test pattern representing the inverse checkerboard pattern 180, steps 502 and 508 can be performed with the first pattern 176 representing the inverse checkerboard pattern 180 and the second pattern representing the checkerboard pattern 178.
  • Similar pattern assignments can be applied for performing a first dynamic stress test 170 with the logical golden test pattern representing the checkerboard pattern 178 and for performing a second dynamic stress test 170 with the logical golden test pattern representing the inverse checkerboard pattern 180. It will be noted that in the implementation just described, using both the checkerboard pattern and the inverted checkerboard pattern ensures that every bit of the full-span memory' array 142 is tested with both a ‘0’ value and a ‘1 ’ value.
  • the first pattern 176 can be the same or different than the second pattern 176, depending on an architecture of the reserve memory.
  • the first pattern 176 and/or the second pattern 176 can be the checkerboard pattern 178, the inverse checkerboard pattern 180, or some combination thereof.
  • the quantity of reserve memory elements 138 represents an odd integer number (e.g., 1, 3, or 5) that are co-located within the full-span memory array 142 (e.g., are located on the left side, the right side, or in a middle of the full-span memory array 142).
  • the first and second patterns 176 are different patterns to effectively write the checkerboard pattern 178 or the inverse checkerboard pattern 180 to the inclusive test array 518, as described above.
  • the first and second patterns 176 can be the same pattern to effectively write the checkerboard pattern 178 or the inverse checkerboard pattern 180 to the inclusive test array 518.
  • the first and second patterns 176 can be the checkerboard pattern 178.
  • the first and second patterns 176 can be the inverse checkerboard pattern 180.
  • a reserve row 162 may be swapped into a temporary live role at a given time (rather than the reserve live column 164).
  • Other bit patterns may be employed to impose other kinds of electrical stresses on the inclusive testing array 518. For example, columns may be filled with all ‘ l ’s, or all ‘0’s; or with alternating columns of all ‘ l ’s and all ‘0's (and similarly for rows).
  • a dynamic stress test 170 may be employed in place of, or in addition to, the static stress test 168.
  • an aspect of the method is to swap one or more reserve memory elements 138 into the inclusive test array 518 in a non-permanent manner, so that these reserve memoiy elements 138 can be substantially tested along with the main memory' elements 136. Any reserve memory' elements 138 that are found to be flawed may then be permanently marked as flawed (and therefore not used for repair) according to systems and methods discussed above.
  • the tested reserve memory elements 138 can be used to repair faulty main memory elements 136, as further described with respect to FIG. 5C.
  • FIG. 5C illustrates an example memory array 522 following a repair operation.
  • some former reserve row(s) 162 have been applied for repair and so are now permanently active row(s) 524; these permanently active rows 524 are now also fully stress tested.
  • some former reserve columns 164 have been applied for repair and so are now permanently active column(s) 526, and these permanently active column(s) 526 are now fully stress tested.
  • reserve memory elements 138 may also be one or more reserve memory elements 138 that remain in reserve for possible future use, but again have been fully stress tested. This means they may be put into use in the field, if necessary to replace failing main memory 7 elements 136, with a high degree of reliability and confidence.
  • former reserve memory elements 138 that are now permanently deactivated reserve memory elements 528. They may be marked as deactivated according to systems and methods described above in this document, and they will not be called into use as repair elements in the field. This again helps ensure the overall reliability of the die 102 and its individual banks 140 (or full-span memory arrays 142).
  • the methods disclosed herein may be performed via processors under the control of program code that is executed internally by one or more microcontrollers onboard the die 102. These processors are or may be integral parts of the BIST controller 208 and/or the BIRA engine 210. While not shown in the figures, in some implementations the RMA circuit 302 may have an internal microcontroller, which may for example be programmed to generate various sequences of the temporary' repair signatures 304. In addition, some code executed by the present methods may be processed by the ETD 118 (see FIG. 2), which has its own processor 204 and memory' 206.
  • ETD 118 may itself be a remote server connected to the die 102 via a network or cloud connection.
  • This distributed computing system may include, via the ETD 118, one or more data inputs and data interfaces that may be used to modify or view parameters of the current system and method (such as die test patterns), for example via a keyboard, mouse, screen display, virtual reality goggles, voice control, or similar.
  • data inputs and data interfaces that may be used to modify or view parameters of the current system and method (such as die test patterns), for example via a keyboard, mouse, screen display, virtual reality goggles, voice control, or similar.
  • the distributed computing system can be implemented with any one or combination of hardware, firmware, or fixed logic circuitry.
  • the distributed computing system may also include one or more computer-readable medium, such as one or more memory devices that enable persistent and/or non-transitory data storage (in contrast to mere signal transmission), examples of which include: random access memory (RAM) which is apart and separate from the die 102 being subject to test; non-volatile memory (e.g., any one or more of a read-only memory (ROM), flash memory, EPROM, EEPROM, etc.), and a disk storage device.
  • RAM random access memory
  • non-volatile memory e.g., any one or more of a read-only memory (ROM), flash memory, EPROM, EEPROM, etc.
  • the disk storage device may be implemented as any type of magnetic or optical storage device, such as a hard disk drive, a recordable and/or rewriteable compact disc (CD), any type of a digital versatile disc (DVD), and the like.
  • the distributed computing system can also include a mass storage medium device (storage medium).
  • controllers or processors of the distributed computing system run any operating systems, applications, microapplications, software drivers, hardware drivers, system components, engines, or managers required to implement early-life failure detection in reserve memory.
  • FIGs. 6 and 7 depict example methods 600 and 700 for implementing aspects of early -life failure detection in reserve memory.
  • Methods 600 and 700 are shown as sets of operations (or acts) performed but not necessarily limited to the order or combinations in which the operations are shown herein. Further, any of one or more of the operations may be repeated, combined, reorganized, or linked to provide a wide array of additional and/or alternate methods.
  • At 602 in FIG. 6. at least one main memory element within a memory array is temporarily replaced within at least one reserve memory element of the memory array.
  • the RMA circuit 302 outputs the temporary repair signature 304 along data path 324, as show n in FIG. 3B.
  • the temporary repair signature 304 causes the die 102 to replace at least one main memory element 136 with at least one reserve memory element 138 of the full-span memory’ array 142, as shown in FIG. 5C.
  • This repair operation is temporary in that later on, the RMA circuit 302 can stop providing the temporary repair signature 304 (e.g., switch to providing the repair signature 224). Assuming the repair signature 224 is "empty.” this causes the die 102 to return the reserve memory element 138 to a dormant state.
  • the main memory' element 136 is a main row 156, and the reserve memory element 138 is a reserve row 162.
  • the main memory element 136 is a main column 158, and the reserve memory element 138 is a reserve column 164, as shown in FIG. 1C.
  • the main memory element 136 can include multiple main rows 156 (or multiple main columns 158), and the reserve memory' element 138 can include multiple reserve rows 162 (or multiple reserve columns 164).
  • the memory array with the at least one reserve memory element is stress tested to identify whether the at least one reserve memory element is faulty.
  • the BIST controller 208 and/or the ETD 118 stress tests the live memory' array 160, which includes the reserv e memory' element 138 to identify whether the reserve memory element 138 is faulty'.
  • the stress test can be a static stress test 168 and/or a dynamic stress test 170, as shown in FIG. ID.
  • Various techniques can be employed to determine if the at least one reserve memory' element 138 is faulty. In one example, the data within the at least one reserve memory' element 138 is read and compared to a corresponding portion in the golden test pattern 218, as described above.
  • any discrepancy between the read data and the corresponding portion in the golden test pattern 218 can indicate the presence of one or more faulty cells 154 within the reserve memory element 138.
  • a subsequent write and/or read operation is performed after the stress testing.
  • any detected fault associated with the write and/or read operation can indicate the presence of one or more faulty' cells 154 within the reserve memory' element 138.
  • subsequent read and/or write operations can be performed using the ERE signal 308 and the RMA circuit 302 to temporarily activate the reserve memory' element 138.
  • main memory' elements of a memory' array and at least one reserve memory element of the memory array are activated.
  • the at least one reserve memory element comprises a group of memory cells that are similar in structure to at least one main memory’ element of the main memory elements and suitable as a memory replacement for the at least one main memory element.
  • the die 102 activates the main memory elements 136 and the at least one reserve memory element 138. This activating step can be performed in multiple steps.
  • the die 102 can be operated in according to a reserve-element test mode to temporarily activate the one or more reserve memory elements 138, as described with respect to step 502 in FIG. 5 A.
  • the die 102 can be operated in according to a main-element test mode to activate the main memory' elements 136, as described with respect to step 508 in FIG. 5B.
  • a golden test pattern is written to the main memory 7 elements and the at least one reserve memory element to result in a stored test pattern in the memory array.
  • the BIST controller 208 or the ETD 118 causes the golden test pattern 218 to be written to the full-span memory array 142 to result in a stored test pattern.
  • the golden test pattern 218 can be the checkboard pattern 178 or the inverted checkboard pattern 180 of FIG. ID.
  • the writing of the golden test pattern 218 can be performed in multiple steps, such as those described with respect to steps 504 and 510 in FIG. 5B.
  • a memory' element within the memory' array is determined to be faulty by comparing the stored test pattern with the golden test pattern.
  • the TDO 220 is generated from the full-span memory' array 142 and passed to the BIST controller 208 or the ETD 118.
  • the BIST controller 208 or the ETD 118 compares the stored test pattern with the golden test pattern 218 to identify a faulty memory element (e.g., a faulty main memory' element 136 and/or a faulty’ reserve memory element 138 within the full-span memory’ array 142).
  • the fault information 222 can be passed to the BIRA engine 210, and an appropriate repair can be made if the fault corresponds with a main memory element 136. If the reserve memory' element 138 is determined to be faulty 7 , the die 102 can be discarded or programmed in such a way that the faulty 7 reserve memory element 138 will not be available for use.
  • Example 1 An apparatus comprising a die, the die comprising: a memory 7 array 7 comprising: a plurality' of main memory elements each comprising a group of memory 7 cells; and at least one reserve memory 7 element comprising another group of memory 7 cells substantially similar in structure to at least one of the main memory elements of the plurality, and suitable as a memory replacement for the at least one of the main memory 7 elements of the plurality 7 ; a reserve-memory access circuit (RMA circuit) communicatively coupled with the plurality of main memory elements and the at least one reserve memory element, the RMA circuit configured to: cause the die to temporarily swap a memory address of a selected main memory element with an address of the at least one reserve memory element, wherein, responsive to the swapping of the memory address, an addressable portion of the memory array temporarily comprises the reserve memory element and the remaining plurality of main memory' elements; and a controller configured to: generate test patterns for the memory array: and run a memory' stress test on the addressable portion of the memory' array.
  • RMA circuit reserve-
  • Example 2 The apparatus of example 1, wherein: the RMA circuit is communicatively coupled to one specific reserve memory element, and the RMA circuit is configured to store a temporary' repair signature indicative of an address of the selected main memory' element.
  • Example 3 The apparatus of example 1 or 2, further comprising: a plurality of respective RMA circuits each communicatively coupled with a respective different reserve memory' element, wherein each RMA circuit is configured to store a respective different temporary repair signature indicative of an address of a different respective selected main memory element.
  • Example 4 The apparatus of any previous example, wherein: the RMA circuit is communicatively coupled wi th a plurality of reserve memory' elements; and the RMA circuit is configured to store temporary repair signatures indicative of a plurality of addresses of the main memory elements.
  • Example 5 The apparatus of example 4, wherein: the RMA circuit is configured to swap each of the plurality of reserve memory’ elements with one of the main memory elements.
  • Example 6 The apparatus of any previous example, wherein: the RMA circuit is configured to: store a temporary' repair signature that identifies the main memory' element to be temporarily swapped with the reserve memory element; and receive a test control signal (TCS), and upon assertion of the TCS output the temporary repair signature to cause the die to temporarily swap the memory address of the selected main memory element with the address of the reserve memory element; and the controller of the die is configured to test the reserve memory' element.
  • TCS test control signal
  • Example 7 The apparatus of example 6, wherein the RMA circuit further comprises a multiplexer configured to: receive the stored temporary' repair signature and receive a repair signature from a register; receive the TCS; and select between transmitting the stored temporary’ repair signature and transmitting the repair signature based on the received TCS.
  • a multiplexer configured to: receive the stored temporary' repair signature and receive a repair signature from a register; receive the TCS; and select between transmitting the stored temporary’ repair signature and transmitting the repair signature based on the received TCS.
  • Example 8 The apparatus of example 7, wherein: the RMA circuit further comprises an AND gate configured to: receive an expose reserve elements (ERE) signal, indicative when asserted that a test pattern controller is initiating a memory test utilizing the reserve memory element, the test pattern controller being either internal to or external to the die; receive an inverted repair enable signal (RES) from the register, that when asserted is indicative that a repair has not been performed utilizing the reserve memory element; and generate the test control signal based on an AND operation of the ERE signal and the inverted RES; and the assertion of the ERE and the assertion of the inverted RES result in the multiplexer selecting for the temporary repair signature for testing of the reserve memory element.
  • ERP expose reserve elements
  • RES repair enable signal
  • Example 9 The apparatus of any previous example, wherein each main memory element of the plurality comprises either a row of memory cells or a column of memory cells.
  • Example 10 The apparatus of any previous example, wherein the temporary swap of the reserve memory element and the selected main memory element comprises sending to a memory address router of the die an instruction to assign the memory' address of the selected main memory' element to the reserve memory element while avoiding triggering a fuse event in a long-term, programmable, updateable memory of the die that would otherwise make the memory swap permanent.
  • Example 11 The apparatus of any previous example, wherein: the controller is configured to: provide a golden test pattern suitable for testing of the memory array; write a first test pattern to the memory 7 array 7 when the reserve memory element is in a state of being not addressable; and write a second test pattern to the memory’ array when the reserve memory element is in a state of being addressable: and a resulting logical test pattern for writing to the memory array is the golden test pattern that is written to memory' addresses that include both the reserve memory 7 element and the plurality 7 of main memory elements.
  • Example 12 The apparatus of example 11, wherein the golden test pattern is one of a checkerboard pattern and an inverse checkerboard pattern.
  • Example 13 The apparatus of any preceding example wherein each group of memory cells of the plurality of main memory elements are, by default, live memory cells at initial manufacture, the at least one die further comprising a built-in self-repair (BISR) module comprising: the controller configured to determine test patterns for the memory 7 array and to detect memory element fault information for the memory array; and the reserve-memory access (RMA) circuit configured to select between two alternative modes of test operations: a main-element test mode, wherein the reserve memory' element is in a state of not being addressable for testing by the controller; and a reserve-element test mode, wherein the reserve memory element is in a state of being addressable for testing by the controller.
  • BISR built-in self-repair
  • RMA reserve-memory access
  • Example 14 An apparatus comprising at least one die, the at least one die comprising: a memory' array comprising: a plurality of main memory' elements each comprising a group of memory' cells that are, by default, live memory cells at initial manufacture; and at least one reserve memory element comprising another group of memory cells substantially similar in structure to a main memory element of the plurality, and suitable as a memoiy replacement for the main memory element of the plurality 7 ; and a built-in self-repair (BISR) module comprising: a controller configured to determine test patterns for the memory array and to detect memory element fault information for the memory array; and a reserve-memory access (RMA) circuit configured to select between two alternative modes of test operations: a main-element test mode, wherein the reserve memory element is in a state of not being addressable for testing by the controller; and a reserve-element test mode, wherein the reserve memoiy 7 element is in a state of being addressable for testing by the controller.
  • BISR built-in self-rep
  • Example 15 The apparatus of example 13 or 14, wherein the BISR module further comprises: a built-in repair analysis (BIRA) engine configured to collect the memory 7 element fault information and to generate one or more repair signatures based on the fault information; and a long-term, programmable, updateable memoiy 7 (LTPUM) configured to maintain longterm, permanent storage of the generated repair signatures, and configured to communicate the repair signatures to a memory address router of the die.
  • BIRA built-in repair analysis
  • LTPUM long-term, programmable, updateable memoiy 7
  • Example 16 The apparatus of any one of examples 13 to 15, wherein the BISR module is configured to maintain a stored indication of a faulty reserve memory element, wherein the faulty 7 reserve memory element is not employed for repairs.
  • Example 17 The apparatus of any one of examples 13 to 16, wherein: the RMA circuit comprises a stress-test register and a multiplexer (MUX); the stress-test register is configured to store a temporary' repair signature indicative of the main memory element of the plurality for swapping in the reserve memory element; and the MUX is configured to selectively transmit, to a memory address router of the die, the temporary repair signature or a repair signature for the die.
  • MUX multiplexer
  • Example 18 The apparatus of example 17, wherein the RMA circuit further comprises an AND gate configured to: receive two control signals; and output, based on the two control signals, a test control signal to control whether the MUX transmits the temporary' repair signature or the repair signature.
  • Example 19 The apparatus of example 18, wherein: the two control signals comprise a first control signal from a test device that is external to the die and a second control signal that is generated internally by the die; the first control signal determines a factory' controlled die testing process; and the second control signal is indicative that the reserve memory element either has already’ been swapped for a main memory element or that the reserve memory element has not been swapped for the main memory' element.
  • Example 20 The apparatus of any one of examples 13 to 19, wherein: the controller is configured to: provide a predetermined golden test pattern suitable for testing the memory' array including both the plurality' of main memory' elements and the reserve memory element; write a first test pattern to the main memory' array based on the RMA circuit selecting the main-element test mode; and write a second test pattern to the main memory array based on the RMA circuit selecting the reserve-element test mode; and a resulting test pattern written to the memory' array is the predetermined golden test pattern, which is written to memory addresses that include both the reserve memory element and the plurality of main memory elements.
  • Example 21 A method comprising: activating a full-span memory array of a die, the full-span memory array comprising all main memory elements of a memory' array of the die and all of at least one reserve memory' element of the memory array of the die, the at least one reserve memory element comprising a group of memory cells that are similar in structure to at least one main memory element of the main memory elements and suitable as a memory replacement for the at least one main memory' element; writing to the full-span memory' array a golden test pattern to result in a stored test pattern in the full-span memory array; and determining a faulty memory element within the full -span memory’ array by comparing the stored test pattern with the golden test pattern.
  • Example 22 A method comprising: activating main memory elements of a memory array and at least one reserve memory' element of the memory array, the at least one reserve memory element comprising a group of memory' cells that are similar in structure to at least one main memory' element of the main memory' elements and suitable as a memory' replacement for the at least one main memory' element; writing, to the main memory elements and the at least one reserve memory element, a golden test pattern to result in a stored test pattern in the memory array; and determining a faulty memory element within the memory' array by comparing the stored test pattern with the golden test pattern.
  • Example 23 The method of example 21 or 22, wherein: the activating and the writing comprises: enabling a reserve memory' element of the at least one reserve memory' element to form a first live memory array with the reserve memory' element enabled and a specified main memory' element of the at least one main memory element disabled; writing a first test pattern to the first live memory array; disabling the reserve memory element and enabling the specified main memory' element to form a second live memory array; and writing a second test pattern to the second live memory array; the first test pattern is written prior to the second test pattern; the writing of the first test pattern and the writing of the second test pattern logically combine to form the golden test pattern; and the golden test pattern comprises a predetermined pattern for memory' testing.
  • Example 24 The method of any one of examples 21 to 23, wherein the first test pattern and the second test pattern are different test patterns.
  • Example 25 The method of any one of examples 21 to 24, wherein the golden test pattern comprises at least one of a checkerboard pattern and an inverse checkerboard pattern, the golden test pattern comprising a first golden test pattern.
  • Example 26 The method of any one of examples 21 to 25, further comprising: writing, to the memory array and as part of the stress testing, a second golden test pattern to result in a second stored test pattern in the memory array; reading, from the memory array and as part of the stress testing, the second stored test pattern; and comparing, as part of the stress testing, the second stored test pattern with the second golden test pattern to identify another faulty memory element within the memory array.
  • Example 27 The method of example 26, wherein either or both of the steps of writing the first test pattern and writing the second test pattern comprise writing the test pattern under an electrically or environmentally stressed condition.
  • Example 28 The method of example 27, wherein the electrically stressed condition comprises at least one of a static stress test and a dynamic stress test.

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Abstract

Techniques and apparatuses are described that perform early-life failure detection in reserve memory. The techniques and associated apparatuses ensure reserve memory elements (138) in a memory array are fully tested at the time of manufacture with sufficient and/or similar levels of stress testing as main (non-reserve) memory elements (136). The reserve memory elements (138) are designed to serve as a backup for failed main memory elements (136). On-die hardware (a "reserve memory access (RMA) circuit") is provided to ensure that the reserve memory elements (138), which are typically not accessible, can be temporarily accessed for testing purposes. The described techniques provide for testing the reserve memory elements (138) along with the main memory elements (136) at appropriate testing phases through the use of the hardware, and via a software/algorithm for an enhanced static stress methodology.

Description

EARLY-LIFE FAILURE DETECTION IN RESERVE MEMORY
BACKGROUND
[0001] Modem computational devices of all kinds employ electronic memory. A form of memory that is employed in computers, tablets, cell phones, and other devices is random access memory' (RAM). Today's deep submicron technologies allow the implementation of multiple memories on a single silicon wafer. Due to their high component density, memories are prone to structural defects and failure during manufacture, which impacts the total die yield from the wafer.
SUMMARY
[0002] Techniques and apparatuses are described that implement early-life failure detection in reserve memory. In example aspects, a thorough testing of reserve memory during the production process is employed. These techniques entail hardware for temporarily activating reserve memory' within a die, and added reserve memory testing procedures/methods during the manufacturing process. These techniques (a) force the reserve memory to be temporarily accessible during the manufacturing testing process, and (b) then subject the reserve memory to enhanced stress testing. This brings the level of testing of reserve memory to be on par with the level of testing for the main memory'.
[0003] Aspects described below include an apparatus with a die. The die includes a memory’ array, a reserve-memory access circuit (RMA circuit), and a controller. The memory array includes a plurality of main memory elements and at least one reserve memory' element. Each main memory' element includes a group of memory’ cells. The reserve memory element includes another group of memory' cells substantially similar in structure to at least one of the main memory' elements of the plurality, and suitable as a memory replace for the at least one of the main memory’ elements of the plurality. The RMA circuit is communicatively coupled w'ith the plurality of main memory elements and the at least one reserve memory element. The RMA circuit is configured to cause the die to temporarily swap a memory’ address of a selected main memory element with an address of the at least one reserve memory’ element. An addressable portion of the memory’ array now temporarily comprises the reserve memory element and the remaining plurality of mam memory elements. That is, responsive to the swapping of the memory address, the addressable portion of the memory’ array temporarily comprises the reserve memory’ element and the remaining plurality of main memory elements The controller is configured to generate test patterns for the memory array. Additionally, the controller is configured to run a memory stress test on the addressable portion of the memory array. The memory stress test may be run using the generated test patterns.
[0004] Aspects described below also include an apparatus with at least one die. The die includes a memory array with a plurality of main memory elements and at least one reserve memory' element. Each main memory element includes a group of memory cells that are. by default, live memory cells at initial manufacture. The reserve memory element includes another group of memory' cells substantially similar in structure to a main memory' element of the plurality', and suitable as a memory' replacement for the main memory element of the plurality. The die also includes a built-in self-repair (BISR) module with a controller and a reserve-memory access (RMA) circuit. The controller is configured to determine test patterns for the memory array and to detect memory element fault information for the memory array. The reserve-memory access (RMA) circuit is configured to select between two alternative modes of test operations: a main- element test mode and a reserve-element test mode. In the main-element test mode, the reserve memory element is in a state of not being addressable for testing by the controller. In the reserveelement test mode, the reserve memory element is in a state of being addressable for testing by the controller.
[0005] Aspects described below also include a method. The method includes activating main memory elements of a memory array and at least one reserve memory element of the memory’ array. The at least one reserve memory element includes a group of memory cells that are similar in structure to at least one main memory' element of the main memory elements and suitable as a memory' replacement for the at least one main memory element. The method also includes writing, to the main memory elements and the at least one reserve memory element, a golden test pattern to result in a stored test pattern in the memory array. The method additionally includes determining a faulty memory element within the memory' array by comparing the stored test pattern with the golden test pattern.
[0006] Aspects described below also include a system with means for performing early -life failure detection in reserve memory.
BRIEF DESCRIPTION OF DRAWINGS
[0007] Apparatuses for and techniques for performing early-life failure detection in reserve memory are described with reference to the following drawings. The same numbers are used throughout the drawings to reference like features and components:
FIG. 1A illustrates an example production process for memory' in w'hich detection for early -life failure in reserve memory' may be employed; FIG. IB illustrates an example implementation of a product in which may be deployed a die that supports early-life failure detection in reserve memory;
FIG. 1C illustrates an example die that supports early -life failure detection of reserve memory;
FIG. ID illustrates stress tests that can be performed while applying aspects of early lifefailure detection in reserve memory;
FIG. 2 illustrates an example die with a built-in self-repair (BISR) module capable of performing aspects of early-life failure detection in reserve memory';
FIG. 3A illustrates an example die with an enhanced BIST module capable of performing aspects of early-life failure detection in reserve memory';
FIG. 3B illustrates an example implementation of a reserve-memory7 access (RMA) circuit that performs aspects of early-life failure detection in reserve memory7;
FIG. 4 illustrates an example logic table for a reserve-memory access (RMA) circuit that performs aspects of early -life failure detection in reserve memory;
FIG. 5A illustrates an example method of testing and repairing a die;
FIG. 5B illustrates an example full-span memory array in three successive stages during testing and repairing according to FIG. 5A;
FIG. 5C illustrates an example of a full-span memory array after application of the example testing and repairing according to FIG. 5 A;
FIG. 6 illustrates an example method for performing aspects of early -life failure detection in reserve memory; and
FIG. 7 illustrates another example method for performing aspects of early-life failure detection in reserve memory.
DETAILED DESCRIPTION
[0008] Memory can be extremely compact with electrically-sensitive components. During the manufacturing process, microchips are tested extensively in order to weed out (throw out) dies that are identified as failing. This ensures such flawed components are never used in consumer and business devices.
[0009] Discarding dies, however, can be w asteful. One way to address this problem is to enhance the die via reserve memory locations. An in-factory test can be used to identify the faulty regions within a main memory of the die. If a small segment of the main memory is determined to have failed during manufacture, it can be replaced at the factory7 with the reserve memory before the die is integrated within a product. [0010] However, a problem arises with existing factory testing procedures. With current procedures, the reserve memory is sometimes not tested at all. To the extent that some reserve memory is partially tested, the reserve memory7 may not be stress-tested to the same extent as the main memory. This means that potentially flawed/vulnerable reserve memory may be present on a die that is put into use in an electronic device in the field. If and when such reserve memory is later called into service in the field (during an automated, in-service self-repair), there is an elevated risk of overall memory7 failure.
[0011] To address this challenge, techniques of early-life failure detection in reserve memory7 are described. These techniques (a) force the reserve memory to be temporarily accessible during the testing process, and (b) then subject the reserve memory to enhanced stress testing. This brings the level of testing of reserve memory7 to be on par with the level of testing for the main memory7. Any reserve memory that is found to be either defective or vulnerable to failure can be marked on-chip as defective. Such segments of defective reserve memory7 will then not be called into use as replacements during field operations.
Memory Manufacturing and Testing
[0012] FIG. 1A is an illustration of an example manufacturing process 100 (also called “fabrication” or “production”) for dies 102 (or dice 102) in which detection of early-life failure in reserve memory may be employed. A die 102 can be implemented with any suitable memory7 including, but not limited to, random-access memory, dynamic random-access memory7 (DRAM), synchronous DRAM, three-dimensional (3D) stacked DRAM, double-data-rate (DDR) memory , low-power double-data-rate (LPDDR) memory (e.g.. LPDDR DRAM or LPDDR SDRAM), or static random-access memory (SRAM). The die 102 can also be referred to as a system-on-chip (SoC) or a chip. The die 102 can be implemented within a memory7 device or a memory module. Some memory7 devices can include multiple dies 102. FIG. 1A is a hybrid figure that interleaves method steps and tangible elements of the manufacturing process 100.
[0013] The process 100 begins with highly purified silicon wafers 104, typically round and flat, that are blank (that is, have no other structural form(s) or materials deposited on them). The silicon wafers 104 form the substrate for integrated circuit manufacture. In some cases, other substrates materials, such as gallium arsenide, may be employed.
[0014] The “first” step 106 is actually dozens or even hundreds of steps, depending on how they are characterized for descriptive purposes. The steps may involve photolithography, etching various kinds of structures on the silicon wafers, and depositing numerous chemical elements (semiconductors, metals, and insulators) in highly specific, extremely dense, microscopic patterns. The details of this processing step 106 are outside the scope of this document, and are not essential to understanding the present system and method. The result of processing step 106 is the patterned wafer 108.
[0015] In typical production, the patterned wafer 108 will now contain literally billions of microscopic electronic components such as transistor, resistors, and capacitors, suitably connected with conductive metals to implement the present technology, namely a die 102. The patterned wafer 108 can contain hundreds of dies 102, all still structurally connected on the silicon wafer 104. The “squares” illustrated for the patterned wafer 108 are each a die 102. The cut-off squares on the edges of the wafer 108 are partial/incomplete dies 102, and are disposed of during the manufacturing process 100.
[0016] A dicing and packaging step 110 entails slicing the dies 102 into separate dies, and possibly mounting them on a suitable packaging material (not illustrated). The packing material may be partly ceramic or plastic or other non-conducting materials, and also provide for electrical connections to the dies 102. By way of terminology, each memory-die-as-integrated- with- packaging is still referred to simply as a die 102. The result of the dicing and packaging step 1 10 may be a collection 112 of dozens, hundreds, or even thousands of individual, untested dies 102. [0017] The structure of a die 102 is discussed in some detail further below in this document. It can be said here that the structure includes many millions of microscopic — and potentially fragile — electronic components (transistors, capacitors, etc ). During the processing step 106, some microscopic components may be imperfectly formed. This may result in portions of the die 102 that either do not work right out of the factory; or which may be prone to short-term failure once they are put into use with electricity running through them in the field.
[0018] As a result, there is need for a testing and repairing step 114 at the factory. Some of the internal details of the testing are the subject of much of this document. Structurally, the testing process may entail mounting each single die 102 on a die test bed 116, which can drive patterns of electrical signals through the die 102. The electrical patterns may be generated (wholly or partly) by an external testing device (ETD) 118, which is coupled to the die test bed 116 via a communicative coupling 120, as further shown in FIG. 2. The ETD 118 can be a specialized computer.
[0019] The results of testing may be three-fold: Some dies 102 may be found to be working flawlessly. Other dies 102 may be found to have some defects, but can still be repaired internally at the factory. This is discussed further below in this document. Still other dies 102 may be found to be failed beyond repair, and are disposed of at the factory before ever reaching a consumer. The aggregate result of the testing may be a collection 122 of multiple tested and functional die 102. Improved systems and methods of testing at the factory are the subject of much of this document.
[0020] Once the collection 122 of multiple functional and tested dies 102 is obtained, the dies 102 can be used in further device manufacture. This may be done in part at the same factory where the dies 102 are produced, though likely on different production lines; or the dies 102 may be shipped to other factories for incorporation into products.
[0021] In step 124, the dies 102 are first arranged and mounted into ranks to form a module 126. For example, eight or nine dies 102 are arranged in one row, or sixteen or eighteen dies 102 are arranged in two rows on a circuit board to form the module 126. In this example, the module 126 can be a dual in-line memory module (DIMM). The module 126 can plug into the motherboard of a product 128 such as a computer or a cell phone. This is discussed further with FIG. IB.
Operating Environment
[0022] FIG. IB illustrates an example implementation of a product 128 which may be deployed with the die 102 that is factory -produced using the techniques for early -life failure detection in reserve memory. The product 128 is illustrated with various non-limiting example devices including a desktop computer 128-1, a tablet 128-2, a laptop 128-3, a television 128-4, a computing watch 128-5. computing glasses 128-6, a gaming system 128-7, a microwave 128-8, and a vehicle 128-9. Other devices not illustrated in the figure may also be a product 128, such as a home sendee device, a smart speaker, a smart thermostat, a baby monitor, a Wi-Fi™ router, a drone, a trackpad, a drawing pad, a netbook, an electronic reader, a home automation and control system, a wall display, a home appliance, automotive control systems, medical testing or medical treatment devices, security systems, defense systems, factory or industrial monitoring/control devices, drones, aviation systems, or any other electronic device.
[0023] The product 128 can include a host device 130, one or more computer processors 132, and a computer-readable medium 134. Elements of the host device 130 (not illustrated in the figure) may include a motherboard for mounting electronic components. The product 128 can optionally include a cabinet, casing, or other physical structure that may provide both for mounting electronic components and control interfaces, and also provide other functionalities as well. One or more peripherals (not shown) such as keyboard, mice, buttons, display screens, touch screen displays, ports, and other such elements, may provide for user interface(s) and/or communications with networks or other electronic devices. The product 128 can be the result of the host device 130 combined with a chosen group of peripherals that best meets the product requirements. [0024] The computer processor 132 (also known as a microprocessor or a central processing unit (CPU) can access data that is stored on the at least one computer-readable medium 134. In an example implementation, the computer-readable medium 134 provides storage of program software and program data. Applications and/or an operating system embodied as computer- readable instructions on the computer-readable medium 134 can be executed by the computer processor 132 to provide numerous types of functionalities well known in the arts. Fixed or variable program data may also be stored in and/or read from the computer-readable medium 134. [0025] The computer-readable medium 134 may implemented using the module 126 with one or more dies 102. In an example implementation, the module 126 is implemented as dual in-line memory modules (DIMM) or other types of memory cards, which in turn are configured with DRAM. The computer-readable medium 134 can also include other types of memory that are not illustrated. Other ty pes of memory' can include, without limitation: static random access memory' (SRAM), a solid state drive (SSD), a hard disk drive (HDD), optical memories, holographic memories, and other types of memory known in the art or to be developed.
[0026] The die 102 may be configured to include main memory and reserve memory. The main memory7 is composed of main memory' elements 136. The reserve memory is composed of one or more reserve memory' elements 138. The reserve memory' element 138 is similar in structure to a main memory element 136. In this way, the reserve memory element 138 can be a suitable replacement for the main memory element 136. Example structures of the reserve memory' element 138 and the main memory element 136 can include a row or a column, as further described with respect to FIG. 1C.
[0027] Generally speaking, the reserve memory (also referred to in the art as "backup memory ’ “redundant memory,” or “spare memory”) is defined as memory that is not by default available (or addressable) for use as storage as the memory7, but — if and when a portion of the main memory7 fails — the reserve memory' may be called into use as a replacement for the failed portion of the main memory'. This memory replacement (or memory swap) can occur if the main memory begins to fail over time or prior to field use if memory problems are identified at the factory during testing in step 114 (see FIG. 1 A above).
[0028] It will be apparent that the ongoing reliability7 of the die 102 is ty pically essential for the reliable operations of the product 128 in the field. Memory' failure can result in total loss of product operations. Necessarily, then, the reserve memory (e.g., the one or more reserve memory’ elements 138) should be at least as reliable as the main memory (e.g., the mam memory7 elements 136). The reserve memory' may in particular be factory -tested according to the systems and methods described further herein. Die Structure
[0029] FIG. 1C is an illustration of an example die 102 with multiple banks 140. The die 102 may be capable of performing aspects of early-life failure detection of reserve memory. A die 102 may have multiple banks 140, and each bank 140 may have multiple full-span memory- arrays 142. In this document; for convenience of illustration and exposition, each bank 140 is considered to have one full-span memory' array 142. The full-span memory array 142 may also have sub-arrays (not shown).
[0030] The term “bank’" includes not only the full-span memory array 142 of storage cells, but also the associated electronics local to the array, including: a memory address router 144 (MAR 144) (also known in the art as a “memory wrapper”), a row' address decoder 146 (RAD 146), sense amplifiers 148, a column multipl exor/demulti plexor (MUX/DEMUX) 150 (all these elements are discussed further below ), and a built-in self-repair (BISR) module 152. Example implementations of the BISR module 152 are further described with respect to FIGs. 2, 3 A, and 3B.
[0031] The basic building block of the die 102 is a cell 154 (e.g., a memory cell or a storage cell). Each cell 154 consists of fundamental electrical components, such as a capacitor and a transistor (not illustrated), and stores a single bit of data. A single bit is either a ‘1‘ or a ‘O’, represented as a presence of an electric charge such as one volt, or a zero voltage, respectively. When a bit (‘0’ or ‘ 1’) is written into the cell 154. the transistor is used to charge or discharge the capacitor. A charged capacitor is typically representative of a ‘ 1 ’, while a discharged capacitor is typically representative of a ‘0.’
[0032] Most often, cells 154 are organized into a rectangular array of main rows 156 and main columns 158, fonning a main memory array 160. The main rows 156 and the main columns 158 are example representations of the main memory elements 136. When the computer processor 132 of the product 128 accesses a chunk of the main memory array 160, it activates the main row' 156 containing the cells 154 storing the desired data; reads the desired data; and transfers it to the computer processor 132.
[0033] FIG. 1C depicts an example of athirty-two row (156) by sixteen column (158) bit-oriented main memory array 160, which has an accompanying, additional four additional reserve rows 162 and four additional reserve columns 164. The reserve row's 162 and the reserve columns 164 are example representations of reserve memory' elements 138. The collection of reserve row s 162 and reserve columns 164 can referred to as reserve (or redundant) memory. A reserve memory’ element 138 is a group of cells 154 that is substantially similar (e.g., substantially identical) in structure and/or storage capabilities to any one of the main memory’ elements 136 (any one of the main rows 156 or main columns 158), and suitable as a memory replacement for the any one of the main memory elements 136.
[0034] It will be noted that in a ty pical implementation, the reserve rows 162 are parallel to and immediately adjacent to the main rows 156; and the reserve columns 164 are similarly parallel to and immediately adjacent to the main columns 158. As a result, the functional main memory' array 160 available for storage is thirty -two rows by sixteen columns; but the full-span memory' array 142 of cells (which includes the main memory' array 160 and the reserve rows/columns 162/164) is thirty -six rows by twenty columns.
[0035] As will become apparent from the disclosure below, a main row 156 and/or a main column 158 may be any of '‘live” (operating effectively) or “defective” (live-but-not-properly functioning, or taken out of service due to defects). Whether it is “live” or “defective”, structurally a main row 156 is still a row, and a main column 158 is similarly still a column. Therefore in this document and the accompanying figures the reference numbers do not distinguish “live” from “defective.” That is, there are “main rows 156”, “live main rows 156”, and “defective main rows 156”; and similarly there are “main columns 158”, “live main columns 158”, and “defective main columns 158.” The distinction is identified via the adjectives “live” and “defective”, but not via the reference numbers.
[0036] Reserve rows 162 and reserve columns 164 are structurally distinct from the main rows 156 and the main columns 158 respectively. The reserve memory elements 138 are by default not active (that is, not addressable for writing or reading). During testing and/or normal operation, the reserve memory elements 138 can be dormant (e.g., not addressable) or live (addressable and put into use to temporarily or permanently replace a main memory element 136). Note that reserve rows 162 and reserve columns 164 may be referred to collectively as "reserve memory.”
[0037] It will also be noted that actual full-span memory arrays 142 may have many higher numbers of rows and columns. In an example case, there are 8,192 main columns (158) of live cells (154) and 65.536 main rows (156) of live cells (154). Even with these much larger main memory arrays 160 — and fully analogous to the smaller array of FIG. 1C — the reserve rows 164 and reserve columns 164 of a 8,192 x 65,536 array are structurally additional rows and columns in the full-span memory array 142. That is, the reserve rows 162 and reserve columns 164 are generally placed adjacent to the main rows 156 and the main columns 158. Other implementations are also possible in which the reserve rows 162 and/or the reserve columns 164 are placed between main rows 156 and/or main columns 158, respectively. With memory swapping (see FIGs. 5B and 5C), the number of addressable rows/columns at any one time remains fixed at 65,536 x 8,192. This is because when a live main row 156 is defective and therefore deactivated, it is replaced by a reserve row 162; and similarly for columns.
[0038] Finally, it will be noted that the configuration shown in FIG. 1C is for example only, and not limiting. There may be more or fewer reserve rows 162 or reserve columns 164. All reserve columns 164 may be placed together on the left, or all together on the right, or may be distributed between the main columns 158; similar placement considerations apply to reserve rows 162. In some implementations, the reserve rows/columns 162/164 may be placed elsewhere on the bank 140, that is, not adjacent to the main rows/columns 156/158.
[0039] If a dormant reserve row 162 is allocated to replace a live main row 156, which is defective, then the row address of the defective main row 156 is called a row repair address (RRA). Then a decoder (not illustrated) decodes the RRA into control signals for switching row multiplexers to skip the defective main row 156 once a row address enable (RAE) signal is asserted. The RRA is mapped, via the multiplexers, to the address of a designated reserve row 162. The reconfiguration of a main column 158, which is defective, and a dormant reserve column 164 is performed in a similar way: give a column repair address (CRA); map the CRA to the address of a reserve column 164; and assert a column address enable signal (CAE) to repair the defective main column 158 using the reserve column 164 (which goes from dormant to live). The row and column multiplexers are not illustrated in the figure, but are an internal element of the memory’ address router 144.
[0040] The memoiy bank 140 also includes a variety of essential electronic components, only some of which are illustrated in the figure. These include a row address decoder 146 and column multiplexer/demultiplexer (MUX/DEMUX) 150, which together sene to select individual cells 154 or groups of cells in the main memory array 160 or the full -span memory array 142. The memory bank 140 can also include sense amplifiers 148 (or an array of sense amplifiers), which detects the ‘0’ value or ‘1 ’ value in a specific cell 154. Additionally, the memory’ bank 140 can include the physical address reconfiguration mechanism, or router, already referred to above as the memoiy address router 144.
[0041] The full-span memory array 142 also includes the one or more resene columns 164 and/or one or more reserve rows 162. By design, rows and columns with the lives cells 154 (shaded white) are designated to store bits (‘ 1 ’s or ‘0’s) in their cells. At initial production of the die 102, all the live cells 154 together are referred to synonymously as the “main memory array’' 160 or the “live array” 160.
[0042] The cells of the reserve column(s) 164 and reserve row(s) 162 (w ith cross-hatch shading) are designated, by default, to normally not store anything, and so are initially dormant (e.g., not addressable). If not called into use at some point, they remain dormant. These reserve memory elements 138 are present precisely for the purpose their name suggests: they are reserved or backup memory in case one or more “live'’ cells 154 turn into “unlive” cells 154 - that is, in case of cell failure leading to a defective cell. Reserve rows and columns 162 and 164 may be thought of colloquially as “spare” rows or columns; though unlike, for example, spare tires, a spare row or spare column is not physically moved around to replace a defective “tire.”
[0043] It will be noted that as reserve rows/columns 162/164 are swapped into a live role during repair, the main (live) memory array 160 evolves to omit any damaged main rows or columns 156, 158, and to include the swapped-in reserve rows/columns 162/164. See also FIG. 5C for further illustration and discussion of row swapping/column swapping.
[0044] The memory address router 144 is one element among others of the specialized electronics, which can be used to configure the bank 140 for repair. When a faulty live cell 154 is detected, the memory’ address router 144 can be programmed to turn the entire main row 156 or entire main column 158 containing the cell 154 to an “inactive” state. The memory address router 144 further swaps the now inactive main row 156 or main column 158 for a previously dormant reserve row’ 162 or column 164.
[0045] In summary’, it will be noted again that the swapping of a reserve row/column 162/164 for a formerly-live main row/column 156/158 is not accomplished by physically transporting or moving the rows or columns on the bank 140. Rather, it is accomplished by reconfiguring various cell/row/column addressing mechanisms (which are inside the memory address router 144), and which are also part of and internal to the bank 140. The details of this row/column swapping via address reconfigurations in the memory address router 144 are known to those of ordinary skill in the art and are not essential to understanding the present system and method, though they may entail setting various signal routing switches to reroute some address signals.
[0046] The BISR module 152 works in conjunction with the memory’ address router 144 to effect testing and repair of the banks 140. The BISR module 152 is discussed further below in conjunction with FIGs. 2, 3A, 3B, and other figures.
[0047] It should be noted that normally, as part of a repair process for a full-span memory’ array 142, when a memory’ swap occurs it is permanent. This is accomplished in part via an on- die fuse bank, which is essentially a long-term programmable memory (see FIG. 2 below’ for further discussion). However, it is an element of the present system and method that, for testing purposes, a swap between a main memory’ element 136 and a reserve memory element 138 may be made on a temporary basis (e.g., a non-permanent basis). This is discussed further below. To avoid any possible confusion, it is noted that defective main row s 156 are only sw apped for reserve rows 162, and defective main columns 158 are only swapped for reserve columns 164. Rows are not swapped for columns, or vice versa.
Stress Testing
[0048] FIG. ID provides plots of two different types of memory stress tests, which may be applied to a bank 140 during the testing step 114 in FIG. 1 A. Example stress tests depicted in FIG. ID include a static stress test 168 and a dynamic stress test 170. These two types of stress tests 168, 170 are examples only, and other tests are known in the art or may be envisioned. It will be noted that a stress test may be applied more than once during manufacture, and may be applied in varied environmental conditions. For example, either or both stress tests 168, 170 may be run at normal room temperatures, or when the die 102 is exposed to elevated temperatures, and/or when the die 102 is exposed to reduced (chilled temperatures). Such environmental variations simulate real-world conditions that the die may be exposed in the course of normal field operations. Varied environmental pressures or other environmental variations, such as vibrations, may also be applied during stress testing.
[0049] A die 102 is normally operated with a supply voltage set at a nominal voltage 172 (or at a nominal voltage level). The supply voltage can be referred to in the art as VDD (or sometimes Vdd or VDD), and this voltage is provided to the memory cells 154. Stress testing may in some implementations entail operating the die 102 at a higher voltage than the nominal voltage 172. This higher voltage is referred to as a test voltage 174 (or an elevated voltage). In example stress tests, the test voltage 174 can be significantly larger than the nominal voltage 172.
[0050] The static stress test 168 is graphically illustrated at the top of FIG. ID. The static stress test 168 adjusts the supply voltage between the nominal voltage 172 and the test voltage 174. During time periods that the supply voltage is set at the nominal voltage 172, a pattern 176 is written to the live memory' array 160. The pattern 176 can be designed to test for particular types of failures, including those associated with a stuck-at fault (SAF), a transition fault (TF), leakage, or short circuits between cells 154. Example patterns 176 can include a checkerboard pattern 178 (alternating 0’s and l’s) or an inverted checkerboard pattern 180 (alternating l’s and 0’s), which are further explained with respect to FIG. 5B. For the static stress test 168, the test voltage 174 may, for example, be 1.5 times larger than the nominal voltage 172.
[0051] The dynamic stress test 170 is graphically illustrated at the bottom of FIG. ID. Similar to the static stress test 168, the dynamic stress test 170 adjusts the supply voltage between the nominal voltage 172 and the test voltage 174. In contrast to the static stress test 168, the dynamic stress test 170 writes the pattern 176 to the live memory array 160 during the time period that the supply voltage is set at the test voltage 174.
[0052] With either the static stress test 168 or the dynamic stress test 170, the cells 154 of the die 102 are pushed well-bey ond their nonnal operating conditions (that is, well above their normal operating voltages). If attempts to write data to, or read data from, a cell 154 pass before stress testing these cells 154 but fail after stress testing, the main row 156 or main column 158 containing the cell 154 may be identified as defective. This determination may be made by the built-in selfrepair module 152, which is further described in FIG. 2.
The Built-In Self-Repair Module
[0053] FIG. 2 illustrates memory testing and repair elements 200, namely an example die 102 with an example BISR module 152, which may also be referred to as a “reconfiguration circuit,” according to methods of early-life failure detection during manufacture. A die 102 with such a configuration, including both the reserve memory element(s) 138 and the BISR module 152, may be called a repairable die.
[0054] Note that as drawn in the figure, the BISR module 152 may appear as external to the die 102. However, this is simply an “exploded” view7 of the BISR module 152, for purposes of illustration only. This is indicated by the dotted lines in the figure that indicate the BISR module 152 as a module which, in this particular example illustration, is situated on a lower-left comer of the die 102. The lower left location on the die is example only, and is not limiting. It will therefore also be understood that the connections between the BISR module 152 and a repair port 202 and between the BISR module 152 and the memory7 address router 144 are actually internal connections of the die 102, and specifically of the memory bank 140.
[0055] Note also that the die 102 may' have multiple BISR modules 152, as indicated by the shadowing of the “small” BISR module 152 on the die 102 in the figure. There may, for example, be one BISR module 152 for each memory bank 140. In some implementations, each BISR module 152 may be incorporated directly into the silicon “real estate” space of its corresponding memory bank 140 (this configuration is not illustrated in the figure).
[0056] FIG. 2 also illustrates the ETD 118, which may be communicatively coupled 120 to the BISR module 152 of the die 102. The coupling 120 may be via a wired or wireless connection. The coupling 120 may further be via the die test bed 116. which is not shown in FIG. 2 but is illustrated in FIG. 1A.
[0057] The ETD 118 may be a dedicated, specialized controller, or may be a general purpose computer that runs softw are. The software can configure the on-board processor to run tests on the die 102. Either way, the ETD 1 18 will include its own processor 204, memory 206, and all other hardware elements required to perform its tasks. The purposes of the ETD 118 may be to provide control signals that initiate or direct the operations of the BISR module 152. The ETD 118 may also provide specialized or custom bit patterns for memory testing, as well as possibly regulate other external environmental conditions for testing (for example, the room temperature). The details of operations of the ETD 1 18 will not be covered in this document. But it will be understood that various control or operational signals, indicated below as being received by the BISR module 152, may be generated by the ETD 118.
[0058] The BISR module 152 may have several internal sub-modules, including a built-in selftest (BIST) controller 208, a built-in repair analysis (BIRA) engine 210, a long-term, programmable, updateable memory (LTPUM) 212, and a built-in self-repair (BISR) register 214. The long-term, programmable, updateable memory (LTPUM) 212 may alternatively be referred to simply as a memory. The BIST controller 208 may generate binary test patterns for the die 102 under test. If-and-when a fault is detected in an active main memory element 136 by the BIST controller 208, the fault information is sent to the BIRA engine 210 for further processing. Note that both of the BIST controller 208 and the ETD 118, alone or in combination, may be referred to as “test pattern generators” and/or “test pattern controllers.”
[0059] It will be noted that the tests administered by the BIST controller 208 may be entirely built-in and self-initiated; or may be directed, controlled, and/or initiated to varying degrees by the ETD 118. The BIST controller 208 may include an address-and-data-generator-and- comparator (ADGC) 216, which: generates target addresses for testing; generates “golden” test patterns 218 (or a golden test data pattern) for sending to the bank 140; and compares returned data (test data out 220 (TDO 220)) against the original golden test pattern 218 to identify memory' faults. In some implementations, golden test patterns 218 may be stored long-term in registers or other small memory' regions of static random access memory' (SRAM) or read-only memory' (ROM), or otherwise hard-coded into circuity, to ensure the stability and reliability of the golden test data.
[0060] The BIRA engine 210 collects the fault information 222 sent from the BIST controller 208, and allocates reserve memory elements 138 (that is, it allocates reserve rows/columns 162/164) to replace the live-but-faulty main rows/columns 156/158. This allocation is done according to both the fault information 222 (which is generated by the BIST controller 208), and according to some designated, pre-coded reserve analysis algorithm(s) employed by the BIRA engine 210. The allocated redundancies map the failed main memory' addresses to reserve memory addresses, and are known as repair signatures 224. The established repair signatures 224 are stored in the short- term, during a testing process, in a BIRA register 226.
[0061] The LTPUM 212 stores established repair signatures 224 for long-term, permanent use - including permanent storage during power-down on the entire product 128, which contains the die 102. In an implementation, the LTPUM 212 may be updatable on multiple occasions (as the die 102 may be subject to successive memory failures/repairs over its lifetime). The repair signatures 224 of the LTPUM 212 are used upon system boot-up to restore any previously made repairs to the die 102. Although not explicitly shown in FIG. 2, other components can be coupled between the LTPUM 212 and the BISR register 214. For example, a control circuit or a decoder can interpret (e.g., decode) the information stored within the LTPUM 212 and put it in a format that is usable by other components for the repair operation.
[0062] An example type of LTPUM 212 includes a fuse array. While a fuse array is a known and commonly used fonn of such memory7, other ty pes of LTPUM 212 may be employed as well. When a fuse is blown in the fuse array, or other permanent-storage binary element is set in an LTPUM 212, this may be referred to as a "fuse event/’ A “blowing” or setting of a fuse is a onetime only process; that is, a fuse event, once done cannot be undone. However, enough fuses can be included in the fuse array to allow for progressive programming (successive fuse-blowing) over time, for any anticipated number of repairs. The ultimate result of a fuse event is to permanently disconnect those main elements 136 that are flagged as having faulty bits, and replace them with appropriate redundant elements 138.
[0063] The BISR register 214 sen es as a kind of way-station or transportation interface for repair signatures 224, and possibly for other internal data and signals, to be transported between: the BIST controller 208. the BIRA engine 210, the LTPUM 212. and other interface elements of the die 102. These other elements may include the memory7 address router 144 (which configures memory pathway re-mappings in the banks 140), and the repair port 202, which may receive address and enable signals 228 and test patterns 176 (e.g., the golden test pattern 218). The BISR register 214 may actually have multiple internal registers to manage and route data flow. To implement the techniques for early -life failure detection in reserve memory, the BISR register 214 is coupled to a reserve-memory access circuit, which is further described with respect to FIG. 3A. [0064] The repair port 202 of the die 102 may receive a variety7 of signals pertaining to testing and repairing the die 102. These may include the address and enable signals 228 alluded to above, and/or various test patterns 176, and other signals and control commands, which may facilitate a memory testing process. These are generally apart from the repair signatures 224, which are received by the memory address router 144. [0065] The BISR module 152 performs memory testing and repair during the manufacturing process 100 to improve the process yield. The detailed sequential order of signal and data transport among and between elements of the BISR module 152, and between and among other elements of the die 102, is not essential to understanding of the present techniques and apparatuses. However, the overall flow of the built-in self-repair process is briefly summarized below.
[0066] First, assume that a repair process has yet to occur. At this point, the repair signature 224 can be considered "empty" or has information that indicates the reserve memon' elements 138 are to remain dormant. The BIST controller 208 tests the live memory array 160. The BIST controller 208 generates golden test patterns 218 for banks 140 on the die 102 and compares test responses (e.g., the TDO 220) with the golden test patern 218 for identifying the fault sites. “Golden” test data is defined as test data that is stored via hardware memory elements with extremely high reliability, so the golden test patern is a known, reliable reference for memory testing.
[0067] Next, the fault information of the die 102 is sent to the B1RA engine 210 and collected in the memory fault storing logic of the BIRA engine 210. Also, a reserve analyzer (a processor or processing unit of the BIRA engine 210, not illustrated) determines the memoiy repair solution autonomously. That is, the BIRA engine 210 allocates redundancies (replacements of defective main memory elements 136 with reserve memory elements 138) according to various algorithms known or to be invented.
[0068] As soon as the repair analysis process is completed by the BIRA engine 210, the established repair signatures 224 are programmed (or "blown") into the LTPUM 212 for permanent storage. The repair signatures 224 may also be transmitted to the memory address router 144 for immediate implementation.
[0069] Subsequently, during power-on of the die 102, the repair signatures 224 are loaded (via intermediary circuits) from the LTPUM 212 into the memory7 address routers 144 (specifically, into repair registers of the address routers, not illustrated in the figures). As a result, the memory7 address routers 144 are thereby configured to ensure that proper swapping occurs in the banks 140; that is, a reserve memory element 138 is suitably employed to replace a main memory element 136 that was previously identified as defective.
[0070] The reserve memory in other dies that do not perform early -life failure detection in reserve memory may not be fully tested, or even tested at all. during the manufacturing process. This is because the testing process, as described above, only tests live cells 154. The cells of reserve memory elements 138 do not become live until if/ when they have been swapped into use. Therefore, they are only partially tested or not tested at all during factory7 testing according to the above methods. As such, potentially vulnerable reserve memory elements 138 may become part of a product 128 in the field, where such vulnerable reserve memory elements 138 may introduce instability . To address this, the BISR module 152 includes additional circuitry that enables the reserve memory element 138 to be temporarily addressable for testing, as further described with respect to FIG. 3A.
Enhanced Stress Testing and Repair with a Reserve-Memory Access Circuit
[0071] FIG. 3A illustrates enhanced memory testing and repair 300 that is performed using a reserve-memory access (RMA) circuit 302 (RMA circuit 302) of the built-in self-repair module 152. The reserve-memory access (RMA) circuit 302 enables techniques for thorough, testing of reserve memory elements 138. As before (with FIG. 2), the BISR module 152 as a whole, including the RMA circuit 302, is illustrated in an exploded view, and is actually an onboard module of either the individual banks 140 or at least the die 102. Although some of the signals, components, and/or connections shown in FIG. 2 are not shown explicitly in FIG. 3 A due to space constraints, it is to be understood that the BISR module 152 of FIG. 3 A is similar to the BISR module 152 of FIG. 2. The BISR module 152 shown in FIG. 3A differs from the BISR module 152 shown in FIG. 2 in that the RMA circuit 302 is explicitly depicted in the BISR module 152 of FIG. 3 A.
[0072] In the depicted configuration, the RMA circuit 302 is integrated into the BISR module 152. In an alternative implementation, the RMA circuit 302 may be a separate module on the die 102 that is suitably communicatively coupled with other elements of the BISR module 152 (those the same as or similar to the BISR module 152 as illustrated in FIG. 2 above).
[0073] The purpose and function of the RMA circuit 302 is to enable reserve memory' elements 138 to be temporarily swapped for live main memory elements 136, so that the reserve memory elements 138 can be subject to testing (e.g., during the manufacturing process 100 of FIG. 1A or during other built-in self-tests). During the temporary syvap, it can be determined if one or more selected, reserve memory elements 138 — now made temporarily live in response to the swapping — can function properly.
[0074] The RMA circuit 302 is shoyvn in block form in FIG. 3A. As suggested in the figure by the shadowing of the RMA circuit 302, more than one RMA circuit 302 may be employed. For example, in one implementation, each RMA circuit 302 may be associated with a specific reserve memory element 138 or a specific set of reserve memory elements 138. This is discussed further beloyv. [0075] As shown in FIG. 3A, in one implementation, any one RMA circuit 302 is communicatively coupled with the ETD 118 and/or the BIST controller 208; with the BISR register 214; and with the memory address router 144. At a high level, the RMA circuit 302 is coupled between the BISR register 214 and the memory address router 144 so that it can utilize the existing repair architecture of the die 102 and provide a temporary repair signature 304 to enable one or more reserve memory elements 138 to be temporarily addressable fortesting. More specifically, the temporary' repair signature 304 acts like a typical repair signature 224 and causes the die 102 to make one or more reserve memory' elements 138 live while suppressing (e.g., deactivating) a matching number of main memory elements 136. In some implementations, other components in the die 102 that are downstream from the RMA circuit 302 and perform aspects of the repair operation may be unaw are of whether the information passed from the BISR module 152 represents an established repair signature 224 (e.g., provided by the LTPUM 212) or a temporary' repair signature 304.
[0076] The RMA circuit 302 is designed in a manner that supports testing of the main memory' elements, testing of the reserve memory' elements, and repair operations. In a situation in which the die 102 has yet to be repaired and the die 102 is undergoing testing, the RMA circuit 302 can selectively cause a reserve memory' element 138 to be addressable or not addressable for the test. To support testing of the reserve memory element 138, the RMA circuit 302 passes the temporary’ repair signature 304, which specifies an address of a predetermined main memory element 136 for swapping in the repair memory element 138. To support testing of the main memory' elements 136, the RMA circuit 302 passes a null signal or an ’’empty’" signal that indicates that no repair is to be made. During normal operation, the RMA circuit 302 supports the repair operations by passing the repair signature 224 to the memory address router 144.
[0077] Generally speaking, after testing the reserve memory elements 138, the RMA circuit 302 allows the repair signature 224 to be passed and the temporarily-swapped reserve memory' elements 138 can be restored to reserve status (for possible future use in the field), or may be marked as “failed” if appropriate. In an implementation, the RMA circuit 302 can be understood as being configured to select between two alternative modes of test operations of the BISR module 152: (A) a main-element test mode, w'herein no reserve memory' element 138 is targeted for testing by the BIST controller 208; and (B) a reserve-element test mode, where a current reserve memory element(s) 138 is targeted for testing by the BIST controller 208. This process is further described w'ith respect to FIG. 5A.
[0078] If a reserve memory' element 138 is found to be defective during factory testing, the die 102 and in particular the bank 140 marks the defective reserve memory' element 138 as “bad”, so it is not utilized in future repairs. Stated generally, the die 102 maintains a persistent stored indication of flawed reserve memory elements 138, so they are not used for repair in the field. In various implementations of the present system and method this may be done in any number of ways. For example, the BISR module 152 may have a flawed reserve-memory (FRM) register 306, possibly in the form of a write-once read-many (WORM) memory that may be used to store suitable on- chip identification/identifiers for the defective reserve memory elements 138. The FRM register 306 may be communicatively coupled (not shown in the figures) with any of the BIST controller 208, the BIRA engine 210, the memory address router 144, or other elements of the die 102 as required so that defective reserve memory elements 138 are not employed for repair. In an implementation, the FRM register 306 may be integrated into, or be an extension of, any of: the BISR register 214, the LTPUM 212, the memory address router 144, or even the BIST controller 208 or the BIRA engine 210.
[0079] In an alternative implementation, defective reserve memory elements 138 may be more directly identified or marked proximately to the defective row/column. For example, each reserve memory elements 138 may have an adjacent extra bit or register (not shown in the figures) that may be a write-once bit/register for permanent storage. The write-once bit/register may be set for example to one (‘1’) by default to identify a valid reserve memory elements 138, but set to zero CO’) if needed to identify that the reserve memory elements 138 is flawed or damaged.
[0080] Some signals depicted in FIG. 3A are further described with respect to FIG. 3B. These signals include the expose redundant elements (ERE) signal 308 (ERE signal 308) and the repair enable signal (RES) 310 (RES 310). An example implementation of the RMA circuit 302 is further described with respect to FIG. 3B.
[0081] FIG. 3B illustrates internal elements of an example RMA circuit 302. The purpose and function of the RMA circuit 302 is discussed immediately above. It will be noted that both the hardw are wiring and the internal signals needed to enable such function could be implemented with a variety of different circuits and with a variety of possible components. Therefore it is emphasized that the configuration shown in FIG. 3B (and discussed in detail immediately below) is only one example possibility7 among others that may be envisioned and that fall within the scope of the appended claims.
[0082] In the example implementation illustrated in FIG. 3B, the RMA circuit 302 contains: a stress-test (ST) register 312; a multiplexer 314; and an (optional) AND gate 316 (indicated with a dashed border). The functions of these elements, and their interoperations, are described immediately below7. It will be noted that the BISR module 152 also contains an optional NOT gate 318 (indicated w ith a dashed border). In an implementation, the NOT gate 318 may not be part of the RAIA circuit 302; in an alternative implementation, the NOT gate 318 may be part of the RMA circuit 302. The NOT gate 318 is discussed further below.
[0083] The ST register 312 may store the temporary' repair signature 304. Although the term “stress-test” register 312 is associated with the “stress test”, generally speaking the ST register 312 can be used to enable testing of reserve memory elements 138 for any type of test that is performed prior to integration within the product 128 or any type of built-in self-test performed in the field. [0084] The temporary' repair signature 304 may in various implementations: (i) be hard-coded into the ST register 312 (in ROM or reprogrammable memory), (ii) be obtained from the ETD 118 (see previous FIGs. 2 and 3A), and/or (hi) be obtained from the BIST controller 208. In some implementations, the ST register 312 can store additional information, such as stress-test code bits that provide any necessary, ancillary' signaling that is required to implement the swap. For example, a stress-test code bit may indicate, via communication with the either the memory' address router 144 or the repair port 202, that the swap is in fact only temporary’ (and so should not be burned into the LTPLJM 212).
[0085] Presented immediately below are two possible implementations, which are for example only and are not limiting, for uses/operations of the ST register 312. In a first implementation, each RMA circuit 302 is associated with or coupled with one reserve memory' element 138 (or possibly with a set or group of reserve memory elements 138). This association or coupling establishes that the associated reserve memory elements 138 is to be tested when its specific RMA circuit 302 provides the temporary' repair signature 304.
[0086] In such an implementation, the temporary repair signature 304 may be used to store the address of the main memory element 136 that is to be temporarily swapped with the reserve memory element 138 associated with the RMA circuit 302. A plurality of respective RMA circuits 302 may each be communicatively coupled with a respective different reserve memory' element 138 so that each RMA circuit 302 is configured to store a respective different temporary' repair signature 304 indicative of an address (or addresses) of a different respective selected main memory element(s) 136. In an implementation where the RMA circuit 302 is associated with multiple (‘n’) reserve memory elements 138, the ST register 312 may store an associated ‘n’ temporary repair signatures 304 associated with ‘n’ addresses of main memory elements 136 for respective swappings.
[0087] In a second implementation, the RMA circuit 302 may be associated with all of the reserve memory elements 138, or with a large cluster for reserve memory element 138. For example, a RMA circuit 302 may be associated with all the reserve rows 162 or with all the reserve columns 164. In such an implementation, the temporary' repair signature 304 may be a digital code, possibly a compressed code, that operationally reflects the row/column structure of the banks 140 employed on the die 102. In particular, the digital code may be reflective of the organization, locations, and or electrical access routes (addresses, etc.) of the reserve memory elements 138 in relation to the main memory elements 136 on the dies 102.
[0088] This discussion assumes similar configurations of designs for the rows and columns are used by each bank 140 on the die 102. If different row/column configurations are used by different banks 140, the temporary repair signature 304 may vary among RMA circuits 302 on the same die 102. For example, for a TSMC™ N3/4/5 die (from Taiwan Semiconductor, Inc.™), the temporary repair signature 304 may be {1 'bl. 8'b0}. For another example, a Synopsis™ N7 die (from Synopsis, Inc.™), the temporary repair signature 304 may be { 1’bl , 11 ’b0} . The details of how a temporary repair signature 304 (compressed or not) may indicate locations, arrangements, or addresses of reserve memory7 elements 138 are beyond the scope of this document. Numerous possible systems or methods of such encoding may be employed, consistent with the appended claims.
[0089] In such an implementation, the addresses of the main memory elements 136 to be temporarily swapped may be determined in a number of ways. The RMA circuit 302 may have an RMA microcontroller and firmware, or hard-coded RMA logic (neither illustrated in the figure), to select the memory elements for swapping. The selection may be made by the BIST controller 208 or the ETD 118.
[0090] In an implementation, stress-test code bits may not be required. For example, the equivalent signals which may be associated with stress-test code bits may instead be embedded in or integrated with the temporary repair signature 304. Either or both of the repair port 202 or the memory address router 144 may have associated logic that may recognize suitable signals or codes indicative that only a temporary swap is being made.
[0091] In combination with stress-test codes (if needed), the temporary7 repair signature 304 in the ST register 312 may be employed to program the registers of the memory address router 144 to temporarily "swap ouf' selected main memory elements 136. and simultaneously to temporarily “swap into” live mode one or more reserve memory elements 138. The swap being temporary, it may also be later reversed (immediately after testing, for example), which would: (i) restore the affected, default main memory element(s) 136 to their live mode of operation, and (ii) restore the affected reserve memory element(s) 138 to a dormant status.
[0092] The RMA circuit 302’s multiplexer (MUX) 314 is configured to receive as input both the temporary repair signature 304 via data path 320, and also to receive in parallel the repair signature 224 from the BISR register 214 via data path 322. At any given moment of use, the MUX 314 will be configured to transmit one of (i) the temporary repair signature 304, or (ii) the repair signature 224 (e.g., the established repair signature) via the data path 324 to the memory address router 144. Other implementations are also possible in which the data path 324 also passes the output of the MUX 314 to any of the repair port 202 of the die 102, the BIST controller 208, or the BIRA engine 210.
[0093] Upon transmitting of the temporary repair signature 304, one or more banks 140 of the die 102 are configured to test the reserve memory elements 138 of the die 102. The temporary' repair signature 304 indicates which among the main memory elements 136 are to be swapped for the testing, while the test pattern 176 provided by the BIST controller 208 may convey a variety’ of parameters pertaining to the stress test duration, timing, voltages, and/or patterns. Upon transmitting of the repair signature 224, one or more banks 140 of the die 102 are configured — typically in the field, during use of the product 128 — to repair the bank(s) 140, where the repair signature 224 indicates which among the reserve memory’ element(s) 138 is to be substituted for a dysfunctional main memory element(s) 136.
[0094] An input test control signal (TCS) 326 to the MUX 314 determines the choice between a MUX output of the temporary’ repair signature 304 or a MUX output of the repair signature 224. For example, an input signal value of ‘U to the MUX 314 may select for the temporary repair signature 304, while an input signal value of ‘0’ may select for the repair signature 224. In an implementation not illustrated, the TCS 326 to the MUX 314 may come from a single source, such as the BIST controller 208. In such an implementation, the AND gate 316 is not employed. [0095] In the implementation shown in FIG. 3B, the TCS 326 to the MUX 314 comes from the AND gate 316. In this implementation, the AND gate 316 may receive two control signals. A first control signal can be the expose reserve elements (ERE) signal 308, which is received via signal path 328. This signal may be from a factory-controlled die testing process in step 114 of FIG. 1A. In some implementations, the ERE signal 308 is provided by an off-chip source, such as the ETD 118. In other implementations, the ERE signal 308 is provided by an on-chip source, such as the BIST controller 208. In general, the ERE signal 308 indicates whether or not testing of the reserve memory elements 138 is requested.
[0096] A second control signal may come from an on-chip source, such as the RES 310 via signal path 330, which may issue for example from the BISR register 214. For example, the RES 310 can be a particular bit associated with the repair signature 224. As is the nature of AND gates, if both of the two input control signals are high (’ 1’), the output value of the AND gate 316 is high, and the temporary repair signature 304 is selected for output by the MUX 314. If either or both input signals are low (‘O’), the output value of the AND gate 316 is low ('O’), and the repair signature 224 is selected for output by the MUX 314.
[0097] It will be noted that, in the implementation illustrated, the RES 310 from the BISR register 214 is first passed through the NOT gate 318 before reaching the signal path 330 to the AND gate 316. The effect is that when an actual repair of the die 102 is intended (so the RES 310 is asserted high), the input to the AND gate 316 is low and MUX 314 outputs the repair signature 224.
[0098] If a repair of the die 102 has yet to occur, the RES 310 is asserted low (‘0’). At the same time, the NOT gate 318 turns the low RES 310 to a high ('! ’) value for transmission over the signal path 330 to the AND gate 316. If the ERE signal 308 is also asserted high, then the AND gate 316 output signal (e.g., the TCS 326) is high. The MUX 314 selects for the temporary repair signature 304, and a test (e.g., the statis stress test 168 or the dynamic stress test 170) can be performed on the reserve memory elements 138 and the remaining (non-swapped) main memory’ elements 136.
[0099] It will be noted that other circuit configurations are possible. For just one example, the BISR register 214 or other elements may have an entirely separate repair disable signal line, making the NOT gate 318 superfluous. Similarly, the configuration discussed above requires two asserted inputs 328 and 330 to select for the temporary’ repair signature 304 via the MUX 314. In an alternative circuit configuration, only one input may be required to initiate testing, in which case the AND gate 316 may be superfluous.
[0100] As noted above, but repeated here - a function of the RMA circuit 302 is to enable reserve memory elements 138 to be temporarily swapped for main memory elements 136 of the live memory array 160, so that the reserve memory elements 138 can be subject to testing, including stress testing during manufacturing. The RMA circuit 302 may also provide for, or help provide for, switching betw een a permanent repair mode and a reserve-element testing mode.
[0101] When in a repair-element test mode, the RMA circuit 302 may employ the ST register 312. The ST register 312 may maintain and provide for the temporary repair signature 304, such as to enable the die 102 to test the reserve memory elements 138. The RMA circuit 302 may also employ the MUX 314 to select between repair mode operations and a resen e-element testing mode.
[0102] The circuit configuration illustrated in FIG. 3B is for example only, and other arrangements of components may be employed to achieve the effects and input/output operations described above, consistent with the appended claims. It will be noted that during factory testing of the die 102, and in particular testing of the banks 140, the RMA circuit 302 may be configured to put the die 102 into a reserve-element test mode to identify possibly flawed or error-prone reserve memory elements 138. In the process, the RMA circuit 302 can also be configured to put the die 102 into a main-element test mode to identify possibly flawed or error-prone main memory elements 136. The identifying of the flawed or error-prone elements can be performed by the BIST controller 208 or the ETD 118, or via both in combination. In the event that such defective main memory elements 136 are found in factory testing, the control circuitry of the die 102 (for example, the BIST controller 208 or the BIRA engine 210) may be used to program the LTPUM 212. An impact of the RMA circuit 302 for testing and normal operations is further described with respect to FIG. 4.
[0103] FIG. 4 illustrates an example logic table. Table 2 (400), for the RMA circuit 302. In an implementation, the RMA circuit 302 may receive two inputs, the ERE signal 308 and the RES 310 (or a version thereof, such as an inverted version of the RES 310). In an alternative implementation, the RMA circuit 302 may receive the RES 310 and then internally invert the signal (that is, apply a logical NOT operation). The latter implementation is actually illustrated in FIG. 3B.
[0104] The ERE signal 308 (which is again a short-hand for “expose redundant elements” signal) may be received either from the ETD 118, or may be received from the BIST controller 208 of the die 102 or another component of the die 102. The ERE signal 308, as its name suggests, is specifically applied to signal to the RMA circuit 302 that reserve memory elements 138 are desired/intended to be tested.
[0105] The RES 310 (which is again short-hand for “repair enable” signal) may be routed to the RMA circuit 302 by way of (for example) the BISR register 214. In other implementations, the RES 310 can be provided by the ETD 118 and/or the BIST controller 208. The RES 310 may either comprise or be reflective of a portion of the repair signature 224. In general, the RES 310 may indicate that a reserve memory element 138 has already been swapped into use (e.g., a repair operation has already been established). If the repair operation has already been established, then the reserve memory element 138 may have already been tested. During normal operations, such as when the die 102 is integrated within the product 128, the RES 310 enables the previously- established repair signature 224 to be passed to the die 102.
[0106] In some situations, the repair signature 224 may not be populated or may be considered empty (e g., void of data or invalid). This can be the case prior to completion of the die testing and repair 114 step in FIG. 1A. This can also be the case if there are currently no main memory' elements 136 identified as defective. If the repair signature 224 is empty, the die 102 is considered to have no defective main memory' elements 136 or is considered to have no main memory' elements 136 that have been identified as being defective. As such, the die 102 does not swap any of the active main memory elements 136 with the reserve memory elements 138.
[0107] The logic of Table 1 (shown generally at 400) should therefore be apparent to persons skilled in the arts. Different outcomes can occur depending on whether the die 102 is undergoing testing (e.g., stress testing) or is operating in a product 128, which is referred to as "normal operations” in Table 1. If the NOT RES 310 is ‘O’, this indicates that there is a valid repair signature 224 that has been previously established and stored in the LTPUM 212. During both testing and normal operations, the NOT RES 310 causes the RMA circuit 302 to output the repair signature 224. As such, the reserve memory element 138 associated with the RMA circuit 302 is utilized as a replacement for the main memory element 136 specified in the repair signature 224. In this case, the assertion of the ERE signal 308 is a “do-not-care” (DNC) situation. In other words, the NOT RES 310 causes the RMA circuit 302 to output the repair signature 224 regardless of whether the ERE signal 308 is asserted to ‘ 1 ' or ‘0.’
[0108] If the NOT RES 310 is ‘ 1,’ this indicates that the repair signature 224 has not been previously established (e.g., the repair signature 224 is empty or indicates the absence of a repair operation). During both testing and normal operations, if the ERE signal 308 is ‘O’, the RMA circuit 302 outputs the “empty” repair signature 224. As such, the main memory elements 136 remain addressable and the reserve memory element 138 associated with the RMA circuit 302 remains in a non-addressable state (e.g., remain dormant). For testing, this means that the main memory elements 136 can be tested. For normal operations, this means that the main memory' element 136 are utilized for read and/or write operations. In general, the BIST controller 208 and/or the ETD 118 set the ERE signal 308 to ‘0’ during testing to enable testing of the main memory elements 136. During normal operations, the ERE signal 308 can be set to ’0’ by default. [0109] If the NOT RES 310 is ‘1 ’ and the ERE signal 308 is ‘ 1,’ the RMA circuit 302 outputs the temporary7 repair signature 304. As such, the reserve memory' element 138 associated with the RMA circuit 302 is utilized as a replacement for the main memory element 136 specified in the temporary repair signature 304. This means that the reserve memory element 138 transitions from a non-addressable state (e.g., the dormant state) to an addressable state (e.g., a live state). In this case, the reserve memory' element 138 can be tested to perform aspects of early -life failure detection in reserve memory.
[0110] The particular circuit architecture for the RMA circuit 302 above (FIG. 3B) is example only. Any circuit design that can implement the logic of Table 1 (400), and which can be suitably integrated with a BISR module 152 or made interoperable with a BISR module 152, falls within the scope of the current disclosure and the appended claims. Although the above examples are described with respect to a single RMA circuit 302 that is associated with a single reserve memory element 138, the operations described above can be similar applied to multiple RMA circuits 302 and/or an RMA circuit that is associated with multiple reserve memory' elements 138.
Early-Life Failure Detection in Reserve Memory
[0111] FIG. 5A illustrates an example method 500 for performing early-life failure detection in reserve memory. The method 500 can also be referred to as enhanced stress testing. The method 500 ensures the reserve memory elements 138 are subject to substantial and robust testing 114 during the manufacturing process 100.
[0112] It will be noted that the example method 500 may be executed by instruction control via the BIST controller 208 and/or the ETD 118. Either or both of the BIST controller 208 and/or the ETD 118 may include a computer-readable storage medium comprising computer-executable instructions that, alone or in combination, execute some aspect of the method. The computer- readable storage medium may for example comprise hard-coded instruction sets (fixed logic circuitry), firmware, or read-only memory with program code to be executed by microcontrollers of the BIST controller 208 and/or the ETD 118.
[0113] Before diving into the specific steps of method 500, it is helpful to reconsider the strategy' behind the method 500. A bank 140 can have a full-span memory array 142 including both the main memory array 160 and any unused reserve memory elements 138. However, at any one time, it is only possible to access the main memory' array 160, which is a subset of the full-span memory' array 142. The main memory array 160 does not include unused (e.g., still dormant) reserve memory elements 138. The method 500 effectively overcomes this limitation for testing purposes.
[0114] Method 500 is discussed concurrently with reference to FIG. 5B, which illustrates an example full-span memory' array 142 in three successive stages during testing 114. It will be noted that the full-span memory array 142 of FIG. 5B is illustrated with only one reserve row 162 and one reserve column 164. The number of reserv e rows 162 and reserve columns 164 is for example only, and more could be employed (as in FIG. 1C), consistent with the general principles and operations of example method 500. In the example described below, the RES 310 is assumed to be ‘0,’ meaning that a repair has yet to be established.
[0115] At 502. the die 102 operates in accordance with a reserve-element test mode. As part of the reserve-element test mode, the ERE signal 308 is asserted to ‘ 1 ’ by the BIST controller 208 and/or the ETD 118, as indicated at 504. As explained with respect to FIG. 4, this causes the RMA circuit 302 output the temporary' repair signature 304. The temporary repair signature 304 causes the die 102 to swap a designated reserve memory element 138 with a main memon' element 136 associated with the temporary repair signature 304. In other words, a reserve memory' element 138 becomes enabled (e.g., addressable or live), and so becomes effectively a part of the main memory array 160.
[0116] As part of the reserve-element test mode, the BISR module 152 generates a first pattern 176 for writing to the main memory array 1 0. For example, the BIST controller 208 and/or the ETD 118 may generate or provide the first pattern 176. Because the reserve memory' element 138 has been temporarily included in the main memory array 160, the first pattern 176 is written to the memory elements that include the reserve memory element 138. The first pattern 176 can be the checkerboard pattern 178 or the inverse checkerboard pattern 180.
[0117] With reference now to FIG. 5B, the result of this step is intended to be a transition from the full-span memory array 142 shown at 514 to the main memory' array 160 shown at 516. Consider in this case that the reserve memory element represents the reserve column 164. Also, the main memory' element 136 associated with the temporary repair signature 304 is the left-most main column 158. As shown in the main memory' array' 160 at 516, a pattern of data is written to the reserve column 164 and the remaining main memory elements 136 (e.g., the main memory' elements 136 that do not include the main column 158 associated with the temporary repair signature 304). The swapped-out main column 158 of the default main memory array 160 — which in the figure happens to be the left-most or first column — has no bits impressed on it by the write operation.
[0118] Returning to FIG. 5A, step 502 implements aspects of early -life failure detection in reserve memory. To continue testing the main memory’ element 136 that was swapped out in step 502, the method can optionally proceed to step 508. The step 508 can be used to perform aspects of stress testing, as described with respect to FIG. ID.
[0119] In step 508, the die 102 operates in accordance with a main-element test mode. As part of the main-element test mode, the ERE signal 308 is asserted to ‘0’ by the BIST controller 208 and/or the ETD 118, as indicated at 510. As explained with respect to FIG. 4, this causes the RMA circuit 302 to output the repair signature 224, which is ‘‘empty” at this stage. Accordingly, the die 102 “un-sw'aps” the tw'o previously-swapped elements. More specifically, the reserve column 164 returns to a dormant, non-addressable state and the main column 158 returns to alive, addressable state. The reserve memory element 138 is again a reserve memory element, and the main memory element 136 specified in the temporary repair signature 304 is restored to its status as a member of the main memory’ array 160. The result is that the main memory7 element 136, which was effectively hidden from writing during step 506, may now have data written to it. [0120] As part of the main-element test mode, the BISR module 152 generates a second pattern 176 for writing to the main memory array 160. For example, the BIST controller 208 and/or the ETD 118 may generate or provide the second pattern 176. With reference again to FIG. 5B, the result of step 512 is intended to be a transition from the main memory array 160 at 516 to the inclusive test array (ITA) 518 at 520.
[0121] The effective net result of steps 502 and 508 is that the first test pattern 176 and the second test pattern 176, written consecutively, form a logical test pattern for writing to the inclusive testing array (ITA) 518. The ITA 518 covers or spans all elements of the default main memoij' array 160 and the reserve column 164. This logical golden test pattern 218 is imprinted upon the series of electronic signalings, which drives the write operation.
[0122] Several points will be noted. First, it is apparent that the reserve row 162 is not included in the above procedure. To fill and test the reserve row 162, an analogous but entirely separate procedure would be needed for the rows - either successive to or prior to the procedure above for the reserve column 164.
[0123] Second, and more generally: if the full-span memory array 142 includes multiple reserve columns 164, the procedure above can be repeated — with suitable modifications, such as changing the bit patterns, and possibly writing a more extended series of bit paterns (that is, more than just two bit patterns), along with possibly multiple column swaps — to ensure that in the end, the entire full-span memory array 142 is writen to with the logical test patern (or other desired test patterns). In other words, it is possible to activate all of the reserve memory elements 138, possibly in a time sequence, with different elements or groups of elements being activated at different times; again, this makes it possible to write to the entire full-span memory array 142 with all reserve memory elements 138 included.
[0124] Third, it is stated above that a test patern is ‘‘intended” to be writen, or that a “logical test pattern” is formed for writing. What is meant by this is the following: The BIST controller 208 generates (or stores or accesses) one or more so-called “golden test patem(s)” 218, such as a checkboard patern 178 or an inverse checkerboard pattern 180 that is intended as a template for what should be writen to the full-span memory array 142. Further, suitable write operation(s) are performed to write that patern to the memory
[0125] However - the entire point of testing is to identify failed storage cells, or to identify operative cells that may be prone to failure under stressed conditions. Should there be some failed storage cells (or “prone to failure” cells) on the full-span memory array 142; then a bit value that is actually written to those flawed cells, or a bit value that is later read from those flawed cells. may not be the intended bit value. It is because of this fact that that BIST controller 208 can identify flawed rows or columns at all.
[0126] In view of this, the test pattern illustrated in FIG. 5B (and specifically at 520) is an idealized/logical golden test pattern as it would occur (to be written to and read from) an inclusive test array 518 that had no flawed cells at all. Stated another way. the final test pattern illustrated may be considered as the golden test pattern 218. Many newly produced, real-world dies 102 will have flawed cells, and the golden test pattern 218 would not be flawlessly imprinted at first. However, post-stress-testing and especially post-repair, it is presumed and intended that all the live memory elements 136 and/or 138 are now fully reliable, and so the die 102 will flawlessly store and retrieve the golden test patterns 218 (as well as any other data written to memory).
[0127] The steps 502 and 508 can be used to perform aspects of a stress test, the details of this test are discussed above in conjunction with FIG. ID. In some example implementations, the ADGC 216 of the BIST controller 208 compares the data with the golden test pattern 218 to identify’ flaws in the inclusive test array 518, which includes potential flaws or vulnerabilities in the reserve column 164.
[0128] The steps 502 and 504 can be performed multiple times for different logical test patterns and/or for different ty pes of stress tests. For example, to perform a first static stress test 168 with the logical golden test pattern representing the checkerboard pattern 178, steps 502 and 508 can be performed with the first pattern 176 representing the checkerboard pattern 178 and the second pattern 176 representing the inverted checkerboard pattern 180. To perform a second static stress test 168 with the logical golden test pattern representing the inverse checkerboard pattern 180, steps 502 and 508 can be performed with the first pattern 176 representing the inverse checkerboard pattern 180 and the second pattern representing the checkerboard pattern 178. Similar pattern assignments can be applied for performing a first dynamic stress test 170 with the logical golden test pattern representing the checkerboard pattern 178 and for performing a second dynamic stress test 170 with the logical golden test pattern representing the inverse checkerboard pattern 180. It will be noted that in the implementation just described, using both the checkerboard pattern and the inverted checkerboard pattern ensures that every bit of the full-span memory' array 142 is tested with both a ‘0’ value and a ‘1 ’ value.
[0129] In various examples, the first pattern 176 can be the same or different than the second pattern 176, depending on an architecture of the reserve memory. For stress testing purposes, the first pattern 176 and/or the second pattern 176 can be the checkerboard pattern 178, the inverse checkerboard pattern 180, or some combination thereof. [0130] Consider an example in which the quantity of reserve memory elements 138 represents an odd integer number (e.g., 1, 3, or 5) that are co-located within the full-span memory array 142 (e.g., are located on the left side, the right side, or in a middle of the full-span memory array 142). In this case, the first and second patterns 176 are different patterns to effectively write the checkerboard pattern 178 or the inverse checkerboard pattern 180 to the inclusive test array 518, as described above.
[0131] In another example in which the quantity of reserve memory elements 138 is an even integer number (e.g., 2, 4, or 6), the first and second patterns 176 and can be the same pattern to effectively write the checkerboard pattern 178 or the inverse checkerboard pattern 180 to the inclusive test array 518. Consider a case in which there are two reserve columns 164 on the left side of the full-span memory array 142. To write the checkerboard pattern 178 to the inclusive test array 518, the first and second patterns 176 can be the checkerboard pattern 178. As another example, to write the inverse checkerboard pattern 180 to the inclusive test array 518, the first and second patterns 176 can be the inverse checkerboard pattern 180. In general, persons skilled in the art can determine appropriate patterns 176 that will result in the desired logical test pattern for the inclusive test array 518. These persons can apply the steps described with respect to the reserv e-element test mode and the main-element test mode to realize the desired logical test pattern given any type of architecture of the reserve memory (e.g., an architecture having an even number of elements, an odd number of elements, elements positioned on a left side, a right side, or in a middle of the main memory elements 136, elements distributed between the main memory' elements 136, and so forth).
[0132] Persons skilled in the relevant arts will appreciate that the above method 500 is for example only, and may be adapted in a variety of ways. As noted already, a reserve row 162 may be swapped into a temporary live role at a given time (rather than the reserve live column 164). Other bit patterns may be employed to impose other kinds of electrical stresses on the inclusive testing array 518. For example, columns may be filled with all ‘ l ’s, or all ‘0’s; or with alternating columns of all ‘ l ’s and all ‘0's (and similarly for rows). It will also be recognized that, with suitable alterations to the reserve-memory-element swappings, and possibly with the use of additional or more frequent reserve-memory-element swappings, a dynamic stress test 170 may be employed in place of, or in addition to, the static stress test 168.
[0133] In all such methods of enhanced testing, an aspect of the method is to swap one or more reserve memory elements 138 into the inclusive test array 518 in a non-permanent manner, so that these reserve memoiy elements 138 can be substantially tested along with the main memory' elements 136. Any reserve memory' elements 138 that are found to be flawed may then be permanently marked as flawed (and therefore not used for repair) according to systems and methods discussed above. The tested reserve memory elements 138 can be used to repair faulty main memory elements 136, as further described with respect to FIG. 5C.
[0134] FIG. 5C illustrates an example memory array 522 following a repair operation. As may be seen from the figure, some former reserve row(s) 162 have been applied for repair and so are now permanently active row(s) 524; these permanently active rows 524 are now also fully stress tested. Similarly, some former reserve columns 164 have been applied for repair and so are now permanently active column(s) 526, and these permanently active column(s) 526 are now fully stress tested.
[0135] There may also be one or more reserve memory elements 138 that remain in reserve for possible future use, but again have been fully stress tested. This means they may be put into use in the field, if necessary to replace failing main memory7 elements 136, with a high degree of reliability and confidence.
[0136] Finally, there may be one or more former reserve memory elements 138 that are now permanently deactivated reserve memory elements 528. They may be marked as deactivated according to systems and methods described above in this document, and they will not be called into use as repair elements in the field. This again helps ensure the overall reliability of the die 102 and its individual banks 140 (or full-span memory arrays 142).
Distributed Processing System
[0137] As described above in some detail, the methods disclosed herein may be performed via processors under the control of program code that is executed internally by one or more microcontrollers onboard the die 102. These processors are or may be integral parts of the BIST controller 208 and/or the BIRA engine 210. While not shown in the figures, in some implementations the RMA circuit 302 may have an internal microcontroller, which may for example be programmed to generate various sequences of the temporary' repair signatures 304. In addition, some code executed by the present methods may be processed by the ETD 118 (see FIG. 2), which has its own processor 204 and memory' 206.
[0138] Together, these elements, with associated registers described throughout the application, may constitute an extended or distributed processing system - either distributed across the die 102, or distributed across both the die 102 and the ETD 118. It is noted that the ETD 118 may itself be a remote server connected to the die 102 via a network or cloud connection.
[0139] This distributed computing system may include, via the ETD 118, one or more data inputs and data interfaces that may be used to modify or view parameters of the current system and method (such as die test patterns), for example via a keyboard, mouse, screen display, virtual reality goggles, voice control, or similar.
[0140] Alternatively or in addition, the distributed computing system can be implemented with any one or combination of hardware, firmware, or fixed logic circuitry. The distributed computing system may also include one or more computer-readable medium, such as one or more memory devices that enable persistent and/or non-transitory data storage (in contrast to mere signal transmission), examples of which include: random access memory (RAM) which is apart and separate from the die 102 being subject to test; non-volatile memory (e.g., any one or more of a read-only memory (ROM), flash memory, EPROM, EEPROM, etc.), and a disk storage device. The disk storage device may be implemented as any type of magnetic or optical storage device, such as a hard disk drive, a recordable and/or rewriteable compact disc (CD), any type of a digital versatile disc (DVD), and the like. The distributed computing system can also include a mass storage medium device (storage medium).
[0141] The controllers or processors of the distributed computing system run any operating systems, applications, microapplications, software drivers, hardware drivers, system components, engines, or managers required to implement early-life failure detection in reserve memory.
Example Methods
[0142] FIGs. 6 and 7 depict example methods 600 and 700 for implementing aspects of early -life failure detection in reserve memory. Methods 600 and 700 are shown as sets of operations (or acts) performed but not necessarily limited to the order or combinations in which the operations are shown herein. Further, any of one or more of the operations may be repeated, combined, reorganized, or linked to provide a wide array of additional and/or alternate methods. In portions of the following discussion, reference may be made to the process 100 of FIG. 1, and entities detailed in FIGs. 2 and 3A, reference to which is made for example only. The techniques are not limited to performance by one entity or multiple entities operating on one device.
[0143] At 602 in FIG. 6. at least one main memory element within a memory array is temporarily replaced within at least one reserve memory element of the memory array. For example, the RMA circuit 302 outputs the temporary repair signature 304 along data path 324, as show n in FIG. 3B. The temporary repair signature 304 causes the die 102 to replace at least one main memory element 136 with at least one reserve memory element 138 of the full-span memory’ array 142, as shown in FIG. 5C. This repair operation is temporary in that later on, the RMA circuit 302 can stop providing the temporary repair signature 304 (e.g., switch to providing the repair signature 224). Assuming the repair signature 224 is "empty." this causes the die 102 to return the reserve memory element 138 to a dormant state.
[0144] In a first example, the main memory' element 136 is a main row 156, and the reserve memory element 138 is a reserve row 162. In a second example, the main memory element 136 is a main column 158, and the reserve memory element 138 is a reserve column 164, as shown in FIG. 1C. In a third example, the main memory element 136 can include multiple main rows 156 (or multiple main columns 158), and the reserve memory' element 138 can include multiple reserve rows 162 (or multiple reserve columns 164).
[0145] At 604. the memory array with the at least one reserve memory element is stress tested to identify whether the at least one reserve memory element is faulty. For example, the BIST controller 208 and/or the ETD 118 stress tests the live memory' array 160, which includes the reserv e memory' element 138 to identify whether the reserve memory element 138 is faulty'. The stress test can be a static stress test 168 and/or a dynamic stress test 170, as shown in FIG. ID. [0146] Various techniques can be employed to determine if the at least one reserve memory' element 138 is faulty. In one example, the data within the at least one reserve memory' element 138 is read and compared to a corresponding portion in the golden test pattern 218, as described above. Any discrepancy between the read data and the corresponding portion in the golden test pattern 218 can indicate the presence of one or more faulty cells 154 within the reserve memory element 138. In another example, a subsequent write and/or read operation is performed after the stress testing. In this case, any detected fault associated with the write and/or read operation can indicate the presence of one or more faulty' cells 154 within the reserve memory' element 138. In some implementations, subsequent read and/or write operations can be performed using the ERE signal 308 and the RMA circuit 302 to temporarily activate the reserve memory' element 138.
[0147] At 702 in FIG. 7, main memory' elements of a memory' array and at least one reserve memory element of the memory array are activated. The at least one reserve memory element comprises a group of memory cells that are similar in structure to at least one main memory’ element of the main memory elements and suitable as a memory replacement for the at least one main memory element. For example, the die 102 activates the main memory elements 136 and the at least one reserve memory element 138. This activating step can be performed in multiple steps. For example, the die 102 can be operated in according to a reserve-element test mode to temporarily activate the one or more reserve memory elements 138, as described with respect to step 502 in FIG. 5 A. Also, the die 102 can be operated in according to a main-element test mode to activate the main memory' elements 136, as described with respect to step 508 in FIG. 5B. [0148] At step 704, a golden test pattern is written to the main memory7 elements and the at least one reserve memory element to result in a stored test pattern in the memory array. For example, the BIST controller 208 or the ETD 118 causes the golden test pattern 218 to be written to the full-span memory array 142 to result in a stored test pattern. The golden test pattern 218 can be the checkboard pattern 178 or the inverted checkboard pattern 180 of FIG. ID. The writing of the golden test pattern 218 can be performed in multiple steps, such as those described with respect to steps 504 and 510 in FIG. 5B.
[0149] At step 706, a memory' element within the memory' array is determined to be faulty by comparing the stored test pattern with the golden test pattern. For example, the TDO 220 is generated from the full-span memory' array 142 and passed to the BIST controller 208 or the ETD 118. The BIST controller 208 or the ETD 118 compares the stored test pattern with the golden test pattern 218 to identify a faulty memory element (e.g., a faulty main memory' element 136 and/or a faulty’ reserve memory element 138 within the full-span memory’ array 142). The fault information 222 can be passed to the BIRA engine 210, and an appropriate repair can be made if the fault corresponds with a main memory element 136. If the reserve memory' element 138 is determined to be faulty7, the die 102 can be discarded or programmed in such a way that the faulty7 reserve memory element 138 will not be available for use.
Conclusion
[0150] Although techniques using, and apparatuses including, early-life failure detection in reserv e memory7 have been described in language specific to features and/or methods, it is to be understood that the subj ect of the appended claims is not necessarily limited to the specific features or methods described. Rather, the specific features and methods are disclosed as example implementations of early-life failure detection in reserve memory'.
[0151] Some Examples are described below.
[0152] Example 1: An apparatus comprising a die, the die comprising: a memory7 array7 comprising: a plurality' of main memory elements each comprising a group of memory7 cells; and at least one reserve memory7 element comprising another group of memory7 cells substantially similar in structure to at least one of the main memory elements of the plurality, and suitable as a memory replacement for the at least one of the main memory7 elements of the plurality7; a reserve-memory access circuit (RMA circuit) communicatively coupled with the plurality of main memory elements and the at least one reserve memory element, the RMA circuit configured to: cause the die to temporarily swap a memory address of a selected main memory element with an address of the at least one reserve memory element, wherein, responsive to the swapping of the memory address, an addressable portion of the memory array temporarily comprises the reserve memory element and the remaining plurality of main memory' elements; and a controller configured to: generate test patterns for the memory array: and run a memory' stress test on the addressable portion of the memory' array.
[0153] Example 2: The apparatus of example 1, wherein: the RMA circuit is communicatively coupled to one specific reserve memory element, and the RMA circuit is configured to store a temporary' repair signature indicative of an address of the selected main memory' element.
[0154] Example 3: The apparatus of example 1 or 2, further comprising: a plurality of respective RMA circuits each communicatively coupled with a respective different reserve memory' element, wherein each RMA circuit is configured to store a respective different temporary repair signature indicative of an address of a different respective selected main memory element.
[0155] Example 4: The apparatus of any previous example, wherein: the RMA circuit is communicatively coupled wi th a plurality of reserve memory' elements; and the RMA circuit is configured to store temporary repair signatures indicative of a plurality of addresses of the main memory elements.
[0156] Example 5: The apparatus of example 4, wherein: the RMA circuit is configured to swap each of the plurality of reserve memory’ elements with one of the main memory elements. [0157] Example 6: The apparatus of any previous example, wherein: the RMA circuit is configured to: store a temporary' repair signature that identifies the main memory' element to be temporarily swapped with the reserve memory element; and receive a test control signal (TCS), and upon assertion of the TCS output the temporary repair signature to cause the die to temporarily swap the memory address of the selected main memory element with the address of the reserve memory element; and the controller of the die is configured to test the reserve memory' element.
[0158] Example 7: The apparatus of example 6, wherein the RMA circuit further comprises a multiplexer configured to: receive the stored temporary' repair signature and receive a repair signature from a register; receive the TCS; and select between transmitting the stored temporary’ repair signature and transmitting the repair signature based on the received TCS.
[0159] Example 8: The apparatus of example 7, wherein: the RMA circuit further comprises an AND gate configured to: receive an expose reserve elements (ERE) signal, indicative when asserted that a test pattern controller is initiating a memory test utilizing the reserve memory element, the test pattern controller being either internal to or external to the die; receive an inverted repair enable signal (RES) from the register, that when asserted is indicative that a repair has not been performed utilizing the reserve memory element; and generate the test control signal based on an AND operation of the ERE signal and the inverted RES; and the assertion of the ERE and the assertion of the inverted RES result in the multiplexer selecting for the temporary repair signature for testing of the reserve memory element.
[0160] Example 9: The apparatus of any previous example, wherein each main memory element of the plurality comprises either a row of memory cells or a column of memory cells. [0161] Example 10: The apparatus of any previous example, wherein the temporary swap of the reserve memory element and the selected main memory element comprises sending to a memory address router of the die an instruction to assign the memory' address of the selected main memory' element to the reserve memory element while avoiding triggering a fuse event in a long-term, programmable, updateable memory of the die that would otherwise make the memory swap permanent.
[0162] Example 11 : The apparatus of any previous example, wherein: the controller is configured to: provide a golden test pattern suitable for testing of the memory array; write a first test pattern to the memory7 array7 when the reserve memory element is in a state of being not addressable; and write a second test pattern to the memory’ array when the reserve memory element is in a state of being addressable: and a resulting logical test pattern for writing to the memory array is the golden test pattern that is written to memory' addresses that include both the reserve memory7 element and the plurality7 of main memory elements.
[0163] Example 12: The apparatus of example 11, wherein the golden test pattern is one of a checkerboard pattern and an inverse checkerboard pattern.
[0164] Example 13 : The apparatus of any preceding example wherein each group of memory cells of the plurality of main memory elements are, by default, live memory cells at initial manufacture, the at least one die further comprising a built-in self-repair (BISR) module comprising: the controller configured to determine test patterns for the memory7 array and to detect memory element fault information for the memory array; and the reserve-memory access (RMA) circuit configured to select between two alternative modes of test operations: a main-element test mode, wherein the reserve memory' element is in a state of not being addressable for testing by the controller; and a reserve-element test mode, wherein the reserve memory element is in a state of being addressable for testing by the controller. [0165] Example 14: An apparatus comprising at least one die, the at least one die comprising: a memory' array comprising: a plurality of main memory' elements each comprising a group of memory' cells that are, by default, live memory cells at initial manufacture; and at least one reserve memory element comprising another group of memory cells substantially similar in structure to a main memory element of the plurality, and suitable as a memoiy replacement for the main memory element of the plurality7; and a built-in self-repair (BISR) module comprising: a controller configured to determine test patterns for the memory array and to detect memory element fault information for the memory array; and a reserve-memory access (RMA) circuit configured to select between two alternative modes of test operations: a main-element test mode, wherein the reserve memory element is in a state of not being addressable for testing by the controller; and a reserve-element test mode, wherein the reserve memoiy7 element is in a state of being addressable for testing by the controller.
[0166] Example 15: The apparatus of example 13 or 14, wherein the BISR module further comprises: a built-in repair analysis (BIRA) engine configured to collect the memory7 element fault information and to generate one or more repair signatures based on the fault information; and a long-term, programmable, updateable memoiy7 (LTPUM) configured to maintain longterm, permanent storage of the generated repair signatures, and configured to communicate the repair signatures to a memory address router of the die.
[0167] Example 16: The apparatus of any one of examples 13 to 15, wherein the BISR module is configured to maintain a stored indication of a faulty reserve memory element, wherein the faulty7 reserve memory element is not employed for repairs. [0168] Example 17: The apparatus of any one of examples 13 to 16, wherein: the RMA circuit comprises a stress-test register and a multiplexer (MUX); the stress-test register is configured to store a temporary' repair signature indicative of the main memory element of the plurality for swapping in the reserve memory element; and the MUX is configured to selectively transmit, to a memory address router of the die, the temporary repair signature or a repair signature for the die.
[0169] Example 18: The apparatus of example 17, wherein the RMA circuit further comprises an AND gate configured to: receive two control signals; and output, based on the two control signals, a test control signal to control whether the MUX transmits the temporary' repair signature or the repair signature.
[0170] Example 19: The apparatus of example 18, wherein: the two control signals comprise a first control signal from a test device that is external to the die and a second control signal that is generated internally by the die; the first control signal determines a factory' controlled die testing process; and the second control signal is indicative that the reserve memory element either has already’ been swapped for a main memory element or that the reserve memory element has not been swapped for the main memory' element.
[0171] Example 20: The apparatus of any one of examples 13 to 19, wherein: the controller is configured to: provide a predetermined golden test pattern suitable for testing the memory' array including both the plurality' of main memory' elements and the reserve memory element; write a first test pattern to the main memory' array based on the RMA circuit selecting the main-element test mode; and write a second test pattern to the main memory array based on the RMA circuit selecting the reserve-element test mode; and a resulting test pattern written to the memory' array is the predetermined golden test pattern, which is written to memory addresses that include both the reserve memory element and the plurality of main memory elements. [0172] Example 21 : A method comprising: activating a full-span memory array of a die, the full-span memory array comprising all main memory elements of a memory' array of the die and all of at least one reserve memory' element of the memory array of the die, the at least one reserve memory element comprising a group of memory cells that are similar in structure to at least one main memory element of the main memory elements and suitable as a memory replacement for the at least one main memory' element; writing to the full-span memory' array a golden test pattern to result in a stored test pattern in the full-span memory array; and determining a faulty memory element within the full -span memory’ array by comparing the stored test pattern with the golden test pattern.
[0173] Example 22: A method comprising: activating main memory elements of a memory array and at least one reserve memory' element of the memory array, the at least one reserve memory element comprising a group of memory' cells that are similar in structure to at least one main memory' element of the main memory' elements and suitable as a memory' replacement for the at least one main memory' element; writing, to the main memory elements and the at least one reserve memory element, a golden test pattern to result in a stored test pattern in the memory array; and determining a faulty memory element within the memory' array by comparing the stored test pattern with the golden test pattern.
[0174] Example 23: The method of example 21 or 22, wherein: the activating and the writing comprises: enabling a reserve memory' element of the at least one reserve memory' element to form a first live memory array with the reserve memory' element enabled and a specified main memory' element of the at least one main memory element disabled; writing a first test pattern to the first live memory array; disabling the reserve memory element and enabling the specified main memory' element to form a second live memory array; and writing a second test pattern to the second live memory array; the first test pattern is written prior to the second test pattern; the writing of the first test pattern and the writing of the second test pattern logically combine to form the golden test pattern; and the golden test pattern comprises a predetermined pattern for memory' testing.
[0175] Example 24: The method of any one of examples 21 to 23, wherein the first test pattern and the second test pattern are different test patterns.
[0176] Example 25: The method of any one of examples 21 to 24, wherein the golden test pattern comprises at least one of a checkerboard pattern and an inverse checkerboard pattern, the golden test pattern comprising a first golden test pattern.
[0177] Example 26: The method of any one of examples 21 to 25, further comprising: writing, to the memory array and as part of the stress testing, a second golden test pattern to result in a second stored test pattern in the memory array; reading, from the memory array and as part of the stress testing, the second stored test pattern; and comparing, as part of the stress testing, the second stored test pattern with the second golden test pattern to identify another faulty memory element within the memory array.
[0178] Example 27: The method of example 26, wherein either or both of the steps of writing the first test pattern and writing the second test pattern comprise writing the test pattern under an electrically or environmentally stressed condition.
[0179] Example 28: The method of example 27, wherein the electrically stressed condition comprises at least one of a static stress test and a dynamic stress test.

Claims

CLAIMS What is claimed is:
1. An apparatus comprising a die, the die comprising: a memory array comprising: a plurality of main memory elements each comprising a group of memon' cells; and at least one reserve memory' element comprising another group of memory' cells substantially similar in structure to at least one of the main memory' elements of the plurality, and suitable as a memory replacement for the at least one of the main memory elements of the plurality; a reserve-memory access circuit (RMA circuit) communicatively coupled with the plurality' of main memory' elements and the at least one reserve memory element, the RMA circuit configured to: cause the die to temporarily swap a memory' address of a selected main memory' element with an address of the at least one reserve memory element, wherein, responsive to the swapping of the memory' address, an addressable portion of the memory' array temporarily comprises the reserve memory element and the remaining plurality of main memory elements; and a controller configured to: generate test patterns for the memory array; and run a memory stress test on the addressable portion of the memory' array.
2. The apparatus of claim 1, wherein: the RMA circuit is communicatively coupled to one specific reserve memory element, and the RMA circuit is configured to store a temporary' repair signature indicative of an address of the selected main memory element.
3. The apparatus of claim 1, further comprising: a plurality of respective RMA circuits each communicatively coupled with a respective different reserve memory' element, wherein each RMA circuit is configured to store a respective different temporary repair signature indicative of an address of a different respective selected main memory element.
4. The apparatus of any one of claims 1 to 3, wherein: the RMA circuit is configured to: store a temporary' repair signature that identifies the main memory' element to be temporarily swapped with the reserve memory element; and receive a test control signal (TCS), and upon assertion of the TCS output the temporary repair signature to cause the die to temporarily swap the memory address of the selected main memory element with the address of the reserve memory element; and the controller of the die is configured to test the reserve memory' element.
5. The apparatus of claim 4, wherein the RMA circuit further comprises a multiplexer configured to: receive the stored temporary' repair signature and receive a repair signature from a register; receive the TCS; and select between transmitting the stored temporary’ repair signature and transmitting the repair signature based on the received TCS.
6. The apparatus of claim 5, wherein: the RMA circuit further comprises an AND gate configured to: receive an expose reserve elements (ERE) signal, indicative when asserted that a test pattern controller is initiating a memory test utilizing the reserve memory element, the test pattern controller being either internal to or external to the die; receive an inverted repair enable signal (RES) from the register, that when asserted is indicative that a repair has not been performed utilizing the reserve memory element; and generate the test control signal based on an AND operation of the ERE signal and the inverted RES; and the assertion of the ERE and the assertion of the inverted RES result in the multiplexer selecting for the temporary repair signature for testing of the reserve memory element.
7. The apparatus of any previous claim, wherein each main memory element of the plurality' comprises either a row of memory cells or a column of memory cells.
8. The apparatus of any previous claim, wherein the temporary swap of the reserve memory' element and the selected main memory element comprises sending to a memory address router of the die an instruction to assign the memory' address of the selected main memory' element to the reserve memory element while avoiding triggering a fuse event in a long-term, programmable, updateable memory of the die that would otherwrse make the memory swap permanent.
9. The apparatus of any previous claim, wherein: the controller is configured to: provide a golden test pattern suitable for testing of the memory array; write a first test pattern to the memory array when the reserve memory element is in a state of being not addressable; and write a second test pattern to the memory' array when the reserve memory element is in a state of being addressable: and a resulting logical test pattern for wnting to the memory array is the golden test pattern that is written to memory' addresses that include both the reserv e memory element and the plurality of main memory' elements.
10. The apparatus of claim 9, wherein the golden test pattern is one of a checkerboard pattern and an inverse checkerboard pattern.
11. An apparatus comprising at least one die, the at least one die comprising: a memory' array comprising: a plurality of main memory' elements each comprising a group of memory' cells that are, by default, live memory cells at initial manufacture; and at least one reserve memory element comprising another group of memory cells substantially similar in structure to a main memory element of the plurality, and suitable as a memoiy replacement for the main memory element of the plurality7; and a built-in self-repair (BISR) module comprising: a controller configured to determine test patterns for the memory array and to detect memory element fault information for the memory array; and a reserve-memory access (RMA) circuit configured to select between two alternative modes of test operations: a main-element test mode, wherein the reserve memory element is in a state of not being addressable for testing by the controller; and a reserve-element test mode, wherein the reserve memoiy7 element is in a state of being addressable for testing by the controller.
12. The apparatus of claim 11. wherein the BISR module further comprises: a built-in repair analysis (BIRA) engine configured to collect the memory element fault information and to generate one or more repair signatures based on the fault information; and a long-term, programmable, updateable memory7 (LTPUM) configured to maintain longterm, permanent storage of the generated repair signatures, and configured to communicate the repair signatures to a memory address router of the die.
13. The apparatus of claim 11 or 12, wherein the BISR module is configured to maintain a stored indication of a faulty7 reserve memory element, wherein the faulty7 reserve memory element is not employed for repairs.
14. The apparatus of any one of claims 11 to 13, wherein: the RMA circuit comprises a stress-test register and a multiplexer (MUX); the stress-test register is configured to store a temporary' repair signature indicative of the main memory element of the plurality for swapping in the reserve memory element; and the MUX is configured to selectively transmit, to a memory address router of the die, the temporary repair signature or a repair signature for the die.
15. The apparatus of claim 14, wherein the RMA circuit further comprises an AND gate configured to: receive two control signals; and output, based on the two control signals, a test control signal to control whether the MUX transmits the temporary' repair signature or the repair signature.
16. The apparatus of claim 15, wherein: the two control signals comprise a first control signal from a test device that is external to the die and a second control signal that is generated internally by the die; the first control signal determines a factory' controlled die testing process; and the second control signal is indicative that the reserve memory element either has already’ been swapped for a main memory element or that the reserve memory element has not been swapped for the main memory' element.
17. The apparatus of any one of claims 11 to 16. wherein: the controller is configured to: provide a predetermined golden test pattern suitable for testing the memory' array including both the plurality' of main memory' elements and the reserve memory element; write a first test pattern to the main memory' array based on the RMA circuit selecting the main-element test mode; and write a second test pattern to the main memory array based on the RMA circuit selecting the reserve-element test mode; and a resulting test pattern written to the memory array is the predetermined golden test pattern, which is written to memory addresses that include both the reserve memory’ element and the plurality of main memory elements.
18. A method comprising: activating main memory elements of a memory array and at least one reserve memory' element of the memory7 array, the at least one reserve memory7 element comprising a group of memory cells that are similar in structure to at least one main memory element of the main memoryelements and suitable as a memory7 replacement for the at least one main memory7 element; writing, to the main memory elements and the at least one reserve memory element, a golden test pattern to result in a stored test pattern in the memory7 array; and determining a faulty memory7 element within the memory array by comparing the stored test pattern with the golden test pattern.
19. The method of claim 18, wherein: the activating and the writing comprises: enabling a reserve memory element of the at least one reserve memory element to form a first live memory array with the reserve memory element enabled and a specified main memory7 element of the at least one main memory element disabled; writing a first test pattern to the first live memory7 array; disabling the reserve memory element and enabling the specified main memory7 element to form a second live memory array; and writing a second test pattern to the second live memory array; the first test pattern is written prior to the second test pattern; the writing of the first test pattern and the writing of the second test pattern logically combine to form the golden test pattern; and the golden test pattern comprises a predetermined pattern for memory testing.
20. The method of claim 19, wherein the first test pattern and the second test pattern are different test patterns.
PCT/US2024/024629 2024-04-15 2024-04-15 Early-life failure detection in reserve memory Pending WO2025221237A1 (en)

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Citations (2)

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Publication number Priority date Publication date Assignee Title
US20020136066A1 (en) * 2001-01-22 2002-09-26 Huang Johnnie A. Built-in self-repair wrapper methodology, design flow and design architecture
US20180174665A1 (en) * 2016-12-20 2018-06-21 Ampere Computing Llc Method to dynamically inject errors in a repairable memory on silicon and a method to validate built-in-self-repair logic

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020136066A1 (en) * 2001-01-22 2002-09-26 Huang Johnnie A. Built-in self-repair wrapper methodology, design flow and design architecture
US20180174665A1 (en) * 2016-12-20 2018-06-21 Ampere Computing Llc Method to dynamically inject errors in a repairable memory on silicon and a method to validate built-in-self-repair logic

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