WO2025216970A1

WO2025216970A1 - Dielectric etch with reduced distortion

Info

Publication number: WO2025216970A1
Application number: PCT/US2025/022957
Authority: WO
Inventors: William Thie; Taeseung Kim; Neil Macaraeg MACKIE
Original assignee: Lam Research Corp
Current assignee: Lam Research Corp
Priority date: 2024-04-10
Filing date: 2025-04-03
Publication date: 2025-10-16
Anticipated expiration: 2026-10-10

Abstract

A method for etching features in a stack is provided. A plurality of cycles is provided wherein each cycle comprises providing a first etch, comprising flowing a first etch gas comprising a first etchant and a metal containing passivant, forming the first etch gas into a first plasma, and exposing the stack to the first plasma to simultaneously etch features into the stack and deposit electrically conductive metal containing passivation on sidewalls of the features, and providing a second etch, comprising flowing a second etch gas comprising a second etchant, forming the second etch gas into a second plasma, and exposing the stack to the second plasma to simultaneously etch features into the stack and remove at least some of the electrically conductive metal containing passivation on sidewalls of the features.

Description

DIELECTRIC ETCH WITH REDUCED DISTORTION

CROSS-REFERENCE TO RELATED APPLICATION

[0001] This application claims the benefit of priority of U.S. Application No. 63/632,163, filed April 10, 2024, which is incorporated herein by reference for all purposes.

BACKGROUND

[0002] The background description provided here is for the purpose of generally presenting the context of the disclosure. Information described in this background section, as well as aspects of the description that may not otherwise qualify as prior art at the time of filing, are neither expressly nor impliedly admitted as prior art against the present disclosure.

[0003] The disclosure relates to methods of forming semiconductor devices on a semiconductor wafer. More specifically, the disclosure relates to the selective etching features in a stack with respect to a mask, such as a hardmask.

[0004] The smallest feature dimensions of semiconductor devices are constantly shrinking to follow Moore’s law. In the formation of features with small widths and high aspect ratios are etched into one or more silicon containing layers. Photoresist, amorphous carbon, or another mask material may be used as a mask. Improved etch selectivity allows for a thinner mask, resulting in improved resolution.

[0005] Example contexts where etch processes may occur include, but are not limited to, memory applications. As the semiconductor industry advances and device dimensions become smaller, such features become increasingly harder to etch in a uniform manner, especially for high aspect ratio features having narrow widths and/or deep depths. Conventional etch processes may result in feature distortion and sidewall striation.

[0006] For 3D devices such as three dimensional “not and” devices (3D NAND) vertical height is increased to improve bit density. As a result, higher aspect ratio features are etched.

SUMMARY

[0007] To achieve the foregoing and in accordance with the purpose of the present disclosure, a method for etching features in a stack is provided. A plurality of cycles is provided wherein each cycle comprises providing a first etch, comprising flowing a first etch gas comprising a first etchant and a metal containing passivant, forming the first etch gas into a first plasma, and exposing the stack to the first plasma to simultaneously etch features into the stack and deposit electrically conductive metal containing passivation on sidewalls of the features, and providing a second etch, comprising flowing a second etch gas comprising a second etchant, forming the second etch gas into a second plasma, and exposing the stack to the second plasma to simultaneously etch features into the stack and remove at least some of the electrically conductive metal containing passivation on sidewalls of the features.

[0008] These and other features of the present disclosure will be described in more detail below in the detailed description and in conjunction with the following figures.

BRIEF DESCRIPTION OF THE DRAWINGS

[0009] The present disclosure is illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings and in which like reference numerals refer to similar elements and in which:

[0010] FIG. 1 is a high level flow chart of an embodiment.

[0011] FIGS. 2A-E are schematic cross-sectional views of structures processed according to some embodiments.

[0012] FIGS. 3A-I are schematic cross-sectional views of structures processed according to different experiments.

[0013] FIGS. 4A-C are schematic cross-sectional views of structures processed according to different experiments.

[0014] FIGS. 5A-C are schematic cross-sectional views of structures processed according to different experiments.

[0015] FIG. 6 is a schematic view of an etch chamber that may be used in an embodiment. [0016] FIG. 7 is a schematic view of a computer system that may be used in practicing an embodiment.

DETAILED DESCRIPTION OF THE EXEMPLARY EMBODIMENTS

[0017] The present disclosure will now be described in detail with reference to a few exemplary embodiments thereof as illustrated in the accompanying drawings. In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present disclosure. It will be apparent, however, to one skilled in the art, that the present disclosure may be practiced without some or all of these specific details. In other instances, well-known process steps and/or structures have not been described in detail in order to not unnecessarily obscure the present disclosure.

[0018] In the formation of semiconductor devices, a stack with one or more dielectric layers may be etched. In some embodiments, the stack comprises one or more silicon containing layers, such as one or more layers of silicon carbide (SiC), silicon nitride (SiN), silicon oxynitride (SiON), and silicon oxide (SiC>2), under a mask of a material, such as amorphous carbon, and photoresist. As the aspect ratios increase, conventional processes suffer from multiple issues, including the limited capability to control CDs, mask profile, mask morphology, and local distortions due to charging effects. Depending on the application, such issues can sometimes be mitigated. However, this usually leads to tradeoffs or compromises in the etch profiles, throughput, and uniformity.

[0019] The features etched into a stack may be cylinders, trenches, slits, U-shapes, or other recessed features. The aspect ratio of such a feature is defined as the lateral critical dimension divided by the depth. As the aspect ratio of such features continues to increase, several issues arise including (1) insufficient mask selectivity, (2) etch resolution, (3) twisting of the features, (4) non-circularity of the features, (5) aspect-ratio dependent etch rate, (6) bowing etch profile, (7) feature distortion, (8) side edge striation or roughness, and (9) low etch rate.

[0020] Insufficient mask selectivity is problematic when the etch process removes an excessive amount of the mask, so that no mask remains at the end of the process, or when the amount of mask remaining is insufficient to properly transfer the pattern from the mask to the stack. One common result of insufficient mask selectivity is the degradation of the feature profile near the top of the recessed features. In order to compensate for insufficient mask selectivity, a thicker mask may be formed. However, a thicker mask results in lower mask fidelity due to mask open limitations and an overall higher aspect ratio, which compounds issues during the etching of both mask and underlayer materials.

[0021] Twisting refers to random deviations between the intended bottom locations of the features and the actual final bottom locations of the features (e.g., with the final location of a feature corresponding to the position of the bottom of the feature after the feature is etched). For instance, in some cases, it is intended that cylindrical features are etched in a regular array. When some or all features randomly deviate at the bottom away from this array, they are understood to have twisted from their ideal trajectory as defined from the initial lithography and mask starting point.

[0022] Non-circularity of the features refers to deviations of the bottom hole shape away from a circular hole shape. This issue is relevant when etching circular features such as cylinders, where it is desired that the bottoms of the recessed features are circular. When the bottom hole shape deviates away from a circular shape, it often forms a shape closer to an ellipse, triangle, or irregular polygon. In many cases, these non-circular shapes are not desirable as they deviate from the intended structural design.

[0023] Aspect-ratio-dependent etch rate refers to an issue where the etch rate slows down as the aspect ratio of the features increases. In other words, as the features are etched further into the stack, the etching process slows down. This issue is problematic because it can lead to low throughput and associated high processing costs.

[0024] Bowing etch profile refers to the tendency for the features to etch laterally in the stack such that the final profile bows outwards excessively somewhere along the depth of the features. In other words, the actual maximum critical dimension of the features exceeds the desired maximum critical dimension of the features, which can compromise the integrity of the structures being formed or limit the electrical performance of the final devices.

[0025] In a 3D feature, distortion can occur in multiple planes. Distortion can occur in the x- y plane, which can be called a kink or dislocation, or can occur in the z plane, which can be called a twist. Distortions in any of these planes may cause interference with adjacent features. [0026] Striation or edge roughness is when the sides of the feature are jagged instead of smooth.

[0027] Low etch rate refers to an etch rate that is slower than desired for a particular application. A low etch rate is problematic because it leads to long etch times, reduced throughput, and high processing costs.

[0028] Unfortunately, techniques that improve some of these issues, such as insufficient mask selectivity, often make other issues worse. As such, these issues are balanced against one another when designing an etching operation. For example, conventional commercially practiced dielectric etch processes often result in substantial bowing. Previously, such tradeoffs have been difficult to avoid.

[0029] In an anisotropic etch, a highly directional ion energy results in an etch front that has a significantly different chemical and energy environment than the sidewalls resulting in vertical etch and byproduct removal simultaneously with protection and passivation of the sidewall preventing isotropic etch. For example, the etch front etch rate can be over -300 times higher than the sidewall etch rate. Some embodiments modify the sidewalls by providing an electrically conductive species.

[0030] Some embodiments provide an etch of a stack comprising one or more silicon containing layers by simultaneously etching the stack and providing an electrically conductive metal containing sidewall passivation. In some embodiments, the stack may comprise one or more of silicon nitride, silicon carbide, silicon carbon nitride (SiCN), silicon oxynitride, and silicon oxide.

[0031] In order to facilitate understanding, FIG. 1 is a high level flow chart of a process used in some embodiments. A stack is provided (step 104) into an etch or plasma process chamber. In some embodiments, the stack comprises a stack of one or more silicon containing layers. In some embodiments, the one or more of silicon containing layers may comprise silicon carbide, silicon nitride, silicon oxynitride, and silicon oxide. In some embodiments, the silicon oxide, silicon carbide, and silicon nitride are dielectric layers. In some embodiments, the stack further comprises a mask. The mask may be amorphous carbon, photoresist, or another mask material. FIG. 2A is a schematic cross-sectional view of a stack 204 that may be etched in some embodiments. In some embodiments, the stack 204 comprises a substrate 208 under a plurality of bilayers 212 disposed below a patterned mask 216. In some embodiments, one or more layers may be disposed between the substrate 208 and the plurality of bilayers 212 and/or the plurality of bilayers 212 and the patterned mask 216. In some embodiments, each bilayer 212 comprises a silicon oxide layer 224 and a silicon nitride layer 228. In some embodiments, trilayers or more may be etched.

[0032] The stack is etched in the etch chamber. In order to etch the stack, a first etch gas comprising a first etchant and metal containing passivant is provided (step 108). In some embodiments, the first etchant is a halogen containing component. In some embodiments, the halogen containing component comprises at least one of a hydrofluorocarbon (C_xH_yF_z), such as fluoromethane (CH3F), difluoromethane (CH2F2), and fluoroform (CHF3), hydrogen bromide (HBr), hydrogen fluoride (HF), hydrogen chloride (HQ), hydrogen iodide (HI), boron trichloride (BCI3), chlorine (CI2), iodomethane (CH3I), bromomethane (CHiBr), chloromethane (CH3C1), nitrogen trifluoride (NF3), phosphorus trifluoride (PF3), sulfur hexafluoride (SFe), fluorocarbon (CxFy), where x and y are integers greater than zero, such as carbon tetrafluoride (CF4), octafluorocyclobutane (C4F8), and hexafluorobutadiene (C4F6), and halogenated fluorocarbon (CnFmX) where X is halogen of fluorine, chlorine, or bromine and where n and m are integers greater than zero. In some embodiments, the metal containing passivant contains a component containing at least one of molybdenum (Mo), rhenium (Re), tantalum (Ta), tungsten (W), or vanadium (V). In some embodiments, the metal containing passivant comprises a metal halide or metal fluoride, such as rhenium hexafluoride (ReFe), molybdenum hexafluoride (MoFe), tantalum pentafluoride (TaFs), tungsten hexafluoride (WFe), and vanadium fluoride (VF5). In some embodiments, the first etch gas further comprises an inert diluent. In some embodiments, the inert diluent is one or more noble gases, such as helium (He), Neon (Ne), argon (Ar), Krypton (Kr), and Xenon (Xe). In some embodiments, the etch gas comprises C4F6, CH2F2, oxygen (O2), carbonyl sulfide (COS), octofluoropropane (CsFs), and MoFe. [0033] The first etch gas is formed into a first plasma (step 112). In some embodiments, an excitation power is provided to transform the etch gas into the first plasma. The excitation power may be provided at various frequencies. In various embodiments, the excitation power is provided at frequencies of at least one of 13.56 megahertz (MHz), 60 MHz, 27 MHz, 2 MHz, 1 MHz, and 400 kilohertz (kHz). The excitation power may be sinusoidal (radio frequency (RF)) or non-sinusoidal.

[0034] The first plasma is used to etch the stack to form etch features and provide an electrically conductive metal passivation of the sidewalls of the etch features (step 116). The etchant in the plasma etches the etch layer to etch the features into the etch layer. The metal passivant forms an electrically conductive metal passivation layer on the sidewalls of the etch features. As a result, the first plasma simultaneously etches the etch layer and forms an electrically conductive metal passivation layer. In some embodiments, a bias is provided to provide a more directional etch.

[0035] FIG. 2B is a schematic cross-sectional view of the stack 204 after the stack 204 has been partially etched forming features 240. Part of the mask 216 has been etched away. During the partial etch, the patterned mask 216 is partially etched and reshaped. In the example shown in FIG. 2B, the patterned mask 216 has sidewall deposition, so that the patterned mask 216 becomes necked forming a narrow portion. The neck 241 causes the features 240 to be tapered. In addition, the first etch deposits an electrically conductive metal containing sidewall passivation 242 on the sidewalls of the features 240.

[0036] Optional processing (step 136) may be provided in some embodiments. In some embodiments, a neck removal or neck enlargement process is provided to remove the neck 241 formed in the mask. In some embodiments, the neck removal process comprises forming a plasma from a neck removal gas. In some embodiments, the neck removal gas comprises at least one of oxygen (O2), fluorine (F2), carbon tetrafluoride (CF4), ammonia (NF3), hydrogen fluoride (HF), sulfur hexafluoride (SFe), chlorine (CI2), phosphorus trifluoride (PF3), bromine (Br2), and iodine (I2). Oxygen may be used to enlarge the neck by laterally removing carbon containing polymer. FIG. 2C is a schematic cross-sectional view of a stack 204 after the neck 241 (shown in FIG. 2B) is removed by the neck removal process. In some embodiments, a pressure of greater than 15 millitorr (mTorr) is provided to facilitate neck enlargement.

[0037] At least some of the electrically conductive metal containing sidewall passivation layer is removed. A second etch gas comprising a second etchant is provided (step 120). In some embodiments, the second etchant is a halogen containing component. In some embodiments, the halogen containing component comprises at least one of a hydrofluorocarbon (C_xH_yF_z), such as fluoromethane (CH3F), difluoromethane (CH2F2), and fluoroform (CHF3), a fluorocarbon (C_xFy), such as carbon tetrafluoride (CF4), octafluorocyclobutane (C4F8), and hexafluorobutadiene (C4F6), hydrogen bromide (HBr), hydrogen fluoride (HF), hydrogen chloride (HC1), hydrogen iodide (Hl), boron trichloride (BCI3), octofluoropropane (C3F8), and chlorine (CI2), iodomethane (CH3I), bromomethane (CHsBr), chloromethane (CH3C1), fluorocarbon (CxFy), where x and y are integers greater than zero, and halogenated fluorocarbon (CnFmX) where X is halogen of fluorine, chlorine, or bromine and where n and m are integers greater than zero. In some embodiments, the second etch gas further comprises an inert diluent. In some embodiments, the inert diluent is one or more noble gases, such as helium (He), Neon (Ne), argon (Ar), Krypton (Kr), and Xenon (Xe). In some embodiments, the etch gas comprises C4F6, CH2F2, O2, and COS. In some embodiments, the second etch gas is free of metal containing components.

[0038] The second etch gas is formed into a first plasma (step 124). In some embodiments, excitation power is provided to transform the etch gas into the first plasma. The excitation power may be provided at various frequencies. In various embodiments, the excitation power is provided at frequencies of at least one of 13.56 megahertz (MHz), 60 MHz, 27 MHz, 2 MHz, 1 MHz, and 400 kilohertz (kHz). The excitation power may be sinusoidal (radio frequency (RF)) or non-sinusoidal.

[0039] The second plasma is used to remove at least some of the electrically conductive metal containing sidewall passivation 242. The second plasma may further etch the features in the stack (step 128). As a result, the second plasma may simultaneously remove some of the electrically conductive metal containing sidewall passivation 242 and etch features in the stack. FIG. 2D is a schematic cross-sectional view of the stack 204 after the electrically conductive metal containing sidewall passivation 242 (shown in FIG. 2C) has been removed. The features 240 are further etched and the taper of the features 240 is reduced. Some embodiments may reduce the taper without further etching the etch front.

[0040] The cycle of providing the first etch and the second etch is repeated at least once (step 132). In some embodiments, the cycle providing the first etch and the second etch is provided for at least 2 cycles. In some embodiments, the cycle providing the first etch and the second etch is provided in the range of 2 to 10,000 cycles. In some embodiments, the cycle providing the first etch and the second etch is provided for at least 3 cycles. In some embodiments, the cycle providing the first etch and the second etch is provided for at least 10 cycles.

[0041] FIG. 2E is a schematic cross-sectional view of a stack 204 after the first etch and the second etch are repeated for a plurality of cycles. The features 240 have been etched to contacts 232. The features 240 have a reduced taper and reduced striation and distortion.

[0042] It has been found that deep high aspect ratio etching of contact holes or slits is subject to distortion. Experiments were performed to compare an etch without a metal passivation, with an etch using a tungsten passivation, and an etch using a molybdenum passivation. In order to facilitate understanding, FIG. 3A shows top schematic views of parts of a mask 304 used in some embodiments where an etch is provided without a metal containing passivant, where the mask 304 defines a plurality of contact holes 308. In this example, the contact holes 308 are substantially circular. FIG. 3B shows a cross-sectional schematic view from the top of parts of the stack 312 at a depth showing maximum bowing of the contact holes 308. The contact holes 308 are substantially circular. FIG. 3C shows a cross-sectional schematic view from the top of parts of the stack 312 at an etch front of the contact holes 308. The contact holes 308 have an almost linear etch front. The almost linear etch front of the contact holes 308 is caused by a distortion. The greater the distortion of the contact holes 308 the greater the percentage of device failure.

[0043] FIG. 3D shows top schematic views of parts of a mask 324 used in some embodiments, where the metal passivant is WFe and where the mask 324 defines a plurality of contact holes 328. In this example, the contact holes 328 are substantially circular. FIG. 3E shows a cross-sectional schematic view from the top of parts of the stack 332 at a depth showing maximum bowing of the contact holes 328. The contact holes 328 are substantially circular. FIG. 3F shows a cross-sectional schematic view from the top of parts of the stack 332 at an etch front of the contact holes 328. A view in a silicon oxide region 334 shows cross-sectional views of the contact holes 328 in a silicon oxide layer at the etch front. A view in a silicon nitride region 336 shows cross-sectional views of the contact holes 328 in a silicon nitride layer at the etch front. The contact holes 328 at the etch front in the silicon oxide region 334 are more linear than circular but are more circular than the contact holes formed without any metal passivation. The contact holes 328 at the etch front in the silicon nitride region 336 are more circular but have significant striation as evidenced by the jagged border of the contact holes. In some embodiments, the striation is caused by tungsten islands deposited on the sidewall and etch front that may create micro-masking during etch. [0044] FIG. 3G shows top schematic views of parts of a mask 344 used in some embodiments, where the metal passivant is MoFe and where the mask 344 defines a plurality of contact holes 348. In this example, the contact holes 348 are substantially circular. FIG. 3H shows a cross-sectional schematic view from the top of parts of the stack 352 at a depth showing the maximum bowing of the contact holes 348. The contact holes 348 are substantially circular. FIG. 31 shows a cross-sectional schematic view from the top of parts of the stack 352 at an etch front of the contact holes 348. A view in a silicon oxide region 354 shows cross-sectional views of the contact holes 348 in a silicon oxide layer. A view in a silicon nitride region 356 shows cross-sectional views of the contact holes 348 in a silicon nitride layer. The contact holes 348 at the etch front in the silicon oxide region 354 are more circular than linear and in addition, have striations. The contact holes 348 at the etch front in the silicon nitride region 356 are more circular and in addition have reduced striations. In some embodiments, molybdenum is able to deposit about equally on both silicon oxide and silicon nitride allowing for a reduced striation compared to using tungsten, because tungsten does not deposit on silicon oxide as much as on silicon nitride.

[0045] In some embodiments, the electrically conductive metal passivation layer is able to conduct electricity and more uniformly distribute charge. The etch process may cause a charge build up at the etch front. Such a charge build up causes changes in the trajectories of ions that result in distortions. For example, a charge buildup may cause ions directed to the edge front at the bottoms of features to be deflected, causing the ions to instead be deflected into the sidewalls of the features resulting in the sidewalls of the features to be etched. The etching of the sidewalls results in feature distortion or striation or roughening of the sidewalls. In addition, the electrically conductive metal passivation layer may be more etch resistant and may help reduce bowing. In addition, it has been found that providing both the etchant and the metal containing passivant in the etch gas provides a more robust process that allows for an optimization that helps reduce distortion. In some embodiments, some of the metal passivation layer may be deposited on the etch front and may also cause necking and tapering. Providing an etch step that removes at least some of the electrically conductive metal passivation layer reduces necking, wall striations, micromasking, and tapering.

[0046] Experiments were performed to show how using an electrically conductive metal passivation reduces kinks that are formed when metal passivation is not used. In order to facilitate understanding, FIG. 4A is a top view of a patterned mask 404 with a sparse contact pattern region 408, a dense contact pattern region 412, and a slit 416. FIG. 4B is a cross- sectional view part of a stack 424 that has been etched with a process that does not deposit a conductive metal containing sidewall passivation. The slit 436 has a kink 438 and a plurality of mouse bites 439. The kink 438 occurs near a transition from the sparse contact pattern region 408 and the dense contact pattern region 412. The dense contact pattern region 412 would have a different electric field than the sparse contact pattern region 408 because there is no electrically conductive metal containing sidewall that can be used to discharge electrostatic build up at the etch front. In some embodiments, the mouse bites may be caused by localized electrostatic charge buildup in the hole array that creates a localized electric field that attracts incoming etchant ions to arrive at that specific location to create the indentations or mouse bites. FIG. 4C is a cross-sectional view part of a stack 444 that has been etched with a process that deposits a conductive metal containing sidewall passivation. The slit 456 does not have a kink or mouse bites. The dense contact pattern region 412 may have the same electric field as the sparse contact pattern region 408 since the electrically conductive metal containing sidewall discharges electrostatic buildup at the etch front.

Molybdenum

[0047] In some embodiments, the metal containing passivant comprises molybdenum. In some embodiments, the metal containing passivant comprises molybdenum hexafluoride. Molybdenum is able to deposit about equally on both silicon oxide and silicon nitride allowing for reduced striation compared to using tungsten because tungsten does not preferentially deposit on silicon oxide as much as on silicon nitride. As a result, molybdenum is able to form electrically conductive metal sidewall passivation on both silicon oxide and silicon nitride and therefore is able to dissipate or distribute electrostatic charge in both silicon oxide and silicon nitride layers.

[0048] In some embodiments, during the first etch, the ratio of the flow of the metal containing passivant in the first etch gas to the total flow of the first etch gas is in the range of 0.005% to 0.25%. In some embodiments, during the first etch, the ratio of the flow of the metal containing passivant in the first etch gas to the total flow of the first etch gas is in the range of 0.05% to 0.25% by volume. For example, the total flow rate of the first etch gas may be in the range of 200 to 400 standard cubic centimeters per minute (seem) and the flow rate of the metal containing passivant may be in the range of 0.3 to 0.5 seem. The flow rate of the metal containing passivant is tuned to allow a high enough metal deposition to distribute the electrostatic charge and a low enough metal deposition to allow the electrically conductive metal containing passivation to be removed during each cycle. In some embodiments, all of the electrically conductive metal containing passivation is removed.

[0049] In some embodiments, during etching, the stack temperature is heated to a temperature in the range of 0°C to 100°C in order to reduce micromasking caused by polymer deposition that may contain metals in order to reduce striation. In addition, it has been found that a leaner etch chemistry further reduces polymer deposition and may be used to reduce wiggling. In some embodiments, an optional cleaning, polymer removal step, may be added to one or more cycles in order to remove polymer at the etch front to further reduce micromasking.

[0050] In some embodiments, a hydrogen atom is used to attach a metal containing passivant to silicon oxide or silicon nitride. In some embodiments, the hydrogen atom is supplied by CH2F2, since CH2F2 is able to provide two hydrogen atoms.

Various Embodiments

[0051] In some embodiments, the stack may be a single silicon containing layer. In some embodiments, the stack may be a plurality of silicon containing layers. For example, the stack may be a stack of alternating layers of silicon nitride and silicon oxide (ONON). In some embodiments, etch parameters such as pressure, excitation power, bias power, and temperature may be tuned to optimize other etch characteristics, such as selectivity, aspect ratio, dense versus isolation loading, profile control, CD control, and tapering. In some embodiments, the bias is adjusted in order to adjust the aspect ratio. In addition, in some embodiments, the etch parameters are more robust, allowing for a larger parameter window.

[0052] FIG. 5A is a schematic illustration of a top view of a mask 500 for etching a stack in another embodiment. At least one U-shaped mask feature 504 is patterned in the mask 500. In some embodiments, the U-shaped mask feature 504 defines an island 506. The island 506 has a pair of 90 degree inner comers 508a, b. The island 506 has a uniform width “d”, as shown.

[0053] FIG. 5B is a schematic illustration of a top view 520 of an etch front of a stack that is etched without a metal containing passivant. At least one U-shaped feature 524 has been etched into the stack defining an island 526. The island 526 has a reduced d near the 90 degree inner corners 528a, b. Without being bound by theory, it is believed that charge accumulation at the 90 degree inner comers 528a, b causes ions from the plasma to be deflected to the 90 degree inner corners 528 a, b causing the island 526 to be narrower near the 90 degree inner corners 528a, b decreasing d. Such a distortion may increase device defects. [0054] FIG. 5C is a schematic illustration of a top view 540 of an etch front of a stack that is etched with a WFe passivant. At least one U-shaped feature 544 has been etched into the stack defining an island 546. The island 546 has a uniform d that is not as reduced near the 90 degree inner corners 548a, b compared to the reduction of d caused by an etch without a metal containing passivant. Without being bound by theory, it is believed that the metal containing passivant forms an electrically conductive passivation layer on the sidewalls of the features allowing charges caused to be disbursed away from the 90 degree inner corners 548a, b so that ions from the plasma are not deflected to the 90 degree inner comers so that d is not as significantly reduced. As a result, device defects are reduced.

APPARATUS

[0055] To facilitate understanding, FIG. 6 is a schematic view of a plasma processing chamber 600 for plasma processing substrates, in an embodiment. In one or more embodiments, the plasma processing chamber 600 comprises a gas distribution plate 606 providing a gas inlet and an electrostatic chuck (ESC) 616, within a plasma processing chamber 604, enclosed by a chamber wall 650. Within the plasma processing chamber 604, the substrate 202 is positioned on top of the ESC 616 that acts as a substrate support. The ESC 616 may provide a bias from an ESC power source 648. A gas source 610 is connected to the plasma processing chamber 604 through the gas distribution plate 606. An ESC temperature controller 651 is connected to the ESC 616 and provides temperature control of the ESC 616. An excitation power source 630 provides excitation power to the ESC 616 and an upper electrode. In this embodiment, the upper electrode is the gas distribution plate 606. In a preferred embodiment, 400 kilohertz (kHz), 13.56 megahertz (MHz), 1 MHz, 2 MHz, 60 MHz, and/or optionally, 27 MHz power sources make up the excitation power source 630 and the ESC power source 648. A controller 635 is controllably connected to the excitation power source 630, the ESC power source 648, an exhaust pump 620, and the gas source 610. A high flow liner 660 is a liner within the plasma processing chamber 604, which confines gas from the gas source and has slots 662. The slots 662 maintain a controlled flow of gas to pass from the gas source 610 to the exhaust pump 620. An example of such a plasma processing chamber is the Flex® etch system manufactured by Lam Research Corporation of Fremont, CA. The process chamber can be a CCP (capacitively coupled plasma) reactor or an ICP (inductively coupled plasma) reactor. The plasma processing chamber 604 is able to provide both the first etch and the second etch so that the first etch and second etch are performed in-situ without moving the substrate 202 from the substrate support or ESC 616. [0056] FIG. 7 is a high level block diagram illustrating a computer system 700 for implementing the controller 635 used in embodiments of the present inventions. The computer system may have many physical forms ranging from an integrated circuit, a printed circuit board, and a small handheld device up to a huge supercomputer. The computer system 700 may include one or more processors 702, and further can include an electronic display device 704 (for displaying graphics, text, and other data), a main memory 706 (e.g., random access memory (RAM)), storage device 708 (e.g., hard disk drive), removable storage device 710 (e.g., optical disk drive), user interface devices 712 (e.g., keyboards, touch screens, keypads, mice or other pointing devices, etc.), and/or a communication interface 714 (e.g., wireless network interface). The communication interface 714 may allow software and/or data to be transferred between the computer system 700 and external devices via a link. The system may also include a communications infrastructure 716 (e.g., a communications bus, cross-over bar, or network) to which the aforementioned devices/modules may be connected.

[0057] Information transferred via communications interface 714 may be in the form of signals such as electronic, electromagnetic, optical, or other signals capable of being received by communications interface 714, via a communication link that carries signals and may be implemented using wire or cable, fiber optics, a phone line, a cellular phone link, a radio frequency link, and/or other communication channels. With such a communications interface, it is contemplated that the one or more processors 702 might receive information from a network or might output information to the network in the course of performing the above-described method steps. Furthermore, method embodiments may execute solely upon the processors or may execute over a network such as the Internet in conjunction with remote processors that share a portion of the processing.

[0058] The term “non-transient computer readable medium” is used generally to refer to media such as main memory, secondary memory, removable storage, and storage devices, such as hard disks, flash memory, disk drive memory, CD-ROM, and other forms of persistent memory and shall not be construed to cover transitory subject matter, such as carrier waves or signals. Examples of computer code include machine code, such as produced by a compiler, and files containing higher level code that are executed by a computer using an interpreter. Computer readable media may also be computer code transmitted by a computer data signal embodied in a carrier wave and representing a sequence of instructions that are executable by a processor. [0059] While this disclosure has been described in terms of several exemplary embodiments, there are alterations, modifications, permutations, and various substitute equivalents, which fall within the scope of this disclosure. It should also be noted that there are many alternative ways of implementing the methods and apparatuses of the present disclosure. It is therefore intended that the following appended claims be interpreted as including all such alterations, modifications, permutations, and various substitute equivalents as fall within the true spirit and scope of the present disclosure. As used herein, the phrase “A, B, or C” should be construed to mean a logical (“A OR B OR C”), using a non-exclusive logical “OR,” and should not be construed to mean ‘only one of A or B or C. Each step within a process may be an optional step and is not required. Different embodiments may have one or more steps removed or may provide steps in a different order. In addition, various embodiments may provide different steps simultaneously instead of sequentially.

Claims

CLAIMS What is claimed is:

1. A method for etching features in a stack, comprising a plurality of cycles wherein each cycle comprises: a) providing a first etch, comprising: i) flowing a first etch gas comprising a first etchant and a metal containing passivant; ii) forming the first etch gas into a first plasma; and hi) exposing the stack to the first plasma to simultaneously etch features into the stack and deposit electrically conductive metal containing passivation on sidewalls of the features; and b) providing a second etch, comprising: i) flowing a second etch gas comprising a second etchant; ii) forming the second etch gas into a second plasma; and iii) exposing the stack to the second plasma to simultaneously etch features into the stack and remove at least some of the electrically conductive metal containing passivation on sidewalls of the features.

2. The method, as recited in claim 1, wherein the first etchant and second etchant each comprise a halogen containing component.

3. The method, as recited in claim 1, wherein the metal containing passivant comprises a component containing at least one of molybdenum, rhenium, tantalum, tungsten, and vanadium.

4. The method, as recited in claim 1, wherein the metal containing passivant comprises MoFg.

5. The method, as recited in claim 1, wherein the plurality of cycles comprises at least 2 cycles.

6. The method, as recited in claim 1, wherein the stack comprises at least one silicon oxide layer and at least one silicon nitride layer.

7. The method, as recited in claim 1, wherein each cycle further comprises a neck enlargement step.

8. The method, as recited in claim 1, wherein the second etch gas is metal containing passivant free.

9. The method, as recited in claim 1, wherein the etchant comprises at least one of a fluorocarbon and a hydrofluorocarbon.

10. The method, as recited in claim 1, wherein during the first etch the etch gas has a total flow rate and the metal containing passivant has a flow rate, wherein a ratio by flow rate of the metal containing passivant to the total flow rate is in a range of 0.005% to 0.25%.

11. The method, as recited in claim 1, wherein during the first etch the etch gas further comprises a hydrogen containing component.

12. The method, as recited in claim 1, further comprising a polymer removal step.

13. The method, as recited in claim 1, wherein the second etch removes all of the electrically conductive metal containing passivation for each cycle.

14. The method, as recited in claim 1, wherein the forming the first etch gas into the first plasma comprises providing an excitation power.

15. The method, as recited in claim 1, wherein the forming the second etch gas into the second plasma comprises providing an excitation power.

16. The method, as recited in claim 1, wherein the providing the first etch and the providing the second etch are performed in-situ.