WO2025208673A1 - 显示装置 - Google Patents

显示装置

Info

Publication number
WO2025208673A1
WO2025208673A1 PCT/CN2024/089370 CN2024089370W WO2025208673A1 WO 2025208673 A1 WO2025208673 A1 WO 2025208673A1 CN 2024089370 W CN2024089370 W CN 2024089370W WO 2025208673 A1 WO2025208673 A1 WO 2025208673A1
Authority
WO
WIPO (PCT)
Prior art keywords
gate
level
transistor
control signal
output
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
PCT/CN2024/089370
Other languages
English (en)
French (fr)
Inventor
张欢喜
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Wuhan China Star Optoelectronics Semiconductor Display Technology Co Ltd
Original Assignee
Wuhan China Star Optoelectronics Semiconductor Display Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Wuhan China Star Optoelectronics Semiconductor Display Technology Co Ltd filed Critical Wuhan China Star Optoelectronics Semiconductor Display Technology Co Ltd
Priority to KR1020247025673A priority Critical patent/KR102743448B1/ko
Priority to KR1020247041061A priority patent/KR102904084B1/ko
Publication of WO2025208673A1 publication Critical patent/WO2025208673A1/zh
Pending legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0267—Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays

Definitions

  • An embodiment of the present application provides a display device comprising a display panel and a gate driver module.
  • the display panel comprises a plurality of sub-pixels, at least one of which comprises a light-emitting device, a driving transistor, a compensation transistor, and a reset transistor.
  • the driving transistor is configured to generate a driving current to drive the light-emitting device to emit light.
  • the output terminal of the reset transistor and the output terminal of the compensation transistor are electrically connected to the control terminal of the driving transistor.
  • the input terminal of the compensation transistor is electrically connected to the output terminal of the driving transistor.
  • the input terminal of the reset transistor is configured to receive a reset signal.
  • FIG. 1A and 1B are schematic structural diagrams of a display device provided in an embodiment of the present application.
  • 4A and 4B are timing diagrams corresponding to sub-pixels provided in the related art.
  • 5A and 5B are schematic structural diagrams of a first gate driving unit and a second gate driving unit provided in an embodiment of the present application;
  • FIG7 is a schematic diagram of the high-frequency and low-frequency image display principles provided by an embodiment of the present application.
  • FIG9 is a timing diagram of sub-pixels corresponding to a writing frame and a holding frame provided in an embodiment of the present application.
  • the present application provides a display device, wherein a first gate driving unit includes a plurality of cascaded first gate driving circuits, a second gate driving unit includes a plurality of cascaded second gate driving circuits, the first gate driving circuit controls the level of a first gate control signal generated according to a first frequency-divided control signal, and the second gate driving circuit controls the level of a second gate control signal generated according to a second frequency-divided control signal, the control terminals of the compensation transistors of the plurality of sub-pixels are electrically connected to the first output terminals of the multi-stage first gate driving circuit outputting the first gate control signal, and the control terminals of the reset transistors of the plurality of sub-pixels are electrically connected to the first output terminals of the multi-stage second gate driving circuit outputting the second gate control signal, so that the reset transistors and the compensation transistors are electrically connected to each other.
  • the compensation transistor and the reset transistor are no longer controlled by the gate control signal generated by the same gate driving unit, but are controlled by gate control signals generated by different gate driving units, so that the reset transistor of one sub-pixel and the compensation transistor of another sub-pixel no longer have a synchronous working state due to being controlled by the same gate control signal, but the working states of the reset transistor and the compensation transistor of different sub-pixels are independent, and then, in conjunction with the first frequency-dividing control signal and the second frequency-dividing control signal, the frequency of the second gate control signal received by the reset transistor in the same sub-pixel is the same as the frequency of the first gate control signal received by the compensation transistor, thereby improving the problem of display abnormality in some sub-pixels at corresponding frequency-dividing positions in the display panel.
  • FIG. 1A to FIG. 1B are schematic structural diagrams of a display device provided in an embodiment of the present application.
  • the present application provides a display device including a display panel DP and a gate driving module GM, wherein the gate driving module GM is electrically connected to the display panel DP.
  • the display panel DP includes a plurality of sub-pixels Spi.
  • the gate driving module GM is electrically connected to the plurality of sub-pixels Spi to cooperate with the plurality of sub-pixels Spi to enable the display panel DP to achieve a display function.
  • the display panel DP includes a plurality of scan lines
  • the gate driving module GM is electrically connected to the plurality of sub-pixels Spi through the plurality of scan lines.
  • At least one sub-pixel Spi includes a light-emitting device Di, a driving transistor Tdr, a compensation transistor Tc, and a reset transistor Tr.
  • the light emitting device Di includes a light emitting diode.
  • the light emitting device Di includes an organic light emitting diode, a sub-millimeter light emitting diode, a micro light emitting diode, etc.
  • the driving transistor Tdr and the light emitting device Di are electrically connected between a first voltage terminal Vdd and a second voltage terminal Vss.
  • the driving transistor Tdr is configured to generate a driving current to drive the light emitting device Di to emit light.
  • the input terminal of the driving transistor Tdr is electrically connected to the first voltage terminal Vdd
  • the output terminal of the driving transistor Tdr is electrically connected to the anode of the light-emitting device Di
  • the cathode of the light-emitting device Di is electrically connected to the second voltage terminal Vss
  • the voltage supplied by the first voltage terminal Vdd is greater than the voltage supplied by the second voltage terminal Vss.
  • An input terminal of the reset transistor Tr is configured to receive a reset signal transmitted by the reset line VLr, and an output terminal of the reset transistor Tr is electrically connected to a control terminal of the driving transistor Tdr.
  • the input terminal of the compensation transistor Tc is electrically connected to the output terminal of the driving transistor Tdr, and the output terminal of the compensation transistor Tc is electrically connected to the control terminal of the driving transistor Tdr.
  • the active layer of the oxide transistor includes indium gallium zinc oxide and the like.
  • the multiple scan lines include multiple first scan lines GL1 and multiple second scan lines GL2, the control ends of the compensation transistors Tc of the multiple sub-pixels Spi are electrically connected to the multiple first scan lines GL1, and the control ends of the reset transistors Tr of the multiple sub-pixels Spi are electrically connected to the multiple second scan lines GL2.
  • An input terminal of the first light emitting control transistor Te1 is electrically connected to the first voltage terminal Vdd, and an output terminal of the first light emitting control transistor Te1 is electrically connected to an input terminal of the driving transistor Tdr.
  • the multiple first sub-gate driver circuits ga1 are configured to provide gate control signals to the reset transistors Tr and compensation transistors Tc of the multiple sub-pixels Spi.
  • the multiple second sub-gate driver circuits ga2 are configured to provide gate control signals to the second initialization transistors Ti2 of the multiple sub-pixels Spi.
  • the multiple third sub-gate driver circuits ga3 are configured to provide light emission control signals to the first and second light emission control transistors Te1 and Te2 of the multiple sub-pixels Spi.
  • the data transistor Tda can be controlled by the gate control signal output by the first sub-gate driver unit gm1 or by the gate control signals output by other gate driver units.
  • the first initial transistor Ti1 can share a gate control signal provided by the same gate drive unit as the data transistor Tda, or a corresponding gate control signal can be provided by the third sub-gate drive unit gm3.
  • the gate control signal received by the control terminal of the compensation transistor Tc and the gate control signal received by the control terminal of the reset transistor Tr are generated by first sub-drive circuits at different levels.
  • the gate control signal received by the control terminal of the reset transistor Tr of the sub-pixel Spi in the nth row of the display panel DP is generated by the first sub-gate drive circuit at the n-2th level, while the gate control signal received by the control terminal of the compensation transistor Tc of the sub-pixel Spi in the nth row is generated by the first sub-gate drive circuit at the nth level.
  • the first sub-gate drive unit gm1 adopts a bilateral drive design.
  • Figures 4A and 4B are timing diagrams corresponding to the subpixel Spi provided in the related art.
  • Pscan corresponds to the gate control signal received by the control terminal of the first initial transistor Ti1 and the control terminal of the second initial transistor Ti2
  • Pscan_T2 corresponds to the gate control signal received by the control terminal of the data transistor Tda
  • Nscan_T3 corresponds to the gate control signal received by the control terminal of the compensation transistor Tc
  • Nscan_T4 corresponds to the gate control signal received by the control terminal of the reset transistor Tr
  • EM corresponds to the gate control signal received by the control terminals of the first emission control transistor Te1 and the second emission control transistor Te2.
  • the display panel DP cannot achieve zone-by-zone frequency display using the timing diagram shown in FIG4A .
  • the present application provides a display device.
  • the gate driving module GM includes a plurality of frequency-dividing control lines FL, a first gate driving unit GM1 and a second gate driving unit GM2 .
  • the plurality of frequency division control lines FL transmit a plurality of frequency division control signals, and the plurality of frequency division control signals include a first frequency division control signal NF1 and a second frequency division control signal NF2.
  • the first gate drive circuit GA1 and the second gate drive circuit GA2 both include a first output terminal O1 , which outputs a first gate control signal Nscan1 , and a second gate drive circuit GA2 outputs a second gate control signal Nscan2 .
  • the first output terminals O1 of the plurality of first gate driving circuits GA1 are electrically connected to the plurality of sub-pixels Spi through the plurality of first scan lines GL1
  • the first output terminals O1 of the plurality of second gate driving circuits GA2 are electrically connected to the plurality of sub-pixels Spi through the plurality of second scan lines GL2.
  • the control ends of the compensation transistors Tc of multiple sub-pixels Spi are electrically connected to the first output end O1 of the multi-stage first gate driving circuit GA1, and the control ends of the reset transistors Tr of multiple sub-pixels Spi are electrically connected to the first output end O1 of the multi-stage second gate driving circuit GA2, so that the reset transistor Tr and the compensation transistor Tc are no longer controlled by the gate control signal generated by the same gate driving unit, but the compensation transistor Tc and the reset transistor Tr are controlled by the gate control signals generated by different gate driving units, so that the reset transistor Tr of one sub-pixel Spi and the compensation transistor Tc of another sub-pixel Spi are no longer in a synchronized working state due to being controlled by the same gate control signal, but the working states of the reset transistors Tr and the compensation transistors Tc of different sub-pixels Spi are independent.
  • the first gate drive circuit GA1 can realize the level control of the first gate control signal Nscan1 according to the first frequency-division control signal NF1
  • the second gate drive circuit GA2 can realize the level control of the second gate control signal Nscan2 according to the second frequency-division control signal NF2
  • the first frequency-division control signal NF1 and the second frequency-division control signal NF2 can make the frequency of the second gate control signal Nscan2 received by the reset transistor Tr in the same sub-pixel Spii the same as the frequency of the first gate control signal Nscan1 received by the compensation transistor Tc, so that the conduction frequency of the reset transistor Tr and the compensation transistor Tc in the same sub-pixel Spii is the same, thereby improving the problem of abnormal display of the sub-pixel Spii in some sub-pixels Spi at the corresponding frequency-division position in the display panel DP because the gate control signal used by the compensation transistor Tc is low-frequency, while the gate control signal used by the reset transistor Tr is still high
  • the display panel DP includes a display area AA and a first non-display area DA1 and a second non-display area DA2 located on opposite sides of the display area AA.
  • a plurality of sub-pixels Spi are located in the display area AA
  • a first gate driver unit GM1 is located in the first non-display area DA1
  • a second gate driver unit GM2 is located in the second non-display area DA2.
  • control terminals of the compensation transistors Tc of the plurality of sub-pixels Spi are electrically connected to the first output terminals O1 of the multi-stage first gate drive circuit GA1
  • control terminals of the reset transistors Tr of the plurality of sub-pixels Spi are electrically connected to the first output terminals O1 of the multi-stage second gate drive circuit GA2
  • a unilateral drive design is implemented for the compensation transistors Tc of the plurality of sub-pixels Spi
  • a unilateral drive design is implemented for the reset transistors Tr of the plurality of sub-pixels Spi.
  • the multi-stage first gate drive circuit GA1 is electrically connected to the control terminals of the compensation transistors Tc of the plurality of sub-pixels Spi via a unilateral drive method
  • the multi-stage second gate drive circuit GA2 is electrically connected to the control terminals of the reset transistors Tr of the plurality of sub-pixels Spi via a unilateral drive method. This is beneficial for reducing the bezel size of the display panel DP.
  • a single gate driver circuit can be configured to simultaneously output multiple gate control signals. Accordingly, the multiple gate control signals output by the single gate driver circuit can be used to control the conduction states of different transistors in the same sub-pixel Spi.
  • the first gate driver circuit GA1 includes a second output terminal O2, and the second output terminal O2 of the first gate driver circuit GA1 outputs a third gate control signal Pscan1.
  • the control terminals of the data transistors Tda of the plurality of sub-pixels Spi are electrically connected to the second output terminals O2 of the plurality of first gate driver circuits GA1, so that the data transistors Tda of the plurality of sub-pixels Spi are controlled by the third gate control signal Pscan1 output by the plurality of first gate driver circuits GA1.
  • the second gate driver circuit GA2 includes a second output terminal O2, and the second output terminal O2 of the second gate driver circuit GA2 outputs a fourth gate control signal Pscan2.
  • the control terminals of the data transistors Tda of the plurality of sub-pixels Spi are electrically connected to the second output terminals O2 of the plurality of second gate driver circuits GA2, so that the data transistors Tda of the plurality of sub-pixels Spi are controlled by the fourth gate control signal Pscan2 output by the plurality of second gate driver circuits GA2.
  • the first gate driver circuit GA1 and the second gate driver circuit GA2 both include a second output terminal O2.
  • the second output terminal O2 of the first gate driver circuit GA1 outputs the third gate control signal Pscan1, and the second output terminal O2 of the second gate driver circuit GA2 outputs the fourth gate control signal Pscan2.
  • the control terminals of the data transistors Tda of the plurality of sub-pixels Spi are electrically connected to the second output terminals O2 of the plurality of first gate driver circuits GA1 and/or the second output terminals O2 of the plurality of second gate driver circuits GA2.
  • control end of the data transistor Tda can be electrically connected to the second output end O2 of the corresponding first gate drive circuit GA1, or can be electrically connected to the second output end O2 of the corresponding second gate drive circuit GA2, or can be electrically connected to both the second output end O2 of the corresponding first gate drive circuit GA1 and the second output end O2 of the corresponding second gate drive circuit GA2.
  • a single-sided drive design is formed in a sub-pixel Spi, when the control end of the data transistor Tda is electrically connected to the second output end O2 of the corresponding first gate drive circuit GA1 or the second output end O2 of the corresponding second gate drive circuit GA2, a single-sided drive design is formed; and in a sub-pixel Spi, when the control end of the data transistor Tda is electrically connected to both the second output end O2 of the corresponding first gate drive circuit GA1 and the second output end O2 of the corresponding second gate drive circuit GA2, a double-sided drive design is formed.
  • the second output terminals O2 of the plurality of first gate driving circuits GA1 are electrically connected to the plurality of sub-pixels Spi through the plurality of third scan lines GL3; the second output terminals O2 of the plurality of second gate driving circuits GA2 are electrically connected to the plurality of sub-pixels Spi through the plurality of third scan lines GL3.
  • Figures 5A and 5B are schematic diagrams of the structures of the first and second gate drive units provided in embodiments of the present application
  • Figures 6A and 6B are schematic diagrams of the structures of the gate drive circuits provided in embodiments of the present application.
  • the circuit structure of at least one of the first gate drive circuit GA1 and the second gate drive circuit GA2 is shown in Figures 6A and 6B.
  • O21 and O22 each represent a second output terminal
  • Cka and CKb each represent a second clock signal.
  • At least one of the first gate driving circuit GA1 and the second gate driving circuit GA2 includes a node control module 10 , a first frequency division control module 20 and a first output module 30 .
  • the node control module 10 is electrically connected to the first node K1 of the gate driving circuit at this stage.
  • the node control module 10 is configured to control the signal of the first node K1 according to the corresponding start signal STV and the first clock signal XCK.
  • the first-stage first gate driver circuit GA1(1) among the plurality of first gate driver circuits GA1 uses the first start signal stv1 as the start signal STV, so that the first-stage first gate driver circuit GA1(1) controls the signal of the first node K1 of the first-stage first gate driver circuit GA1(1) according to the corresponding first clock signal XCK and the first start signal stv1.
  • the first-stage second gate driver circuit GA2(1) among the plurality of second gate driver circuits GA2 uses the second start signal stv2 as the start signal STV, so that the first-stage second gate driver circuit GA2(1) controls the signal of the first node K1 of the first-stage second gate driver circuit GA2(1) according to the corresponding first clock signal XCK and the second start signal stv2.
  • the M-th first gate drive circuit GA1(M) among the multiple first gate drive circuits GA1 uses the M-A-th first gate control signal Nscan1(M-A) output by the M-A-th first gate drive circuit GA1(M-A) as the start signal STV, so that the M-th first gate drive circuit GA1(M) controls the signal of the first node K1 of the M-th first gate drive circuit GA1(M) according to the corresponding first clock signal XCK and the M-A-th first gate control signal Nscan1(M-A) output by the M-A-th first gate drive circuit GA1(M-A).
  • the N-th-stage second gate drive circuit GA2(N) among the plurality of second gate drive circuits GA2 uses the N-B-th-stage second gate control signal Nscan2(N-B) output by the N-B-th-stage second gate drive circuit GA2(N-B) as the start signal STV, so that the N-th-stage second gate drive circuit GA2(N) controls the signal at the first node K1 of the N-th-stage second gate drive circuit GA2 according to the corresponding first clock signal XCK and the N-B-th-stage second gate control signal Nscan2(N-B) output by the N-B-th-stage second gate drive circuit GA2(N-B).
  • the first-stage first gate control signal Nscan1(1) outputted from the first output terminal O1 of the first-stage first gate driver circuit GA1(1) can be used as the start signal STV by the second-stage first gate driver circuit GA1.
  • a cascade arrangement of multiple second gate driver circuits GA2 can also be obtained.
  • the first M-stage gate drive circuit in the multi-stage gate drive circuit can be called a virtual gate drive circuit (the gate drive circuit shown in the dotted box included in the gate drive unit in Figures 1A to 1B) to provide a corresponding start signal STV to the gate drive circuit cascaded thereafter.
  • Figures 6A and 6B illustrate the structure of the node control module 10 by taking one of the p-th level first gate drive circuit GA1(p) and the p-th level second gate drive circuit GA2(p) as an example.
  • O1(p-1) represents the first output terminal of the p-1-th level first gate drive circuit GA1(p-1).
  • Figures 6A and 6B correspond to representing the p-th level second gate drive circuit GA2(p)
  • O1(p-1) represents the first output terminal of the p-1-th level second gate drive circuit GA2(p-1).
  • p p ⁇ 1.
  • O1(p-1) corresponds to the first start signal stv1 or the second start signal stv2.
  • the node control module 10 includes a first transistor T1 , a second transistor T2 , and a third transistor T3 .
  • the control end of the second transistor T2 is electrically connected to the first control end of the first transistor T1 , the input end of the second transistor T2 is electrically connected to the second power supply end PVGH, and the output end of the second transistor T2 is electrically connected to the output end of the first transistor T1 .
  • the control end of the third transistor T3 is configured to receive the corresponding first clock signal XCK, the input end of the third transistor T3 is electrically connected to the output end of the first transistor T1 , and the output end of the third transistor T3 is electrically connected to the first node K1 .
  • the node control module 10 is also electrically connected to the third node K3 of the gate drive circuit at this level, and the node control module 10 is configured to control the electrical connection between the second power terminal PVGH or the third power terminal NVGL and the first node K1 according to the potential of the third node K3.
  • the node control module 10 includes a fourth transistor T4, a fifth transistor T5, and a sixth transistor T6.
  • the first control terminal and the second control terminal of the fourth transistor T4 are configured to receive a corresponding first clock signal XCK, and the output terminal of the fourth transistor T4 is electrically connected to the first node K1.
  • the control terminal of the fifth transistor T5 and the first control terminal and the second control terminal of the sixth transistor T6 are electrically connected to the third node K3.
  • the input terminal of the fifth transistor T5 is electrically connected to the second power supply terminal PVGH
  • the output terminal of the fifth transistor T5 is electrically connected to the input terminal of the fourth transistor T4
  • the input terminal of the sixth transistor T6 is electrically connected to the third power supply terminal NVGL
  • the output terminal of the sixth transistor T6 is electrically connected to the first node K1.
  • the node control module 10 is configured to control signal transmission between the first power terminal PVGL or the second power terminal PVGH and the third node K3 according to the signal of the first node K1 .
  • the node control module 10 further includes a seventh transistor T7 and an eighth transistor T8.
  • the first control terminal and the second control terminal of the seventh transistor T7 are electrically connected to the first node K1
  • the input terminal of the seventh transistor T7 is electrically connected to the first power supply terminal PVGL
  • the output terminal of the seventh transistor T7 is electrically connected to the third node K3
  • the control terminal of the eighth transistor T8 is electrically connected to the first node K1
  • the input terminal of the eighth transistor T8 is electrically connected to the second power supply terminal PVGH
  • the output terminal of the eighth transistor T8 is electrically connected to the third node K3.
  • the first frequency division control module 20 is electrically connected to the first node K1, the second node K2, and the third node K3 of the gate drive circuit at this stage.
  • the first frequency division control module 20 is configured to control signal transmission between the first node K1 and the second node K2 based on the signal of the third node K3 and the corresponding frequency division control signal.
  • the first frequency-dividing control module 20 includes a first frequency-dividing transistor Tf1 , a second frequency-dividing transistor Tf2 , and a first capacitor C1 .
  • the control end of the first frequency-dividing transistor Tf1 is electrically connected to the third node K3 of the gate drive circuit at this level, and the input end of the first frequency-dividing transistor Tf1 is configured to receive the corresponding frequency-dividing control signal (that is, the input end of the first frequency-dividing transistor Tf1 in the first gate drive circuit GA1 is configured to receive the first frequency-dividing control signal NF1, and the input end of the first frequency-dividing transistor Tf1 in the second gate drive circuit GA2 is configured to receive the second frequency-dividing control signal NF2).
  • the control end of the second frequency dividing transistor Tf2 is electrically connected to the output end of the first frequency dividing transistor Tf1 , the input end of the second frequency dividing transistor Tf2 is electrically connected to the first node K1 , and the output end of the second frequency dividing transistor Tf2 is electrically connected to the second node K2 .
  • a first end of the first capacitor C1 is electrically connected to the control end of the second frequency-dividing transistor Tf2 , and a second end of the first capacitor C1 is electrically connected to the second node K2 .
  • the first output module 30 is electrically connected to the first node K1, the second node K2 and the first output end O1.
  • the first output module 30 is configured to control the gate control signal outputted by the first output end O1 according to the signals of the first node K1 and the second node K2.
  • the first output module 30 includes a first output transistor To1 and a second output transistor To2 .
  • the first control terminal and the second control terminal of the first output transistor To1 are electrically connected to the first node K1 , and the input terminal of the first output transistor To1 is electrically connected to the third power terminal NVGL.
  • the control end of the second output transistor To2 is electrically connected to the second node K2, the input end of the second output transistor To2 is electrically connected to the fourth power supply end NVGH, and the output end of the second output transistor To2 and the output end of the first output transistor To1 are electrically connected to the first output end O1 of the gate drive circuit of this stage.
  • a first frequency-dividing control signal NF1 may be provided for each first gate drive circuit GA1 to implement level control of the first gate control signal Nscan1 output by each first gate drive circuit GA1.
  • a second frequency-dividing control signal NF2 may be provided for each second gate drive circuit GA2 to implement level control of the second gate control signal Nscan2 output by each second gate drive circuit GA2.
  • the first frequency division control modules 20 of multiple cascaded first gate drive circuits GA1 can share the same frequency division control signal to implement level control of multiple first gate control signals Nscan1.
  • the first frequency division control modules 20 of multiple cascaded second gate drive circuits GA2 can share the same frequency division control signal to implement level control of multiple second gate control signals Nscan2.
  • the frequency division control signal applied by the first frequency division control module 20 for controlling the plurality of cascaded second gate drive circuits GA2 is different from the frequency division control signal applied by the first frequency division control module 20 for controlling the plurality of cascaded first gate drive circuits GA1.
  • the multiple frequency-division control lines FL include a first frequency-division control line FL1 and a second frequency-division control line FL2.
  • the first frequency-division control line FL1 transmits a first frequency-division control signal NF1
  • the second frequency-division control line FL2 transmits a second frequency-division control signal NF2.
  • a first frequency-division control module 20 of the multi-stage first gate drive circuit GA1 is electrically connected to the first frequency-division control line FL1, while a first frequency-division control module 20 of the multi-stage second gate drive circuit GA2 is electrically connected to the second frequency-division control line FL2. This reduces the number of frequency-division control signals used in the display device while enabling independent operation of the compensation transistors Tc and reset transistors Tr of the multiple sub-pixels Spi.
  • At least one gate drive circuit further includes a first control module 40.
  • the first control module 40 is electrically connected to the third node K3 of the gate drive circuit at the current stage and the second node K2 of the gate drive circuit at the current stage GDC.
  • the first control module 40 is configured to control signal transmission between the second power supply terminal PVGH and the second node K2 based on the corresponding first clock signal XCK and the potential of the third node K3.
  • the first control terminal and the second control terminal of the ninth transistor T9 are configured to receive the corresponding first clock signal XCK, and the output terminal of the ninth transistor T9 is electrically connected to the second node K2.
  • the control end of the tenth transistor T10 is electrically connected to the third node K3 of the current gate driving circuit, the input end of the tenth transistor T10 is electrically connected to the second power supply end PVGH, and the output end of the tenth transistor T10 is electrically connected to the input end of the ninth transistor T9.
  • the gate control signal received by the control end of the data transistor Tda can be provided by at least one of the first gate driving unit GM1 and the second gate driving unit GM2, at least one of the first gate driving circuit GA1 included in the first gate driving unit GM1 and the second gate driving circuit GA2 included in the second gate driving unit GM2 can also include a second output module 50 to provide the required gate control signal to the data transistor Tda of the corresponding sub-pixel Spi through the second output module 50.
  • the second output module 50 is electrically connected to the first node K1, the third node K3, and the second output terminal O2 of the current-stage gate driver circuit.
  • the second output module 50 is configured to control the gate control signal output by the second output terminal O2 based on the signals at the first and third nodes K1 and K3 and the corresponding second clock signal CK.
  • the second output module 50 includes a third output transistor To3, a fourth output transistor To4, and a second capacitor C2.
  • the control terminal of the third output transistor To3 is electrically connected to the first node K1 , and the input terminal of the third output transistor To3 is configured to receive the corresponding second clock signal CK.
  • a single first gate driving circuit GA1 may include multiple second output modules 50 so that the single first gate driving circuit GA1 can simultaneously output a first gate control signal Nscan1 and multiple third gate control signals Pscan1.
  • the X second output modules 50 of the same first gate drive circuit GA1 are configured to output multiple third gate control signals Pscan1 with phase differences, so that the data transistors Tda driven by the multiple third gate control signals Pscan1 output by the same first gate drive circuit GA1 can be turned on in different time periods, thereby reducing the power consumption of the display device.
  • a single second gate driving circuit GA2 may include a second output module 50 , so that the single second gate driving circuit GA2 can simultaneously output a second gate control signal Nscan2 and a fourth gate control signal Pscan2 .
  • a single second gate driving circuit GA2 may include multiple second output modules 50 so that the single second gate driving circuit GA2 can simultaneously output a second gate control signal Nscan2 and multiple fourth gate control signals Pscan2.
  • the X second output modules 50 of the same second gate drive circuit GA2 are configured to output multiple fourth gate control signals Pscan2 with phase differences, so that the data transistors Tda driven by the multiple fourth gate control signals Pscan2 output by the same second gate drive circuit GA2 can be turned on in different time periods, thereby reducing the power consumption of the display device.
  • the phase difference between the first clock signals corresponding to two adjacent first gate drive circuits GA1 is XH
  • the phase difference between the first clock signals corresponding to two adjacent second gate drive circuits GA2 is XH
  • H represents the unit time length
  • H may be set to correspond to the length of the row cycle.
  • the data transistor Tda of multiple sub-pixels Spii can match the gate control signals used by the compensation transistor Tc and the reset transistor Tr, thereby completing the transmission of the data signal.
  • the compensation transistor Tc and the reset transistor Tr may be controlled to apply gate control signals of different levels to implement the operation of refreshing display data of the sub-pixel Spi.
  • the K+A-th level first gate drive circuit GA1 represents the first gate drive circuit GA1 that is cascaded after the K-th level first gate drive circuit GA1 (K), and the difference in the number of stages between it and the K-th level first gate drive circuit GA1 (K) is A;
  • the K-B-th level second gate drive circuit GA2 represents the second gate drive circuit GA2 that is cascaded before the K-th level second gate drive circuit GA2 (K), and the difference in the number of stages between it and the K-th level second gate drive circuit GA2 (K) is B.
  • the control terminals of the compensation transistors Tc of the sub-pixels Spi in the Lth to L+X-1th rows are electrically connected to the first output terminal O1 of the K+Cth stage first gate driver circuit GA1, where C ⁇ 0.
  • the first gate driving circuit GA1 includes three second output modules 50, and the control terminals of the compensation transistors Tc of the sub-pixels Spi located in the Lth row (i.e., corresponding to the 3K-2 row) to the L+X-1th row (i.e., corresponding to the 3Kth row) are electrically connected to the first output terminal O1 of the Kth stage first gate driving circuit GA1.
  • the control terminal of the reset transistor Tr of the sub-pixel Spi in the Lth row is electrically connected to the first output terminal O1 of the second gate driving circuit GA2 in the K-Dth stages, where D ⁇ 0.
  • the first gate drive circuit GA1 and/or the second gate drive circuit GA2 including the second output module 50 may also include a second frequency division control module 60 to achieve frequency control of the gate control signal output from the second output terminal O2 of the gate drive circuit.
  • the second frequency division control module 60 is electrically connected to the node control module 10 through the first node K1 and the third node K3 of the gate drive circuit of this stage, and is electrically connected to the second output module 50 through the fourth node K4 of the gate drive circuit of this stage.
  • the second frequency division control module 60 is configured to control the signal transmission between the first node K1 and the fourth node K4 according to the corresponding frequency division control signal, thereby controlling the electrical connection between the second output module 50 and the first node K1 through the second frequency division control module 60, and the second output module 50 is configured to control the gate control signal output by the second output terminal O2 according to the signals of the third node K3 and the fourth node K4 and the corresponding second clock signal CK.
  • the second frequency-dividing control module 60 includes a third frequency-dividing transistor Tf3 , a fourth frequency-dividing transistor Tf4 and a third capacitor C3 .
  • the control terminal of the third frequency-dividing transistor Tf3 is electrically connected to the third node K3 of the gate driving circuit at this stage, and the input terminal of the third frequency-dividing transistor Tf3 is configured to receive a corresponding frequency-dividing control signal.
  • the control terminal of the fourth frequency-dividing transistor Tf4 is electrically connected to the output terminal of the third frequency-dividing transistor Tf3 , the input terminal of the fourth frequency-dividing transistor Tf4 is electrically connected to the first node K1 , and the output terminal of the fourth frequency-dividing transistor Tf4 is electrically connected to the fourth node K4 .
  • a frequency division control signal may be provided corresponding to each second frequency division control module 60 to control the frequency of the gate control signal outputted from the second output terminal O2 by the corresponding gate driving circuit.
  • the second frequency-division control modules 60 of multiple cascaded first gate drive circuits GA1 can share the same frequency-division control signal, thereby utilizing the single frequency-division control signal to control the levels of multiple third gate control signals Pscan1.
  • the second frequency-division control modules 60 of multiple cascaded second gate drive circuits GA2 can share the same frequency-division control signal, thereby utilizing the single frequency-division control signal to control the levels of multiple fourth gate control signals Pscan2.
  • the first gate drive circuit GA1 when the first gate drive circuit GA1 includes a second output module 50, the first gate drive circuit GA1 can include a second frequency-division control module 60, and the second frequency-division control modules 60 of the multiple cascaded first gate drive circuits GA1 share the same frequency-division control signal, thereby reducing the number of frequency-division control signals used by the display device.
  • the first gate drive circuit GA1 when the first gate drive circuit GA1 includes multiple second output modules 50 (i.e., X ⁇ 2), the first gate drive circuit GA1 may include at least one second frequency division control module 60. Specifically, the first gate drive circuit GA1 may include a second frequency division control module 60 to control the level of the third gate control signal Pscan output by the multiple second output modules 50. The first gate drive circuit GA1 may include multiple second frequency division control modules 60 to control the level of the third gate control signal Pscan output by the multiple second output modules 50, thereby independently controlling the level states of the multiple third gate control signals Pscan.
  • each second frequency division control module 60 is configured to control the level of the third gate control signal Pscan output by a corresponding second output module 50 according to the corresponding frequency division control signal.
  • the second frequency-division control modules 60 of the multiple cascaded first gate driver circuits GA1 may share the same frequency-division control signal.
  • the second frequency-division control modules 60 of the multiple stages of first gate driver circuits GA1 may be electrically connected to the third frequency-division control line FL3 to reduce the number of frequency-division control signals used by the display device.
  • the frequency division control signals applied by the multiple second frequency division control modules 60 included in the same first gate drive circuit GA1 may be different.
  • each first gate drive circuit GA1 includes two second output modules 50 and two second frequency division control modules 60.
  • the two second output modules 50 include a first sub-output module and a second sub-output module.
  • the two second frequency division control modules 60 include a first sub-frequency division control module and a second sub-frequency division control module.
  • the first sub-frequency division control module is configured to control the level of the third gate control signal Pscan output by the first sub-output module based on a frequency division control signal
  • the second sub-frequency division control module is configured to control the level of the third gate control signal Pscan output by the second sub-output module based on another frequency division control signal.
  • the second output terminal corresponding to the first sub-output module can be O21 in FIG.
  • the second clock signal input terminal corresponding to the first sub-output module can be CKa in FIG. 6B
  • the second clock signal input terminal corresponding to the second sub-output module can be CKb in FIG. 6B .
  • the first sub-frequency division control modules of multiple cascaded first gate driving circuits GA1 share the same frequency division control signal
  • the second sub-frequency division control modules of multiple cascaded first gate driving circuits GA1 share the same frequency division control signal to reduce the number of frequency division control signals used by the display device.
  • the data transistor Tda When the sub-pixel Spi needs to refresh its display data, the data transistor Tda must be turned on so that the data signal can be transmitted to the control terminal of the drive transistor Tdr. Therefore, the gate control signal corresponding to the data transistor Tda must also have a valid level during a specific period (such as the data writing phase described below). Therefore, the frequency-division control signal used to control the first frequency-division control module 20 can be different from the frequency-division control signal used to control the second frequency-division control module 60. This allows the levels of the gate control signal output from the first output terminal O1 and the gate control signal output from the second output terminal O2 in the same gate drive circuit to be independently controlled.
  • the multiple frequency division control lines FL include a third frequency division control line FL3, which transmits a third frequency division control signal PF1.
  • Each first gate driver circuit GA1 includes a second frequency division control module 60.
  • the second frequency division control module 60 of the multi-stage first gate driver circuit GA1 is electrically connected to the third frequency division control line FL3, so as to reduce the number of frequency division control signals used in the display device while making the working states of the data transistors Tda and the compensation transistors Tc of the multiple sub-pixels Spi independent.
  • the plurality of frequency division control lines FL include a fourth frequency division control line FL4, which transmits a fourth frequency division control signal PF2.
  • Each second gate drive circuit GA2 includes a second frequency division control module 60.
  • the second frequency division control module 60 of the multi-stage second gate drive circuit GA2 is electrically connected to the fourth frequency division control line FL4, so as to reduce the number of frequency division control signals used in the display device while making the working states of the data transistors Tda and the reset transistor Tr of the plurality of sub-pixels Spi independent.
  • the multiple frequency division control lines FL include a third frequency division control line FL3 and a fourth frequency division control line FL4, the second frequency division control module of the multi-level first gate drive circuit GA1 is electrically connected to the third frequency division control line FL3, and the second frequency division control module of the multi-level second gate drive circuit GA2 is electrically connected to the fourth frequency division control line FL4, so as to reduce the number of frequency division control signals used by the display device while making the working states of the data transistors Tda, compensation transistors Tc, and reset transistors Tr of multiple sub-pixels Spi independent.
  • the frequency division control line corresponding to the second frequency division control module of the first gate driving unit GM1 can be electrically connected to the frequency division control line corresponding to the second frequency division control module of the second gate driving unit GM2, so that the second frequency division control module of the first gate driving unit GM1 and the second frequency division control module of the second gate driving unit GM2 apply the same frequency division control signal.
  • control terminals of the data transistors Tda of the plurality of sub-pixels Spi in the same row are electrically connected to the second output terminals O2 of the plurality of first gate drive circuits GA1 and the second output terminals O2 of the plurality of second gate drive circuits GA2.
  • the third frequency-dividing control line FL3 and the fourth frequency-dividing control line FL4 are electrically connected so that the third gate control signal Pscan1 and the fourth gate control signal Pscan2 received by the data transistors Tda in the sub-pixels Spi remain identical. This stabilizes the operating state of the data transistors Tda in the sub-pixels Spi and reduces the number of frequency-dividing control signals used.
  • the multiple frequency-division control lines FL may include, in addition to the third frequency-division control line FL3 connected to one second frequency-division control module 60, frequency-division control lines connected to the remaining second frequency-division control modules 60.
  • the multiple frequency-division control lines FL may include a fifth frequency-division control line.
  • One second frequency-division control module 60 in each stage of the first gate drive circuit GA1 is electrically connected to the third frequency-division control line FL3, and another second frequency-division control module 60 in each stage of the first gate drive circuit GA1 is electrically connected to the fifth frequency-division control line, so that the operating states of the two second frequency-division control modules 60 in each first gate drive circuit GA1 are independent.
  • the multiple frequency-division control lines FL may include, in addition to the fourth frequency-division control line FL4 connected to one second frequency-division control module 60, frequency-division control lines connected to the remaining second frequency-division control modules 60. If each second gate driver circuit GA2 includes two second frequency-division control modules 60, the multiple frequency-division control lines FL may include a sixth frequency-division control line.
  • One second frequency-division control module 60 in each stage of the second gate driver circuit GA2 is electrically connected to the fourth frequency-division control line FL4, and another second frequency-division control module 60 in each stage of the second gate driver circuit GA2 is electrically connected to the sixth frequency-division control line, so that the operating states of the two second frequency-division control modules 60 in each second gate driver circuit GA2 are independent.
  • both the first gate driving circuit GA1 and the second gate driving circuit GA2 include multiple second frequency-dividing control modules 60, the frequency-dividing control signals applied by the second frequency-dividing control module corresponding to the third gate control signal Pscan1 and the fourth gate control signal Pscan2 received by the control terminal of the data transistor Tda in the plurality of sub-pixels Spi in the same row can still be maintained identical.
  • the frequency-dividing control signals applied by the second frequency-dividing control module corresponding to the third gate control signal Pscan1 and the fourth gate control signal Pscan2 received by the control terminal of the data transistor Tda in the plurality of sub-pixels Spi in the same row are signals transmitted by the fifth frequency-dividing control line and the sixth frequency-dividing control line
  • the fifth frequency-dividing control line and the sixth frequency-dividing control line can be electrically connected to ensure that the third gate control signal Pscan1 and the fourth gate control signal Pscan2 received by the data transistor Tda remain identical, thereby stabilizing the operating state of the data transistor Tda.
  • the phase difference between the first start signal and the second start signal is the same as the phase difference between the first gate driving circuit GA1 of each stage in the first gate driving unit GM1 and the second gate driving circuit GA2 of the same stage in the second gate driving unit GM2.
  • the control end of the data transistor Tda simultaneously receives the third gate control signal Pscan1 and the fourth gate control signal Pscan2, the corresponding transition moments of the first start signal stv1 and the second start signal stv2 from the active level to the inactive level can be controlled to remain the same, so that the third gate control signal Pscan1 and the fourth gate control signal Pscan2 received by the data transistor Tda of a sub-pixel Spi remain the same, thereby stabilizing the working state of the data transistor Tda.
  • the start signal STV (such as the aforementioned first start signal stv1) corresponding to the first-stage first gate drive circuit GA1(1) in the multi-stage first gate drive circuit GA1 has a transition from an active level to an inactive level at a first moment
  • the start signal STV (such as the aforementioned second start signal stv2) corresponding to the first-stage second gate drive circuit GA2(1) in the multi-stage second gate drive circuit GA2 has a transition from an active level to an inactive level at a first moment.
  • the first moment can be referred to as ta in FIG. 8A below.
  • the transistor is an N-type transistor, then the signal received by the control terminal of the transistor has a valid level, that is, the signal received by the control terminal of the transistor has a high level, and the signal received by the control terminal of the transistor has an invalid level, that is, the signal received by the control terminal of the transistor has a low level. If the transistor is a P-type transistor, then the signal received by the control terminal of the transistor has a valid level, that is, the signal received by the control terminal of the transistor has a low level, and the signal received by the control terminal of the transistor has an invalid level, that is, the signal received by the control terminal of the transistor has a high level.
  • the pulse widths of the active levels of the first start signal stv1 and the second start signal stv2 may be the same or different.
  • the gate control signal corresponding to the data transistor Tda i.e., the third gate control signal Pscan1 and/or the fourth gate control signal Pscan2 can maintain a high frequency or be reduced to a low frequency.
  • the display panel DP is used to implement a static image display.
  • the high-frequency and low-frequency image display principle diagram provided in the embodiment of the present application in FIG7 is used for explanation.
  • the display panel DP When the display panel DP is displayed at a high frequency (such as 120 Hz), the display panel DP needs to perform 120 display data refresh operations within 1 second, that is, 120 frames are included in 1 second, and each frame display is refreshed.
  • the display panel DP is displayed at a low frequency (such as 1 Hz)
  • the display panel DP will also contain 120 frames within 1 second, but only the first frame performs the display data refresh operation.
  • the 119 consecutive frames after the first frame all maintain the image data signal of the first frame, and do not perform the display data refresh operation.
  • the frame for which the display data is refreshed can be recorded as a write frame WF
  • the frame for which the display data is not refreshed can be recorded as a hold frame HF. Therefore, during the write frame WF, the first gate control signal Nscan1 corresponding to the compensation transistor Tc, the second gate control signal Nscan2 corresponding to the reset transistor Tr, and the gate control signal corresponding to the data transistor Tda must all have an active level to overwrite the original data signal stored at the control terminal of the drive transistor Tdr with the newly written data signal, so that the sub-pixel Spi can display again according to the newly written data signal during the write frame.
  • the first gate control signal Nscan1 corresponding to the compensation transistor Tc and the second gate control signal Nscan2 corresponding to the reset transistor Tr of some sub-pixels Spi remain at an inactive level, turning off the compensation transistor Tc and the reset transistor Tr, so that no new data signal is stored at the control terminal of the drive transistor Tdr.
  • the gate control signal corresponding to the data transistor Tda can maintain the same frequency as the write frame WF.
  • the gate control signal corresponding to the data transistor Tda can remain at an inactive level so that the frequency of the gate control signal corresponding to the data transistor Tda during the hold frame HF is lower than the frequency during the write frame WF.
  • the data transistor Tda in the hold frame HF, is turned on according to the corresponding gate control signal to reset the potential of the input terminal of the driving transistor Tdr using the signal transmitted by the data line DL electrically connected to the data transistor Tda.
  • the data transistor Tda remains cut off according to the corresponding gate control signal
  • the second initial transistor Ti2 has a conduction period according to the gate control signal transmitted by the corresponding fourth scan line GL4, so as to utilize the second initial signal transmitted by the second initial line VL2 electrically connected to the second initial transistor Ti2 to reset the potential of the input end of the driving transistor Tdr.
  • At least one gate drive circuit GDC further includes a switch module 70, which is electrically connected between the second frequency division control module 60 and the fourth node K4.
  • the switch module 70 is configured to control the electrical connection between the second frequency division control module 60 and the fourth node K2 according to a corresponding switch control signal SC.
  • the switch module 70 includes an eleventh transistor T11, the control end of the eleventh transistor T11 is configured to receive a switch control signal SC, the input end of the eleventh transistor T11 is electrically connected to the output end of the fourth frequency-dividing transistor Tf4, and the output end of the eleventh transistor T11 is electrically connected to the fourth node.
  • control terminal of the eleventh transistor T11 of the K-th stage first gate driver circuit GA1(K) is configured to receive the K-E-th stage first gate control signal Nscan1(K-E) output by the K-E-th stage first gate driver circuit GA1(K-E), so as to use the K-E-th stage first gate control signal Nscan1(K-E) output by the K-E-th stage first gate driver circuit GA1(K-E) as the switch control signal SC received by the control terminal of the eleventh transistor T11 of the K-th stage first gate driver circuit GA1(K).
  • E the control terminal of the eleventh transistor T11 of the K-th stage first gate driver circuit GA1(K)
  • the switch control signal SC received by the control end of the eleventh transistor T11 of the first-stage first gate drive circuit GA1(1) to the second-stage first gate drive circuit GA1(2) corresponds to the low-level signal VGL
  • the control end of the eleventh transistor T11 of each stage of the gate drive circuit after the second-stage first gate drive circuit GA1(2) is configured to receive the first gate control signal Nscan1 output by the first two stages of the first gate drive circuit GA1
  • the control end of the eleventh transistor T11 of the third-stage first gate drive circuit GA1(3) as shown in FIG5A to FIG5B is configured to receive the first-stage first gate control signal Nscan1(1) output by the first-stage first gate drive circuit GA1(1).
  • the switch control signal SC corresponding to each stage of the second gate drive circuit GA2 in the second gate drive unit GM2 can also be obtained.
  • control terminal of the eleventh transistor T11 is electrically connected to the third node K3 of the previous-stage gate driver circuit, so that the potential of the third node K3 of the previous-stage gate driver circuit is used as a switch control signal SC to control the operating state of the eleventh transistor T11, thereby reducing the load on the first output terminal O1 of the gate driver circuit.
  • control terminal of the eleventh transistor T11 of the K-th-stage first gate driver circuit GA1(K) is electrically connected to the third node K3 of the K-E-th-stage first gate driver circuit GA1(K-E), so that the potential of the third node K3 of the K-E-th-stage first gate driver circuit GA1(K-E) is used as the switch control signal SC received by the control terminal of the eleventh transistor T11 of the K-th-stage first gate driver circuit GA1(K).
  • At least one gate drive circuit further includes a second control module 80.
  • the second control module 80 is electrically connected to the third node K3 of the gate drive circuit GDC at the current stage and the switch module 70.
  • the second control module 80 is configured to control signal transmission between the second power supply terminal PVGH and the switch module 70 based on the corresponding first clock signal XCK and the potential of the third node K3.
  • the second control module 80 includes a twelfth transistor T12 and a thirteenth transistor T13.
  • the first control terminal and the second control terminal of the twelfth transistor T12 are configured to receive the corresponding first clock signal XCK, and the output terminal of the twelfth transistor T12 is electrically connected to the input terminal of the eleventh transistor T11 .
  • the control end of the thirteenth transistor T13 is electrically connected to the third node K3 of the current-stage gate driving circuit GDC, the input end of the thirteenth transistor T13 is electrically connected to the second power supply end PVGH, and the output end of the thirteenth transistor T13 is electrically connected to the input end of the twelfth transistor T12.
  • At least one gate driving circuit GDC further includes a reset module 90.
  • the reset module 90 is electrically connected to the first node K1 and is configured to control signal transmission between the second power terminal PVGH and the first node K1 according to a reset control signal Ctl.
  • the reset module 90 includes a reset transistor Tre, a control terminal of the reset transistor Tre is configured to receive a reset control signal Ctl, an input terminal of the reset transistor Tre is electrically connected to the second power terminal PVGH, and an output terminal of the reset transistor Tre is electrically connected to the first node K1.
  • the reset module 90 is configured to be enabled when the display device is powered on and/or during a blanking interval.
  • the voltage corresponding to the first power terminal PVGL is smaller than the voltage corresponding to the second power terminal PVGH, and the voltage corresponding to the third power terminal NVGL is smaller than the voltage corresponding to the fourth power terminal NVGH.
  • At least one of the first transistor T1 , the fourth transistor T4 , the sixth transistor T6 , the seventh transistor T7 , the ninth transistor T9 , the twelfth transistor T12 and the first output transistor To1 may have only one control terminal.
  • each transistor included in the gate drive circuit GDC may be one of a P-type transistor and an N-type transistor.
  • the semiconductor of each transistor included in the gate drive circuit GDC may be one of a silicon semiconductor and an oxide semiconductor.
  • clock signals transmitted by multiple clock signal lines may be reused as first clock signals and second clock signals corresponding to multiple cascaded gate driving circuits to reduce power consumption of the display device and reduce the frame size of the display panel DP.
  • the multiple first gate drive circuits GA1 included in the first gate drive unit GM1 can share clock signals transmitted by F clock lines as corresponding first and second clock signals.
  • F is 2, 4, 6, 8, etc.
  • the multiple clock lines include a first clock line CKL1, a second clock line CKL2, a third clock line CKL3, and a fourth clock line CKL4.
  • the first gate drive circuit GA1 includes a second output module 50
  • the first clock signal XCK corresponding to the 4m+1-th level first gate drive circuit GA1 (4m+1) corresponds to the signal transmitted by the second clock line CKL2
  • the second clock signal CK corresponding to the 4m+1-th level first gate drive circuit GA1 (4m+1) corresponds to the signal transmitted by the first clock line CKL1
  • the first clock signal XCK corresponding to the 4m+2-th level first gate drive circuit GA1 (4m+2) corresponds to the signal transmitted by the third clock line CKL3
  • the second clock signal CK corresponding to the 4m+2-th level first gate drive circuit GA1 (4m+2) corresponds to the signal transmitted by the third clock line CKL4.
  • the first clock signal XCK corresponding to the first gate driver circuit GA1 (4m+3) of the 4m+3th level corresponds to the signal transmitted by the fourth clock line CKL4, and the second clock signal CK corresponding to the first gate driver circuit GA1 (4m+3) of the 4m+3th level corresponds to the signal transmitted by the third clock line CKL3; the first clock signal XCK corresponding to the first gate driver circuit GA1 (4m+4) of the 4m+4th level corresponds to the signal transmitted by the first clock line CKL1, and the second clock signal CK corresponding to the first gate driver circuit GA1 (4m+4) of the 4m+4th level corresponds to the signal transmitted by the fourth clock line CKL4. m ⁇ 0.
  • each first gate driving circuit GA1 includes multiple second output modules 50 (X ⁇ 2)
  • the multiple clock lines include a first clock line CKL1, a second clock line CKL2, a third clock line CKL3, and a fourth clock line CKL4.
  • the first clock line CKL1 transmits the corresponding second clock signal CK to a second output module 50 of the 2k+1-level first gate drive circuit GA1(2k+1), and the second clock line CKL2 transmits the corresponding second clock signal CK to another second output module 50 of the 2k+1-level first gate drive circuit GA1(2k+1);
  • the third clock line CKL3 transmits the corresponding second clock signal CK to a second output module of the 2k+2-level first gate drive circuit GA1(2k+2)
  • the fourth clock line CKL4 transmits the corresponding second clock signal CK to another second output module of the 2k+2-level first gate drive circuit GA1(2k+2), k ⁇ 0.
  • each first gate driving circuit GA1 includes a first sub-output module, a second sub-output module and a third sub-output module, and the multiple clock lines may further include a fifth clock line CKL5 and a sixth clock line CKL6.
  • the first clock line CKL1 transmits the corresponding second clock signal CK to the first sub-output module of the first gate drive circuit GA1 (2k+1) of the 2k+1 level
  • the second clock line CKL2 transmits the corresponding second clock signal CK to the second sub-output module of the first gate drive circuit GA1 (2k+1) of the 2k+1 level
  • the third clock line CKL3 transmits the corresponding second clock signal CK to the third sub-output module of the first gate drive circuit GA1 (2k+1) of the 2k+1 level
  • the fourth clock line CKL4 transmits the corresponding second clock signal CK to the first sub-output module of the first gate drive circuit GA1 (2k+2) of the 2k+2 level
  • the fifth clock line CKL5 transmits the corresponding second clock signal CK to the second sub-output module of the first gate drive circuit GA1 (2k+2) of the 2k+2 level
  • the sixth clock line CKL6 transmits the corresponding second clock signal CK to the third sub
  • the fifth clock line CKL5 transmits the corresponding second clock signal CK to the first sub-output module of the 2k+1-level first gate drive circuit GA1(2k+1)
  • the sixth clock line CKL6 transmits the corresponding second clock signal CK to the second sub-output module of the 2k+1-level first gate drive circuit GA1(2k+1)
  • the first clock line CKL1 transmits the corresponding second clock signal CK to the third sub-output module of the 2k+1-level first gate drive circuit GA1(2k+1)
  • the second clock line CKL2 transmits the corresponding second clock signal CK to the first sub-output module of the 2k+2-level first gate drive circuit GA1(2k+2)
  • the third clock line CKL3 transmits the corresponding second clock signal CK to the second sub-output module of the 2k+2-level first gate drive circuit GA1(2k+2)
  • the fourth clock line CKL4 transmits the corresponding second clock signal CK to the third sub-out
  • the sixth clock line CKL6 transmits the corresponding second clock signal CK to the first sub-output module of the 2k+1-level first gate drive circuit GA1(2k+1), the first clock line CKL1 transmits the corresponding second clock signal CK to the second sub-output module of the 2k+1-level first gate drive circuit GA1(2k+1), and the second clock line CKL2 transmits the corresponding second clock signal CK to the third sub-output module of the 2k+1-level first gate drive circuit GA1(2k+1); the third clock line CKL3 transmits the corresponding second clock signal CK to the first sub-output module of the 2k+2-level first gate drive circuit GA1(2k+2), the fourth clock line CKL4 transmits the corresponding second clock signal CK to the second sub-output module of the 2k+2-level first gate drive circuit GA1(2k+2), and the fifth clock line CKL5 transmits the corresponding second clock signal CK to the third sub-output module of the
  • phase difference between the clock signal transmitted by the first clock line CKL1 and the clock signal transmitted by the second clock line CKL2 is ⁇ 1
  • the phase difference between the clock signal transmitted by the second clock line CKL2 and the clock signal transmitted by the third clock line CKL3 is ⁇ 2
  • the phase difference between the clock signal transmitted by the third clock line CKL3 and the clock signal transmitted by the fourth clock line CKL4 is ⁇ 3
  • the phase difference between the clock signal transmitted by the fourth clock line CKL4 and the clock signal transmitted by the fifth clock line CKL5 is ⁇ 4
  • the phase difference between the clock signal transmitted by the fifth clock line CKL5 and the clock signal transmitted by the sixth clock line CKL6 is ⁇ 5
  • the phase difference between the clock signal transmitted by the sixth clock line CKL6 and the clock signal transmitted by the sixth clock line CKL6 is ⁇ 6.
  • each first gate driving circuit GA1 includes multiple second output modules 50 (X ⁇ 2)
  • the multiple first gate driving circuits GA1 included in the first gate driving unit GM1 share clock signals transmitted by multiple clock lines among F clock lines as corresponding first clock signals XCK.
  • the first gate driver unit GM1 includes multiple first gate driver circuits GA1 that share four clock lines for clock signal transmission
  • the third clock line CKL1 transmits the corresponding first clock signal XCK to the 2k+1th stage first gate driver circuit GA1(2k+1)
  • the first clock line transmits the corresponding first clock signal XCK to the 2k+2th stage first gate driver circuit GA1(2k+2).
  • each first gate driver circuit GA1 has three second output modules 50, and the three second output modules 50 include a first sub-output module, a second sub-output module, and a third sub-output module.
  • the fourth clock line CKL4 transmits the corresponding first clock signal XCK to the 2k+1th-stage first gate driver circuit GA1(2k+1), and the first clock line CKL1 transmits the corresponding first clock signal XCK to the 2k+2th-stage first gate driver circuit GA1(2k+2).
  • each first gate drive circuit GA1 includes multiple second output modules 50 (X ⁇ 2)
  • multiple clock lines can be independently set to provide corresponding first clock signals XCK to the multi-stage first gate drive circuit GA1, so that among the F clock lines, no part of the clock lines simultaneously provide corresponding first clock signals XCK and second clock signals CK to the multi-stage first gate drive circuit GA1, so that the loads corresponding to the multiple clock lines are similar, thereby improving the quality of the third gate control signal Pscan1 output by the multi-stage first gate drive circuit GA1.
  • phase difference of the first clock signal XCK corresponding to the two adjacent first gate drive circuits GA1 is XH
  • the phase difference of the third gate control signal output by the first sub-output module in the two adjacent first gate drive circuits GA1 is XH
  • the phase difference of the third gate control signal output by the second sub-output module in the two adjacent first gate drive circuits GA1 is XH
  • the plurality of first gate driving circuits GA1 included in the second gate driving unit GM2 may share clock signals transmitted by G clock lines as corresponding first clock signals XCK and second clock signals CK, where G is 2, 4, 6, 8, etc.
  • the matching connection relationship between the multi-stage first gate driving circuit GA1 and the multiple clock lines can be referred to to obtain the matching connection relationship between the multi-stage second gate driving circuit GA2 and the multiple clock lines.
  • the first gate driving unit GM1 and the second gate driving unit GM2 may share multiple clock lines, or may not share multiple clock lines.
  • the first gate driving unit GM1 and the second gate driving unit GM2 share multiple clock lines, which can also help to keep the third gate control signal Pscan1 and the fourth gate control signal Pscan2 correspondingly received by the data transistor Tda in the sub-pixel Spi the same, thereby improving the operating stability of the data transistor Tda.
  • first gate driving circuit GA1 and the second gate driving unit GA2 both include a second output module 50, and the first gate driving unit GM1 and the second gate driving unit GM2 share four clock lines, the connection relationship between the first gate driving unit GM1, the second gate driving unit GM2 and the multiple clock lines is explained.
  • the first clock signal XCK corresponding to the 4m+1-level first gate driver circuit GA1(4m+1) and the 4m+1-level second gate driver circuit GA2(4m+1) corresponds to the signal transmitted by the second clock line CKL2
  • the second clock signal CK corresponding to the 4m+1-level first gate driver circuit GA1(4m+1) and the 4m+1-level second gate driver circuit GA2(4m+1) corresponds to the signal transmitted by the first clock line CKL1
  • the first clock signal XCK corresponding to the 4m+2-level first gate driver circuit GA1(4m+2) and the 4m+2-level second gate driver circuit GA2(4m+2) corresponds to the signal transmitted by the third clock line CKL3
  • the second clock signal CK corresponding to the 4m+2-level first gate driver circuit GA1(4m+2) and the 4m+2-level second gate driver circuit GA2(4m+2) corresponds to the signal transmitted by the second clock line CKL2
  • the first clock line CKL1 transmits the corresponding second clock signal CK to a second output module of the 2k+1-stage first gate driving circuit GA1 (2k+1) and a second output module of the 2k+1-stage second gate driving circuit GA2 (2k+1)
  • the second clock line CKL2 transmits the corresponding second clock signal CK to another second output module of the 2k+1-stage first gate driving circuit GA1 (2k+1) and another second output module of the 2k+1-stage second gate driving circuit GA2 (2k+1)
  • the third clock line CKL3 transmits the corresponding second clock signal CK to a second output module of the 2k+2-stage first gate driving circuit GA1 (2k+2) and a second output module of the 2k+2-stage second gate driving circuit GA2 (2k+2).
  • the fourth clock line CKL4 transmits the fourth clock line CKL4
  • the third clock line CKL1 transmits the corresponding first clock signal XCK to the 2k+1-th level first gate drive circuit GA1 (2k+1) and the 2k+1-th level second gate drive circuit GA2 (2k+1), and the first clock line transmits the corresponding first clock signal XCK to the 2k+2-th level first gate drive circuit GA1 (2k+2) and the 2k+2-th level second gate drive circuit GA2 (2k+2).
  • the connection relationship between the first gate driving unit GM1, the second gate driving unit GM2 and the multiple clock lines can also be obtained.
  • first gate drive circuit GA1 and the second gate drive circuit GA2 can be the same or different.
  • both the first gate drive circuit GA1 and the second gate drive circuit GA2 can adopt the circuit structure shown in Figures 6A and 6B.
  • one of the first gate drive circuit GA1 and the second gate drive circuit GA2 adopts the circuit structure shown in Figures 6A and 6B, while the other of the first gate drive circuit GA1 and the second gate drive circuit GA2 adopts a circuit structure that can implement frequency division control in related art.
  • the level of the first frequency-dividing control signal NF1 By controlling the level of the first frequency-dividing control signal NF1, the level of the first gate control signal Nscan1 output by the multi-stage first gate drive circuit GA1 can be controlled. Similarly, by controlling the level of the frequency-dividing control signal corresponding to the second frequency-dividing module of the first gate drive circuit GA1, the level of the third gate control signal Pscan1 output by the multi-stage first gate drive circuit GA1 can be controlled. Similarly, by controlling the level of the second frequency-dividing control signal NF2, the level of the second gate control signal Nscan2 output by the multi-stage second gate drive circuit GA2 can be controlled. Similarly, by controlling the level of the second frequency-dividing module of the second gate drive circuit GA2, the level of the fourth gate control signal Pscan2 output by the multi-stage second gate drive circuit GA2 can be controlled.
  • Figures 8A to 8D are timing diagrams of the first gate control signal and the second gate control signal provided in an embodiment of the present application.
  • Figures 8A to 8B correspond to timing diagrams in which each gate drive circuit includes a second output module
  • Figures 8C to 8D correspond to timing diagrams in which each gate drive circuit includes two second output modules.
  • Nscan in Figures 8C to 8D can represent either the first or second gate control signal
  • Pscan in Figures 8C to 8D can represent either the third or fourth gate control signal.
  • the second transistor T2, the third transistor T3, the fifth transistor T5, the eighth transistor T8, the tenth transistor T10, the eleventh transistor T11, the thirteenth transistor T13, the first frequency-dividing transistor Tf1 to the fourth frequency-dividing transistor Tf4, the second output transistor To2 to the fourth output transistor To4 are P-type transistors
  • the first transistor T1, the fourth transistor T4, the sixth transistor T6, the seventh transistor T7, the ninth transistor T9, the twelfth transistor T12 and the first output transistor To1 are N-type transistors
  • the first-stage first gate drive circuit GA1 adopts the first starting signal stv1 as the starting signal
  • the first-stage second gate drive circuit GA2 adopts the second starting signal stv2 as the starting signal
  • the p-th stage first gate drive circuit GA1(p) adopts the first gate outputted from the first output terminal O1 of the p-1-th stage first gate drive circuit GA1(p-1) Taking the p-th level second gate drive circuit GA2(p) as the starting
  • the first clock signal XCK corresponding to the p-th stage first gate driver circuit GA1(p) and the p-th stage second gate driver circuit GA2(p) is provided by the second clock line CKL2, and the corresponding second clock signal CK is provided by the first clock line CKL1.
  • the first clock signal XCK corresponding to the p-th stage first gate driver circuit GA1(p) and the p-th stage second gate driver circuit GA2(p) is provided by the first clock line CKL1
  • the corresponding second clock signal CK is provided by the third clock line CKL3 and the fourth clock line CKL4
  • each gate driver circuit corresponding to Figures 8C and 8D includes a second frequency division control module.
  • the first clock signal CK1 transmitted by the first clock line CKL1 is at a high level
  • the second clock signal CK2 transmitted by the second clock line CKL2 is at a low level
  • the third clock signal CK3 transmitted by the third clock line CKL3 is at a high level
  • the fourth clock signal CK4 transmitted by the fourth clock line CKL4 is at a high level.
  • the p-1th stage first gate control signal Nscan1(p-1) to the p-2th stage first gate control signal Nscan1(p-2) and the p-1th stage second gate control signal Nscan2(p-1) to the p-2th stage second gate control signal Nscan2(p-2) are at a low level.
  • the first frequency division control signal NF1, the second frequency division control signal NF2, the third frequency division control signal PF1, and the fourth frequency division control signal PF2 are at a low level.
  • the third transistor T3 is turned off.
  • the first clock signal CK1 is at a high level
  • the second clock signal CK2 is at a low level
  • the third clock signal CK3 is at a high level
  • the fourth clock signal CK4 is at a high level.
  • the p-1th stage first gate control signal Nscan1(p-1) to the p-2th stage first gate control signal Nscan1(p-2) are at a high level
  • the p-1th stage second gate control signal Nscan2(p-1) to the p-2th stage second gate control signal Nscan2(p-2) are at a low level
  • the first to fourth frequency division control signals NF1 to PF2 are at a low level.
  • the first transistor T1, the third transistor T3, the sixth transistor T6, the eighth transistor T8, and the second output transistor To2 are turned on, the second frequency-dividing transistor Tf2 and the fourth frequency-dividing transistor Tf4 remain turned on, and the second transistor T2, the fourth transistor T4, the fifth transistor T5, the seventh transistor T7, the ninth transistor T9, the tenth transistor T10, the eleventh transistor T11, the twelfth transistor T12, the thirteenth transistor T13, the first frequency-dividing transistor Tf1, the third frequency-dividing transistor Tf3, the first output transistor To1, the third output transistor To3, and the fourth output transistor To4 are turned off.
  • the fourth power supply terminal NVGH is electrically connected to the first output terminal O1.
  • the p-th stage first gate control signal Nscan1(p) has a high level, and the p-th stage third gate control signal Pscan1(p) remains high.
  • the first clock signal CK1 is at a high level
  • the second clock signal CK2 is at a high level
  • the third clock signal CK3 is at a low level
  • the fourth clock signal CK4 is at a high level.
  • the p-1th stage first gate control signal Nscan1(p-1) through the p-2th stage first gate control signal Nscan1(p-2) are at a high level
  • the p-1th stage second gate control signal Nscan2(p-1) through the p-2th stage second gate control signal Nscan2 are at a low level
  • the first through fourth frequency division control signals NF1 through PF2 are at a low level.
  • the p-th stage first gate control signal Nscan1 ( p ) and the p-th stage third gate control signal Pscan1 ( p ) maintain a high level.
  • the third transistor T3 is turned off.
  • the p-th stage second gate control signal Nscan2(p) through the p+11-th stage second gate control signal Nscan2(p+11) remain low, and the p-th stage fourth gate control signal Pscan2(p) through the p+11-th stage fourth gate control signal Pscan2(p+11) remain high.
  • Phase 4 t4 The first clock signal CK1 is high, the second clock signal CK2 is low, the third clock signal CK3 is high, and the fourth clock signal CK4 is high.
  • the p-1th stage first gate control signal Nscan1(p-1) to the p-2th stage first gate control signal Nscan1(p-2) are high
  • the p-1th stage second gate control signal Nscan2(p-1) to the p-2th stage second gate control signal Nscan2 are high
  • the first frequency division control signal NF1, the second frequency division control signal NF2, the third frequency division control signal PF1, and the fourth frequency division control signal PF2 are low.
  • the p-th stage first gate control signal Nscan1(p) and the p-th stage third gate control signal Pscan1(p) maintain a high level.
  • the p+1-th stage first gate control signal Nscan1(p+1) to the p+4-th stage first gate control signal Nscan1(p+4) and the p+1-th stage third gate control signal Pscan1(p+1) to the p+11-th stage third gate control signal Pscan1(p+11) maintain a high level
  • the p+5-th stage first gate control signal Nscan1(p+5) to the p+11-th stage first gate control signal Nscan1(p+11) maintain a low level.
  • the p-th stage second gate driver circuit GA2(p) performs operations similar to those of the p-th stage first gate driver circuit GA1(p) during the second phase t2.
  • the p-th stage second gate control signal Nscan2(p) and the p-th stage fourth gate control signal Pscan2(p) are both high.
  • the p+1-th stage second gate control signal Nscan2(p+1) through the p+11-th stage second gate control signal Nscan2(p+11) remain low, and the p-th stage fourth gate control signal Pscan2(p) through the p+11-th stage fourth gate control signal Pscan2(p+11) remain high.
  • Phase 5 t5 The first clock signal CK1 is at a low level, the second clock signal CK2 is at a high level, the third clock signal CK3 is at a high level, and the fourth clock signal CK4 is at a high level.
  • the p-1th stage first gate control signal Nscan1(p-1) to the p-2th stage first gate control signal Nscan1(p-2) and the p-1th stage second gate control signal Nscan2(p-1) to the p-2th stage second gate control signal Nscan2 are at a low level.
  • the first frequency division control signal NF1 to the fourth frequency division control signal PF2 are at a low level.
  • the second transistor T2, the fourth transistor T4, the sixth transistor T6, the eighth transistor T8, the ninth transistor T9, the eleventh transistor T11, the twelfth transistor T12, the second frequency-dividing transistor Tf2, the fourth frequency-dividing transistor Tf4, the second output transistor To2, and the third output transistor To3 are turned on, and the first transistor T1, the third transistor T3, the fifth transistor T5, the seventh transistor T7, the tenth transistor T10, the thirteenth transistor T13, the first frequency-dividing transistor Tf1, the third frequency-dividing transistor Tf3, the first output transistor To1, and the fourth output transistor To4 are turned off.
  • the p-th stage first gate control signal Nscan1(p) and the p-th stage second gate control signal Nscan2(p) have a high level
  • the p-th stage third gate control signal Pscan1(p) and the p-th stage fourth gate control signal Pscan2(p) have a low level.
  • the p+1th level first gate control signal Nscan1(p+1) to the p+7th level first gate control signal Nscan1(p+7) and the p+2th level third gate control signal Pscan1(p+2) to the p+11th level third gate control signal Pscan1(p+11) have a high level
  • the p+8th level first gate control signal Nscan1(p+8) to the p+11th level first gate control signal Nscan1(p+11) have a low level.
  • the p+1th level second gate control signal Nscan2(p+1) to the p+3th level second gate control signal Nscan2(p+3) and the p+2th level fourth gate control signal Pscan2(p+2) to the p+11th level fourth gate control signal Pscan2(p+11) have a high level
  • the p+4th level third gate control signal Nscan2(p+4) to the p+11th level third gate control signal Nscan2(p+11) have a low level.
  • Phase 6 t6 The first clock signal CK1 is at a high level, the second clock signal CK2 is at a low level, the third clock signal CK3 is at a high level, and the fourth clock signal CK4 is at a high level.
  • the p-1th stage first gate control signal Nscan1(p-1) to the p-2th stage first gate control signal Nscan1(p-2) and the p-1th stage second gate control signal Nscan2(p-1) to the p-2th stage second gate control signal Nscan2 are at a low level.
  • the first frequency division control signal NF1 to the fourth frequency division control signal PF2 are at a low level.
  • the second transistor T2 In the p-th stage first gate drive circuit GA1(p) and the p-th stage second gate drive circuit GA2(p), the second transistor T2, the third transistor T3, the fifth transistor T5, the seventh transistor T7, the tenth transistor T10, the eleventh transistor T11, the thirteenth transistor T13, the first frequency-dividing transistors Tf1 to Tf4, the first output transistor To1, and the fourth output transistor To4 are turned on, and the first transistor T1, the fourth transistor T4, the sixth transistor T6, the eighth transistor T8, the ninth transistor T9, the twelfth transistor T12, the second output transistor To2, and the third output transistor To3 are turned off.
  • the p-th stage first gate control signal Nscan1(p) and the p-th stage second gate control signal Nscan2(p) have a low level
  • the p-th stage third gate control signal Pscan1(p) and the p-th stage fourth gate control signal Pscan2(p) have a high level.
  • the first clock signal CK1 is high
  • the second clock signal CK2 is high
  • the third clock signal CK3 is low
  • the fourth clock signal CK4 is high
  • the first to fourth frequency division control signals NF1 to PF2 are low.
  • the p-th to p+1-th first gate control signals Nscan1(p) and Nscan1(p+1) and the p+10-th to Nscan1(p+10) to Nscan1(p+11) are low, and the p+2-th to Nscan1(p+2) to Nscan1(p+9) are high.
  • the p+2-th third gate control signal Pscan1(p+2) is low, and the p-th to Pscan1(p+1) and the p+3-th to Pscan1(p+3) are high.
  • the p-th level second gate control signal Nscan2(p) to the p+1-th level second gate control signal Nscan2(p+1) and the p+6-th level second gate control signal Nscan2(p+6) to the p+11-th level second gate control signal Nscan2(p+11) are low, and the p+2-th level second gate control signal Nscan2(p+2) to the p+5-th level second gate control signal Nscan2(p+5) are high.
  • the p+2-th level fourth gate control signal Pscan2(p+2) is low, and the p-th level fourth gate control signal Pscan2(p) to the p+1-th level fourth gate control signal Pscan2(p+1) and the p+3-th level fourth gate control signal Pscan2(p+3) to the p+11-th level fourth gate control signal Pscan2(p+11) are high.
  • Phase 8 The first clock signal CK1 is high, the second clock signal CK2 is high, the third clock signal CK3 is high, and the fourth clock signal CK4 is low.
  • the first frequency division control signal NF1 is high, and the second to fourth frequency division control signals NF2 to PF2 are low.
  • the p-th level first gate driver circuit GA1(p) maintains the same state as the seventh level t7 during the eighth stage t8.
  • the p+1-th level first gate driver circuit GA1(p+1) performs an action similar to the action performed by the p-th level first gate driver circuit GA1(p) during the seventh level t7 during the eighth stage t8.
  • the p+2-th level first gate driver circuit GA1(p+2) performs an action similar to the action performed by the p+1-th level first gate driver circuit GA1(p+1) during the eighth stage t8.
  • the p-th to p+3-th second gate control signals Nscan2(p+3) and the p+8-th to p+11-th second gate control signals Nscan2(p+8) are low, and the p+4-th to p+7-th second gate control signals Nscan2(p+7) are high.
  • the p+4-th fourth gate control signal Pscan2(p+4) is low, and the p-th to p+3-th fourth gate control signals Pscan2(p+3) and the p+5-th to p+11-th fourth gate control signals Pscan2(p+5) are high.
  • the p-th to p+7-th first gate control signals Nscan1(p+7), the p+11-th to p+11-th first gate control signals Nscan1(p+11), and subsequent first gate control signals Nscan1 are low, and the p+8-th to p+10-th first gate control signals Nscan1(p+10) are high.
  • the p+8-th third gate control signal Pscan1(p+8) is low, and the p-th to p+7-th third gate control signals Pscan1(p+7), and the p+9-th to p+11-th third gate control signals Pscan1(p+9) are high.
  • the third frequency-dividing control signal PF1 the level of the third gate control signal Pscan1 output by the plurality of first gate drive circuits GA1 can be controlled, and by controlling the fourth frequency-dividing control signal PF2, the level of the fourth gate control signal Pscan2 output by the plurality of second gate drive circuits GA2 can be controlled.
  • the third gate control signal Pscan1 and the fourth gate control signal Pscan2 can be made to correspond to the same level, i.e., outputs that do not have an active level.
  • FIG8B a timing diagram of the first gate drive unit GM1 and the second gate drive unit GM2 corresponding to the transition from an active level to an inactive level of the third frequency-dividing control signal PF1 or the fourth frequency-dividing control signal PF2 is shown in FIG8B .
  • the operating principle of the first gate drive unit GM1 and the second gate drive unit GM2 corresponding to the transition from an active level to an inactive level of the third frequency-dividing control signal PF1 or the fourth frequency-dividing control signal PF2 can be similarly derived from the operating principle of the first frequency-dividing control signal NF1 and the second frequency-dividing signal transitioning from an active level to an inactive level.
  • the p+9th stage first gate control signal Nscan1(p+9) output by the p+9th stage first gate driving circuit GA1(p+9) has a high level
  • the p+10th stage first gate control signal Nscan1(p+10) output by the p+10th stage first gate driving circuit GA1(p+10) has a low level.
  • the first transistor T1, the fourth transistor T4, the ninth transistor T9, the twelfth transistor T12, and the first to third frequency dividing transistors Tf1 to Tf3 are turned on, and the second transistor T2, the third transistor T3, the eleventh transistor T11, and the fourth frequency dividing transistor Tf4 are turned off.
  • the fourth frequency-dividing transistor Tf4 of the p+11th-level first gate driving circuit GA1(p+11) is cut off, causing the p+11th-level third gate control signal Pscan1(p+11) to maintain a high level during the period when the second clock signal corresponding to the p+11th-level first gate driving circuit GA1(p+11) is at a low level.
  • the working principle of the second gate driving unit GM2 can also be obtained when the fourth frequency-dividing control signal PF2 jumps from the active level to the inactive level.
  • the working principles of the first gate driving unit GM1 and the second gate driving unit GM2 when they jump from the invalid level to the valid level according to the corresponding frequency-divided control signal can also be obtained, which will not be elaborated here.
  • FIG8A and 8B illustrate the operating principles of the first gate drive unit GM1 or the second gate drive unit GM2 when the first gate drive circuit GA1 or the second gate drive circuit GA2 includes two second output modules 50 and a second frequency division control module 60. This will not be further elaborated here. Accordingly, the timing diagrams of the multiple gate control signals output by the first gate drive unit or the second gate drive unit are shown in FIG8C and FIG8D.
  • the gate drive module GM further includes a third gate drive unit GM3 and a fourth gate drive unit GM4.
  • the third gate drive unit GM3 includes a plurality of cascaded third gate drive circuits GA3, which are configured to generate a plurality of fifth gate control signals Pscan for output to the control ends of the first initial transistors Ti1 and the second initial transistors Ti2 of the plurality of sub-pixels Spi.
  • the fourth gate drive unit GM4 includes a plurality of cascaded fourth gate drive circuits GA4, which are configured to generate a plurality of emission control signals EM for output to the control ends of the first emission control transistors Te1 and the second emission control transistors Te2 of the plurality of sub-pixels Spi.
  • the plurality of third gate drive circuits GA3 are electrically connected to the plurality of fourth scan lines GL4, and the plurality of fourth gate drive circuits GA4 are electrically connected to the plurality of emission control lines EL.
  • each third gate driving circuit GA3 can drive the first initial transistor Ti1 and the second initial transistor Ti2 of at least one row of sub-pixels Spi
  • each fourth gate driving circuit GA4 can drive the first light-emitting control transistor Te1 and the second light-emitting control transistor Te2 of at least one row of sub-pixels Spi.
  • the third gate drive circuit GA3 and the fourth gate drive circuit GA4 may adopt the same or different circuit structures, and the circuit structures adopted by the third gate drive circuit GA3 and the fourth gate drive circuit GA4 may refer to the designs in related technologies.
  • Figure 9 is a timing diagram of the sub-pixel corresponding to the write frame and the hold frame provided by an embodiment of the present application.
  • the operating principle of the pixel drive circuit is described below, taking as an example an example where the compensation transistor Tc and the reset transistor Tr are N-type transistors, and the drive transistor Tdr, the data transistor Tda, the first emission control transistor Te1, the second emission control transistor Te2, the first initial transistor Ti1, and the second initial transistor Ti2 are P-type transistors.
  • the emission control signal EM transmitted by the emission control line EL and the gate control signal received by the data transistor Tda are high.
  • the gate control signal received by the reset transistor Tr i.e., the first gate control signal Nscan1
  • the gate control signal received by the compensation transistor Tc i.e., the second gate control signal Nscan2
  • the fifth gate control signal Pscan transmitted by the fourth scan line GL4 is low.
  • the first initial signal transmitted by the first initial line VL1 is transmitted to the anode of the light-emitting device Di to reset the anode potential of the light-emitting device Di.
  • the second initial signal transmitted by the second initial line VL2 is transmitted to the input and output terminals of the driving transistor Tdr to reset the potentials of the input and output terminals of the driving transistor Tdr.
  • the first gate control signal Nscan1, the emission control signal EM, the third gate control signal Pscan1, the fourth gate control signal Pscan2, and the fifth gate control signal received by the data transistor Tda are at a high level Pscan, and the second gate control signal Nscan2 is at a low level.
  • the reset transistor Tr is turned on, and the reset signal Vr is transmitted to the gate of the drive transistor Tdr to reset the potential of the control terminal of the drive transistor Tdr.
  • the second gate control signal Nscan2 the emission control signal EM, and the fifth gate control signal Pscan are high, while the first gate control signal Nscan1, the third gate control signal Pscan1 received by the data transistor Tda, and the fourth gate control signal Pscan2 are low.
  • the data transistor Tda and the compensation transistor Tc are turned on, and the data signal is transmitted to the control terminal of the drive transistor Tdr.
  • the second reset stage Si2 and the data writing stage Sw can also include a stage of controlling the reset transistor Tr and the compensation transistor Tc to be turned on at the same time, so that the reset signal Vr can be transmitted to the output end and input end of the driving transistor Tdr, thereby realizing the potential reset of the output end and input end of the driving transistor Tdr.
  • the light-emitting control signal EM, the third gate control signal Pscan1 and the fourth gate control signal Pscan2 received by the data transistor Tda are high, the first gate control signal Nscan1, the second gate control signal Nscan2, and the fifth gate control signal Pscan are low, the first initial signal is transmitted to the anode of the light-emitting device Di, and the second initial signal is transmitted to the input and output ends of the driving transistor Tdr.
  • the third gate control signal Pscan1, the fourth gate control signal Pscan2, and the fifth gate control signal Pscan received by the data transistor Tda are at a high level
  • the light-emitting control signal EM, the first gate control signal Nscan1, and the second gate control signal Nscan2 are at a low level
  • the first light-emitting control transistor Te1 and the second light-emitting control transistor Te2 are turned on
  • the driving transistor Tdr generates a driving current to drive the corresponding light-emitting device Di to emit light.
  • the light-emitting control signal EM, the third gate control signal Pscan1 and the fourth gate control signal Pscan2 received by the data transistor Tda are high levels
  • the first gate control signal Nscan1, the second gate control signal Nscan2, and the fifth gate control signal are Pscan low levels
  • the first initial signal is transmitted to the anode of the light-emitting device Di
  • the second initial signal is transmitted to the input and output ends of the driving transistor Tdr.
  • the write frame WF includes a first reset phase Si1, a second reset phase Si2, a data write phase Sw, a third reset phase Si3, and a light emitting phase Sd.
  • the hold frame HF includes a fourth reset phase Si4, a fifth reset phase Si5, and a light emitting phase Sd.
  • the control end of the compensation transistor Tc of the sub-pixel Spii located in the Lth row is electrically connected to the first output end O1 of the K+1th level first gate driving circuit GA1 (K+1)
  • the control end of the reset transistor Tr of the sub-pixel Spii located in the Lth row is electrically connected to the first output end O1 of the K-3th level second gate driving circuit GA2 (K-3)
  • the control end of the data transistor Tda of the sub-pixel Spii located in the Lth row is electrically connected to the second output end O2 of the K-level first gate driving circuit GA1 (K) and the second output end O2 of the K-level second gate driving circuit GA2 (K)
  • the K-level gate driving circuit uses the gate control signal output by the first output end O1 of the K-1th level gate driving circuit as the control signal.
  • a display cycle may include one frame or multiple frames.
  • a display cycle includes one frame, that frame corresponds to the write frame WF for the multiple rows of sub-pixels Spi.
  • the first frame F1 corresponds to the write frame WF for the multiple rows of sub-pixels Spi.
  • the 5th level second gate driving circuit GA2 (5) needs to output the 9th level fourth gate control signal Pscan2 (9) to the 10th level fourth gate control signal Pscan2 (10) that meet the high frequency requirement, and also needs to output the 5th level second gate control signal Nscan2 (5) that meets the low frequency requirement. That is, when the same gate driving circuit includes multiple second output modules, the gate driving circuit is still required to output gate control signals with different frequencies.
  • the matching design of the first gate driving unit GM1, the second gate driving unit GM2, the frequency division control signal, and the sub-pixel Spi provided in the present application can meet the above requirements.

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Abstract

一种显示装置，多个子像素（Spi）的补偿晶体管（Tc）的控制端与多级第一栅极驱动电路（GA1）的第一输出端（O1）对应电性连接，多个子像素（Spi）的复位晶体管（Tr）的控制端与多级第二栅极驱动电路（GA2）的第一输出端（O1）对应电性连接，同一子像素（Spi）中，复位晶体管（Tr）接收的第二栅极控制信号（Nscan2）的频率与补偿晶体管（Tc）接收的第一栅极控制信号（Nscan1）的频率相同。

Description

显示装置
本申请要求于2024年04月03日递交的中国专利申请第202410404491.X号的优先权，在此全文引用上述中国专利申请公开的内容以作为本申请的一部分。
技术领域
本申请涉及显示技术领域，具体涉及显示装置。
 背景技术
像素驱动电路中，与驱动晶体管控制端电性连接的补偿晶体管和复位晶体管常采用同一栅极驱动单元中不同级数的栅极驱动电路所输出的栅极控制信号进行控制，且复位晶体管会先于补偿晶体管导通，使复位信号可以作用于驱动晶体管的控制端，实现对驱动晶体管的控制端电位的复位。但在显示面板对应不同的显示区应用不同的显示频率进行显示时，显示面板中对应分频位置的部分子像素会因补偿晶体管所用的栅极控制信号为低频，而复位晶体管所用栅极控制信号仍为高频，导致子像素出现显示异常的问题。
 发明概述
本申请实施例提供一种显示装置，可以改善显示面板中对应分频位置的部分子像素出现显示异常的问题。
本申请实施例提供一种显示装置，包括显示面板以及栅极驱动模块。所述显示面板包括多个子像素，至少一所述子像素包括发光器件、驱动晶体管、补偿晶体管和复位晶体管，所述驱动晶体管被配置为生成驱动电流以驱动所述发光器件发光，所述复位晶体管的输出端及所述补偿晶体管的输出端与所述驱动晶体管的控制端电性连接，所述补偿晶体管的输入端与所述驱动晶体管的输出端电性连接，所述复位晶体管的输入端被配置为接收复位信号。栅极驱动模块与所述显示面板电性连接，栅极驱动模块包括多条传输分频控制信号的分频控制线、第一栅极驱动单元和第二栅极驱动单元。多个分频控制信号包括第一分频控制信号和第二分频控制信号，所述第一栅极驱动单元包括多个级联的第一栅极驱动电路，所述第二栅极驱动单元包括多个级联的第二栅极驱动电路，所述第一栅极驱动电路被配置为根据所述第一分频控制信号控制所生成的第一栅极控制信号的电平，所述第二栅极驱动电路被配置为根据所述第二分频控制信号控制所生成的第二栅极控制信号的电平。其中，所述第一栅极驱动电路和所述第二栅极驱动电路均包括第一输出端，多个所述子像素的所述补偿晶体管的控制端与多级所述第一栅极驱动电路的所述第一输出端对应电性连接，以接收多个所述第一栅极控制信号；多个所述子像素的所述复位晶体管的控制端与多级所述第二栅极驱动电路的所述第一输出端对应电性连接，以接收多个所述第二栅极控制信号；同一所述子像素中，所述复位晶体管接收的所述第二栅极控制信号的频率与所述补偿晶体管接收的所述第一栅极控制信号的频率相同。
 附图说明
图1A~图1B是本申请实施例提供的显示装置的结构示意图；
图2A~图2B是本申请实施例提供的子像素的结构示意图；
图3是相关技术中提供的子像素与栅极驱动模块的连接示意图；
图4A~图4B是相关技术中提供的子像素对应的时序图；
图5A~图5B是本申请实施例提供的第一栅极驱动单元和第二栅极驱动单元的结构示意图；
图6A~图6B是本申请实施例提供的栅极驱动电路的结构示意图；
图7是本申请实施例提供的高频及低频画面显示原理示意图；
图8A~图8D是本申请实施例提供的第一栅极控制信号和第二栅极控制信号的时序图；
图9是本申请实施例提供的子像素对应写入帧和保持帧的时序图。
 本发明的实施方式
为使本申请的目的、技术方案及效果更加清楚、明确，以下参照附图并举实施例对本申请进一步详细说明。应当理解，此处所描述的具体实施例仅用以解释本申请，并不用于限定本申请。
本申请提供一种显示装置，通过使第一栅极驱动单元包括多个级联的第一栅极驱动电路，第二栅极驱动单元包括多个级联的第二栅极驱动电路，第一栅极驱动电路根据第一分频控制信号控制所生成的第一栅极控制信号的电平，第二栅极驱动电路根据第二分频控制信号控制所生成的第二栅极控制信号的电平，多个子像素的补偿晶体管的控制端与多级第一栅极驱动电路输出第一栅极控制信号的第一输出端对应电性连接，多个子像素的复位晶体管的控制端与多级第二栅极驱动电路输出第二栅极控制信号的第一输出端对应电性连接，以使复位晶体管和补偿晶体管不再受控于同一栅极驱动单元生成的栅极控制信号，而是使得补偿晶体管和复位晶体管受控于不同栅极驱动单元生成的栅极控制信号，从而使得一子像素的复位晶体管和另一子像素的补偿晶体管不再因受控于同一栅极控制信号而具有同步的工作状态，而是使不同子像素的复位晶体管和补偿晶体管之间的工作状态得以独立，进而配合第一分频控制信号和第二分频控制信号使同一子像素中，复位晶体管接收的第二栅极控制信号的频率与补偿晶体管接收的第一栅极控制信号的频率相同，从而使显示面板中对应分频位置的部分子像素出现显示异常的问题得以改善。
具体地，图1A~图1B是本申请实施例提供的显示装置的结构示意图，本申请提供一种显示装置，包括显示面板DP以及栅极驱动模块GM，栅极驱动模块GM与显示面板DP电性连接。
可选地，显示面板DP包括自发光显示面板。
显示面板DP包括多个子像素Spi，栅极驱动模块GM与多个子像素Spi电性连接，以配合多个子像素Spi使显示面板DP实现显示功能。
可选地，显示面板DP包括多条扫描线，栅极驱动模块GM与多个子像素Spi通过多条扫描线电性连接。
图2A~图2B是本申请实施例提供的子像素Spi的结构示意图，至少一子像素Spi包括发光器件Di、驱动晶体管Tdr、补偿晶体管Tc和复位晶体管Tr。
可选地，发光器件Di包括发光二极管。可选地，发光器件Di包括有机发光二极管、次毫米发光二极管、微型发光二极管等。
驱动晶体管Tdr与发光器件Di电性连接于第一电压端Vdd和第二电压端Vss之间，驱动晶体管Tdr被配置为生成驱动电流以驱动发光器件Di发光。
可选地，驱动晶体管Tdr的输入端与第一电压端Vdd电性连接，驱动晶体管Tdr的输出端与发光器件Di的阳极电性连接，发光器件Di的阴极与第二电压端Vss电性连接，第一电压端Vdd供给的电压大于第二电压端Vss供给的电压。
复位晶体管Tr的输入端被配置为接收复位线VLr传输的复位信号，复位晶体管Tr的输出端与驱动晶体管Tdr的控制端电性连接。
补偿晶体管Tc的输入端与驱动晶体管Tdr的输出端电性连接，补偿晶体管Tc的输出端与驱动晶体管Tdr的控制端电性连接。
可选地，补偿晶体管Tc和复位晶体管Tr为硅晶体管或氧化物晶体管，补偿晶体管Tc和复位晶体管Tr为P型晶体管或N型晶体管。可选地，为降低驱动晶体管Tdr的控制端向驱动晶体管Tdr输出端及复位线VLr的漏电，补偿晶体管Tc和复位晶体管Tr为氧化物晶体管。为兼容现有制程工艺，补偿晶体管Tc和复位晶体管Tr为N型晶体管。
可以理解的，氧化物晶体管的有源层包括铟镓锌氧化物等。
可选地，多条扫描线包括多条第一扫描线GL1和多条第二扫描线GL2，多个子像素Spi的补偿晶体管Tc的控制端与多条第一扫描线GL1电性连接，多个子像素Spi的复位晶体管Tr的控制端与多条第二扫描线GL2电性连接。
请继续参阅图1A~图1B和图2A~图2B，显示面板DP包括多条数据线DL，至少一子像素Spi还包括数据晶体管Tda，数据晶体管Tda的输入端被配置为接收所对应电性连接的数据线DL传输的数据信号，数据晶体管Tda的输出端与驱动晶体管Tdr的输入端电性连接。
可选地，多条扫描线包括多条第三扫描线GL3，多个子像素Spi的数据晶体管Tda的控制端与多条第三扫描线GL3电性连接。显示装置包括源极驱动芯片SDC，源极驱动芯片SDC与多条数据线DL连接，以输出多个数据信号。
请继续参阅图2A~图2B，至少一子像素Spi还包括第一初始晶体管Ti1、第一发光控制晶体管Te1、第二发光控制晶体管Te2和第一存储电容Cst1。
第一初始晶体管Ti1的输入端被配置为接收第一初始线VL1传输的第一初始信号，第一初始晶体管Ti1的输出端与发光器件Di的阳极电性连接。
第一发光控制晶体管Te1的输入端与第一电压端Vdd电性连接，第一发光控制晶体管Te1的输出端与驱动晶体管Tdr的输入端电性连接。
第二发光控制晶体管Te2的输入端与驱动晶体管Tdr的输出端电性连接，第二发光控制晶体管Te2的输出端与发光器件Di的阳极电性连接。
第一存储电容Cst1的第一端与第一电压端Vdd电性连接，第一存储电容Cst1的第二端与驱动晶体管Tdr的控制端电性连接。
可选地，多条扫描线包括多条第四扫描线GL4和多条发光控制线EL，多条第四扫描线GL4与多个子像素Spi的第一初始晶体管Ti1的控制端电性连接，多条发光控制线EL与多个子像素Spi的第一发光控制晶体管Te1的控制端和第二发光控制晶体管Te2的控制端电性连接。
可选地，请继续参阅图2B，子像素Spi还包括第二存储电容Cst2，第二存储电容Cst2的第一端与数据晶体管Tda的控制端电性连接，第二存储电容Cst2的第二端与驱动晶体管Tdr的控制端电性连接。
可选地，为改善因显示频率切换导致的驱动晶体管Tdr的阈值电压偏移，子像素Spi还包括第二初始晶体管Ti2，第二初始晶体管Ti2的输入端被配置为接收第二初始线VL2传输的第二初始信号，第二初始晶体管Ti2的输出端与驱动晶体管Tdr的输入端电性连接，如图2B所示。
可选地，多条第四扫描线GL4与多个子像素Spi的第二初始晶体管Ti2的控制端电性连接。
图3是相关技术中提供的子像素与栅极驱动模块的连接示意图；在相关技术中，栅极驱动模块GM包括第一子栅极驱动单元gm1、第二子栅极驱动单元gm2和第三子栅极驱动单元gm3，第一子栅极驱动单元gm1包括多个级联的第一子栅极驱动电路ga1，第二子栅极驱动单元gm2包括多个级联的第二子栅极驱动电路ga2，第三子栅极驱动单元gm3包括多个级联的第三子栅极驱动电路ga3。多个第一子栅极驱动电路ga1被配置为向多个子像素Spi的复位晶体管Tr和补偿晶体管Tc提供栅极控制信号，多个第二子栅极驱动电路ga2被配置为向多个子像素Spi的第二初始晶体管Ti2提供栅极控制信号，多个第三子栅极驱动电路ga3被配置为向多个子像素Spi的第一发光控制晶体管Te1和第二发光控制晶体管Te2提供发光控制信号。数据晶体管Tda可受控于第一子栅极驱动单元gm1输出的栅极控制信号，也可受控于其他栅极驱动单元输出的栅极控制信号。第一初始晶体管Ti1可与数据晶体管Tda共用同一栅极驱动单元提供的栅极控制信号，也可由第三子栅极驱动单元gm3提供对应的栅极控制信号。其中，同一子像素Spi中，补偿晶体管Tc的控制端接收的栅极控制信号与复位晶体管Tr的控制端接收的栅极控制信号由不同级的第一子驱动电路生成。如显示面板DP中第n行子像素Spi的复位晶体管Tr的控制端接收的栅极控制信号由第n-2级第一子栅极驱动电路生成，第n行子像素Spi的补偿晶体管Tc的控制端接收的栅极控制信号由第n级第一子栅极驱动电路生成。第一子栅极驱动单元gm1采用双边驱动的设计形式。
图4A~图4B是相关技术中提供的子像素Spi对应的时序图。其中，Pscan对应为第一初始晶体管Ti1的控制端、第二初始晶体管Ti2的控制端接收的栅极控制信号，Pscan_T2对应为数据晶体管Tda的控制端接收的栅极控制信号，Nscan_T3对应为补偿晶体管Tc的控制端接收的栅极控制信号，Nscan_T4对应为复位晶体管Tr的控制端接收的栅极控制信号， EM对应为第一发光控制晶体管Te1和第二发光控制晶体管Te2的控制端接收的栅极控制信号。
其中，子像素Spi采用图4A所示的时序图进行显示时，因复位晶体管Tr和补偿晶体管Tc对应的栅极控制信号具有两次有效脉冲，显示面板DP应用图4A所示的时序无法实现分区分频显示。在子像素Spi采用图4B所示的时序图进行显示时，即使复位晶体管Tr和补偿晶体管Tc对应的栅极控制信号具有一次有效脉冲，但由于同一子像素Spi中，补偿晶体管Tc的控制端接收的栅极控制信号与复位晶体管Tr的控制端接收的栅极控制信号由不同级的第一子栅极驱动电路ga1提供，且复位晶体管Tr会先于补偿晶体管Tc导通，因而，在对应显示面板DP分频位置附近的部分行，子像素Spi中的复位晶体管Tr会根据对应的栅极控制信号导通，使驱动晶体管Tdr的控制端的电位的得以复位，而补偿晶体管Tc会因对应的栅极控制信号为变为低频而保持截止，从而使得子像素Spi中无新数据信息被存储至驱动晶体管Tdr的控制端，也无原数据信号被保留在驱动晶体管Tdr的控制端，导致子像素Spi出现显示异常。
为使显示面板DP可以实现分区分频显示，且改善显示面板DP对应分频位置的部分行的子像素Spi出现显示异常的问题，本申请提供一种显示装置。
请继续参阅图1A~图1B，栅极驱动模块GM包括多条分频控制线FL、第一栅极驱动单元GM1和第二栅极驱动单元GM2。
多条分频控制线FL传输多个分频控制信号，多个分频控制信号包括第一分频控制信号NF1和第二分频控制信号NF2。
第一栅极驱动单元GM1包括多个级联的第一栅极驱动电路GA1，第一栅极驱动电路GA1被配置为根据第一分频控制信号NF1控制所生成的第一栅极控制信号Nscan1的电平。
第二栅极驱动单元GM2包括多个级联的第二栅极驱动电路GA2，第二栅极驱动电路GA2被配置为根据第二分频控制信号NF2控制所生成的第二栅极控制信号Nscan2的电平。
其中，第一栅极驱动电路GA1和第二栅极驱动电路GA2均包括第一输出端O1，第一栅极驱动电路GA1的第一输出端O1输出第一栅极控制信号Nscan1，第二栅极驱动电路GA2的第一输出端O1输出第二栅极控制信号Nscan2。
可选地，多个第一栅极驱动电路GA1的第一输出端O1通过多条第一扫描线GL1与多个子像素Spi电性连接，多个第二栅极驱动电路GA2的第一输出端O1通过多条第二扫描线GL2与多个子像素Spi电性连接。
请继续参阅图1A~图1B和图2A~图2B，多个子像素Spi的补偿晶体管Tc的控制端与多级第一栅极驱动电路GA1的第一输出端O1对应电性连接，多个子像素Spi的复位晶体管Tr的控制端与多级第二栅极驱动电路GA2的第一输出端O1对应电性连接，以使复位晶体管Tr和补偿晶体管Tc不再受控于同一栅极驱动单元生成的栅极控制信号，而是使得补偿晶体管Tc和复位晶体管Tr受控于不同栅极驱动单元生成的栅极控制信号，从而使得一子像素Spi的复位晶体管Tr和另一子像素Spi的补偿晶体管Tc不再因受控于同一栅极控制信号而具有同步的工作状态，而是使不同子像素Spi的复位晶体管Tr和补偿晶体管Tc之间的工作状态得以独立。并且，因第一栅极驱动电路GA1可根据第一分频控制信号NF1实现第一栅极控制信号Nscan1的电平控制，第二栅极驱动电路GA2可根据第二分频控制信号NF2实现第二栅极控制信号Nscan2的电平控制，因而，通过第一分频控制信号NF1和第二分频控制信号NF2，可使同一子像素Spi中，复位晶体管Tr接收的第二栅极控制信号Nscan2的频率与补偿晶体管Tc接收的第一栅极控制信号Nscan1的频率相同，从而使同一子像素Spi中复位晶体管Tr和补偿晶体管Tc的导通频率相同，继而改善显示面板DP中对应分频位置的部分子像素Spi因补偿晶体管Tc所用的栅极控制信号为低频，而复位晶体管Tr所用栅极控制信号仍为高频，导致子像素Spi出现显示异常的问题。
可选地，请继续参阅图1A~图1B，显示面板DP包括显示区AA和位于显示区AA相对两侧的第一非显示区DA1和第二非显示区DA2。其中，多个子像素Spi位于显示区AA，第一栅极驱动单元GM1位于第一非显示区DA1，第二栅极驱动单元GM2位于第二非显示区DA2。通过使第一栅极驱动单元GM1和第二栅极驱动单元GM2分设于第一非显示区DA1和第二显示区DA2，以使显示面板DP的边框尺寸可以被降低。
相应地，因多个子像素Spi的补偿晶体管Tc的控制端与多级第一栅极驱动电路GA1的第一输出端O1对应电性连接，多个子像素Spi的复位晶体管Tr的控制端与多级第二栅极驱动电路GA2的第一输出端O1对应电性连接，因而，对应对多个子像素Spi的补偿晶体管Tc实现了单边驱动设计，对应对多个子像素Spi的复位晶体管Tr实现了单边驱动设计，即多级所述第一栅极驱动电路GA1通过单边驱动的方式电性连接于多个所述子像素Spi的所述补偿晶体管Tc的控制端，多级所述第二栅极驱动电路GA2通过单边驱动的方式电性连接于多个所述子像素Spi的所述复位晶体管Tr的控制端。有利于降低显示面板DP的边框尺寸。
可选地，为节省功耗及缩减显示面板DP的边框尺寸，单个栅极驱动电路可设置成同时输出多个栅极控制信号的形式。相应地，单个栅极驱动电路输出的多个栅极控制信号可用于控制同一子像素Spi中不同晶体管的导通状态。
如第一栅极驱动电路GA1包括第二输出端O2，第一栅极驱动电路GA1的第二输出端O2输出第三栅极控制信号Pscan1。其中，多个子像素Spi的数据晶体管Tda的控制端与多个第一栅极驱动电路GA1的第二输出端O2电性连接，以使多个子像素Spi的数据晶体管Tda受控于多个第一栅极驱动电路GA1输出的第三栅极控制信号Pscan1。
如第二栅极驱动电路GA2包括第二输出端O2，第二栅极驱动电路GA2的第二输出端O2输出第四栅极控制信号Pscan2。其中，多个子像素Spi的数据晶体管Tda的控制端与多个第二栅极驱动电路GA2的第二输出端O2电性连接，以使多个子像素Spi的数据晶体管Tda受控于多个第二栅极驱动电路GA2输出的第四栅极控制信号Pscan2。
如第一栅极驱动电路GA1和第二栅极驱动电路GA2均包括第二输出端O2，第一栅极驱动电路GA1的第二输出端O2输出第三栅极控制信号Pscan1，第二栅极驱动电路GA2的第二输出端O2输出第四栅极控制信号Pscan2。而多个子像素Spi的数据晶体管Tda的控制端与多个第一栅极驱动电路GA1的第二输出端O2和/或多个第二栅极驱动电路GA2的第二输出端O2电性连接。
即在一子像素Spi中，数据晶体管Tda的控制端可与对应的第一栅极驱动电路GA1的第二输出端O2电性连接，也可与对应的第二栅极驱动电路GA2的第二输出端O2电性连接，还可与对应的第一栅极驱动电路GA1的第二输出端O2和对应的第二栅极驱动电路GA2的第二输出端O2电性连接。因此，在一子像素Spi中，数据晶体管Tda的控制端与对应的第一栅极驱动电路GA1的第二输出端O2或对应的第二栅极驱动电路GA2的第二输出端O2电性连接时，形成了单边驱动设计；在一子像素Spi中，数据晶体管Tda的控制端与对应的第一栅极驱动电路GA1的第二输出端O2和对应的第二栅极驱动电路GA2的第二输出端O2电性连接时，形成了双边驱动设计。可选地，多个第一栅极驱动电路GA1的第二输出端O2通过多条第三扫描线GL3与多个子像素Spi电性连接；多个第二栅极驱动电路GA2的第二输出端O2通过多条第三扫描线GL3与多个子像素Spi电性连接。
图5A~图5B是本申请实施例提供的第一栅极驱动单元和第二栅极驱动单元的结构示意图，图6A~图6B是本申请实施例提供的栅极驱动电路的结构示意图。其中，第一栅极驱动电路GA1和第二栅极驱动电路GA2中的至少一个的电路结构如图6A~图6B所示。图6A~图6B中的O21和O22均对应表示第二输出端，Cka和CKb均对应表示第二时钟信号。
第一栅极驱动电路GA1和第二栅极驱动电路GA2中的至少一个包括节点控制模块10、第一分频控制模块20和第一输出模块30。
节点控制模块10与本级栅极驱动电路的第一节点K1电性连接，节点控制模块10被配置为根据对应的启动信号STV和第一时钟信号XCK控制第一节点K1的信号。
可选地，请继续参阅图5A~图5B，多个第一栅极驱动电路GA1中的第1级第一栅极驱动电路GA1(1)将第一起始信号stv1作为启动信号STV，以使第1级第一栅极驱动电路GA1(1)根据对应的第一时钟信号XCK以及第一起始信号stv1，控制第1级第一栅极驱动电路GA1(1)的第一节点K1的信号。多个第二栅极驱动电路GA2中的第1级第二栅极驱动电路GA2(1)将第二起始信号stv2作为启动信号STV，以使第1级第二栅极驱动电路GA2(1)根据对应的第一时钟信号XCK以及第二起始信号stv2，控制第1级第二栅极驱动电路GA2(1)的第一节点K1的信号。
可选地，多个第一栅极驱动电路GA1中的第M级第一栅极驱动电路GA1(M)将第M-A级第一栅极驱动电路GA1(M-A)输出的第M-A级第一栅极控制信号Nscan1(M-A)作为启动信号STV，以使第M级第一栅极驱动电路GA1(M)根据对应的第一时钟信号XCK以及第M-A级第一栅极驱动电路GA1(M-A)输出的第M-A级第一栅极控制信号Nscan1(M-A)，控制第M级第一栅极驱动电路GA1(M)的第一节点K1的信号。其中，M＞1，A≥1。多个第二栅极驱动电路GA2中的第N级第二栅极驱动电路GA2(N)将第N-B级第二栅极驱动电路GA2(N-B)输出的第N-B级第二栅极控制信号Nscan2(N-B)作为启动信号STV，以使第N级第二栅极驱动电路GA2(N)根据对应的第一时钟信号XCK以及第N-B级第二栅极驱动电路GA2(N-B)输出的第N-B级第二栅极控制信号Nscan2(N-B)，控制第N级第二栅极驱动电路GA2的第一节点K1的信号。其中，N＞1，B≥1。
如第1级第一栅极驱动电路GA1(1)的第一输出端O1输出的第1级第一栅极控制信号Nscan1(1)可被第2级第一栅极驱动电路GA1作为启动信号STV。与之相似的，还可得到多个第二栅极驱动电路GA2的级联设置。
需要说明的是，多级栅极驱动电路中的前M级栅极驱动电路可以被称为虚拟栅极驱动电路(如图1A~图1B中的栅极驱动单元所包括的虚线框所示的栅极驱动电路)，以为级联于其后的栅极驱动电路提供对应的启动信号STV。
可选地，请继续参阅图6A~图6B，以第p级第一栅极驱动电路GA1(p)和第p级第二栅极驱动电路GA2(p)中的一个为例，对节点控制模块10的结构进行说明。其中，图6A~图6B对应表示第p级第一栅极驱动电路GA1(p)时，O1(p-1)表示第p-1级第一栅极驱动电路GA1(p-1)的第一输出端。图6A~图6B对应表示第p级第二栅极驱动电路GA2(p)时，O1(p-1)表示第p-1级第二栅极驱动电路GA2(p-1)的第一输出端。其中，p≥1。在p=1时，O1(p-1)对应为第一起始信号stv1或第二起始信号stv2。
如图6A~图6B所示，节点控制模块10包括第一晶体管T1、第二晶体管T2和第三晶体管T3。
第一晶体管T1的第一控制端和第二控制端被配置为接收对应的启动信号STV，第一晶体管T1的输入端与第一电源端PVGL电性连接。
第二晶体管T2的控制端与第一晶体管T1的第一控制端电性连接，第二晶体管T2的输入端与第二电源端PVGH电性连接，第二晶体管T2的输出端与第一晶体管T1的输出端电性连接。
第三晶体管T3的控制端被配置为接收对应的第一时钟信号XCK，第三晶体管T3的输入端与第一晶体管T1的输出端电性连接，第三晶体管T3的输出端与第一节点K1电性连接。
可选地，节点控制模块10还与本级栅极驱动电路的第三节点K3电性连接，节点控制模块10被配置为根据第三节点K3的电位控制第二电源端PVGH或第三电源端NVGL与第一节点K1之间的电性连接。
可选地，节点控制模块10包括第四晶体管T4、第五晶体管T5以及第六晶体管T6。
第四晶体管T4的第一控制端和第二控制端被配置为接收对应的第一时钟信号XCK，第四晶体管T4的输出端与第一节点K1电性连接。第五晶体管T5的控制端和第六晶体管T6的第一控制端、第二控制端与第三节点K3电性连接，第五晶体管T5的输入端与第二电源端PVGH电性连接，第五晶体管T5的输出端与第四晶体管T4的输入端电性连接，第六晶体管T6的输入端与第三电源端NVGL电性连接，第六晶体管T6的输出端与第一节点K1电性连接。
请继续参阅图6A~图6B，节点控制模块10被配置为根据第一节点K1的信号，控制第一电源端PVGL或第二电源端PVGH与第三节点K3之间的信号传输。
可选地，节点控制模块10还包括第七晶体管T7和第八晶体管T8。
第七晶体管T7的第一控制端和第二控制端与第一节点K1电性连接，第七晶体管T7的输入端与第一电源端PVGL电性连接，第七晶体管T7的输出端与第三节点K3电性连接，第八晶体管T8的控制端与第一节点K1电性连接，第八晶体管T8的输入端与第二电源端PVGH电性连接，第八晶体管T8的输出端与第三节点K3电性连接。
请继续参阅图6A~图6B，第一分频控制模块20电性连接于本级栅极驱动电路的第一节点K1、第二节点K2和第三节点K3，第一分频控制模块20被配置为根据所述第三节点K3的信号和对应的分频控制信号控制第一节点K1和第二节点K2之间的信号传输。
可选地，第一分频控制模块20包括第一分频晶体管Tf1、第二分频晶体管Tf2以及第一电容C1。
第一分频晶体管Tf1的控制端与本级栅极驱动电路的第三节点K3电性连接，第一分频晶体管Tf1的输入端被配置为接收对应的分频控制信号(即第一栅极驱动电路GA1中的第一分频晶体管Tf1的输入端被配置为接收第一分频控制信号NF1，第二栅极驱动电路GA2中的第一分频晶体管Tf1的输入端被配置为接收第二分频控制信号NF2)。
第二分频晶体管Tf2的控制端与第一分频晶体管Tf1的输出端电性连接，第二分频晶体管Tf2的输入端与第一节点K1电性连接，第二分频晶体管Tf2的输出端与第二节点K2电性连接。
第一电容C1的第一端与第二分频晶体管Tf2的控制端电性连接，第一电容C1的第二端与第二节点K2电性连接。
请继续参阅图6A~图6B，第一输出模块30与第一节点K1、第二节点K2和第一输出端O1电性连接，第一输出模块30被配置为根据第一节点K1和第二节点K2的信号控制第一输出端O1输出的栅极控制信号。
可选地，第一输出模块30包括第一输出晶体管To1和第二输出晶体管To2。
第一输出晶体管To1的第一控制端和第二控制端与第一节点K1电性连接，第一输出晶体管To1的输入端与第三电源端NVGL电性连接。
第二输出晶体管To2的控制端与第二节点K2电性连接，第二输出晶体管To2的输入端与第四电源端NVGH电性连接，第二输出晶体管To2的输出端和第一输出晶体管To1的输出端与本级栅极驱动电路的第一输出端O1电性连接。
可选地，可对应每一第一栅极驱动电路GA1设置一第一分频控制信号NF1，以实现对每一第一栅极驱动电路GA1输出的第一栅极控制信号Nscan1的电平控制。与之相似的，可对应每一第二栅极驱动电路GA2设置一第二分频控制信号NF2，以实现对每一第二栅极驱动电路GA2输出的第二栅极控制信号Nscan2的电平控制。
可选地，为节省显示装置所用分频控制信号的数量，可以使多个级联的第一栅极驱动电路GA1的第一分频控制模块20共用同一分频控制信号，以实现对多个第一栅极控制信号Nscan1的电平控制。与之相似的，可使多个级联的第二栅极驱动电路GA2的第一分频控制模块20共用同一分频控制信号，以实现对多个第二栅极控制信号Nscan2的电平控制。
为使显示面板DP实现分频显示，同一子像素Spi中，补偿晶体管Tc和复位晶体管Tr的导通时间和导通时长具有区别。因此，控制多个级联的第二栅极驱动电路GA2的第一分频控制模块20所应用的分频控制信号与控制多个级联的第一栅极驱动电路GA1的第一分频控制模块20所应用的分频控制信号不同。
即请继续参阅图5 A~图5B，多条分频控制线FL包括第一分频控制线FL1和第二分频控制线FL2，第一分频控制线FL1传输第一分频控制信号NF1，第二分频控制线FL2传输第二分频控制信号NF2。多级第一栅极驱动电路GA1的第一分频控制模块20与第一分频控制线FL1电性连接，多级第二栅极驱动电路GA2的第一分频控制模块20与第二分频控制线FL2电性连接，以在减少显示装置所用的分频控制信号的数量的同时，使多个子像素Spi的补偿晶体管Tc和复位晶体管Tr的工作状态独立。
可选地，请继续参阅图6 A~图6B，至少一栅极驱动电路还包括第一控制模块40，第一控制模块40与本级栅极驱动电路的第三节点K3和本级栅极驱动电路GDC的第二节点K2电性连接，第一控制模块40被配置为根据对应的第一时钟信号XCK和第三节点K3的电位，控制第二电源端PVGH和第二节点K2之间的信号传输。
可选地，第一控制模块40包括第九晶体管T9和第十晶体管T10。
第九晶体管T9的第一控制端和第二控制端被配置为接收对应的第一时钟信号XCK，第九晶体管T9的输出端与第二节点K2电性连接。
第十晶体管T10的控制端与本级栅极驱动电路的第三节点K3电性连接，第十晶体管T10的输入端与第二电源端PVGH电性连接，第十晶体管T10的输出端与第九晶体管T9的输入端电性连接。
因数据晶体管Tda的控制端所接收的栅极控制信号可由第一栅极驱动单元GM1和第二栅极驱动单元GM2中的至少一个提供，因此，第一栅极驱动单元GM1包括的第一栅极驱动电路GA1和第二栅极驱动单元GM2包括的第二栅极驱动电路GA2中的至少一个还可以包括第二输出模块50，以通过第二输出模块50为对应子像素Spi的数据晶体管Tda提供所需的栅极控制信号。
第二输出模块50与本级栅极驱动电路的第一节点K1、第三节点K3和第二输出端O2电性连接，第二输出模块50被配置为根据第一节点K1和第三节点K3的信号以及对应的第二时钟信号CK控制第二输出端O2输出的栅极控制信号。请继续参阅图6 A~图6B，第二输出模块50包括第三输出晶体管To3、第四输出晶体管To4和第二电容C2。
第三输出晶体管To3的控制端与第一节点K1电性连接，第三输出晶体管To3的输入端被配置为接收对应的第二时钟信号CK。
第四输出晶体管To4的控制端与第三节点K3电性连接，第四输出晶体管To4的输入端与第二电源端PVGH电性连接，第四输出晶体管To4的输出端和第三输出晶体管To3的输出端与本级栅极驱动电路GDC的第二输出端O2电性连接。
第二电容C2的第一端与第三输出晶体管To3的控制端电性连接，第二电容C2的第二端与本级栅极驱动电路GDC的第二输出端O2电性连接。
可选地，第一栅极驱动电路GA1包括X个第二输出模块50和X个第二输出端O2，每一第二输出模块50与一第二输出端O2对应电性连接。其中，X≥1。
即如图6A所示，单个第一栅极驱动电路GA1可以包括一个第二输出模块50，以使单个第一栅极驱动电路GA1可同时输出一第一栅极控制信号Nscan1和一第三栅极控制信号Pscan1。
可选地，如图6B所示，为缩减显示面板DP的边框尺寸，单个第一栅极驱动电路GA1可以包括多个第二输出模块50，以使单个第一栅极驱动电路GA1可同时输出一第一栅极控制信号Nscan1和多个第三栅极控制信号Pscan1。
可选地，为提高第一栅极驱动电路GA1的多个第二输出模块50的利用率，在第一栅极驱动电路GA1包括多个第二输出模块50（即X＞1）时，同一第一栅极驱动电路GA1的X个第二输出模块50被配置为输出多个具有相位差的第三栅极控制信号Pscan1，以使被同一第一栅极驱动电路GA1输出的多个第三栅极控制信号Pscan1驱动的数据晶体管Tda可在不同的时段内被导通，以降低显示装置的功耗。
与之相似的，第二栅极驱动电路GA2包括X个第二输出模块50和X个第二输出端O2，每一第二输出模块50与一第二输出端O2对应电性连接。其中，X≥1。
即如图6A所示，单个第二栅极驱动电路GA2可以包括一个第二输出模块50，以使单个第二栅极驱动电路GA2可同时输出一第二栅极控制信号Nscan2和一个第四栅极控制信号Pscan2。
可选地，如图6B所示，为缩减显示面板DP的边框尺寸，单个第二栅极驱动电路GA2可以包括多个第二输出模块50，以使单个第二栅极驱动电路GA2可同时输出一第二栅极控制信号Nscan2和多个第四栅极控制信号Pscan2。
可选地，为提高第二栅极驱动电路GA2的多个第二输出模块50的利用率，在第二栅极驱动电路GA2包括多个第二输出模块50（即X＞1）时，同一第二栅极驱动电路GA2的X个第二输出模块50被配置为输出多个具有相位差的第四栅极控制信号Pscan2，以使被同一第二栅极驱动电路GA2输出的多个第四栅极控制信号Pscan2驱动的数据晶体管Tda可在不同的时段内被导通，以降低显示装置的功耗。
可选地，每一第二输出端O2可与至少位于一行的多个子像素Spi的数据晶体管Tda的控制端电性连接，以使第一栅极驱动电路GA1输出的每一第三栅极控制信号Pscan1或第二栅极驱动电路GA2输出的每一第四栅极控制信号Pscan2可以驱动至少一行子像素Spi的数据晶体管Tda。
可选地，为使多行子像素Spi可按相同的时间间隔依次被对应的栅极控制信号驱动，相邻两级第一栅极驱动电路GA1所对应的第一时钟信号的相位差为XH，相邻两级第二栅极驱动电路GA2所对应的第一时钟信号的相位差为XH； H表示单位时长。
可选地，H可对应设置为行周期时长。
可选地，第一栅极驱动电路GA1输出的每一第三栅极控制信号Pscan1和/或第二栅极驱动电路GA2输出的每一第四栅极控制信号Pscan2可以驱动一行子像素Spi的数据晶体管Tda，位于第L行~第L+X-1行的子像素Spi的数据晶体管Tda的控制端，与第K级第一栅极驱动电路GA1的X个第二输出端O2和/或第K级第二栅极驱动电路GA2的X个第二输出端O2对应电性连接；其中，K≥1，L= XK-(X-1)。如第一栅极驱动电路GA1和第二栅极驱动电路GA2均包括一第二输出模块50（即X=1），第K级第一栅极驱动电路GA1(K)的第二输出端O2和第K级第二栅极驱动电路GA2(K)的第二输出端O2中的至少一个，与位于第L行（也即第K行）的子像素Spi的数据晶体管Tda的控制端电性连接，以使多个子像素Spi的数据晶体管Tda可匹配补偿晶体管Tc和复位晶体管Tr所用栅极控制信号，完成数据信号的传输工作。
如第一栅极驱动电路GA1和第二栅极驱动电路GA2均包括两第二输出模块50（即X=2），第K级第一栅极驱动电路GA1(K)的第二输出端O2和第K级第二栅极驱动电路GA2(K)的第二输出端O2中的至少一个，与位于第L行（也即第2K-1行）~第L+1行（也即第2K行）的子像素Spi的数据晶体管Tda的控制端电性连接，以使多个子像素Spi的数据晶体管Tda可匹配补偿晶体管Tc和复位晶体管Tr所用栅极控制信号，完成数据信号的传输工作。
可选地，可根据栅极驱动单元包括的第二输出模块50的数量，控制补偿晶体管Tc和复位晶体管Tr应用不同级数的栅极控制信号，以实现子像素Spi刷新显示数据的操作。
如请继续参阅图1A，第一栅极驱动电路GA1和第二栅极驱动电路GA2均包括一第二输出模块50（即X=1），位于第L行的子像素Spi的补偿晶体管Tc的控制端与第K+A级第一栅极驱动电路GA1的第一输出端O1电性连接，位于第L行的子像素Spi的复位晶体管Tr的控制端与第K-B级第二栅极驱动电路GA2的第一输出端O1电性连接。其中，A≥1，B≥1。
需要说明的是，第K+A级第一栅极驱动电路GA1(K+A)即表示级联于第K级第一栅极驱动电路GA1(K)之后，且与第K级第一栅极驱动电路GA1(K)的级数之差为A的第一栅极驱动电路GA1；第K-B级第二栅极驱动电路GA2(K-B)即表示级联于第K级第二栅极驱动电路GA2(K)之前，且与第K级第二栅极驱动电路GA2(K)的级数之差为B的第二栅极驱动电路GA2。因而，对应K=1时，第K-B级第二栅极驱动电路GA2(K-B)即表示级联于第1级第二栅极驱动电路GA2(1)之前，且与第1级第二栅极驱动电路GA2(1)的级数之差为B的第二栅极驱动电路GA2。因此，第二栅极驱动电路GA2的首级第二栅极驱动电路GA2可不被对应为第1级第二栅极驱动电路GA2(1)。
可选地，A=1，B=3。即位于第K行的子像素Spi的补偿晶体管Tc的控制端与第K+1级第一栅极驱动电路GA1(K+1)的第一输出端O1电性连接，位于第K行的子像素Spi的复位晶体管Tr的控制端与第K-3级第二栅极驱动电路GA2(K-3)的第一输出端O1电性连接，以使显示面板DP可以利用补偿晶体管Tc和复位晶体管Tr所接收的栅极控制信号，控制多个子像素Spi实现分区分频显示。
而第一栅极驱动电路GA1包括多个第二输出模块50（即X≥2）时，位于第L行~第L+X-1行的子像素Spi的补偿晶体管Tc的控制端与第K+C级第一栅极驱动电路GA1的第一输出端O1电性连接。其中，C≥0。
如请继续参阅图1B，第一栅极驱动电路GA1包括两第二输出模块50，位于第L行（即对应2K-1行）~第L+X-1行（即对应第2K行）的子像素Spi的补偿晶体管Tc的控制端与第K级第一栅极驱动电路GA1（即C=0）的第一输出端O1电性连接。
再如第一栅极驱动电路GA1包括三个第二输出模块50，位于第L行（即对应3K-2行）~第L+X-1行（即对应第3K行）的子像素Spi的补偿晶体管Tc的控制端与第K级第一栅极驱动电路GA1的第一输出端O1电性连接。
位于第L行的子像素Spi的补偿晶体管Tc的控制端与第K+A级第一栅极驱动电路GA1的第一输出端O1电性连接，位于第L行的子像素Spi的复位晶体管Tr的控制端与第K-B级第二栅极驱动电路GA2的第一输出端O1电性连接。其中，A≥1，B≥1。
而第二栅极驱动电路GA2包括多个第二输出模块50（即X≥2）时，位于第L行的子像素Spi的复位晶体管Tr的控制端与第K-D级第二栅极驱动电路GA2的第一输出端O1电性连接。其中，D≥0。
如请继续参阅图1B，第二栅极驱动电路GA2包括两第二输出模块50，位于第L行（即对应2K-1行）~第L+X-1行（即对应第2K行）的子像素Spi的补偿晶体管Tc的控制端与第K-2级第二栅极驱动电路GA2（即D=2）的第一输出端O1电性连接。
再如第二栅极驱动电路GA2包括三个第二输出模块50，位于第L行（即对应3K-2行）~第L+X-1行（即对应第3K行）的子像素Spi的复位晶体管Tr的控制端与第K-2级第二栅极驱动电路GA2的第一输出端O1电性连接。
可选地，为进一步降低显示装置的功耗，包括第二输出模块50的第一栅极驱动电路GA1和/或第二栅极驱动电路GA2还可以包括第二分频控制模块60，以实现对栅极驱动电路的第二输出端O2输出的栅极控制信号的频率控制。
第二分频控制模块60通过本级栅极驱动电路的第一节点K1和第三节点K3与节点控制模块10电性连接，且通过本级栅极驱动电路的第四节点K4与第二输出模块50电性连接，第二分频控制模块60被配置为根据对应的分频控制信号控制第一节点K1和第四节点K4之间的信号传输，从而通过第二分频控制模块60控制第二输出模块50与第一节点K1的电性连接，而第二输出模块50被配置为根据第三节点K3和第四节点K4的信号以及对应的第二时钟信号CK控制第二输出端O2输出的栅极控制信号。
可选地，请继续参阅图6A~图6B，第二分频控制模块60包括第三分频晶体管Tf3、第四分频晶体管Tf4以及第三电容C3。
第三分频晶体管Tf3的控制端与本级栅极驱动电路的第三节点K3电性连接，第三分频晶体管Tf3的输入端被配置为接收对应的分频控制信号。
第四分频晶体管Tf4的控制端与第三分频晶体管Tf3的输出端电性连接，第四分频晶体管Tf4的输入端与第一节点K1电性连接，第四分频晶体管Tf4的输出端与第四节点K4电性连接。
第三电容C3的第一端与第四分频晶体管Tf4的控制端电性连接，第三电容C3的第二端与第四节点K4电性连接。
可选地，可对应每一第二分频控制模块60设置一分频控制信号，以控制对应的栅极驱动电路自第二输出端O2输出的栅极控制信号的频率。
可选地，为节省显示装置所用分频控制信号的数量，可以使多个级联的第一栅极驱动电路GA1的第二分频控制模块60共用同一分频控制信号，以利用一分频控制信号实现对多个第三栅极控制信号Pscan1的电平控制。与之相似的，可使多个级联的第二栅极驱动电路GA2的第二分频控制模块60共用同一分频控制信号，以利用一分频控制信号实现对多个第四栅极控制信号Pscan2的电平控制。可选地，在第一栅极驱动电路GA1包括一第二输出模块50时，第一栅极驱动电路GA1可包括一第二分频控制模块60，多个级联的第一栅极驱动电路GA1的第二分频控制模块60共用同一分频控制信号，以降低显示装置所用分频控制信号的数量。
可选地，在第一栅极驱动电路GA1包括多个第二输出模块50（即X≥2）时，第一栅极驱动电路GA1可包括至少一第二分频控制模块60。即第一栅极驱动电路GA1可设置一第二分频控制模块60以控制多个第二输出模块50输出的第三栅极控制信号Pscan的电平。第一栅极驱动电路GA1可设置多个第二分频控制模块60，以通过多个第二分频控制模块60控制多个第二输出模块50输出的第三栅极控制信号Pscan的电平，从而实现多个第三栅极控制信号Pscan的电平状态的独立控制。
可选地，第一栅极驱动电路GA1设置多个第二分频控制模块60时，每一第二分频控制模块60被配置为根据对应的分频控制信号控制对应的一第二输出模块50输出的第三栅极控制信号Pscan的电平。
可选地，在第一栅极驱动电路GA1包括多个第二输出模块50（即X≥2）时，第一栅极驱动电路GA1包括一第二分频控制模块60时，多个级联的第一栅极驱动电路GA1的第二分频控制模块60共用同一分频控制信号。如多级第一栅极驱动电路GA1的第二分频控制模块60与第三分频控制线FL3电性连接，以降低显示装置所用分频控制信号的数量。
可选地，在第一栅极驱动电路GA1包括多个第二输出模块50（即X≥2）时，第一栅极驱动电路GA1包括多个第二分频控制模块60时，同一第一栅极驱动电路GA1包括的多个第二分频控制模块60所应用的分频控制信号可以不同。
如每一第一栅极驱动电路GA1包括两第二输出模块50和两第二分频控制模块60，两第二输出模块50包括第一子输出模块和第二子输出模块，两第二分频控制模块60包括第一子分频控制模块和第二子分频控制模块，第一子分频控制模块被配置为根据一分频控制信号控制第一子输出模块输出的第三栅极控制信号Pscan的电平，第二子分频控制模块被配置为根据另一分频控制信号控制第二子输出模块输出的第三栅极控制信号Pscan的电平。其中，第一子输出模块对应的第二输出端可为图6B中的O21，第二子输出模块对应的第二输出端可为图6B中的O22。第一子输出模块对应的第二时钟信号输入端可为图6B中的CKa，第二子输出模块对应的第二时钟信号输入端可为图6B中的CKb。
可选地，多个级联的第一栅极驱动电路GA1的第一子分频控制模块共用同一分频控制信号，多个级联的第一栅极驱动电路GA1的第二子分频控制模块共用同一分频控制信号，以降低显示装置所用分频控制信号的数量。
与之相似的，还可得到第二栅极驱动电路GA2包括X个第二输出模块50时，第二栅极驱动电路GA2所对应的第二分频控制模块60的数量及所适配的分频控制信号的设置。
在子像素Spi需刷新显示数据时，数据晶体管Tda需导通，使数据信号可被传输至驱动晶体管Tdr的控制端。因而，数据晶体管Tda所对应的栅极控制信号也需有特定的时段（如后文所述的数据写入阶段）具有有效电平，因而，控制第一分频控制模块20所应用的分频控制信号可与控制第二分频控制模块60所应用的分频控制信号不同，以使同一栅极驱动电路中，自第一输出端O1输出的栅极控制信号的电平与自第二输出端O2输出的栅极控制信号的电平可被独立控制。
相应地，请继续参阅图5A~图5B，多条分频控制线FL包括第三分频控制线FL3，第三分频控制线FL3传输第三分频控制信号PF1，每一第一栅极驱动电路GA1包括一第二分频控制模块60，多级第一栅极驱动电路GA1的第二分频控制模块60与第三分频控制线FL3电性连接，以在减少显示装置所用的分频控制信号的数量的同时，使多个子像素Spi的数据晶体管Tda和补偿晶体管Tc的工作状态独立。
相应地，多条分频控制线FL包括第四分频控制线FL4，第四分频控制线FL4传输第四分频控制信号PF2，每一第二栅极驱动电路GA2包括一第二分频控制模块60，多级第二栅极驱动电路GA2的第二分频控制模块60与第四分频控制线FL4电性连接，以在减少显示装置所用的分频控制信号的数量的同时，使多个子像素Spi的数据晶体管Tda和复位晶体管Tr的工作状态独立。
相应地，多条分频控制线FL包括第三分频控制线FL3和第四分频控制线FL4，多级第一栅极驱动电路GA1的第二分频控制模块与第三分频控制线FL3电性连接，多级第二栅极驱动电路GA2的第二分频控制模块与第四分频控制线FL4电性连接，以在减少显示装置所用的分频控制信号的数量的同时，使多个子像素Spi的数据晶体管Tda、补偿晶体管Tc、复位晶体管Tr的工作状态独立。
可选地，在数据晶体管Tda的控制端接收的栅极控制信号由第一栅极驱动单元GM1和第二栅极驱动单元GM2同时供给时，为使数据晶体管Tda所对应接收的第三栅极控制信号Pscan1和第四栅极控制信号Pscan2保持相同，以使数据晶体管Tda的工作状态稳定，可使第一栅极驱动单元GM1的第二分频控制模块对应的分频控制线与第二栅极驱动单元GM2的第二分频控制模块对应的分频控制线电性连接，从而使第一栅极驱动单元GM1的第二分频控制模块和第二栅极驱动单元GM2的第二分频控制模块应用相同的分频控制信号。
即位于同行的多个子像素Spi的数据晶体管Tda的控制端与多个第一栅极驱动电路GA1的第二输出端O2和多个第二栅极驱动电路GA2的第二输出端O2电性连接。其中，第三分频控制线FL3和第四分频控制线FL4电性连接，以使子像素Spi中数据晶体管Tda所对应接收的第三栅极控制信号Pscan1和第四栅极控制信号Pscan2保持相同，以使子像素Spi的数据晶体管Tda的工作状态稳定，并且还可降低所用分频控制信号的数量。
可以理解的，在每一第一栅极驱动电路GA1包括多个第二分频控制模块60时，多条分频控制线FL除可包括连接于一第二分频控制模块60的第三分频控制线FL3外，还可包括连接于其余第二分频控制模块60的分频控制线。如每一第一栅极驱动电路GA1包括两第二分频控制模块60，多条分频控制线FL可包括第五分频控制线，每级第一栅极驱动电路GA1的一第二分频控制模块60与第三分频控制线FL3电性连接，每级第一栅极驱动电路GA1的另一第二分频控制模块60与第五分频控制线电性连接，以使每一第一栅极驱动电路GA1中的两第二分频控制模块60的工作状态独立。
与之相似的，在每一第二栅极驱动电路GA1包括多个第二分频控制模块60时，多条分频控制线FL除可包括连接于一第二分频控制模块60的第四分频控制线FL4外，还可包括连接于其余第二分频控制模块60的分频控制线。如每一第二栅极驱动电路GA2包括两第二分频控制模块60，多条分频控制线FL可包括第六分频控制线，每级第二栅极驱动电路GA2的一第二分频控制模块60与第四分频控制线FL4电性连接，每级第二栅极驱动电路GA2的另一第二分频控制模块60与第六分频控制线电性连接，以使每一第二栅极驱动电路GA2中的两第二分频控制模块60的工作状态独立。
相应地，在数据晶体管Tda的控制端接收的栅极控制信号由第一栅极驱动单元GM1和第二栅极驱动单元GM2同时供给，第一栅极驱动电路GA1和第二栅极驱动电路GA2均包括多个第二分频控制模块60时，仍可使位于同行的多个子像素Spi的数据晶体管Tda的控制端，接收的第三栅极控制信号Pscan1和第四栅极控制信号Pscan2所对应的第二分频控制模块应用的分频控制信号保持相同。如位于同行的多个子像素Spi的数据晶体管Tda的控制端，接收的第三栅极控制信号Pscan1和第四栅极控制信号Pscan2所对应的第二分频控制模块应用的分频控制信号为第五分频控制线和第六分频控制线传输的信号，那么可控制第五分频控制线和第六分频控制线电性连接，以为使数据晶体管Tda所对应接收的第三栅极控制信号Pscan1和第四栅极控制信号Pscan2保持相同，从而使数据晶体管Tda的工作状态稳定。
因第一栅极驱动单元GM1包括的第1级第一栅极驱动电路GA1(1)应用第一起始信号stv1作为启动信号STV，第二栅极驱动单元GM2包括的第1级第二栅极驱动电路GA2(1)应用第二起始信号stv2作为启动信号STV，第一起始信号和第二起始信号的相位差异和第一栅极驱动单元GM1中每级第一栅极驱动电路GA1与第二栅极驱动单元GM2中同级的第二栅极驱动电路GA2的相位差异相同。因而，在数据晶体管Tda的控制端同时接收第三栅极控制信号Pscan1和第四栅极控制信号Pscan2时，可控制第一起始信号stv1和第二起始信号stv2对应自有效电平至无效电平的跳变时刻保持相同，以使一子像素Spi的数据晶体管Tda所对应接收的第三栅极控制信号Pscan1和第四栅极控制信号Pscan2保持相同，从而使数据晶体管Tda的工作状态稳定。
即多级第一栅极驱动电路GA1中的第1级第一栅极驱动电路GA1(1)对应的启动信号STV（如前述的第一起始信号stv1）于第一时刻具有有效电平至无效电平的跳变，多级第二栅极驱动电路GA2中的第1级第二栅极驱动电路GA2(1)对应的启动信号STV（如前述的第二起始信号stv2）于第一时刻具有有效电平至无效电平的跳变。其中，第一时刻可参阅后文图8A中的ta所示。
可以理解的是，若晶体管为N型晶体管，那么，该晶体管的控制端对应接收的信号具有有效电平即为该晶体管的控制端对应接收的信号具有高电平，该晶体管的控制端对应接收的信号具有无效电平即为该晶体管的控制端对应接收的信号具有低电平。若晶体管为P型晶体管，那么，该晶体管的控制端对应接收的信号具有有效电平即为该晶体管的控制端对应接收的信号具有低电平，该晶体管的控制端对应接收的信号具有无效电平即为该晶体管的控制端对应接收的信号具有高电平。
可选地，第一起始信号stv1和第二起始信号stv2的有效电平的脉宽可以相同或不同。
可选地，在一些实施例中，在一子像素Spi中，当补偿晶体管Tc对应的第一栅极控制信号Nscan1和复位晶体管Tr对应的第二栅极控制信号Nscan2降为低频后，数据晶体管Tda对应的栅极控制信号（即第三栅极控制信号Pscan1和/或第四栅极控制信号Pscan2）可以保持高频，也可以降为低频。
如以显示面板DP实现一静态画面显示为例，结合图7的本申请实施例提供的高频及低频画面显示原理示意图进行说明，当显示面板DP以高频（如120Hz）进行显示时，显示面板DP需在1秒内执行120次显示数据的刷新操作，即1秒内包含120帧画面，每一帧显示均进行显示数据的刷新。当显示面板DP以低频（如1Hz）进行显示时，显示面板DP在1秒内也会也包含120帧画面，但只有第一帧画面执行显示数据的刷新操作，第一帧之后连续的119帧画面均保持第一帧的画面数据信号，而不执行显示数据的刷新操作。其中，进行显示数据刷新的帧可被记为写入帧WF，不进行显示数据刷新的帧可被记为保持帧HF。那么，在写入帧WF，补偿晶体管Tc对应的第一栅极控制信号Nscan1、复位晶体管Tr对应的第二栅极控制信号Nscan2和数据晶体管Tda对应的栅极控制信号均需具有有效电平，才能使驱动晶体管Tdr控制端存储的原有的数据信号被新写入的数据信号覆盖，以使子像素Spi在写入帧重新根据新写入的数据信号实现显示。而在保持帧HF，部分子像素Spi的补偿晶体管Tc对应的第一栅极控制信号Nscan1和复位晶体管Tr对应的第二栅极控制信号Nscan2保持无效电平，使补偿晶体管Tc和复位晶体管Tr截止，以使驱动晶体管Tdr的控制端不存入新的数据信号。在保持帧HF，数据晶体管Tda对应的栅极控制信号可以保持与写入帧WF相同的频率。或者，在保持帧HF，数据晶体管Tda对应的栅极控制信号可以保持为无效电平，以使数据晶体管Tda对应的栅极控制信号在保持帧HF具有的频率低于写入帧WF具有的频率。
可选地，在一些实施例中，在保持帧HF，数据晶体管Tda根据对应的栅极控制信号导通，以利用数据晶体管Tda对应电性连接的数据线DL所传输的信号，对驱动晶体管Tdr的输入端的电位进行复位。
可选地，在一些实施例中，在保持帧HF，数据晶体管Tda根据对应的栅极控制信号保持截止，第二初始晶体管Ti2根据对应的第四扫描线GL4传输的栅极控制信号具有导通时段，以利用第二初始晶体管Ti2对应电性连接的第二初始线VL2传输的第二初始信号，对驱动晶体管Tdr的输入端的电位进行复位。
可选地，请继续参阅图6A~图6B，至少一栅极驱动电路GDC还包括开关模块70，开关模块70电性连接于第二分频控制模块60和第四节点K4之间，开关模块70被配置为根据对应的开关控制信号SC控制第二分频控制模块60和第四节点K2之间的电性连接。
可选地，开关模块70包括第十一晶体管T11，第十一晶体管T11的控制端被配置为接收开关控制信号SC，第十一晶体管T11的输入端与第四分频晶体管Tf4的输出端电性连接，第十一晶体管T11的输出端与第四节点电性连接。
可选地，第K级第一栅极驱动电路GA1(K)的第十一晶体管T11的控制端被配置为接收第K-E级第一栅极驱动电路GA1 (K-E)输出的第K-E级第一栅极控制信号Nscan1 (K-E)，以将第K-E级第一栅极驱动电路GA1(K-E)输出的第K-E级第一栅极控制信号Nscan1 (K-E)，作为第K级第一栅极驱动电路GA1 (K)的第十一晶体管T11的控制端所接收的开关控制信号SC。其中，E≥1。
可选地，第1级第一栅极驱动电路GA1(1)~第2级第一栅极驱动电路GA1(2)的第十一晶体管T11的控制端接收的开关控制信号SC对应为低电平信号VGL，位于第2级第一栅极驱动电路GA1(2)之后的各级栅极驱动电路的第十一晶体管T11的控制端被配置为接收前2级第一栅极驱动电路GA1输出的第一栅极控制信号Nscan1（如图5A~图5B所示的第3级第一栅极驱动电路GA1(3)的第十一晶体管T11的控制端被配置为接收第1级第一栅极驱动电路GA1(1)输出的第1级第一栅极控制信号Nscan1(1)。与之相似的，还可得到第二栅极驱动单元GM2中各级第二栅极驱动电路GA2所对应的开关控制信号SC。
可选地，第十一晶体管T11的控制端与前级栅极驱动电路的第三节点K3电性连接，以利用前级栅极驱动电路的第三节点K3的电位作为开关控制信号SC，控制第十一晶体管T11的工作状态，降低栅极驱动电路的第一输出端O1所带负载。如第K级第一栅极驱动电路GA1(K)的第十一晶体管T11的控制端与第K-E级第一栅极驱动电路GA1(K-E)的第三节点K3电性连接，以将第K-E级第一栅极驱动电路GA1 (K-E)的第三节点K3的电位，作为第K级第一栅极驱动电路GA1 (K)的第十一晶体管T11的控制端所接收的开关控制信号SC。
可选地，请继续参阅图6A~图6B，至少一栅极驱动电路还包括第二控制模块80，第二控制模块80与本级栅极驱动电路GDC的第三节点K3和开关模块70电性连接，第二控制模块80被配置为根据对应的第一时钟信号XCK和第三节点K3的电位，控制第二电源端PVGH和开关模块70之间的信号传输。
可选地，第二控制模块80包括第十二晶体管T12和第十三晶体管T13。
第十二晶体管T12的第一控制端和第二控制端被配置为接收对应的第一时钟信号XCK，第十二晶体管T12的输出端与第十一晶体管T11的输入端电性连接。
第十三晶体管T13的控制端与本级栅极驱动电路GDC的第三节点K3电性连接，第十三晶体管T13的输入端与第二电源端PVGH电性连接，第十三晶体管T13的输出端与第十二晶体管T12的输入端电性连接。
可选地，请继续参阅图6 A~图6B，至少一栅极驱动电路GDC还包括重置模块90，重置模块90与第一节点K1电性连接，重置模块90被配置为根据重置控制信号Ctl控制第二电源端PVGH和第一节点K1之间的信号传输。
可选地，重置模块90包括重置晶体管Tre，重置晶体管Tre的控制端被配置为接收重置控制信号Ctl，重置晶体管Tre的输入端与第二电源端PVGH电性连接，重置晶体管Tre的输出端与第一节点K1电性连接。
可选地，重置模块90被配置为在显示装置开机时和/或消隐间隔期间启用。
可选地，在一些实施例中，第一电源端PVGL对应的电压小于第二电源端PVGH对应的电压，第三电源端NVGL对应的电压小于第四电源端NVGH对应的电压。
可选地，在一些实施例中，第一晶体管T1、第四晶体管T4、第六晶体管T6、第七晶体管T7、第九晶体管T9、第十二晶体管T12和第一输出晶体管To1中的至少一个，可以对应仅具有一个控制端。
可以理解的，栅极驱动电路GDC包括的各晶体管可以为P型晶体管和N型晶体管中的一种。栅极驱动电路GDC包括的各晶体管的半导体可以为硅半导体和氧化物半导体中的一种。
可选地，可复用多条时钟信号线传输的时钟信号作为多个级联的栅极驱动电路对应的第一时钟信号和第二时钟信号，以降低显示装置的功耗，并降低显示面板DP的边框尺寸。
可选地，第一栅极驱动单元GM1包括的多个第一栅极驱动电路GA1可共用F条时钟线传输的时钟信号作为对应的第一时钟信号和第二时钟信号。其中，F为2、4、6、8等。如请继续参阅图5A，以F等于4为例进行说明，多条时钟线包括第一时钟线CKL1、第二时钟线CKL2、第三时钟线CKL3及第四时钟线CKL4。其中，第一栅极驱动电路GA1包括一第二输出模块50时，第4m+1级第一栅极驱动电路GA1(4m+1)对应的第一时钟信号XCK对应为第二时钟线CKL2传输的信号，第4m+1级第一栅极驱动电路GA1(4m+1)对应的第二时钟信号CK对应为第一时钟线CKL1传输的信号；第4m+2级第一栅极驱动电路GA1(4m+2)对应的第一时钟信号XCK对应为第三时钟线CKL3传输的信号，第4m+2级第一栅极驱动电路GA1(4m+2)对应的第二时钟信号CK对应为第二时钟线CKL2传输的信号；第4m+3级第一栅极驱动电路GA1(4m+3)对应的第一时钟信号XCK对应为第四时钟线CKL4传输的信号，第4m+3级第一栅极驱动电路GA1(4m+3)对应的第二时钟信号CK对应为第三时钟线CKL3传输的信号；第4m+4级第一栅极驱动电路GA1(4m+4)对应的第一时钟信号XCK对应为第一时钟线CKL1传输的信号，第4m+4级第一栅极驱动电路GA1(4m+4)对应的第二时钟信号CK对应为第四时钟线CKL4传输的信号。m≥0。
可选地，每一第一栅极驱动电路GA1包括多个第二输出模块50（X≥2）时，第一栅极驱动单元GM1包括的多个第一栅极驱动电路GA1共用F条时钟线传输的时钟信号作为对应的第二时钟信号CK。其中，F=2X。
如请继续参阅图5B，以每一第一栅极驱动电路GA1包括两第二输出模块50（X=2），第一栅极驱动单元GM1包括的多个第一栅极驱动电路GA1共用4条时钟线传输的时钟信号作为对应的第二时钟信号CK为例。多条时钟线包括第一时钟线CKL1、第二时钟线CKL2、第三时钟线CKL3及第四时钟线CKL4。其中，第一时钟线CKL1向第2k+1级第一栅极驱动电路GA1(2k+1)的一第二输出模块50传输对应的第二时钟信号CK，第二时钟线CKL2向第2k+1级第一栅极驱动电路GA1(2k+1) 的另一第二输出模块50传输对应的第二时钟信号CK；第三时钟线CKL3向第2k+2级第一栅极驱动电路GA1(2k+2)的一第二输出模块传输对应的第二时钟信号CK，第四时钟线CKL4向第2k+2级第一栅极驱动电路GA1(2k+2)的另一第二输出模块传输对应的第二时钟信号CK，k≥0。
与之相似的，每一第一栅极驱动电路GA1包括三个第二输出模块50（X=3）时，第一栅极驱动单元GM1包括的多个第一栅极驱动电路GA1可共用6条时钟线传输的时钟信号作为对应的第二时钟信号CK。
如以每一第一栅极驱动电路GA1的三个第二输出模块包括第一子输出模块、第二子输出模块和第三子输出模块，多条时钟线还可包括第五时钟线CKL5和第六时钟线CKL6为例进行说明。
第一时钟线CKL1向第2k+1级第一栅极驱动电路GA1(2k+1)的第一子输出模块传输对应的第二时钟信号CK，第二时钟线CKL2向第2k+1级第一栅极驱动电路GA1(2k+1)的第二子输出模块传输对应的第二时钟信号CK，第三时钟线CKL3向第2k+1级第一栅极驱动电路GA1(2k+1)的第三子输出模块传输对应的第二时钟信号CK；第四时钟线CKL4向第2k+2级第一栅极驱动电路GA1(2k+2)的第一子输出模块传输对应的第二时钟信号CK，第五时钟线CKL5向第2k+2级第一栅极驱动电路GA1(2k+2)的第二子输出模块传输对应的第二时钟信号CK，第六时钟线CKL6向第2k+2级第一栅极驱动电路GA1(2k+2)的第三子输出模块传输对应的第二时钟信号CK。
或者，第五时钟线CKL5向第2k+1级第一栅极驱动电路GA1(2k+1)的第一子输出模块传输对应的第二时钟信号CK，第六时钟线CKL6向第2k+1级第一栅极驱动电路GA1(2k+1)的第二子输出模块传输对应的第二时钟信号CK，第一时钟线CKL1向第2k+1级第一栅极驱动电路GA1(2k+1)的第三子输出模块传输对应的第二时钟信号CK；第二时钟线CKL2向第2k+2级第一栅极驱动电路GA1(2k+2)的第一子输出模块传输对应的第二时钟信号CK，第三时钟线CKL3向第2k+2级第一栅极驱动电路GA1(2k+2)的第二子输出模块传输对应的第二时钟信号CK，第四时钟线CKL4向第2k+2级第一栅极驱动电路GA1(2k+2)的第三子输出模块传输对应的第二时钟信号CK。
或者，第六时钟线CKL6向第2k+1级第一栅极驱动电路GA1(2k+1)的第一子输出模块传输对应的第二时钟信号CK，第一时钟线CKL1向第2k+1级第一栅极驱动电路GA1(2k+1)的第二子输出模块传输对应的第二时钟信号CK，第二时钟线CKL2向第2k+1级第一栅极驱动电路GA1(2k+1)的第三子输出模块传输对应的第二时钟信号CK；第三时钟线CKL3向第2k+2级第一栅极驱动电路GA1(2k+2)的第一子输出模块传输对应的第二时钟信号CK，第四时钟线CKL4向第2k+2级第一栅极驱动电路GA1(2k+2)的第二子输出模块传输对应的第二时钟信号CK，第五时钟线CKL5向第2k+2级第一栅极驱动电路GA1(2k+2)的第三子输出模块传输对应的第二时钟信号CK。
需要说明的是，第一时钟线CKL1传输的时钟信号与第二时钟线CKL2传输的时钟信号的相位差为φ1，第二时钟线CKL2传输的时钟信号与第三时钟线CKL3传输的时钟信号的相位差为φ2，第三时钟线CKL3传输的时钟信号与第四时钟线CKL4传输的时钟信号的相位差为φ3，第四时钟线CKL4传输的时钟信号与第五时钟线CKL5传输的时钟信号的相位差为φ4，第五时钟线CKL5传输的时钟信号与第六时钟线CKL6传输的时钟信号的相位差为φ5，第六时钟线CKL6传输的时钟信号与第六时钟线CKL6传输的时钟信号的相位差为φ6。其中，φ1=φ2=φ3=φ4=φ5=φ6。
可选地，每一第一栅极驱动电路GA1包括多个第二输出模块50（X≥2）时，第一栅极驱动单元GM1包括的多个第一栅极驱动电路GA1共用F条时钟线中的多条时钟线所传输的时钟信号作为对应的第一时钟信号XCK。
如请继续参阅图5B，以每一第一栅极驱动电路GA1包括两第二输出模块50（X=2），第一栅极驱动单元GM1包括的多个第一栅极驱动电路GA1共用4条时钟线传输的时钟信号为例。第三时钟线CKL1向第2k+1级第一栅极驱动电路GA1(2k+1)传输对应的第一时钟信号XCK，第一时钟线向第2k+2级第一栅极驱动电路GA1(2k+2)传输对应的第一时钟信号XCK。
如以每一第一栅极驱动电路GA1三个第二输出模块50，三个第二输出模块50包括第一子输出模块、第二子输出模块和第三子输出模块为例。第四时钟线CKL4向第2k+1级第一栅极驱动电路GA1(2k+1)传输对应的第一时钟信号XCK，第一时钟线CKL1向第2k+2级第一栅极驱动电路GA1(2k+2)传输对应的第一时钟信号XCK。
可选地，在每一第一栅极驱动电路GA1包括多个第二输出模块50（X≥2）时，可独立设置多条时钟线，以为多级第一栅极驱动电路GA1提供对应的第一时钟信号XCK，以使F条时钟线中，不再有部分时钟线同时为多级第一栅极驱动电路GA1提供对应的第一时钟信号XCK和第二时钟信号CK，以使多条时钟线对应的负载相近，进而提高多级第一栅极驱动电路GA1输出的第三栅极控制信号Pscan1的质量。
与之相似的，还可根据相邻两级第一栅极驱动电路GA1所对应的第一时钟信号XCK的相位差为XH，相邻两级第一栅极驱动电路GA1中第一子输出模块输出的第三栅极控制信号的相位差为XH，相邻两级第一栅极驱动电路GA1中第二子输出模块输出的第三栅极控制信号的相位差为XH类似的设计原理，得到每一第一栅极驱动电路GA1包括更多个第二输出模块50时，多级第一栅极驱动电路GA1与多条时钟线的匹配连接关系。
可选地，第二栅极驱动单元GM2包括的多个第一栅极驱动电路GA1可共用G条时钟线传输的时钟信号作为对应的第一时钟信号XCK和第二时钟信号CK。其中，G为2、4、6、8等。
可选地，第一栅极驱动单元GM1对应的时钟线的数量可以与第二栅极驱动单元GM2对应的时钟线的数量相同或不同。
可以理解的，可参照多级第一栅极驱动电路GA1与多条时钟线的匹配连接关系，得到多级第二栅极驱动电路GA2与多条时钟线的匹配连接关系。
可选地，第一栅极驱动单元GM1可以与第二栅极驱动单元GM2共用多条时钟线，也可以不共用多条时钟线。
可选地，第一栅极驱动单元GM1与第二栅极驱动单元GM2共用多条时钟线，以降低因第一栅极驱动单元GM1和第二栅极驱动单元GM2应用的时钟线不同，第一栅极驱动单元GM1和第二栅极驱动单元GM2应用的时钟信号变化步调不一致等因素，导致第一栅极驱动单元GM1生成的栅极控制信号与第二栅极驱动生成的栅极控制信号之间出现匹配关系不对应或匹配时序不一致的情况。第一栅极驱动单元GM1与第二栅极驱动单元GM2共用多条时钟线，可以提高第一栅极驱动单元GM1和第二栅极驱动单元GM2之间的协同配合度，还有利于降低所用时钟线数量，降低功耗。
此外，在数据晶体管Tda的控制端接收的栅极控制信号由第一栅极驱动单元GM1和第二栅极驱动单元GM2同时供给时，第一栅极驱动单元GM1与第二栅极驱动单元GM2共用多条时钟线，还可有利于使子像素Spi中数据晶体管Tda所对应接收的第三栅极控制信号Pscan1和第四栅极控制信号Pscan2保持相同，提高数据晶体管Tda的工作稳定性。
如请继续参阅图5A，以第一栅极驱动电路GA1和第二栅极驱动单元GA2均包括一第二输出模块50，第一栅极驱动单元GM1与第二栅极驱动单元GM2共用四条时钟线为例，对第一栅极驱动单元GM1、第二栅极驱动单元GM2与多条时钟线的连接关系进行说明。第4m+1级第一栅极驱动电路GA1(4m+1)和第4m+1级第二栅极驱动电路GA2(4m+1)对应的第一时钟信号XCK对应为第二时钟线CKL2传输的信号，第4m+1级第一栅极驱动电路GA1(4m+1)和第4m+1级第二栅极驱动电路GA2(4m+1)对应的第二时钟信号CK对应为第一时钟线CKL1传输的信号；第4m+2级第一栅极驱动电路GA1(4m+2)和第4m+2级第二栅极驱动电路GA2(4m+2)对应的第一时钟信号XCK对应为第三时钟线CKL3传输的信号，第4m+2级第一栅极驱动电路GA1(4m+2)和第4m+2级第二栅极驱动电路GA2(4m+2)对应的第二时钟信号CK对应为第二时钟线CKL2传输的信号；第4m+3级第一栅极驱动电路GA1(4m+3)和第4m+3级第二栅极驱动电路GA2(4m+3)对应的第一时钟信号XCK对应为第四时钟线CKL4传输的信号，第4m+3级第一栅极驱动电路GA1(4m+3)和第4m+3级第二栅极驱动电路GA2(4m+3)对应的第二时钟信号CK对应为第三时钟线CKL3传输的信号；第4m+4级第一栅极驱动电路GA1(4m+4)和第4m+4级第二栅极驱动电路GA2(4m+4)对应的第一时钟信号XCK对应为第一时钟线CKL1传输的信号，第4m+4级第一栅极驱动电路GA1(4m+4)和第4m+4级第二栅极驱动电路GA2(4m+4)对应的第二时钟信号CK对应为第四时钟线CKL4传输的信号。其中，m≥0。
如请继续参阅图5B，以第一栅极驱动电路GA1和第二栅极驱动单元GA2均包括两第二输出模块50，第一栅极驱动单元GM1与第二栅极驱动单元GM2共用四条时钟线为例，第一时钟线CKL1向第2k+1级第一栅极驱动电路GA1(2k+1)的一第二输出模块和第2k+1级第二栅极驱动电路GA2(2k+1) 的一第二输出模块传输对应的第二时钟信号CK，第二时钟线CKL2向第2k+1级第一栅极驱动电路GA1(2k+1) 的另一第二输出模块和第2k+1级第二栅极驱动电路GA2(2k+1) 的另一第二输出模块传输对应的第二时钟信号CK；第三时钟线CKL3向第2k+2级第一栅极驱动电路GA1(2k+2)的一第二输出模块和第2k+2级第二栅极驱动电路GA2(2k+2) 的一第二输出模块传输对应的第二时钟信号CK，第四时钟线CKL4向第2k+2级第一栅极驱动电路GA1(2k+2)的另一第二输出模块和第2k+2级第二栅极驱动电路GA2(2k+2) 的另一第二输出模块传输对应的第二时钟信号CK。
相应可选地，第三时钟线CKL1向第2k+1级第一栅极驱动电路GA1(2k+1)和第2k+1级第二栅极驱动电路GA2(2k+1)传输对应的第一时钟信号XCK，第一时钟线向第2k+2级第一栅极驱动电路GA1(2k+2)和第2k+2级第二栅极驱动电路GA2(2k+2)传输对应的第一时钟信号XCK。
与之相似的，还可得到第一栅极驱动单元GM1与第二栅极驱动单元GM2均包括更多个第二输出模块时，第一栅极驱动单元GM1、第二栅极驱动单元GM2与多条时钟线的连接关系。
需要说明的是，第一栅极驱动电路GA1和第二栅极驱动电路GA2的电路结构可以相同，也可不同。如在一些实施例中，第一栅极驱动电路GA1和第二栅极驱动电路GA2均可采用图6A~图6B所示的电路结构。而在另一些实施例中，第一栅极驱动电路GA1和第二栅极驱动电路GA2中的一个采用图6A~图6B所示的电路结构，第一栅极驱动电路GA1和第二栅极驱动电路GA2中的另一个采用相关技术中可以实现分频控制的电路结构。
通过控制第一分频控制信号NF1的电平状态，可以控制多级第一栅极驱动电路GA1输出的第一栅极控制信号Nscan1的电平状态。与之相似地，通过控制第一栅极驱动电路GA1的第二分频模块对应的分频控制信号的电平状态，可以控制多级第一栅极驱动电路GA1输出的第三栅极控制信号Pscan1的电平状态。与之相似地，通过控制第二分频控制信号NF2的电平状态，可以控制多级第二栅极驱动电路GA2输出的第二栅极控制信号Nscan2的电平状态。与之相似地，通过控制第二栅极驱动电路GA2的第二分频模块对应的电平状态，可以控制多级第二栅极驱动电路GA2输出的第四栅极控制信号Pscan2的电平状态。
图8A~图8D是本申请实施例提供的第一栅极控制信号和第二栅极控制信号的时序图。其中，图8A~图8B对应为每一栅极驱动电路包括一第二输出模块的时序图，图8C~图8D对应为每一栅极驱动电路包括两第二输出模块的时序图。图8C~图8D中的Nscan可对应表示为第一栅极控制信号，也可对应表示为第二栅极控制信号，图8C~图8D中的Pscan可对应表示为第三栅极控制信号，也可对应表示为第四栅极控制信号。
以第二晶体管T2、第三晶体管T3、第五晶体管T5、第八晶体管T8、第十晶体管T10、第十一晶体管T11、第十三晶体管T13、第一分频晶体管Tf1~第四分频晶体管Tf4、第二输出晶体管To2~第四输出晶体管To4为P型晶体管，第一晶体管T1、第四晶体管T4、第六晶体管T6、第七晶体管T7、第九晶体管T9、第十二晶体管T12和第一输出晶体管To1为N型晶体管，第1级第一栅极驱动电路GA1采用第一起始信号stv1作为启动信号，第1级第二栅极驱动电路GA2采用第二起始信号stv2作为启动信号；第p级第一栅极驱动电路GA1(p)采用第p-1级第一栅极驱动电路GA1(p-1)的第一输出端O1输出的第一栅极控制信号Nscan1(p-1)作为启动信号STV，第p级第二栅极驱动电路GA2(p)采用第p-1级第二栅极驱动电路GA2(p-1)的第一输出端O1输出的第二栅极控制信号Nscan2(p-1)作为启动信号STV，第p级第一栅极驱动电路GA1(p)对应的开关控制信号SC为第p-2级第一栅极驱动电路GA1(p-2)输出的第p-2级第一栅极控制信号Nscan1(p-2)，第p级第二栅极驱动电路GA2(p)对应的开关控制信号SC为第p-2级第二栅极驱动电路GA2(p-2)输出的第p-2级第二栅极控制信号Nscan2(p-2)为例，对第一栅极驱动单元GM1和第二栅极驱动单元GM2的的工作原理进行说明。其中，p>1；对应图8A~图8B中，第p级第一栅极驱动电路GA1(p)和第p级第二栅极驱动电路GA2(p)对应的第一时钟信号XCK由第二时钟线CKL2提供，对应的第二时钟信号CK由第一时钟线CKL1提供。对应图8C~图8D中，第p级第一栅极驱动电路GA1(p)和第p级第二栅极驱动电路GA2(p)对应的第一时钟信号XCK由第一时钟线CKL1提供，对应的第二时钟信号CK由第三时钟线CKL3和第四时钟线CKL4提供，且对应图8C~图8D的每一栅极驱动电路包括一第二分频控制模块。
请继续参阅图5A、图6A、图8A~图8B，以第一分频控制信号NF1和第二分频控制信号NF2对应具有低电平状态至高电平状态的跳变为例进行说明。
第一阶段t1，第一时钟线CKL1传输的第一个时钟信号CK1具有高电平，第二时钟线CKL2传输的第二个时钟信号CK2具有低电平，第三时钟线CKL3传输的第三个时钟信号CK3具有高电平，第四时钟线CKL4传输的第四个时钟信号CK4具有高电平。第p-1级第一栅极控制信号Nscan1(p-1)~第p-2级第一栅极控制信号Nscan1(p-2)和第p-1级第二栅极控制信号Nscan2(p-1)~第p-2级第二栅极控制信号Nscan2(p-2)为低电平。第一分频控制信号NF1、第二分频控制信号NF2、第三分频控制信号PF1、第四分频控制信号PF2为低电平。
第一时钟信号XCK对应由第二时钟线CKL2提供，第二时钟信号CK对应由第一时钟线CKL1提供的第一栅极驱动电路GA1和第二栅极驱动电路GA2（如第p级第一栅极驱动电路GA1(p)和第p级第二栅极驱动电路GA2(p)等）中，第二晶体管T2、第三晶体管T3、第五晶体管T5、第七晶体管T7、第十晶体管T10、第十一晶体管T11、第十三晶体管T13、第一分频晶体管Tf1~第四分频晶体管Tf4、第一输出晶体管To1和第四输出晶体管To4导通，第一晶体管T1、第四晶体管T4、第六晶体管T6、第八晶体管T8、第九晶体管T9、第十二晶体管T12、第二输出晶体管To2、第三输出晶体管To3截止，第三电源端NVGL与第一输出端O1电性连接，第二电源端PVGH与第二输出端O2电性连接。
第一时钟信号XCK对应不由第二时钟线CKL2提供，第二时钟信号CK对应不由第一时钟线CKL1提供的第一栅极驱动电路GA1和第二栅极驱动电路GA2（如第p+1级第一栅极驱动电路GA1(p+1)~第p+3级第一栅极驱动电路GA1(p+3)和第p+1级第二栅极驱动电路GA2(p+1)~第p+3级第二栅极驱动电路GA2(p+3)等）中，第三晶体管T3截止。因而，第一时钟信号XCK对应不由第二时钟线CKL2提供，第二时钟信号CK对应不由第一时钟线CKL1提供的第一栅极驱动电路GA1输出的第一栅极控制信号Nscan1和第二栅极驱动电路GA2输出的第二栅极控制信号Nscan2维持低电平，而第三栅极控制信号Pscan1和第四栅极控制信号Pscan2维持高电平。
第二阶段t2，第一个时钟信号CK1具有高电平，第二个时钟信号CK2具有低电平，第三个时钟信号CK3具有高电平，第四个时钟信号CK4具有高电平。第p-1级第一栅极控制信号Nscan1(p-1)~第p-2级第一栅极控制信号Nscan1(p-2)为高电平，第p-1级第二栅极控制信号Nscan2(p-1)~第p-2级第二栅极控制信号Nscan2(p-2)为低电平，第一分频控制信号NF1~第四分频控制信号PF2具有低电平。
第p级第一栅极驱动电路GA1(p)中，第一晶体管T1、第三晶体管T3、第六晶体管T6、第八晶体管T8和第二输出晶体管To2导通，第二分频晶体管Tf2、第四分频晶体管Tf4维持导通，第二晶体管T2、第四晶体管T4、第五晶体管T5、第七晶体管T7、第九晶体管T9、第十晶体管T10、第十一晶体管T11、第十二晶体管T12、第十三晶体管T13、第一分频晶体管Tf1、第三分频晶体管Tf3、第一输出晶体管To1、第三输出晶体管To3和第四输出晶体管To4截止。第四电源端NVGH与第一输出端O1电性连接，第p级第一栅极控制信号Nscan1(p)具有高电平，第p级第三栅极控制信号Pscan1(p)维持高电平。
第p级第二栅极驱动电路GA2(p)中在第二阶段t2执行与第一阶段t1相似的动作。第p+1级第一栅极控制信号Nscan1(p+1)~第p+11级第一栅极控制信号Nscan1(p+11)和第p级第二栅极控制信号Nscan2(p)~第p+11级第二栅极控制信号Nscan2(p+11)维持低电平，第p+1级第三栅极控制信号Pscan1(p+1)~第p+11级第三栅极控制信号Pscan1(p+11)和第p级第四栅极控制信号Pscan2(p)~第p+11级第四栅极控制信号Pscan2(p+11)维持高电平。
第三阶段t3，第一个时钟信号CK1具有高电平，第二个时钟信号CK2具有高电平，第三个时钟信号CK3具有低电平，第四个时钟信号CK4具有高电平。第p-1级第一栅极控制信号Nscan1(p-1)~第p-2级第一栅极控制信号Nscan1(p-2)为高电平，第p-1级第二栅极控制信号Nscan2(p-1)~第p-2级第二栅极控制信号Nscan2为低电平，第一分频控制信号NF1~第四分频控制信号PF2具有低电平。
第p级第一栅极控制信号Nscan1(p)和第p级第三栅极控制信号Pscan1(p)维持高电平。
第p级第二栅极驱动电路GA2(p)中，第三晶体管T3截止。第p级第二栅极控制信号Nscan2(p)~第p+11级第二栅极控制信号Nscan2(p+11)维持低电平，第p级第四栅极控制信号Pscan2(p)~第p+11级第四栅极控制信号Pscan2(p+11)维持高电平。
第p+1级第一栅极驱动电路GA1(p+1)和第p+1级第二栅极驱动电路GA2(p+1)在第三阶段t3执行与第p级第一栅极驱动电路GA1(p)和第p级第二栅极驱动电路GA2(p)在第二阶段t2所执行的动作相似的动作。第p+2级第一栅极驱动电路GA1(p+2)和第p+2级第二栅极驱动电路GA2(p+2)在第三阶段t3执行与第p+1级第一栅极驱动电路GA1(p+1)和第p+1级第二栅极驱动电路GA2(p+1)在第二阶段t2所执行的动作相似的动作。以此类推，得到第p+3级第一栅极驱动电路GA1(p+3)~第p+11级第一栅极驱动电路GA1(p+11)和第p+3级第二栅极驱动电路GA2(p+3)~第p+11级第二栅极驱动电路GA2(p+11)在第三阶段t3所执行的动作。
第四阶段t4：第一个时钟信号CK1具有高电平，第二个时钟信号CK2具有低电平，第三个时钟信号CK3具有高电平，第四个时钟信号CK4具有高电平。第p-1级第一栅极控制信号Nscan1(p-1)~第p-2级第一栅极控制信号Nscan1(p-2)为高电平，第p-1级第二栅极控制信号Nscan2(p-1)~第p-2级第二栅极控制信号Nscan2为高电平，第一分频控制信号NF1、第二分频控制信号NF2、第三分频控制信号PF1、第四分频控制信号PF2具有低电平。
第p级第一栅极控制信号Nscan1(p)和第p级第三栅极控制信号Pscan1(p)维持高电平。并且，第p+1级第一栅极控制信号Nscan1(p+1)~第p+4级第一栅极控制信号Nscan1(p+4)和第p+1级第三栅极控制信号Pscan1(p+1)~第p+11级第三栅极控制信号Pscan1(p+11)维持高电平，第p+5级第一栅极控制信号Nscan1(p+5)~第p+11级第一栅极控制信号Nscan1(p+11)维持低电平。
第p级第二栅极驱动电路GA2(p)执行与第p级第一栅极驱动电路GA1(p)于第二阶段t2相似的动作，第p级第二栅极控制信号Nscan2(p)具有高电平和第p级第四栅极控制信号Pscan2(p)具有高电平。第p+1级第二栅极控制信号Nscan2(p+1)~第p+11级第二栅极控制信号Nscan2(p+11)维持低电平，第p级第四栅极控制信号Pscan2(p)~第p+11级第四栅极控制信号Pscan2(p+11)维持高电平。
第五阶段t5：第一个时钟信号CK1具有低电平，第二个时钟信号CK2具有高电平，第三个时钟信号CK3具有高电平，第四个时钟信号CK4具有高电平。第p-1级第一栅极控制信号Nscan1(p-1)~第p-2级第一栅极控制信号Nscan1(p-2)和第p-1级第二栅极控制信号Nscan2(p-1)~第p-2级第二栅极控制信号Nscan2为低电平。第一分频控制信号NF1~第四分频控制信号PF2具有低电平。
在第p级第一栅极驱动电路GA1(p)和第p级第二栅极驱动电路GA2(p)中，第二晶体管T2、第四晶体管T4、第六晶体管T6、第八晶体管T8、第九晶体管T9、第十一晶体管T11、第十二晶体管T12、第二分频晶体管Tf2、第四分频晶体管Tf4、第二输出晶体管To2和第三输出晶体管To3导通，第一晶体管T1、第三晶体管T3、第五晶体管T5、第七晶体管T7、第十晶体管T10、第十三晶体管T13、第一分频晶体管Tf1、第三分频晶体管Tf3、第一输出晶体管To1和第四输出晶体管To4截止。第p级第一栅极控制信号Nscan1(p)和第p级第二栅极控制信号Nscan2(p)具有高电平，第p级第三栅极控制信号Pscan1(p)和第p级第四栅极控制信号Pscan2(p)具有低电平。
第p+1级第一栅极控制信号Nscan1(p+1)~第p+7级第一栅极控制信号Nscan1(p+7)和第p+2级第三栅极控制信号Pscan1(p+2)~第p+11级第三栅极控制信号Pscan1(p+11)具有高电平，第p+8级第一栅极控制信号Nscan1(p+8)~第p+11级第一栅极控制信号Nscan1(p+11)具有低电平。第p+1级第二栅极控制信号Nscan2(p+1)~第p+3级第二栅极控制信号Nscan2(p+3)和第p+2级第四栅极控制信号Pscan2(p+2)~第p+11级第四栅极控制信号Pscan2(p+11)具有高电平，第p+4级第三栅极控制信号Nscan2(p+4)~第p+11级第三栅极控制信号Nscan2(p+11)具有低电平。
第六阶段t6：第一个时钟信号CK1具有高电平，第二个时钟信号CK2具有低电平，第三个时钟信号CK3具有高电平，第四个时钟信号CK4具有高电平。第p-1级第一栅极控制信号Nscan1(p-1)~第p-2级第一栅极控制信号Nscan1(p-2)和第p-1级第二栅极控制信号Nscan2(p-1)~第p-2级第二栅极控制信号Nscan2为低电平。第一分频控制信号NF1~第四分频控制信号PF2具有低电平。
在第p级第一栅极驱动电路GA1(p)和第p级第二栅极驱动电路GA2(p)中，第二晶体管T2、第三晶体管T3、第五晶体管T5、第七晶体管T7、第十晶体管T10、第十一晶体管T11、第十三晶体管T13、第一分频晶体管Tf1~第四分频晶体管Tf4、第一输出晶体管To1和第四输出晶体管To4导通，第一晶体管T1、第四晶体管T4、第六晶体管T6、第八晶体管T8、第九晶体管T9、第十二晶体管T12、第二输出晶体管To2和第三输出晶体管To3截止。第p级第一栅极控制信号Nscan1(p)和第p级第二栅极控制信号Nscan2(p)具有低电平，第p级第三栅极控制信号Pscan1(p)和第p级第四栅极控制信号Pscan2(p)具有高电平。
第p+1级第一栅极驱动电路GA1(p+1)和第p+1级第二栅极驱动电路GA2(p+1)在第六阶段t6执行与第p级第一栅极驱动电路GA1(p)和第p级第二栅极驱动电路GA2(p)在第五阶段t5所执行的动作相似的动作。第p+2级第一栅极驱动电路GA1(p+2)和第p+2级第二栅极驱动电路GA2(p+2)在第六阶段t6执行与第p+1级第一栅极驱动电路GA1(p+1)和第p+2级第二栅极驱动电路GA2(p+2)在第五阶段t5所执行的动作相似的动作。以此类推，得到第p+3级第一栅极驱动电路GA1(p+3)~第p+11级第一栅极驱动电路GA1(p+11)和第p+3级第二栅极驱动电路GA2(p+3)~第p+11级第二栅极驱动电路GA2(p+11)在第六阶段t6所执行的动作。
第七阶段t7：第一个时钟信号CK1具有高电平，第二个时钟信号CK2具有高电平，第三个时钟信号CK3具有低电平，第四个时钟信号CK4具有高电平。第一分频控制信号NF1~第四分频控制信号PF2具有低电平。
第p级第一栅极控制信号Nscan1(p)~第p+1级第一栅极控制信号Nscan1(p+1)和第p+10级第一栅极控制信号Nscan1(p+10)~第p+11级第一栅极控制信号Nscan1(p+11)具有低电平，第p+2级第一栅极控制信号Nscan1(p+2)~第p+9级第一栅极控制信号Nscan1(p+9)具有高电平。第p+2级第三栅极控制信号Pscan1(p+2)具有低电平，第p级第三栅极控制信号Pscan1(p)~第p+1级第三栅极控制信号Pscan1(p+1)和第p+3级第三栅极控制信号Pscan1(p+3)~第p+11级第三栅极控制信号Pscan1(p+11)具有高电平。
第p级第二栅极控制信号Nscan2(p)~第p+1级第二栅极控制信号Nscan2(p+1)和第p+6级第二栅极控制信号Nscan2(p+6)~第p+11级第二栅极控制信号Nscan2(p+11)具有低电平，第p+2级第二栅极控制信号Nscan2(p+2)~第p+5级第二栅极控制信号Nscan2(p+5)具有高电平。第p+2级第四栅极控制信号Pscan2(p+2)具有低电平，第p级第四栅极控制信号Pscan2(p)~第p+1级第四栅极控制信号Pscan2(p+1)和第p+3级第四栅极控制信号Pscan2(p+3)~第p+11级第四栅极控制信号Pscan2(p+11)具有高电平。
第八阶段t8：第一个时钟信号CK1具有高电平，第二个时钟信号CK2具有高电平，第三个时钟信号CK3具有高电平，第四个时钟信号CK4具有低电平。第一分频控制信号NF1具有高电平，第二分频控制信号NF2~第四分频控制信号PF2具有低电平。
第p级第一栅极驱动电路GA1(p)在第八阶段t8维持与第七阶段t7相同的状态。第p+1级第一栅极驱动电路GA1(p+1)在第八阶段t8执行与第p级第一栅极驱动电路GA1(p)在第七阶段t7所执行的动作相似的动作。第p+2级第一栅极驱动电路GA1(p+2)在第八阶段t8执行与第p+1级第一栅极驱动电路GA1(p+1)在第七阶段t7所执行的动作相似的动作，以此类推，得到第p+4级第一栅极驱动电路GA1(p+4)~第p+9级第一栅极驱动电路GA1(p+9)在第八阶段t8所执行的动作。第p+10级第一栅极驱动电路GA1(p+10)在第八阶段t8执行与第p级第一栅极驱动电路GA1(p)在第二阶段t2所执行的动作相似的动作，第p+10级第一栅极控制信号Nscan1(p+10)和第p+10级第三栅极控制信号Pscan1(p+10)具有高电平。
在第p+11级第一栅极驱动电路GA1(p+11)中，第一晶体管T1、第四晶体管T4、第九晶体管T9、第十二晶体管T12、第一分频晶体管Tf1、第三分频晶体管Tf3和第四分频晶体管Tf4导通，第二晶体管T2、第三晶体管T3、第十一晶体管T11、第二分频晶体管Tf2截止。因而，第p+11级第一栅极控制信号Nscan1(p+11)具有低电平，第p+11级第三栅极控制信号Pscan1(p+11)具有高电平。
在第p+11级第一栅极驱动电路GA1(p+11)之后的第一栅极驱动电路GA1中，第一分频晶体管Tf1、第三分频晶体管Tf3和第四分频晶体管Tf4导通，第二分频晶体管Tf2截止。
第p级第二栅极控制信号Nscan2(p)~第p+2级第二栅极控制信号Nscan2(p+2)和第p+7级第二栅极控制信号Nscan2(p+7)~第p+11级第二栅极控制信号Nscan2(p+11)具有低电平，第p+3级第二栅极控制信号Nscan2(p+3)~第p+6级第二栅极控制信号Nscan2(p+6)具有高电平。第p+3级第四栅极控制信号Pscan2(p+3)具有低电平，第p级第四栅极控制信号Pscan2(p)~第p+2级第四栅极控制信号Pscan2(p+2)和第p+4级第四栅极控制信号Pscan2(p+4)~第p+11级第四栅极控制信号Pscan2(p+11)具有高电平。
第九阶段t9：第一个时钟信号CK1具有低电平，第二个时钟信号CK2具有高电平，第三个时钟信号CK3具有高电平，第四个时钟信号CK4具有高电平。第一分频控制信号NF1具有高电平，第二分频控制信号NF2~第四分频控制信号PF2具有低电平。
第p级第一栅极控制信号Nscan1(p)~第p+3级第一栅极控制信号Nscan1(p+3)具有低电平，第p+4级第一栅极控制信号Nscan1(p+4)~第p+10级第一栅极控制信号Nscan1(p+10)具有高电平。第p+4级第三栅极控制信号Pscan1(p+4)具有低电平，第p级第三栅极控制信号Pscan1(p)~第p+3级第三栅极控制信号Pscan1(p+3)和第p+5级第三栅极控制信号Pscan1(p+5)~第p+11级第三栅极控制信号Pscan1(p+11)具有高电平。
在第p+11级第一栅极驱动电路GA1(p+11)中，第一晶体管T1、第三晶体管T3、第六晶体管T6、第八晶体管T8、第四分频晶体管Tf4导通，第四晶体管T4、第五晶体管T5、第七晶体管T7、第九晶体管T9、第十晶体管T10、第十一晶体管T11、第十二晶体管T12、第十三晶体管T13、第一分频晶体管Tf1~第三分频晶体管Tf3、第一输出晶体管To1~第四输出晶体管To4截止，使得第p+11级第一栅极控制信号Nscan1(p+11)维持低电平，第p+11级第三栅极控制信号Pscan1(p+11)维持高电平。
第p级第二栅极控制信号Nscan2(p)~第p+3级第二栅极控制信号Nscan2(p+3)和第p+8级第二栅极控制信号Nscan2(p+8)~第p+11级第二栅极控制信号Nscan2(p+11)具有低电平，第p+4级第二栅极控制信号Nscan2(p+4)~第p+7级第二栅极控制信号Nscan2(p+7)具有高电平。第p+4级第四栅极控制信号Pscan2(p+4)具有低电平，第p级第四栅极控制信号Pscan2(p)~第p+3级第四栅极控制信号Pscan2(p+3)和第p+5级第四栅极控制信号Pscan2(p+5)~第p+11级第四栅极控制信号Pscan2具有高电平。
第十阶段t10：第一个时钟信号CK1具有高电平，第二个时钟信号CK2具有高电平，第三个时钟信号CK3具有高电平，第四个时钟信号CK4具有低电平。第一分频控制信号NF1和第二分频控制信号NF2具有高电平，第三分频控制信号PF1和第四分频控制信号PF2具有低电平。
第p级第一栅极控制信号Nscan1(p)~第p+6级第一栅极控制信号Nscan1(p+6)、第p+11级第一栅极控制信号Nscan1(p+11)及其之后的第一栅极控制信号Nscan1具有低电平，第p+7级第一栅极控制信号Nscan1(p+7)~第p+10级第一栅极控制信号Nscan1(p+10)具有高电平。第p+7级第三栅极控制信号Pscan1(p+7)具有低电平，第p级第三栅极控制信号Pscan1(p)~第p+6级第三栅极控制信号Pscan1(p+6)和第p+8级第三栅极控制信号Pscan1(p+8)~第p+1级第三栅极控制信号Pscan1(p+11)具有高电平。
第p级第二栅极控制信号Nscan2(p)~第p+6级第二栅极控制信号Nscan2(p+6)、第p+11级第二栅极控制信号Nscan2(p+11)及其之后的第二栅极控制信号Nscan2具有低电平，第p+7级第二栅极控制信号Nscan2(p+7)~第p+10级第二栅极控制信号Nscan2(p+10)具有高电平。第p+7级第四栅极控制信号Pscan2(p+7)具有低电平，第p级第四栅极控制信号Pscan2(p)~第p+6级第四栅极控制信号Pscan2(p+6)和第p+8级第四栅极控制信号Pscan2(p+8)~第p+11级第四栅极控制信号Pscan2(p+11)具有高电平。
第十一阶段t11：第一个时钟信号CK1具有低电平，第二个时钟信号CK2具有高电平，第三个时钟信号CK3具有高电平，第四个时钟信号CK4具有高电平。第一分频控制信号NF1和第二分频控制信号NF2具有高电平，第三分频控制信号PF1和第四分频控制信号PF2具有低电平。
第p级第一栅极控制信号Nscan1(p)~第p+7级第一栅极控制信号Nscan1(p+7)、第p+11级第一栅极控制信号Nscan1(p+11)及其之后的第一栅极控制信号Nscan1具有低电平，第p+8级第一栅极控制信号Nscan1(p+8)~第p+10级第一栅极控制信号Nscan1(p+10)具有高电平。第p+8级第三栅极控制信号Pscan1(p+8)具有低电平，第p级第三栅极控制信号Pscan1(p)~第p+7级第三栅极控制信号Pscan1(p+7)和第p+9级第三栅极控制信号Pscan1(p+9)~第p+11级第三栅极控制信号Pscan1(p+11)具有高电平。
第p级第二栅极控制信号Nscan2(p)~第p+7级第二栅极控制信号Nscan2(p+7)、第p+11级第二栅极控制信号Nscan2(p+11)及其之后的第二栅极控制信号Nscan2具有低电平，第p+8级第二栅极控制信号Nscan2(p+8)~第p+10级第二栅极控制信号Nscan2(p+10)具有高电平。第p+8级第四栅极控制信号Pscan2(p+8)具有低电平，第p级第四栅极控制信号Pscan2(p)~第p+7级第四栅极控制信号Pscan2(p+7)和第p+9级第四栅极控制信号Pscan2(p+9)~第p+11级第四栅极控制信号Pscan2(p+11)具有高电平。即第p+11级第二栅极驱动电路GA2(p+11)在第十一阶段t11执行与第p+11级第一栅极驱动电路GA1(p+11)在第九阶段t9所执行的动作相似的动作。
之后，第p+10级第一栅极驱动电路GA1(p+10)和第p+10级第二栅极驱动电路GA2(p+10)根据对应的第一时钟信号和第二时钟信号使第p+10级第一栅极控制信号Nscan1(p+10)和第p+10级第二栅极控制信号Nscan2(p+10)恢复至低电平状态，且第p+10级第三栅极控制信号Pscan1(p+10)和第p+10级第四栅极控制信号Pscan2(p+10)输出低电平后再恢复至高电平。
因而，通过控制第一分频控制信号NF1可以控制多个第一栅极驱动电路GA1输出的第一栅极控制信号Nscan1的电平，通过控制第二分频控制信号NF2可以控制多个第二栅极驱动电路GA2输出的第二栅极控制信号Nscan2的电平。通过控制第一分频控制信号NF1和第二分频信号自有效电平跳变至无效电平的时刻，可使第一栅极控制信号Nscan1和第二栅极控制信号Nscan2对应同一级即不具有有效电平的输出。
与之相似的，通过控制第三分频控制信号PF1可以控制多个第一栅极驱动电路GA1输出的第三栅极控制信号Pscan1的电平，通过控制第四分频控制信号PF2可以控制多个第二栅极驱动电路GA2输出的第四栅极控制信号Pscan2的电平。通过控制第三分频控制信号PF1和第四分频信号自有效电平跳变至无效电平的时刻，可使第三栅极控制信号Pscan1和第四栅极控制信号Pscan2对应同一级即不具有有效电平的输出。因此，第一栅极驱动单元GM1和第二栅极驱动单元GM2对应第三分频控制信号PF1或第四分频控制信号PF2自有效电平跳变至无效电平的时序图如图8B所示，第一栅极驱动单元GM1和第二栅极驱动单元GM2对应第三分频控制信号PF1或第四分频控制信号PF2自有效电平跳变至无效电平的工作原理，可参照第一分频控制信号NF1和第二分频信号有效电平跳变至无效电平的工作原理类似得到。
如对应图8B，在第三分频控制信号PF1对应自有效电平跳变至无效电平的时刻之前的第十二阶段t12，第p+9级第一栅极驱动电路GA1(p+9)输出的第p+9级第一栅极控制信号Nscan1(p+9)具有高电平，第p+10级第一栅极驱动电路GA1(p+10)输出的第p+10级第一栅极控制信号Nscan1(p+10)具有低电平。在第三分频控制信号PF1或第四分频控制信号PF2对应自有效电平跳变至无效电平的时刻之后的第十三阶段t13，第p+11级第一栅极驱动电路GA1(p+11)中，第一晶体管T1、第四晶体管T4、第九晶体管T9、第十二晶体管T12、第一分频晶体管Tf1~第三分频晶体管Tf3导通，第二晶体管T2、第三晶体管T3、第十一晶体管T11、第四分频晶体管Tf4截止。第p+11级第一栅极驱动电路GA1(p+11)的第四分频晶体管Tf4截止致使在第p+11级第一栅极驱动电路GA1(p+11)对应的第二时钟信号为低电平的时段内，第p+11级第三栅极控制信号Pscan1(p+11)维持高电平。
与之相似的，还可得到第四分频控制信号PF2对应自有效电平跳变至无效电平时，第二栅极驱动单元GM2的工作原理。
与之相似的，还可得到第一栅极驱动单元GM1、第二栅极驱动单元GM2根据对应的分频控制信号自无效电平跳变至有效电平时的工作原理，在此不进行赘述。
参照图8A~图8B的分析，可得到第一栅极驱动电路GA1或第二栅极驱动电路GA2包括两第二输出模块50和一第二分频控制模块60时，第一栅极驱动单元GM1或第二栅极驱动单元GM2的工作原理，在此不再进行赘述。相应地，第一栅极驱动单元或第二栅极驱动单元输出的多个栅极控制信号的时序图如图8C~图8D所示。
请继续参阅图1A~图1B，在一些实施例中，栅极驱动模块GM还包括第三栅极驱动单元GM3和第四栅极驱动单元GM4。第三栅极驱动单元GM3包括多个级联的第三栅极驱动电路GA3，多个第三栅极驱动电路GA3被配置为生成多个第五栅极控制信号Pscan，以输出至多个子像素Spi的第一初始晶体管Ti1和第二初始晶体管Ti2的控制端。第四栅极驱动单元GM4包括多个级联的第四栅极驱动电路GA4，多个第四栅极驱动电路GA4被配置为生成多个发光控制信号EM，以输出至多个子像素Spi的第一发光控制晶体管Te1和第二发光控制晶体管Te2的控制端。可选地，多个第三栅极驱动电路GA3与多条第四扫描线GL4电性连接，多个第四栅极驱动电路GA4与多条发光控制线EL电性连接。
可选地，每一第三栅极驱动电路GA3可驱动至少一行的子像素Spi的第一初始晶体管Ti1和第二初始晶体管Ti2，每一第四栅极驱动电路GA4可驱动至少一行的子像素Spi的第一发光控制晶体管Te1和第二发光控制晶体管Te2。
可选地，第三栅极驱动电路GA3和第四栅极驱动电路GA4可采用相同或不同的电路结构，第三栅极驱动电路GA3和第四栅极驱动电路GA4采用的电路结构可参考相关技术中的设计。
图9是本申请实施例提供的子像素对应写入帧和保持帧的时序图。以补偿晶体管Tc和复位晶体管Tr为N型晶体管，驱动晶体管Tdr、数据晶体管Tda、第一发光控制晶体管Te1、第二发光控制晶体管Te2、第一初始晶体管Ti1、第二初始晶体管Ti2为P型晶体管为例，对像素驱动电路的工作原理进行说明。
在第一复位阶段Si1：发光控制线EL传输的发光控制信号EM、数据晶体管Tda接收的栅极控制信号(即第三栅极控制信号Pscan1和第四栅极控制信号Pscan2中的至少一个)为高电平，复位晶体管Tr接收的栅极控制信号（即第一栅极控制信号Nscan1）和补偿晶体管Tc接收的栅极控制信号（即第二栅极控制信号Nscan2）为低电平，第四扫描线GL4传输的第五栅极控制信号Pscan为低电平。第一初始线VL1传输的第一初始信号传输至发光器件Di的阳极，以实现对发光器件Di阳极电位的复位；第二初始线VL2传输的第二初始信号传输至驱动晶体管Tdr的输入端和输出端，实现对驱动晶体管Tdr的输入端和输出端的电位复位。
在第二复位阶段Si2，第一栅极控制信号Nscan1、发光控制信号EM、数据晶体管Tda接收的第三栅极控制信号Pscan1和第四栅极控制信号Pscan2、第五栅极控制信号为高电平Pscan，第二栅极控制信号Nscan2为低电平。复位晶体管Tr导通，复位信号Vr传输至驱动晶体管Tdr的栅极，以实现对驱动晶体管Tdr的控制端的电位复位。
在数据写入阶段Sw，第二栅极控制信号Nscan2、发光控制信号EM、第五栅极控制信号Pscan为高电平，第一栅极控制信号Nscan1、数据晶体管Tda接收的的第三栅极控制信号Pscan1和第四栅极控制信号Pscan2为低电平。数据晶体管Tda、补偿晶体管Tc导通，数据信号被传输至驱动晶体管Tdr的控制端。
其中，在第二复位阶段Si2和数据写入阶段Sw之间，还可包括控制复位晶体管Tr和补偿晶体管Tc同时导通的阶段，以使复位信号Vr可被传输至驱动晶体管Tdr的输出端和输入端，实现对驱动晶体管Tdr的输出端和输入端的电位复位。
在第三复位阶段Si3，发光控制信号EM、数据晶体管Tda接收的的第三栅极控制信号Pscan1和第四栅极控制信号Pscan2为高电平，第一栅极控制信号Nscan1、第二栅极控制信号Nscan2、第五栅极控制信号Pscan为低电平，第一初始信号传输至发光器件Di的阳极，第二初始信号传输至驱动晶体管Tdr的输入端和输出端。
在发光阶段Sd，数据晶体管Tda接收的第三栅极控制信号Pscan1和第四栅极控制信号Pscan2、第五栅极控制信号Pscan为高电平，发光控制信号EM、第一栅极控制信号Nscan1、第二栅极控制信号Nscan2为低电平，第一发光控制晶体管Te1和第二发光控制晶体管Te2导通，驱动晶体管Tdr生成驱动电流以驱动对应的发光器件Di发光。
在第四复位阶段Si4和第五复位阶段Si5，发光控制信号EM、数据晶体管Tda接收的第三栅极控制信号Pscan1和第四栅极控制信号Pscan2为高电平，第一栅极控制信号Nscan1、第二栅极控制信号Nscan2、第五栅极控制信号为Pscan低电平，第一初始信号传输至发光器件Di的阳极，第二初始信号传输至驱动晶体管Tdr的输入端和输出端。
其中，写入帧WF包括第一复位阶段Si1、第二复位阶段Si2、数据写入阶段Sw、第三复位阶段Si3、发光阶段Sd，保持帧HF包括第四复位阶段Si4、第五复位阶段Si5和发光阶段Sd。
结合图1A、图6A、图8A~图8B及图9的分析，以位于第L行的子像素Spi的补偿晶体管Tc的控制端与第K+1级第一栅极驱动电路GA1(K+1)的第一输出端O1电性连接，位于第L行的子像素Spi的复位晶体管Tr的控制端与第K-3级第二栅极驱动电路GA2(K-3)的第一输出端O1电性连接，位于第L行的子像素Spi的数据晶体管Tda的控制端与第K级第一栅极驱动电路GA1(K)的第二输出端O2与第K级第二栅极驱动电路GA2(K)的第二输出端O2电性连接，第K级栅极驱动电路采用第K-1级栅极驱动电路的第一输出端O1输出的栅极控制信号作为控制信号为例，对应用第一栅极驱动单元GM1和第二栅极驱动单元GM2使显示面板DP实现分频显示的原理进行说明。
在一显示周期的第一帧F1，为使多个子像素Spi的驱动晶体管Tdr的控制端均写入新的数据信号，控制第一分频控制信号NF1~第四分频控制信号PF2保持有效电平状态，显示面板DP内多行子像素Spi均经历图9所示的写入帧WF阶段。其中，一显示周期可以包括一帧，也可包括多帧。一显示周期包括一帧时，该帧即对应为多行子像素Spi的写入帧WF。一显示周期包括多帧时，第一帧F1即对应为多行子像素Spi的写入帧WF。
在一显示周期的第二帧F2，若显示面板DP的第1行子像素Spi~第L行子像素Spi采用高频进行显示，第L+1行子像素Spi及其后的多行子像素Spi采用低频进行显示，那么，对应第1行子像素Spi~第L行子像素Spi所应用的第一栅极控制信号Nscan1、第二栅极控制信号Nscan2、第三栅极控制信号Pscan1、第四栅极控制信号Pscan2均需具有有效脉冲，使第1行子像素Spi~第L行子像素Spi均经历图9所示的写入帧WF阶段。而对应第L行子像素Spi及其后的多行子像素Spi所应用的第一栅极控制信号Nscan1、第二栅极控制信号Nscan2、第三栅极控制信号Pscan1、第四栅极控制信号Pscan2均无需具有有效脉冲，使第L行子像素Spi及其后的多行子像素Spi均经历图9所示的保持帧HF阶段。其中，第二帧F2位于第一帧F1后。
如以第L-1行子像素Spi和第n行子像素Spi为例，第L-1行子像素Spi所应用的第一栅极控制信号Nscan1为第K级第一栅极控制信号Nscan1(K)，第L-1行子像素Spi所应用的第二栅极控制信号Nscan2为第K-4级第二栅极控制信号Nscan2(K-4)、第L-1行子像素Spi所应用的第三栅极控制信号Pscan1和第四栅极控制信号Pscan2为第K-1级第三栅极控制信号Pscan1(K-1)和第K-1级第四栅极控制信号Pscan2(K-1)。第K级第一栅极控制信号Nscan1(K)在第二帧F2具有的时序即对应如图9中的第一栅极控制信号Nscan1于写入帧WF所具有的形式，第K-4级第二栅极控制信号Nscan2(K-4)在第二帧F2具有的时序即对应如图9中的第二栅极控制信号Nscan2于写入帧WF所具有的形式，第K-1级第三栅极控制信号Pscan1(K-1)和第K-1级第四栅极控制信号Pscan2(K-2)在第二帧F2的时序即对应如图9中的第三栅极控制信号Pscan1和第四栅极控制信号Pscan2于写入帧WF所具有的形式。
而第L行子像素Spi所应用的第一栅极控制信号Nscan1为第K+1级第一栅极控制信号Nscan1(K+1)，第L行子像素Spi所应用的第二栅极控制信号Nscan2为第K-3级第二栅极控制信号Nscan2(K-3)、第L行子像素Spi所应用的第三栅极控制信号Pscan1和第四栅极控制信号Pscan2为第K级第三栅极控制信号Pscan1(K)和第K级第四栅极控制信号Pscan2(K)。第K+1级第一栅极控制信号Nscan1(K+1) 在第二帧F2具有的时序即对应如图9中的第一栅极控制信号Nscan1于保持帧HF所具有的形式，第K-3级第二栅极控制信号Nscan2(K-3)在第二帧F2具有的时序即对应如图9中的第二栅极控制信号Nscan2于保持帧HF所具有的形式，第K级第三栅极控制信号Pscan1(K)和第K级第四栅极控制信号Pscan2(K)在第二帧F2的时序即对应如图9中的第三栅极控制信号Pscan1和第四栅极控制信号Pscan2于保持帧HF所具有的形式。因而，对于第L-1行子像素Spi而言，第二帧F2仍是写入帧WF；而对于第L行子像素Spi而言，第二帧F2为保持帧HF。第二帧F2，第L-1行子像素Spi的驱动晶体管Tdr的控制端具有数据信号写入，而第L行子像素Spi的驱动晶体管Tdr的控制端不具有数据信号写入，第L-1行子像素Spi和第L行子像素Spi在第二帧F2对应的刷新频率具有了区别，可以使显示面板DP实现分频显示功能。
可选地，在一些实施例中，一子像素Spi对应低频显示时，补偿晶体管Tc、复位晶体管Tr和数据晶体管Tda均降为低频，即控制补偿晶体管Tc、复位晶体管Tr和数据晶体管Tda在保持帧HF均保持截止状态。相应地，因第L-1行子像素Spi应用第K级第一栅极控制信号Nscan1(K)，第K行子像素Spi应用第K级第三栅极控制信号Pscan1(K)和第K级第四栅极控制信号Pscan2(K)，因而，第K级第一栅极驱动电路GA1(K)输出的第一栅极控制信号Nscan1(K)需满足第L-1行子像素Spi实现高频显示需求，第K级第一栅极驱动电路GA1(K)输出的第三栅极控制信号Pscan1(K)需满足第L行子像素Spi实现低频显示需求，第K级第二栅极驱动电路GA2(K)输出的第四栅极控制信号Pscan2(K)需满足第L行子像素Spi实现低频显示需求。因此，第K级第一栅极驱动电路GA1(K)需输出同时满足高频需求的第一栅极控制信号Nscan1(K)，还需输出满足低频需求的第三栅极控制信号Pscan1(K)。因而，在一显示周期的位于第一帧HF1之后的至少一帧内，对应至少一所述第一栅极驱动电路GA1输出的所述第一栅极控制信号Nscan1的频率大于所述第三栅极控制信号Pscan1的频率。与之相似的，第K-3级第二栅极驱动电路GA2(K-3)~第K-1级第二栅极驱动电路GA2(K-1)需输出同时满足高频需求的第K-3级第四栅极控制信号Pscan2(K-3)~第K-1级第四栅极控制信号Pscan2(K-1)，还需输出满足低频需求的第K-3级第二栅极控制信号Nscan2 (K-3)~第K-1级第二栅极控制信号Nscan2(K-1)。因而，在一显示周期的位于第一帧HF1之后的至少一帧内，对应至少一所述第二栅极驱动电路GA2输出的所述第二栅极控制信号Nscan2的频率小于所述第四栅极控制信号Pscan2的频率。即对应同一栅极驱动电路存在需要输出具有不同频率的栅极控制信号的需求。而本申请提供的第一栅极驱动单元GM1、第二栅极驱动单元GM2与分频控制信号、子像素Spi的匹配设计，可以满足上述需求。
与之相似的，在显示面板DP的第1行子像素Spi~第L行子像素Spi采用低频进行显示，第L+1行子像素Spi及其后的多行子像素Spi采用高频进行显示时，第K级第一栅极驱动电路GA1(K)需输出同时满足低频需求的第一栅极控制信号Nscan1(K)，还需输出满足高频需求的第三栅极控制信号Pscan1(K)，因而，在一显示周期的位于第一帧HF1之后的至少一帧内，对应至少一所述第一栅极驱动电路GA1(K)输出的所述第一栅极控制信号Nscan1的频率小于所述第三栅极控制信号Pscan1的频率。与之相似的，第K-3级第二栅极驱动电路GA2(K-3)~第K-1级第二栅极驱动电路GA2(K-1)需输出同时满足低频需求的第K-3级第四栅极控制信号Pscan2(K-3)~第K-1级第四栅极控制信号Pscan2(K-1)   ,还需输出满足高频需求的第K-3级第二栅极控制信号Nscan2 (K-3)~第K-1级第二栅极控制信号Nscan2(n-1)。因而，在一显示周期的位于第一帧HF1之后的至少一帧内，对应至少一所述第二栅极驱动电路GA2输出的所述第二栅极控制信号Nscan2的频率大于所述第四栅极控制信号Pscan2的频率。即仍对应同一栅极驱动电路存在需要输出具有不同频率的栅极控制信号的需求。
与之相似的，对应一栅极驱动电路包括多个第二输出模块的设计，仍有对应同一栅极驱动电路存在需要输出具有不同频率的栅极控制信号的需求。如结合图1B、图6B、图8C~图8D及图9的分析，以位于第L行~第L+X-1行的子像素Spi的补偿晶体管Tc的控制端与第K级第一栅极驱动电路GA1(K)的第一输出端O1电性连接，位于第L行~第L+X-1行的子像素Spi的复位晶体管Tr的控制端与第K-2级第二栅极驱动电路GA2(K-2)的第一输出端O1电性连接，位于第L行的子像素Spi的数据晶体管Tda的控制端与第K级第一栅极驱动电路GA1(K)的一第二输出端O2和第K级第二栅极驱动电路GA2(K)的一第二输出端O2电性连接，位于第L+X-1行的子像素Spi的数据晶体管Tda的控制端与第K级第一栅极驱动电路GA1(K)的另一第二输出端O2和第K级第二栅极驱动电路GA2(K)的另一第二输出端O2电性连接为例进行说明。
在一显示周期的第二帧F2，若显示面板DP的第1行子像素Spi~第10行子像素Spi采用高频进行显示，第11行子像素Spi及其后的多行子像素Spi采用低频进行显示。那么，第6级第一栅极驱动电路GA1(6)需输出同时满足高频需求的第一栅极控制信号Nscan1(6)，还需输出满足高频需求的第11级第三栅极控制信号Pscan1(11)~第12级第三栅极控制信号Pscan1(12)。第5级第二栅极驱动电路GA2(5)需输出同时满足高频需求的第9级第四栅极控制信号Pscan2(9)~第10级第四栅极控制信号Pscan2(10)   ,还需输出满足低频需求的第5级第二栅极控制信号Nscan2 (5)。即对应同一栅极驱动电路包括多个第二输出模块时，仍需要栅极驱动电路输出具有不同频率的栅极控制信号。而本申请提供的第一栅极驱动单元GM1、第二栅极驱动单元GM2与分频控制信号、子像素Spi的匹配设计，可以满足上述需求。
本文中应用了具体个例对本申请的原理及实施方式进行了阐述，以上实施例的说明只是用于帮助理解本申请的方法及其核心思想；同时，对于本领域的技术人员，依据本申请的思想，在具体实施方式及应用范围上均会有改变之处，综上所述，本说明书内容不应理解为对本申请的限制。

Claims (18)

  1. 一种显示装置，其中，包括：
    显示面板，包括多个子像素，至少一所述子像素包括发光器件、驱动晶体管、补偿晶体管和复位晶体管，所述驱动晶体管被配置为生成驱动电流以驱动所述发光器件发光，所述复位晶体管的输出端及所述补偿晶体管的输出端与所述驱动晶体管的控制端电性连接，所述补偿晶体管的输入端与所述驱动晶体管的输出端电性连接，所述复位晶体管的输入端被配置为接收复位信号；以及
    栅极驱动模块，与所述显示面板电性连接，包括多条传输分频控制信号的分频控制线、第一栅极驱动单元和第二栅极驱动单元；多个分频控制信号包括第一分频控制信号和第二分频控制信号，所述第一栅极驱动单元包括多个级联的第一栅极驱动电路，所述第二栅极驱动单元包括多个级联的第二栅极驱动电路，所述第一栅极驱动电路被配置为根据所述第一分频控制信号控制所生成的第一栅极控制信号的电平，所述第二栅极驱动电路被配置为根据所述第二分频控制信号控制所生成的第二栅极控制信号的电平；
    其中，所述第一栅极驱动电路和所述第二栅极驱动电路均包括第一输出端，多个所述子像素的所述补偿晶体管的控制端与多级所述第一栅极驱动电路的所述第一输出端对应电性连接以接收多个所述第一栅极控制信号，多个所述子像素的所述复位晶体管的控制端与多级所述第二栅极驱动电路的所述第一输出端对应电性连接以接收多个所述第二栅极控制信号；同一所述子像素中，所述复位晶体管接收的所述第二栅极控制信号的频率与所述补偿晶体管接收的所述第一栅极控制信号的频率相同。
  2. 根据权利要求1所述的显示装置，其中，
    至少一所述子像素包括数据晶体管，所述数据晶体管的输入端被配置为接收数据信号，所述数据晶体管的输出端与所述驱动晶体管的输入端电性连接；
    所述第一栅极驱动电路和所述第二栅极驱动电路均包括第二输出端，所述第一栅极驱动电路的所述第二输出端输出第三栅极控制信号，所述第二栅极驱动电路的所述第二输出端输出第四栅极控制信号；
    其中，多个所述子像素的所述数据晶体管的控制端与多个所述第一栅极驱动电路的所述第二输出端和/或多个所述第二栅极驱动电路的所述第二输出端电性连接。
  3. 根据权利要求2所述的显示装置，其中，在一显示周期的位于第一帧之后的至少一帧内，对应至少一所述第一栅极驱动电路输出的所述第一栅极控制信号的频率大于或小于所述第三栅极控制信号的频率。
  4. 根据权利要求2所述的显示装置，其中，在一显示周期的位于第一帧之后的至少一帧内，对应至少一所述第二栅极驱动电路输出的所述第二栅极控制信号的频率小于或大于所述第四栅极控制信号的频率。
  5. 根据权利要求2所述的显示装置，其中，多条所述分频控制线包括传输所述第一分频控制信号的第一分频控制线和传输所述第二分频控制信号的第二分频控制线；所述第一栅极驱动电路和所述第二栅极驱动电路均包括：
    节点控制模块，与第一节点电性连接，被配置为根据对应的启动信号和第一时钟信号控制第一节点的信号；
    第一分频控制模块，电性连接于所述第一节点、第二节点和第三节点，被配置为根据所述第三节点的信号和对应的所述分频控制信号控制所述第一节点和所述第二节点之间的信号传输；
    第一输出模块，与所述第一节点、所述第二节点和所述第一输出端电性连接，被配置为根据所述第一节点和所述第二节点的信号控制所述第一输出端输出的栅极控制信号；
    其中，多级所述第一栅极驱动电路的所述第一分频控制模块与所述第一分频控制线电性连接，多级所述第二栅极驱动电路的所述第一分频控制模块与所述第二分频控制线电性连接。
  6. 根据权利要求5所述的显示装置，其中，所述第一栅极驱动电路和所述第二栅极驱动电路中的至少一个包括：
    第二输出模块，与第三节点、第四节点和所述第二输出端电性连接，被配置为根据所述第三节点和所述第四节点的信号以及对应的第二时钟信号控制所述第二输出端输出的栅极控制信号；以及
    第二分频控制模块，通过所述第一节点和所述第三节点与所述节点控制模块电性连接，且通过所述第四节点与对应的所述第二输出模块电性连接，被配置为根据对应的所述分频控制信号控制所述第一节点和所述第四节点之间的信号传输。
  7. 根据权利要求6所述的显示装置，其中，所述第一栅极驱动电路和所述第二栅极驱动电路分别包括X个所述第二输出模块和X个所述第二输出端，每一所述第二输出模块与一所述第二输出端电性连接；
    其中，相邻两级所述第一栅极驱动电路所对应的第一时钟信号的相位差为XH，相邻两级所述第二栅极驱动电路所对应的第一时钟信号的相位差为XH；X≥1，H表示单位时长。
  8. 根据权利要求7所述的显示装置，其中，X＞1，同一所述第一栅极驱动电路的X个所述第二输出模块被配置为输出多个具有相位差的所述第三栅极控制信号，同一所述第二栅极驱动电路的X个所述第二输出模块被配置为输出多个具有相位差的所述第四栅极控制信号。
  9. 根据权利要求7所述的显示装置，其中，每一所述第二输出端与位于一行的多个所述子像素的所述数据晶体管的控制端电性连接；
    位于第L行~第L+X-1行的所述子像素的所述数据晶体管的控制端，与第K级所述第一栅极驱动电路的X个所述第二输出端和/或第K级所述第二栅极驱动电路的X个所述第二输出端对应电性连接；其中，K≥1，L= XK-(X-1)。
  10. 根据权利要求7所述的显示装置，其中，X=1；
    其中，位于第L行的所述子像素的所述补偿晶体管的控制端与第K+1级所述第一栅极驱动电路的所述第一输出端电性连接，位于第L行的所述子像素的所述复位晶体管的控制端与第K-3级所述第二栅极驱动电路的所述第一输出端电性连接。
  11. 根据权利要求10所述的显示装置，其中，还包括：
    多条时钟线，包括第一时钟线、第二时钟线、第三时钟线及第四时钟线；
    其中，第4m+1级所述第一栅极驱动电路和第4m+1级所述第二栅极驱动电路对应的所述第一时钟信号对应为所述第二时钟线传输的信号，第4m+1级所述第一栅极驱动电路和第4m+1级所述第二栅极驱动电路对应的所述第二时钟信号对应为所述第一时钟线传输的信号；第4m+2级所述第一栅极驱动电路和第4m+2级所述第二栅极驱动电路对应的所述第一时钟信号对应为所述第三时钟线传输的信号，第4m+2级所述第一栅极驱动电路和第4m+2级所述第二栅极驱动电路对应的所述第二时钟信号对应为所述第二时钟线传输的信号；第4m+3级所述第一栅极驱动电路和第4m+3级所述第二栅极驱动电路对应的所述第一时钟信号对应为所述第四时钟线传输的信号，第4m+3级所述第一栅极驱动电路和第4m+3级所述第二栅极驱动电路对应的所述第二时钟信号对应为所述第三时钟线传输的信号；第4m+4级所述第一栅极驱动电路和第4m+4级所述第二栅极驱动电路对应的所述第一时钟信号对应为所述第一时钟线传输的信号，第4m+4级所述第一栅极驱动电路和第4m+4级所述第二栅极驱动电路对应的所述第二时钟信号对应为所述第四时钟线传输的信号。
  12. 根据权利要求7所述的显示装置，其中，X≥2；
    其中，位于第L行~第L+X-1行的所述子像素的所述补偿晶体管的控制端与第K级所述第一栅极驱动电路的所述第一输出端电性连接；位于第L行~第L+X-1行的所述子像素的所述复位晶体管的控制端与第K-2级所述第一栅极驱动电路的所述第一输出端电性连接。
  13. 根据权利要求12所述的显示装置，其中，X=2，所述显示装置还包括多条时钟线，包括第一时钟线、第二时钟线、第三时钟线及第四时钟线；
    其中，所述第一时钟线向第2k+1级所述第一栅极驱动电路的一所述第二输出模块和第2k+1级所述第二栅极驱动电路的一所述第二输出模块传输对应的所述第二时钟信号，所述第二时钟线向第2k+1级所述第一栅极驱动电路的另一所述第二输出模块和第2k+1级所述第二栅极驱动电路的另一所述第二输出模块传输对应的所述第二时钟信号；所述第三时钟线向第2k+2级所述第一栅极驱动电路的一所述第二输出模块和第2k+2级所述第二栅极驱动电路的一所述第二输出模块传输对应的所述第二时钟信号，所述第四时钟线向第2k+2级所述第一栅极驱动电路的另一所述第二输出模块和第2k+2级所述第二栅极驱动电路的另一所述第二输出模块传输对应的所述第二时钟信号，k≥0。
  14. 根据权利要求13所述的显示装置，其中，所述第三时钟线向第2k+1级所述第一栅极驱动电路和第2k+1级所述第二栅极驱动电路传输对应的所述第一时钟信号；所述第一时钟线向第2k+2级所述第一栅极驱动电路和第2k+2级所述第二栅极驱动电路传输对应的所述第一时钟信号。
  15. 根据权利要求6所述的显示装置，其中，多条所述分频控制线包括第三分频控制线和第四分频控制线；所述第一栅极驱动电路和所述第二栅极驱动电路分别包括一所述第二分频控制模块；
    其中，多级所述第一栅极驱动电路的所述第二分频控制模块与所述第三分频控制线电性连接，多级所述第二栅极驱动电路的所述第二分频控制模块与所述第四分频控制线电性连接。
  16. 根据权利要求15所述的显示装置，其中，位于同行的多个所述子像素的所述数据晶体管的控制端与多个所述第一栅极驱动电路的所述第二输出端和多个所述第二栅极驱动电路的所述第二输出端电性连接；
    其中，所述第三分频控制线和所述第四分频控制线电性连接。
  17. 根据权利要求6所述的显示装置，其中，多级所述第一栅极驱动电路中的第一级所述第一栅极驱动电路对应的所述启动信号于第一时刻具有有效电平至无效电平的跳变，多级所述第二栅极驱动电路中的第一级所述第二栅极驱动电路对应的所述启动信号于所述第一时刻具有有效电平至无效电平的跳变。
  18. 根据权利要求1所述的显示装置，其中，多级所述第一栅极驱动电路通过单边驱动的方式电性连接于多个所述子像素的所述补偿晶体管的控制端，多级所述第二栅极驱动电路通过单边驱动的方式电性连接于多个所述子像素的所述复位晶体管的控制端。
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