WO2025202089A1

WO2025202089A1 - Image sensor with row driver circuit

Info

Publication number: WO2025202089A1
Application number: PCT/EP2025/057925
Authority: WO
Inventors: Michael SHEKHTMAN; Noam Zeev ESHEL
Original assignee: Sony Europe BV; Sony Semiconductor Solutions Corp
Current assignee: Sony Europe BV; Sony Semiconductor Solutions Corp
Priority date: 2024-03-26
Filing date: 2025-03-24
Publication date: 2025-10-02
Anticipated expiration: 2026-09-26

Abstract

A pixel control line of an image sensor is connected to pixel circuits of a pixel row. A row driver circuit drives a first digital voltage level to the pixel control line in a first time period and has a high output impedance in a second time period. A source follower amplifier controls a voltage on the pixel control line depending on a signal applied to a gate of the source follower amplifier in the second time period. The row driver circuit may drive a second digital voltage level to the pixel control line in a time period following the second time period.

Description

IMAGE SENSOR WITH ROW DRIVER CIRCUIT

The present disclosure relates to an image sensor with a row driver circuit that outputs a pixel control signal to a plurality of pixel circuits. In particular, the present disclosure relates to row driver circuits with outputs having a high-impedance state.

BACKGROUND

Image sensors for solid-state imaging devices have pixel arrays with pixel circuits organized in pixel rows and pixel columns. Pixel circuits in the same pixel row receive the same pixel control signals. Pixel circuits in the same pixel columns may share the same data signal line. Each pixel circuit includes one or more photoelectric conversion elements and pixel transistors. The photoelectric conversion elements generate photocurrents that are proportional to the received radiation intensity. The pixel transistors control an initialization of the photoelectric conversion elements in an initialization period, the integration of the photocurrents in an exposure period, the conversion of the integrated photocurrents into analog voltage signals, and the output of the analog voltage signals in a readout period.

A vertical scanning unit generates preamplifier pixel control signals. Row driver circuits convert the preamplifier pixel control signals into pixel control signals that are transmitted on pixel control lines that connect the output of the row driver circuits to the pixel transistors of the pixel circuits controlled by the row driver circuit. For image sensors with rolling shutter, the same pixel control signal is transmitted to all pixel transistors with the same function in the pixel circuits with the same row address. For image sensors with global shutter, the same pixel control signal is applied to all pixel transistors with the same function regardless of the row address.

SUMMARY

Steep slopes (edges) of pixel control signals at the beginning of a pixel control line near the output of the row driver circuit can become less steep at the end of pixel control lines remote from the output of the row driver circuit. Differently steep signal slopes can cause pixel circuits at the end of a pixel row to switch later than pixel circuits at the beginning of the pixel row. When a large number of pixel transistors simultaneously switch from a state in which the pixel circuits draw little current to a state in which the pixel circuits draw more current, the supply voltage of the pixel circuits may drop slightly for a short time. When a pixel transistor that connects a floating node to a reference potential is switched off, channel charge can accumulate at the floating node and distort the pixel signal.

The present disclosure mitigates such and other shortcomings of the prior art. For this purpose, a pixel control line of an image sensor is connected to pixel circuits of a pixel row. A row driver circuit drives a first digital voltage level to the pixel control line in a first time period and has a high output impedance in a second time period. A source follower amplifier controls a voltage on the pixel control line depending on a signal that is applied to a gate of the source follower amplifier in the second time period. In a time period after the second time period, the row driver circuit may apply a second digital voltage level to the pixel control line.

Since the output signal of the source follower amplifier follows the signal applied to the gate of the source follower amplifier, the source follower amplifier provides an additional degree of freedom for shaping a pixel control signal transmitted on the pixel control line. The additional design option can be used to slow down transitions between different signal states and/or signal levels of the pixel control signal. For example, in an image sensor with global shutter, a leading edge of an active global select signal, which triggers the transmission of analog pixel signals from the radiation receiving parts of the pixel circuits to the signal storage parts can be made less steep to avoid significant dips in the pixel supply voltage. The turn-off phase of reset transistors can be extended to prevent the accumulation of channel charge at a floating node.

Compared to methods that provide row driver circuits with long transistor channels for a similar purpose, the embodiments are area efficient and less susceptible to process variations. In comparison with examples providing the row driver circuits as current mode drivers with adjustable constant current sink/source, the slope of the pixel control signal does not or only to a low degree depend on the pixel load, which is slightly different for each pixel circuit, and which is susceptible for process parameter fluctuations, voltage supply fluctuations and temperature variations.

BRIEF DESCRIPTION OF THE DRAWINGS

A more complete appreciation of the disclosure and many of the attendant advantages thereof will be readily obtained as the same becomes better understood by reference to the following detailed description when considered in connection with the accompanying drawings, wherein:

FIG. 1 is a simplified block diagram of a solid-state imaging device with an image sensor that comprises row driver circuits and source follower amplifiers controlling the voltage on pixel control lines in accordance with an embodiment of the present technology.

FIG. 2A and FIG. 2B show a circuit diagram of a transistor circuit with a row driver circuit including a p- channel field effect transistor (pFET) and a source follower amplifier, and a time diagram for a pixel control signal and a voltage ramp signal applied to a gate of the source follower amplifier in accordance with an embodiment.

FIG. 3 A and FIG. 3B show a circuit diagram of a transistor circuit with a row driver circuit including an n- channel field effect transistor (nFET) and a source follower amplifier, and a time diagram for a pixel control signal and a voltage ramp signal applied to a gate of the source follower amplifier in accordance with another embodiment.

FIG. 4 is a simplified block diagram of a source follower amplifier receiving a voltage ramp signal from a voltage ramp circuit in accordance with an embodiment of the present technology. FIG. 5 is a simplified block diagram of an integrator circuit of the voltage ramp circuit of FIG. 4.

FIG. 6 is a simplified circuit diagram of an integrator circuit of the voltage ramp circuit of FIG. 4.

FIG. 7A, FIG. 7B and FIG. 7C show various states of the integrator circuit of FIG. 6.

FIG. 8 is a circuit diagram of an integrator circuit of the voltage ramp circuit of FIG. 4 according to another embodiment.

FIG. 9A shows a circuit diagram of a combination of a row driver circuit with CMOS inverter output and a source follower amplifier with pFET in accordance with an embodiment.

FIG. 9B shows a time diagram for signals applied to and output from the row driver circuit and source follower amplifier of FIG. 9A.

FIG. 10A shows a circuit diagram of a combination of a row driver circuit with CMOS inverter output and a source follower amplifier with nFET in accordance with another embodiment.

FIG. 10B shows a time diagram for signals applied to and output from the row driver circuit and source follower amplifier of FIG. 10A.

FIG. 11 is a simplified block diagram of a solid-state imaging device with an image sensor employing global shutter and source follower amplifiers controlling the voltage on pixel control lines in accordance with an embodiment of the present technology.

FIG. 12 is a circuit diagram of a pixel circuit with reset transistor and select transistor for illustrating effects of the embodiments.

FIG. 13A and FIG. 13B show diagrams for illustrating effects of the embodiments on the timing of pixel control signals received from pixel circuits at the beginning of a pixel control line near the row driver circuit and from pixel circuits at an end of the pixel control line remote from the row driver circuit.

FIG. 14 and FIG. 15 include diagrams illustrating differences between reset signals and floating diffusion potentials of pixel circuits at the beginning of a pixel row and at the end of the pixel row for embodiments with and without source follower amplifier according to an embodiment.

FIG. 16 is a schematic circuit diagram of a pixel circuit for global shutter, in accordance with an embodiment. FIG. 17 is a time diagram illustrating the effect of the source follower amplifier on a current consumption gradient for a pixel select signal becoming active, in accordance with an embodiment.

FIG. 18 is a diagram showing an example of a laminated structure of a solid-state imaging device according to an embodiment of the present disclosure.

FIG.19 is a block diagram depicting an example of a schematic configuration of a vehicle control system.

FIG. 20 is a diagram of assistance in explaining an example of installation positions of an outside-vehicle information detecting section and an imaging section of the vehicle control system of FIG. 19.

DETAILED DESCRIPTION

Embodiments for implementing techniques of the present disclosure (also referred to as “embodiments” in the following) will be described below in detail using the drawings. The techniques of the present disclosure are not limited to the described embodiments, and various features in the embodiments are illustrative only. The same elements or elements with the same functions are denoted by the same reference signs. Duplicate descriptions are omitted.

Connected electronic elements may be electrically connected through a direct, permanent low-resistive connection, e.g., through a conductive line. The terms “electrically connected” and “signal -connected” may also include a connection through other electronic elements provided and suitable for permanent and/or temporary signal transmission and/or transmission of energy. Electronic elements can be electrically connected or signal-connected via resistors, capacitors, electronic switches such as FETs (field effect transistors), or transistor circuits such as transmission gates. Directly electrically connected electronic elements are connected through a low-resistive wiring, an ohmic contact and/or a unipolar semiconductor junction.

The load path of a transistor is the controlled current path through a transistor. A voltage applied to the gate of a field effect transistor (FET) controls the current flow through the load path (controlled path) between source and drain of the FET by field effect.

A digital signal alternates between at least one active level and at least one inactive level. A digital signal having an active level is active. A digital signal having an inactive level is inactive. For each signal separately, the active level can be a digital high level and the inactive level a digital low level, or the active level can be the digital low level and the inactive level the digital high level.

Though in the following a technology for improving image quality of solid-state imaging devices is described in the context of certain types of pixel circuits for voltage domain global shutter pixels and rowwise signal readout, the technology may also be used for other types of pixel circuits and for pixel-wise signal readout. FIG. 1 illustrates a configuration example of a solid-state imaging device 90 in accordance with embodiments of the present technology. The solid-state imaging device 90 includes an image sensor 70 and a signal processing unit 80. The image sensor 70 includes a pixel array 10, a column signal processing unit 20, a vertical scanning unit 30, a readout buffer memory 40 and a sensor controller 50.

The pixel array unit 10 includes a plurality of identical pixel circuits 100. Each pixel circuit 100 is uniquely identifiable by a position in a pixel row 11 in combination with a position in a pixel column 12.

The pixel circuits 100 may be any active pixel sensors for intensity readout with one or two photoelectric conversion elements and three, four, or more pixel transistors 105. When a pixel circuit 100 is selected, the pixel circuit 100 is signal-connected to a data signal line 19 and outputs an analog pixel signal through the data signal line 19. A voltage level of the analog pixel signal depends on a illumination intensity detected by the pixel circuit 100.

The photoelectric conversion elements of the pixel array 10 are typically arranged matrix-like in columns and rows corresponding the pixel rows 11 and pixel columns 12, wherein a subset of pixel circuits 100 assigned to the same column of photoelectric conversion elements 101 may form a pixel column 12, and a subset of pixel circuits 100 assigned to the same row of photoelectric conversion elements 101 may form a pixel row 11.

The vertical scanning unit 30 includes a decoder unit 35 and a plurality of row driver circuits 220. The decoder unit 35 generates preamplifier control signals for controlling the pixel transistors 105 according to driver timing signals provided by the sensor controller 50. The preamplifier control signals are logic signals with voltage amplitudes and output driver currents as specified for the technology in which the decoder unit 35 is realized. The row driver circuits 220 convert the preamplifier control signals into more robust digital signals. The voltage levels of the digital signals are defined by the specifications of the addressed pixel transistors 105. The driving capability of the row driver circuits 220 match the load imposed by the pixel control lines 201 that connect the outputs of the row driver circuits 220 with the gates of the receiving pixel transistors 105.

Each pixel control signal is transmitted to a group of pixel circuits 100 through a pixel control line 210 that connects an output of row driver circuit 220 with inputs of the pixel circuits 100 of the group of pixel circuits 100. All pixel circuits 100 of a selected group of pixel circuits 100 receive the same pixel control signals synchronously. The selected group of pixel circuits 100 may include some pixel circuits 100 of one pixel row 11, all pixel circuits 100 of one pixel row 11, some or all pixel circuits 100 of more than one pixel row 11, or all pixel circuits 100 of the pixel array 10. In the following part of the description, “pixel row” is often referred to as an example of “group of pixel circuits” for simplicity. The pixel control signals may control pixel reset, pixel exposure, pixel-internal temporal storage of photocurrent charge, transmission of charges or analog voltage signals from a radiation sensitive portion to a voltage storage portion, and output of the analog pixel signals through the data signal lines 19.

At least some of the row driver circuits 220 drive a first digital voltage level to the pixel control line 210 in a first time period, have a high output impedance in a second time period, and may drive a second digital voltage level complementary to the first digital voltage level at some point after the second time period. The row driver circuits 20 are combined with source follower amplifiers 230, wherein the source follower amplifiers 230 control a voltage on the pixel control line 210 in the second time period. The controlled voltage depends on a signal applied to a gate of the source follower amplifier 230 through a source follower control line 239 in the second time period. The source follower amplifiers 230 can be used to shape the slopes of the pixel control signals according to various requirements.

The column signal processing unit 20 may include a column signal processing circuit for each data signal line 19 or for each pair of data signal lines 19. The column signal processing circuit converts the analog pixel signals into digital pixel values, may preprocess the digital pixel values and output the digital pixel values or the preprocessed digital pixel values to the readout buffer memory 40. The readout buffer memory 40 temporarily stores the digital pixel values.

The sensor controller 50 generates the driver timing signal and outputs the driver timing signals to the decoder unit 35 of the vertical scanning unit 30. The sensor controller 50 generates column control signals for controlling the column signal processing unit 20 and may generate a readout control signal that controls the readout of the digital pixel values from the readout buffer memory 40 to the signal processing unit 80 and/or to a digital interface.

FIG. 2A and FIG. 2B are related to a minimum configuration for a combination of a row driver circuit 220 and a source follower amplifier 230 for the case where the source follower amplifier 230 shapes the falling slope of a pixel control signal.

FIG. 3A and FIG. 3B are related to a minimum configuration for a combination of a row driver circuit 220 and a source follower amplifier 230 for the case where the source follower amplifier 230 shapes the rising slope of a pixel control signal.

For both cases, the image sensor 70 includes a pixel control line 210 connected to pixel circuits 100 of a pixel row 11. A row driver circuit 220 drives a first digital voltage level to the pixel control line 210 in a first time period tl and has a high output impedance in a second time period t2. A source follower amplifier 230 controls a voltage on the pixel control line 210 depending on a signal applied to a gate of the source follower amplifier 230 in the second time period t2. Sometime after the end of the second time period t2, the row driver circuit 220 may drive a complementary second digital voltage level to the pixel control line 210. The row driver circuit 220 may drive the second digital voltage beginning directly after the second time period t2 or after a third time period following the second time period t2. In FIG. 2A, the row driver circuit 220 includes a p channel field effect transistor (pFET) 226 with a load path connected between a high potential VI and the pixel control line 210. The gate of the pFET 226 of the row driver circuit 220 (row driver pFET 226) receives a preamplifier control signal VC1. The source follower amplifier 230 comprises a pFET 231 with a load path connected between the pixel control line 210 and a low potential V2. The gate ofthe pFET 231 of the source follower amplifier 230 (source follower pFET 231) receives a source follower control signal through a source follower control line 239. For the following examples, the source follower control signal is a voltage ramp signal VRMP.

According to FIG. 2B, the preamplifier control signal VC1 turns on the row driver pFET 226 and connects the pixel control line 210 to the high potential VI for the first time period tl. The voltage ramp signal VRMP has a high level at which the source follower pFET 231 is completely or almost completely off for the first time period 11 so that the pixel control line 210 is charged to the high potential V 1. Shortly before tx and at the latest at tx at the end of the first time period tl, the preamplifier control signal VC1 turns off the row driver pFET 226 for at least the time period t2. At tx the voltage ramp signal VRMP begins to fall. The source follower pFET 231 discharges the pixel control line 210 at a rate given by the slew rate of the falling slope of the voltage ramp signal VRMP. The voltage of the pixel control line 210 reaches the threshold voltage Vthl of the source follower pFET 231 at ty at the end of the second time period t2. The row driver circuit 220 may be configured to drive an active low level to the pixel control line 210 in a time period sometime after the end of the second time period t2.

The voltage level of the pixel control signal VOUT is equal to the high potential V 1 for the first time period tl and decreases in the second time period t2 at a rate given by the slew rate of the falling slope of the voltage ramp signal VRMP down to a threshold voltage Vthl of the source follower pFET 231.

The rate at which the voltage ramp signal VRMP falls is significantly lower than the slew rate of the preamplifier control signals. For example, the slew rate of the falling slope of the voltage ramp signal VRMP is at most 50%, 10%, or 5% of the slew rate of the falling slope of the preamplifier control signal VC1. For example, the preamplifier signal rise/fall time may be in a range from 100ns to 200ns and the fall time of the voltage ramp signal VRMP can be in a range from about 300ns to 3000ns.

In FIG. 3 A, the row driver circuit 220 includes an n channel field effect transistor (nFET) 221 with a load path connected between the pixel control line 210 and a low potential V2. The gate of the nFET 221 of the row driver circuit 220 (row driver nFET 221) receives a preamplifier control signal VC2. The source follower amplifier 230 comprises an nFET 236 with a load path connected between the high potential V2 and the pixel control line 210. The gate of the nFET 236 of the source follower amplifier 230 (source follower nFET 236) receives a source follower control signal through a source follower control line 239. For the following examples, the source follower control signal is a voltage ramp signal VRMP.

According to FIG. 3B, the preamplifier control signal VC2 turns on the row driver nFET 221 and connects the pixel control line 210 to the low potential V2 for the first time period tl . The voltage ramp signal VRMP has a low level at which the source follower nFET 236 is completely or almost completely off for the first time period tl such that the pixel control line 210 is discharged to the low potential V2. Shortly before tx and at the latest at tx at the end of the first time period tl, the preamplifier control signal VC2 turns off the row driver nFET 221 for at least the time period t2. At tx the voltage ramp signal VRMP begins to rise. The source follower nFET 236 charges the pixel control line 210 at a rate given by the slew rate of the rising slope of the voltage ramp signal VRMP. The voltage of the pixel control line 210 reaches a voltage (V2- Vth2) given by the high potential V2 reduced by the threshold voltage Vth2 of the source follower nFET 236 at ty at the end of the second time period t2. The row driver circuit 220 may be configured to drive an active high level to the pixel control line 210 in a time period after ty at the end of the second time period t2.

The voltage level of the pixel control signal VOUT is equal to the low potential V2 for the first time period tl and increases at a rate given by the slew rate of the rising slope of the voltage ramp signal VRMP up to VI - Vth2, wherein Vth2 is the threshold voltage of the source follower nFET 236.

The rate at which the voltage ramp signal VRMP rises is significantly lower than the slew rate of the preamplifier control signals. For example, the slew rate of the nsing slope of the voltage ramp signal VRMP is at most 0%, 10%, or 5% of the slew rate of the falling slope of the preamplifier control signal VC2. For example, the preamplifier signal rise/fall time may be in a range from 100ns to 200ns and the rise time of the voltage ramp signal VRMP can be in a range from about 300ns to 3000ns.

FIG. 4 shows a voltage ramp circuit 240 configured to output a voltage ramp signal VRMP to the gate of the source follower amplifier 230.

The voltage ramp signal VRMP may have a slow falling slope or a slow rising slope, wherein a slew rate of the slow slope is at most 50%, 10%, or 5% of the slew rate of the fast slope. The slew rate may be constant or at least approximately constant for at least 90% of the voltage difference covered by the slope.

The voltage ramp circuit 240 includes a current source 243 configured to output a constant auxiliary current IAUX and an integrator circuit 244 configured to obtain the voltage ramp signal VRMP by integrating the auxiliary current.

The current source 243 may include configurable registers to select one of several selectable constant auxiliary currents.. An integrator input line 249 transmits the constant auxiliary current IAUX from the current source 243 to the integrator circuit 244. By integrating the constant auxiliary current, the integrator circuit 244 inherently generates a linear voltage ramp signal VRMP with constant slew rate.

FIG. 5 illustrates an integrator circuit 244 that includes an inverting amplifier element 245 and a capacitive element 246 in a feedback path between an amplifier output and an amplifier input of the amplifier element 245. The constant auxiliary current lAUX is supplied to the input of the integrator circuit 244 through the integrator input line 249. The integrator circuit 244 outputs the voltage ramp signal VRMP on a source follower control line 239.

The integrator circuit 244 illustrated in FIG. 6 generates a descending voltage ramp. An integrator circuit 244 generating an ascending ramp can be formed analogously.

The integrator circuit 244 is disconnectable from the current source 243 to autozero the amplifier element 245, initialize a voltage across the capacitive element 246, and initialize an output voltage of the amplifier element 245 in an autozeroing period.

The inverting amplifier element 245 includes an amplifier nFET 247 with the load path connected between the source follower control line 239 and a reference potential VRL. An integrator control signal SINTEG controls a first switch 251 between the integrator input line 249 and the gate of the amplifier nFET 247. An integrator initialization signal SINIT controls a second switch 252 between the positive supply potential VDD and a first electrode of the capacitive element 246. The second electrode of the capacitive element 246 is electrically connected to the gate of the amplifier nFET 247. An integrator-on-signal SON controls a third switch 253 between the source follower control line 239 and the first electrode of the capacitive element 246. An integrator autozeroing signal SAZ controls a fourth switch 254 between the source follower control line 239 and the gate of the amplifier nFET 247. A constant current source 248 of the integrator circuit 244 is electrically connected between the positive supply potential VDD and the source follower control line 239.

Each of the first, second, third, and fourth switches 251, 252, 253, 254 can include a field effect transistor and/or a transmission gate. The constant current source 248 may be a field effect transistor with constant gate voltage. The source follower control line 239 may branch into a plurality of connection lines transmitting the voltage ramp signal VRMP to a plurality of source follower amplifiers 230-0, 230-1, ... assigned to different pixel rows.

FIG. 7A illustrates a first operation phase of the integrator circuit 244 of FIG. 6 up to tri. In the first operation phase, an active integrator initialization signal SINIT switches the second switch 252 on and an active integrator autozeroing signal SAZ switches the fourth switch 254 on. The first switch 251 and the third switch 253 are switched off. The fourth switch 254 short-circuits drain and gate of the amplifier nFET, so that the voltage ramp signal VRMP at the source follower control line 239 adjusts to the threshold voltage VGS of the amplifier nFET 247. The first electrode of the capacitive element 246 is precharged with the positive supply potential VDD via the second switch 252. The voltage across the precharged capacitive element 246 is VDD-VGS.

FIG. 7B illustrates a second operation phase between tri and tr2. In the second operation phase, the integrator-on-signal SON becomes active and switches the third switch 253 on to connect constant current source 248 with the source follower control line 239 and the first electrode of the capacitive element 246. The integrator autozeroing signal SAZ becomes inactive and switches off the fourth switch 254 to separate the gate from the drain of the amplifier nFET 247. The first switch 251 remains switched off and the second switch 252 remains switched on. The gate of the amplifier nFET 247 remains at low level. The constant current source 248 charges the source follower control line 239 to the positive supply potential VDD

FIG. 7C illustrates a third operation phase between tr2 and tr3. In the third operation phase, the integrator control signal SINTEG becomes active and switches on the first switch 251 to connect the integrator input line 249 with the gate of the amplifier nFET 247. The integrator initialization signal SINIT becomes inactive and switches off the second switch 252 to separate the first electrode of the capacitive element 246 from the positive supply potential VDD. The third switch 253 remains switched on and the fourth switch 254 remains switched off. The capacitive element 247 integrates the constant auxiliary current IAUX. The voltage at the gate of the amplifier nFET 247 linearly increases and the potential of the source follower control line 239 decreases accordingly.

FIG. 8 shows details of an integrator circuit 244 and a row driver circuit 220. The first switch 251 includes a current mirror, wherein the constant auxiliary current IAUX is a copy of a constant DAC output current IDAC. The integrator control signal SINTEG is applied to a pFET in a tail path of the current mirror. An active integrator control signal SINTEG switches on a tail current of the current mirror. An inactive integrator control signal SINTEG pulls the gate of the current mirror to the positive supply potential VDD and thus turns it off. The second switch 252 includes a pFET. The integrator initialization signal SINIT is applied to the gate of the pFET. The third switch 253 includes a transmission gate controlled by the inverted and the non-inverted instances of the integrator-on-signal SON. The fourth switch 254 includes an nFET. The integrator autozeroing signal SAZ is applied to the gate of the nFET. The integrator control signal SINTEG further controls a fifth switch 255 between the drain of the amplifier nFET 247 and the source follower control line 239. The fifth switch 255 includes a transmission gate connecting the source follower control line 239 to the drain of the amplifier nFET 247 when the integrator control signal SINTEG is active. The fifth switch 255 further includes a pFET connecting the source follower control line 239 to the positive supply potential VDD when the integrator control signal SINTEG is inactive. The row driver circuit 220 includes a CMOS inverter with the load paths of a pFET 226 and an nFET 221 electrically connected in series between the positive supply potential and the reference potential. The pixel control line 210 is shown with a line capacitance Cl.

In each of FIG. 9A with FIG. 9B and FIG. 10A with FIG. 10B, the row driver circuit 220 drives a second digital voltage level to the pixel control line 210 in a time period following the second time period t2.

The first and second digital voltage levels are complementary to each other. The second digital voltage level is the low level if the first digital voltage is the high level. The second digital voltage level is the high level if the first digital voltage is the low level. The row driver circuit 220 includes a pFET 226 and an nFET 221. Load paths of pFET 226 and the nFET 221 are electrically connected in series between the positive supply potential VDD and the reference potential VRL. A first digital preamplifier control signal VC1 is applied to the gate of the pFET 226. A second digital preamplifier control signal VC2 is applied to the gate of the nFET 221.

In FIG. 9A, the first digital voltage level is a digital high level. The source follower amplifier 230 includes a pFET 231 with a source/drain path electrically connected between the pixel control line 210 and a reference potential VRL. In the second time period t2, the voltage on the pixel control line 210 decreases.

In FIG. 9B, line 401 illustrates the voltage ramp signal VRMP applied to the gate of the source amplifier 230, line 402 the pixel control signal VOUT on the pixel control line 210, and line 403 the second preamplifier control signal VC2. The first preamplifier control signal VC1 switches on the row driver pFET 226 and connects the pixel control line 210 to the positive supply potential VDD for a first time period tl. The voltage ramp signal VRMP has a high level during the first time period tl so that the row driver pFET 226 can charge the pixel control line 210 to the positive supply potential VDD. At the beginning of the second time period t2, the first preamplifier control signal VC1 turns off the row driver pFET 226. The voltage ramp signal VRMP begins to fall. The source follower pFET 231 discharges the pixel control line 210 at a rate given by the slew rate of the falling slope of the voltage ramp signal VRMP. The pixel control signal VOUT on the pixel control line 210 reaches the threshold voltage Vthl of the source follower pFET 231 at the end of the second time period t2. The voltage of the pixel control line 210 may remain nearly unchanged for a third period t3. At the end of the third time period t3, the second preamplifier control signal VC2 becomes active and turns on the row driver nFET 221. The row driver nFET 221 pulls the potential of the pixel control line 210 down to the reference potential VRL for a fourth time period t4.

In FIG. 10A, the first digital voltage level is a digital low level, the source follower amplifier 230 includes an nFET 236 with a source/drain path electrically connected between the pixel control line 210 and a positive supply potential VDD. In the second time period t2, the voltage on the pixel control line 210 increases.

According to FIG. 10B, the second preamplifier control signal VC2 switches on the row driver nFET 221 for a first time period tl. The voltage ramp signal VRMP has a low level during the first time period tl so that the row driver nFET 221 can pull down the pixel control line 210 to the reference potential VRL for the first time period tl. At the beginning of the second time period t2, the second preamplifier control signal VC2 turns off the row driver nFET 221. The voltage ramp signal VRMP begins to rise. The source follower nFET 236 charges the pixel control line 210 at a rate given by the slew rate of the rising slope of the voltage ramp signal VRMP. The potential of the pixel control line 210 reaches the positive supply potential VDD reduced by the threshold voltage Vth2 of the source follower nFET 236 at the end of the second time period t2. The voltage of the pixel control line 210 may remain unchanged for a third time period t3. At the end of the third time period t3, the first preamplifier control signal VC 1 switches on the row driver pFET 226. The row driver pFET 226 pulls up the potential of the pixel control line 210 to the positive supply potential VDD for a fourth time period t4. The image sensor 70 of FIG. 11 includes a plurality of pixel rows 11 and a plurality of the pixel control lines 210, wherein each pixel control line 210 is connected to the pixel circuits 100 of a single pixel row 11. A plurality of the row driver circuits 220 drives the first digital voltage level to the pixel control lines 210 in the first time period and has a high output impedance in the second time period. A decoder unit 35 simultaneously applies a digital preamplifier signal to the inputs of the plurality row driver circuits 220.

The image sensor 70 further includes a plurality of the source follower amplifiers 230 configured to control voltages on the pixel control lines 210 depending on a signal applied to a gate of the source follower amplifiers 230 in the second time period. A voltage ramp circuit 240 outputs a voltage ramp signal to the gates of the source follower amplifiers 230.

First pixel control lines 210-1 connect first row driver circuits 220-1 with reset transistors 107 of the pixel circuits 100. For the first pixel control lines 210-1, the first digital voltage level is the digital high level. First source follower amplifiers 230-1 include pFETs with the load paths electrically connected between the first pixel control lines 210-1 and the reference potential VRL. The voltage on the first pixel control lines 210-1 falls in the second time periods.

Second pixel control lines 210-2 connect second row driver circuits 220-2 with select transistors 109 of the pixel circuits 100. For the second pixel control lines 210-2, the first digital voltage level is the digital low level. Second source follower amplifiers 230-2 include nFETs with the load paths electrically connected between the positive supply potential VDD and the first pixel control lines 210-1. The voltage on the second pixel control lines 210-2 rises in the second time periods.

The image sensor 70 further includes a first voltage ramp circuit 240-1 outputting a first voltage ramp signal to the gates of the first source follower amplifiers 231-1 in the second time period. A second voltage ramp circuit 240-2 outputs a second voltage ramp signal to the gates of the second source follower amplifiers 231-2 in the second time period.

FIG. 12 shows details of one example for the pixel circuits 100 of FIG. l and FIG. 11. The pixel circuit 100 includes a photoelectric conversion element 101. The photoelectric conversion element 101 photoelectrically converts incident electromagnetic radiation into electric charges. The amount of electric charge generated in the photoelectric conversion element 101 corresponds to the intensity of the incident electromagnetic radiation. The photoelectric conversion element 101 may include or consist of a photodiode which converts electromagnetic radiation incident on a detection surface into a detector current by means of the photoelectric effect. The electromagnetic radiation may include visible light, infrared radiation and/or ultraviolet radiation. The amplitude of the detector current corresponds to the intensity of the incident electromagnetic radiation, wherein in the intensity range of interest the detector current increases approximately linearly with increasing intensity of the detected electromagnetic radiation. Each pixel circuit 100 further includes a charge accumulation region 105 for temporarily storing charge as a function of received light intensity, and a reset transistor 107 for initializing a charge in the charge accumulation region 105 in response to an active reset signal RST applied to a gate of the reset transistor 107. The pixel control line 210 is electrically connected to the gates of the reset transistors 107 of the pixel row 11.

The charge accumulation region 105 can include a floating diffusion region and/or a capacitor electrode. In a reset phase, a potential Vfd of the charge accumulation region 105 is a function of the pixel dark current representing the noise. In a data phase, the potential Vfd is a function of the integrated photocurrent. The pixel control line 210 can be one of the first pixel control lines 210-1 of FIG. 11.

The reset signal RST is supplied to the gate of the reset transistor 107 through a reset control line. The reset signal RST changes between an active signal level (“active reset signal”) and an inactive signal level (“inactive reset signal”). In response to an active reset signal RST, the reset transistor 107 connects the charge accumulation region 105 to the positive supply potential VDD. In the illustrated embodiment, the active signal level is the high level.

A load path of a transfer transistor 102 is electrically connected between a cathode of the photoelectric conversion element 101 and the charge accumulation region 105. The transfer transistor 102 serves as transfer element for transferring charge from the photoelectric conversion element 101 to the charge accumulation region 105 in an integration period. The charge accumulation region 105 serves as temporary local charge storage. A transfer signal TRG is supplied to the gate (transfer gate) of the transfer transistor 102 through a transfer control line. The transfer signal TRG changes between an active signal level (“active transfer signal”) and an inactive signal level (“inactive transfer signal”). In response to an active transfer signal TRG, the transfer transistor 102 transfers electrons photoelectrically converted by the photoelectric conversion element 101 to the charge accumulation region 105. In the illustrated embodiment, the active signal level is the high level.

An amplifier transistor 108 is in a source follower configuration with the controlled load path electrically connected between the positive supply potential VDD and a data node 18. The data node 18 may form a signal interface between a radiation sensitive portion and a voltage storage portion of a pixel circuit 100 of the global shutter type or a data signal line connecting pixel circuits of the same pixel column. The charge accumulation region 105 is connected to the gate of the amplifier transistor 108. A potential at the gate of the front stage amplifier transistor 118 is equal to the potential Vfd of the charge accumulation region 105.

Each pixel circuit 100 includes a select transistor 109 configured to pass a pixel voltage signal in response to an active select signal SEL applied to a gate of the select transistor 109, and wherein the pixel control line 210 is electrically connected to the gates of the select transistors 109 of the pixel row 11.

A load path of the amplifier transistor 108 and a load path of the select transistor 109 are electrically connected in series between the positive supply potential VDD and the data node 18. A row select signal SEL is supplied to the gate of the select transistor 109 through a select control line. The select signal SEL changes between an active signal level (“active select signal”) and an inactive signal level (“inactive select signal”). In the illustrated embodiment, the select transistor 109 is an nFET and the active signal level is the high level.

FIG. 13A and FIG. 13B each show a row driver circuit 220 outputting a reset signal RST on a pixel control line 210 electrically connected to the reset transistors of a pixel row 11 with 1280 pixel circuits 100. The pixel circuit 100 at the near end on the left side of the pixel row 11 is close to the output of the row driver circuit 220. The pixel circuit 100 at the far end on the right side of the pixel row 11 is further away from the output of the row driver circuit 220. Without further wiring, the row driver circuit 220 outputs a reset signal RST with steep, fast slopes.

In FIG. 13 A, the inherent delay on the pixel control line 210 increasingly distorts the reset signal RST along the pixel control line 210 as the distance to the output of the row driver circuit 220 increases. The fast fall time at the near end suffers comparatively high dispersion until the reset signal RST reaches the far end. Charge injection into the charge accumulation structure 105 when the reset transistors 107 are turned off vanes across the pixel row and can result in an artifact characterized by an artificial brightness gradient along the pixel row direction.

In FIG. 13B, source follower amplifiers 230 are connected between the pixel control line 210 and the reference potential VRL. A voltage ramp signal VRMP controls the source follower amplifiers 230. The falling slopes of the reset signal RST are flatter and have slower slew rates. The slow fall time at the near end has a comparatively low dispersion until the reset signal RST reaches the far end. The longer the fall time is in relation to the time constant of the pixel control line 210, the more uniform the falling slope is over the length of the pixel control line 210. Gradient artifacts can be significantly reduced.

In the upper diagram of FIG. 14, line 501 shows the falling slope of the reset signal RST for a row driver configuration as illustrated in FIG. 13A at the near end and line 502 shows the falling slope of the reset signal RST at the far end. The timing difference for the threshold voltage can be some ten nanoseconds.

In the lower diagram of FIG. 14, line 511 shows the response of the potential Vfd of the charge accumulation structure 105 to the reset signal RST at the near end and line 512 shows the response of the potential Vfd of the charge accumulation structure 105 to the reset signal RST at the far end. The potential Vfd at the far end can be some ten mV higher that at the near end.

In the upper diagram of FIG. 15, line 521 shows the falling slope of the reset signal RST for a row driver configuration as illustrated in FIG. 13B at the near end and line 522 shows the falling slope of the reset signal RST at the far end. The timing difference is comparatively small.

In the lower diagram of FIG. 15, line 531 shows the response of the potential Vfd of the charge accumulation structure 105 to the reset signal RST at the near end and line 532 shows the response of the potential Vfd of the charge accumulation structure 105 to the reset signal RST at the far end. The potential difference between the far end and the near end is about one order of magnitude lower than without source follower amplifier 230.

FIG. 16 shows a pixel circuit 100 of an image sensor for global shutter. Each pixel circuit 100 includes a radiation receiving portion 310, 320 configured to supply a pixel voltage signal with a voltage level being a function of incoming radiation intensity, a voltage storage portion 330 configured to receive and temporarily store the pixel voltage signal, and at least one select transistor 109 for passing the pixel voltage signal from the radiation receiving portion 310, 320 to the voltage storage portion 330 in response to an active global shutter signal SEL applied to a gate of the select transistor 109.

The illustrated pixel circuit 100 includes two radiation receiving portions 310, 320. Each radiation receiving portion 310, 320 is a four-transistor pixel for analog readout as described above with reference to FIG. 12. An active first global shutter signal SEL1 switches on the select transistor 109 in the first radiation receiving portion 310 and the first radiation receiving portion 310 outputs analog pixel voltage signals for the data phase and the reset phase to the voltage storage portion 330. An active second global shutter signal SEL2 switches on the select transistor 109 in the second radiation receiving portion 320 and the second radiation receiving portion 320 outputs the analog pixel voltages for the data phase and the reset phase to the voltage storage portion 330. The voltage storage portion 330 consecutively stores the analog pixel voltages on capacitors.

The radiation receiving portions 310, 320 can be formed on a first chip 910. The voltage storage portion 330 can be formed on a second chip 920. The first chip 910 and the second chip 920 are bonded together. The pixel voltage signals are transmitted through directly bonded connections 915 from the first chip 910 to the second chip 920.

The lower diagram in FIG. 17 shows the rising slope of different select signals SEL with active high level. The select signal SEL may be each of the first and second global shutter signals SEL1, SEL2 of FIG. 16. Line 911 shows the select signal with the fastest rising slope. Lines 912, 913, 914 show select signals with increasingly slower rising slope.

In the upper diagram of FIG. 17, line 921 shows the inrush current for a select signal SEL with a slew rate as indicated by line 911, line 922 the inrush current for a select signal SEL with a slew rate as indicated by line 912, line 923 shows the inrush current for a select signal SEL with a slew rate as indicated by line 913, and line 924 shows the inrush current for a select signal SEL with a slew rate as indicated by line 914.

If the select signal is a global shutter signal, a large number of pixel circuits are triggered simultaneously for pixel readout, and a peak inrush current may be in a range of 0.5 A. The high inrush current can cause a high instantaneous supply voltage drop and may overload an external power supply. Both effects have a detrimental effect on the performance of the image sensor. The source follower amplifier enables precise control of the tum-on signal slope and thus optimization of the inrush current compared to a possible time delay associated with the slower signal slope.

The present disclosure is related to a solid-state imaging device that includes an image sensor 70 as illustrated in FIG. 1 or FIG. 11. The image sensor includes a pixel array 10 having a plurality of pixel rows 11, wherein each pixel row 11 includes a plurality of pixel circuits 100. The image sensor includes first pixel control lines 210-1, wherein each first pixel control line 210-1 is connected to the pixel circuits 100 of a single pixel row 11. The image sensor includes first row driver circuits 220-1, wherein each first row driver circuit 220-1 is configured to output a first digital voltage level to a single first pixel control line 210- 1 in a first time period and to have a high output impedance in a second time period. The image sensor includes first source follower amplifiers 230-1, wherein each first source follower amplifier 230-1 is configured to control a voltage on one of the first pixel control lines 210-1 depending on a signal applied to a gate of the first source follower amplifier 230-1 in the second time period.

A first voltage ramp circuit 240-1 may be configured to output a voltage ramp signal to the gates of the first source follower amplifiers 231 in the second time period. The image sensor may include second pixel control lines 210-2, wherein each second pixel control line 210-2 is connected to the pixel circuits 100 of a single pixel row 11. The image sensor may include second row driver circuits 220-2, wherein each second row dnver circuit 220-2 is configured to output a second digital voltage level to a single second pixel control line 210-2 in a fifth time period and to have a high output impedance in a sixth time period. The image sensor may include second source follower amplifiers 230-2, wherein each second source follower amplifier 230-2 is configured to control a voltage on one of the second pixel control lines 210-2 depending on a signal applied to a gate of the second source follower amplifier 230-2 in the sixth time period. A second voltage ramp circuit 240-2 may be configured to output a second voltage ramp signal to the gates of the second source follower amplifiers 230-2 in the sixth time period.

Each pixel circuit 100 may include a charge accumulation region 105 for temporarily storing a charge as a function of received light intensity, and a reset transistor 107 for initializing the charge in the charge accumulation region 105 in response to a reset signal applied to a gate of the reset transistor 107. The first pixel control lines 210-1 are electrically connected to the gates of the reset transistors 107.

Alternatively or in addition, each pixel circuit 100 may include a radiation receiving portion 310, 320 configured to supply a pixel voltage signal with a voltage level being a function of incoming radiation intensity, a voltage storage portion 330 configured to receive and temporarily store the pixel voltage signal, and a select transistor 109 for passing the pixel voltage signal from the radiation receiving portion 310, 320 to the voltage storage portion 330. Each second pixel control line 210-2 is electrically connected to the gates of the select transistors 109.

FIG. 18 is a diagram illustrating an example in which the image sensors 70 of FIG. 1 and FIG. 11A is formed by a stacked CMOS image sensor (CIS) having a two-layer structure with a first chip 910 (radiation receiving chip) and a second chip 920 (processing chip). The radiation receiving chip includes at least the photoelectric conversion elements. For example, the radiation receiving chip may include only the photoelectric conversion elements, only the conversion portions of the pixel circuits, or the conversion portions and at least some elements of the PWM portions of the pixel circuits. The image sensor assembly is formed as one sensor by bonding the radiation receiving chip and the processing chip while electrically bringing contact pads on the radiation receiving chip in contact with corresponding contact pads on the processing chip.

FIG. 19 is a block diagram depicting an example of schematic configuration of a vehicle control system as an example of a system to which the technology according to an embodiment of the present disclosure can be applied.

The vehicle control system 12000 includes a plurality of electronic control units connected to each other via a communication network 12001. In the example depicted in FIG. 19, the vehicle control system 12000 includes a driving system control unit 12010, a body system control unit 12020, an outside-vehicle information detecting unit 12030, an in-vehicle information detecting unit 12040, and an integrated control unit 12050. In addition, a microcomputer 12051, a sound/image output section 12052, and a vehiclemounted network interface 12053 are illustrated as a functional configuration of the integrated control unit 12050.

The driving system control unit 12010 controls the operation of devices related to the driving system of the vehicle in accordance with various kinds of programs. For example, the driving system control unit 12010 functions as a control device for a driving force generating device for generating the driving force of the vehicle, such as an internal combustion engine, a driving motor, or the like, a driving force transmitting mechanism for transmitting the driving force to wheels, a steering mechanism for adjusting the steering angle of the vehicle, a braking device for generating the braking force of the vehicle, and the like.

The body system control unit 12020 controls the operation of various kinds of devices provided to a vehicle body in accordance with various kinds of programs. For example, the body system control unit 12020 functions as a control device for a keyless entry system, a smart key system, a power window device, or various kinds of lamps such as a headlamp, a backup lamp, a brake lamp, a turn signal, a fog lamp, or the like. In this case, radio waves transmitted from a mobile device as an alternative to a key or signals of various kinds of switches can be input to the body system control unit 12020. The body system control unit 12020 receives these input radio waves or signals, and controls a door lock device, the power window device, the lamps, or the like of the vehicle.

The outside-vehicle information detecting unit 12030 detects information about the outside of the vehicle including the vehicle control system 12000. The outside-vehicle information detecting unit 12030 can be connected with an imaging section 12031. The outside-vehicle information detecting unit 12030 makes the imaging section 12031 imaging an image of the outside of the vehicle and receives the imaged image. Based on the received image, the outside-vehicle information detecting unit 12030 may perform processing of detecting an object such as a human, a vehicle, an obstacle, a sign, a character on a road surface, or the like, or processing of detecting a distance thereto.

The imaging section 12031 maybe or may include an image sensor assembly according to the embodiments of the present disclosure. The light received by the imaging section 12031 may contain visible light and/or invisible light such as infrared rays or the like.

The in-vehicle information detecting unit 12040 detects information about the inside of the vehicle and may be or may include an image sensor assembly according to the embodiments of the present disclosure. The in-vehicle information detecting unit 12040 is, for example, connected with a driver state detecting section 12041 that detects the state of a driver. The driver state detecting section 12041, for example, includes a camera that includes the solid-stage imaging device and that is focused on the driver. Based on detection information input from the driver state detecting section 12041, the in-vehicle information detecting unit 12040 may calculate a degree of fatigue of the driver or a degree of concentration of the driver or may determine whether the driver is dozing.

The microcomputer 12051 can calculate a control target value for the driving force generating device, the steering mechanism, or the braking device based on the information about the inside or outside of the vehicle which information is obtained by the outside-vehicle information detecting unit 12030 or the in- vehicle information detecting unit 12040 and output a control command to the driving system control unit 12010. For example, the microcomputer 12051 can perform cooperative control intended to implement functions of an advanced driver assistance system (ADAS) which functions include collision avoidance or shock mitigation for the vehicle, following driving based on a following distance, vehicle speed maintaining driving, a warning of collision of the vehicle, a warning of deviation of the vehicle from a lane, or the like.

In addition, the microcomputer 12051 can perform cooperative control intended for automatic driving, which makes the vehicle to travel autonomously without depending on the operation of the driver, or the like, by controlling the driving force generating device, the steering mechanism, the braking device, or the like on the basis of the information about the outside or inside of the vehicle which information is obtained by the outside-vehicle information detecting unit 12030 or the in-vehicle information detecting unit 12040.

In addition, the microcomputer 12051 can output a control command to the body system control unit 12020 based on the information about the outside of the vehicle which information is obtained by the outsidevehicle information detecting unit 12030. For example, the microcomputer 12051 can perform cooperative control intended to prevent a glare by controlling the headlamp so as to change from a high beam to a low beam, for example, in accordance with the position of a preceding vehicle or an oncoming vehicle detected by the outside-vehicle information detecting unit 12030.

The sound/image output section 12052 transmits an output signal of at least one of a sound or an image to an output device capable of visually or audible notifying information to an occupant of the vehicle or the outside of the vehicle. In the example of FIG. 19, an audio speaker 12061, a display section 12062, and an instrument panel 12063 are illustrated as the output device. The display section 12062 may, for example, include at least one of an on-board display or a head-up display.

FIG. 20 is a diagram depicting an example of the installation position of the imaging section 12031, wherein the imaging section 12031 may include imaging sections 12101, 12102, 12103, 12104, and 12105.

The imaging sections 12101, 12102, 12103, 12104, and 12105 are, for example, disposed at positions on a front nose, side-view mirrors, a rear bumper, and a back door of the vehicle 12100 as well as a position on an upper portion of a windshield within the interior of the vehicle. The imaging section 12101 provided to the front nose and the imaging section 12105 provided to the upper portion of the windshield within the interior of the vehicle obtain mainly an image of the front of the vehicle 12100. The imaging sections 12102 and 12103 provided to the side view mirrors obtain mainly an image of the sides of the vehicle 12100. The imaging section 12104 provided to the rear bumper or the back door obtains mainly an image of the rear of the vehicle 12100. The imaging section 12105 provided to the upper portion of the windshield within the interior of the vehicle is used mainly to detect a preceding vehicle, a pedestrian, an obstacle, a signal, a traffic sign, a lane, or the like.

Incidentally, FIG. 20 depicts an example of photographing ranges of the imaging sections 12101 to 12104. An imaging range 12111 represents the imaging range of the imaging section 12101 provided to the front nose. Imaging ranges 12112 and 12113 respectively represent the imaging ranges of the imaging sections 12102 and 12103 provided to the side view mirrors. An imaging range 12114 represents the imaging range of the imaging section 12104 provided to the rear bumper or the back door. A bird's-eye image of the vehicle 12100 as viewed from above is obtained by superimposing image data imaged by the imaging sections 12101 to 12104, for example.

At least one of the imaging sections 12101 to 12104 may have a function of obtaining distance information. For example, at least one of the imaging sections 12101 to 12104 may be a stereo camera constituted of a plurality of imaging elements, imaging element having pixels for phase difference detection or may include a ToF module including an image sensor according to the embodiments of the present disclosure.

For example, the microcomputer 12051 can determine a distance to each three-dimensional object within the imaging ranges 12111 to 12114 and a temporal change in the distance (relative speed with respect to the vehicle 12100 on the basis of the distance information obtained from the imaging sections 12101 to 12104, and thereby extract, as a preceding vehicle, a nearest three-dimensional object in particular that is present on a traveling path of the vehicle 12100 and which travels in substantially the same direction as the vehicle 12100 at a predetermined speed (for example, equal to or more than 0 km/hour). Further, the microcomputer 12051 can set a following distance to be maintained in front of a preceding vehicle in advance and perform automatic brake control (including following stop control), automatic acceleration control (including following start control), or the like. It is thus possible to perform cooperative control intended for automatic driving that makes the vehicle travel autonomously without depending on the operation of the driver or the like. For example, the microcomputer 12051 can classify three-dimensional object data on three-dimensional objects into three-dimensional object data of a two-wheeled vehicle, a standard-sized vehicle, a large-sized vehicle, a pedestrian, a utility pole, and other three-dimensional objects on the basis of the distance information obtained from the imaging sections 12101 to 12104, extract the classified three-dimensional object data, and use the extracted three-dimensional object data for automatic avoidance of an obstacle. For example, the microcomputer 12051 identifies obstacles around the vehicle 12100 as obstacles that the driver of the vehicle 12100 can recognize visually and obstacles that are difficult for the driver of the vehicle 12100 to recognize visually. Then, the microcomputer 12051 determines a collision risk indicating a risk of collision with each obstacle. In a situation in which the collision risk is equal to or higher than a set value and there is thus a possibility of collision, the microcomputer 12051 outputs a warning to the driver via the audio speaker 12061 or the display section 12062 and performs forced deceleration or avoidance steering via the driving system control unit 12010. The microcomputer 12051 can thereby assist in driving to avoid collision.

At least one of the imaging sections 12101 to 12104 may be an infrared camera that detects infrared rays. The microcomputer 12051 can, for example, recognize a pedestrian by determining whether there is a pedestrian in imaged images of the imaging sections 12101 to 12104. Such recognition of a pedestrian is, for example, performed by a procedure of extracting characteristic points in the imaged images of the imaging sections 12101 to 12104 as infrared cameras and a procedure of determining whether it is the pedestrian by performing pattern matching processing on a series of characteristic points representing the contour of the object. When the microcomputer 12051 determines that there is a pedestrian in the imaged images ofthe imaging sections 12101 to 12104, and thus recognizes the pedestrian, the sound/image output section 12052 controls the display section 12062 so that a square contour line for emphasis is displayed so as to be superimposed on the recognized pedestrian. The sound/image output section 12052 may also control the display section 12062 so that an icon or the like representing the pedestrian is displayed at a desired position.

The example of the vehicle control system to which the technology according to an embodiment of the present disclosure is applicable has been described above. By applying an image sensor according to the embodiments ofthe present disclosure, better image quality can be achieved..

Additionally, embodiments of the present technology are not limited to the above-described embodiments, but various changes can be made within the scope of the present technology without departing from the gist of the present technology.

The image sensor according to the present disclosure may be any device used for analyzing and/or processing radiation such as visible light, infrared light, ultraviolet light, and X-rays. For example, an image sensor according to the embodiments may be any electronic device in the field of traffic, the field of home appliances, the field of medical and healthcare, the field of security, the field of beauty, the field of sports, the field of agriculture, the field of image reproduction or the like. Specifically, in the field of image reproduction, the image sensor according to the embodiments may be a device for capturing an image to be provided for appreciation, such as a digital camera, a smart phone, or a mobile phone device having a camera function. In the field of traffic, for example, a solid-state imaging device including an image sensor according to the embodiments may be integrated in an in-vehicle sensor that captures the front, rear, peripheries, an interior of the vehicle, etc. for safe driving such as automatic stop, recognition of a state of a driver, or the like, in a monitoring camera that monitors traveling vehicles and roads, or in a distance measuring sensor that measures a distance between vehicles or the like.

In the field of home appliances, the image sensor according to the embodiments may be integrated in any type of sensor that can be used in devices provided for home appliances such as TV receivers, refrigerators, and air conditioners to capture gestures of users and perform device operations according to the gestures. Accordingly, the image sensor according to the embodiments may be integrated in home appliances such as TV receivers, refrigerators, and air conditioners and/or in devices controlling the home appliances. Furthermore, in the field of medical and healthcare, the image sensor according to the embodiments may be integrated in any type of sensor, e.g., a solid-state image device, provided for use in medical and healthcare, such as an endoscope or a device that performs angiography by receiving infrared light.

In the field of security, the image sensor according to the embodiments can be integrated in a device provided for use in security, such as a monitoring camera for crime prevention or a camera for person authentication use. Furthermore, in the field of beauty, an image sensor according to the embodiments can be used in a device provided for use in beauty, such as a skin measuring instrument that captures skin or a microscope that captures a probe. In the field of sports, an image sensor according to the embodiments can be integrated in a device provided for use in sports, such as an action camera or a wearable camera for sport use or the like. Furthermore, in the field of agriculture, the image sensor can be used in a device provided for use in agriculture, such as a camera for monitoring the condition of fields and crops.

The present technology can also be configured as described below: [1] An image sensor, including: a pixel control line (210) connected to pixel circuits (100) of a pixel row (11); a row driver circuit (220) configured to drive a first digital voltage level to the pixel control line (210) in a first time period and to have a high output impedance in a second time period; and a source follower amplifier (230) configured to control a voltage on the pixel control line (210) depending on a signal applied to a gate of the source follower amplifier (230) in the second time period.

[2] The image sensor according to [1], further including: a voltage ramp circuit (240) configured to output a voltage ramp signal to the gate of the source follower amplifier (230).

[3] The image sensor according to [2], wherein the voltage ramp circuit (240) includes a current source (243) configured to output a constant auxiliary current and an integrator circuit (244) configured to obtain the voltage ramp signal by integrating the auxiliary current. [4] The image sensor according to [3], wherein the integrator circuit (244) includes an inverting amplifier element (245) and a capacitive element (246) in a feedback path between an amplifier output and an amplifier input of the amplifier element (245).

[5] The image sensor according to [4], wherein the integrator circuit (244) is disconnectable from the current source (243) to autozero the amplifier element (245), to initialize a voltage across the capacitive element (246), and to initialize an output voltage of the amplifier element (245) in an autozeroing period.

[6] The image sensor according to any of [1] to [5], wherein the row driver circuit (220) is further configured to drive a second digital voltage level to the pixel control line (210) in a time period following the second time period.

[7] The image sensor according to any of [1] to [6], wherein the first digital voltage level is a digital high level, the source follower amplifier (230) includes a p channel field effect transistor (231) with a source/drain path electrically connected between the pixel control line (210) and a reference potential, and the voltage on the pixel control line (210) decreases in the second time period.

[8] The image sensor according to any of [1] to [7], wherein the first digital voltage level is a digital low level, the source follower amplifier (230) includes an n channel field effect transistor (236) with a source/drain path electrically connected between the pixel control line (210) and a positive supply potential, and wherein the voltage on the pixel control line (210) increases in the second time period.

[9] The image sensor according to any of [1] to [8], further including: a plurality of the pixel rows (11); a plurality of the pixel control lines (210), wherein each pixel control line (210) is connected to the pixel circuits (100) of a single pixel row; a plurality of the row driver circuits (220) configured to drive the first digital voltage level to the pixel control lines (210) in the first time period and to have a high output impedance in the second time period; and a decoder unit (35) configured to simultaneously apply a digital preamplifier control signal to inputs of the row driver circuits (220).

[10] The image sensor according to [9], including: a plurality of the source follower amplifiers (230) configured to control voltages on the pixel control lines (210) depending on a signal applied to a gate of the source follower amplifiers (230) in the second time period; and a voltage ramp circuit (240) configured to output a voltage ramp signal to the gates of the source follower amplifiers (230).

[11] The image sensor according to [10], further including: a first voltage ramp circuit (240-1) configured to output a first voltage ramp signal to the gates of the first source follower amplifiers (231-1) in the second time period, and a second voltage ramp circuit (240-2) configured to output a second voltage ramp signal to the gates of the second source follower amplifiers (231-2) in the second time period.

[12] The image sensor according to any of [1] to [11], wherein each pixel circuit (100) includes a charge accumulation region (105) for temporarily storing a charge as a function of received light intensity, and a reset transistor (107) for initializing a charge in the charge accumulation region (105) in response to an active reset signal applied to a gate of the reset transistor (107), and wherein the pixel control line (210) is electrically connected to the gates of the reset transistors (107) of the pixel row (11).

[13] The image sensor according to any of [1] to [12], wherein each pixel circuit (100) includes a select transistor (109) configured to pass a pixel voltage signal in response to an active select signal applied to a gate of the select transistor (109), and wherein the pixel control line (210) is electrically connected to the gates of the select transistors (109) of the pixel row (11).

[14] The image sensor according to any of [1] to [13], wherein each pixel circuit (100) includes a radiation receiving portion (310, 320) configured to supply a pixel voltage signal with a voltage level being a function of incoming radiation intensity, a voltage storage portion (330) configured to receive and temporarily store the pixel voltage signal, and at least one select transistor (109) for passing the pixel voltage signal from the radiation receiving portion (310, 320) to the voltage storage portion (330) in response to a global shutter signal applied to a gate of the select transistor (109).

[15] A solid-state imaging device, including: a pixel array (10) including a plurality of pixel rows (11), each pixel row (11) including a plurality of pixel circuits (100); first pixel control lines (210-1), wherein each first pixel control line (210-1) is connected to the pixel circuits (100) of a single pixel row (11); first row driver circuits (220-1), wherein each first row driver circuit (220-1) is configured to output a first digital voltage level to a single first pixel control line (210-1) in a first time period and to have a high output impedance in a second time period; and first source follower amplifiers (230-1), wherein each first source follower amplifier (230-1) is configured to control a voltage on one of the first pixel control lines (210-1) depending on a signal applied to a gate of the first source follower amplifier (230-1) in the second time period.

Claims

1. An image sensor, comprising: a pixel control line connected to pixel circuits of a pixel row; a row driver circuit configured to drive a first digital voltage level to the pixel control line in a first time period and to have a high output impedance in a second time period; and a source follower amplifier configured to control a voltage on the pixel control line depending on a signal applied to a gate of the source follower amplifier in the second time period.

2. The image sensor according to claim 1, further comprising: a voltage ramp circuit configured to output a voltage ramp signal to the gate of the source follower amplifier.

3. The image sensor according to claim 2, wherein the voltage ramp circuit comprises a current source configured to output a constant auxiliary current and an integrator circuit configured to obtain the voltage ramp signal by integrating the auxiliary current.

4. The image sensor according to claim 3, wherein the integrator circuit comprises an inverting amplifier element and a capacitive element in a feedback path between an amplifier output and an amplifier input of the amplifier element.

5. The image sensor according to claim 4, wherein the integrator circuit is disconnectable from the current source to autozero the amplifier element, to initialize a voltage across the capacitive element, and to initialize an output voltage of the amplifier element in an autozeroing period.

6. The image sensor according to claim 1, wherein the row driver circuit is further configured to drive a second digital voltage level to the pixel control line in a time period following the second time period.

7. The image sensor according to claim 1, wherein the first digital voltage level is a digital high level, the source follower amplifier comprises a p channel field effect transistor with a source/drain path electrically connected between the pixel control line and a reference potential, and the voltage on the pixel control line decreases in the second time period.

8. The image sensor according to claim 1, wherein the first digital voltage level is a digital low level, the source follower amplifier comprises an n channel field effect transistor with a source/drain path electrically connected between the pixel control line and a positive supply potential, and wherein the voltage on the pixel control line increases in the second time period.

9. The image sensor according to claim 1, further comprising: a plurality of the pixel rows; a plurality of the pixel control lines, wherein each pixel control line is connected to the pixel circuits of a single pixel row; a plurality of the row driver circuits configured to drive the first digital voltage level to the pixel control lines in the first time period and to have a high output impedance in the second time period; and a decoder unit configured to simultaneously apply a digital preamplifier control signal to inputs of the row driver circuits.

10. The image sensor according to claim 9, comprising: a plurality of the source follower amplifiers configured to control voltages on the pixel control lines depending on a signal applied to a gate of the source follower amplifiers in the second time period; and a voltage ramp circuit configured to output a voltage ramp signal to the gates of the source follower amplifiers.

11. The image sensor according to claim 10, further comprising: a first voltage ramp circuit configured to output a first voltage ramp signal to the gates of the first source follower amplifiers in the second time period, and a second voltage ramp circuit configured to output a second voltage ramp signal to the gates of the second source follower amplifiers in the second time period.

12. The image sensor according to claim 1, wherein each pixel circuit includes a charge accumulation region for temporarily storing a charge as a function of received light intensity, and a reset transistor for initializing a charge in the charge accumulation region in response to an active reset signal applied to a gate of the reset transistor, and wherein the pixel control line is electrically connected to the gates of the reset transistors of the pixel row.

13. The image sensor according to claim to 1, wherein each pixel circuit includes a select transistor configured to pass a pixel voltage signal in response to an active select signal applied to a gate of the select transistor, and wherein the pixel control line is electrically connected to the gates of the select transistors of the pixel row.

14. The image sensor according to claim 1, wherein each pixel circuit comprises a radiation receiving portion configured to supply a pixel voltage signal with a voltage level being a function of incoming radiation intensity, a voltage storage portion configured to receive and temporarily store the pixel voltage signal, and at least one select transistor for passing the pixel voltage signal from the radiation receiving portion to the voltage storage portion in response to a global shutter signal applied to a gate of the select transistor.

15. A solid-state imaging device, comprising: a pixel array comprising a plurality of pixel rows, each pixel row comprising a plurality of pixel circuits; first pixel control lines, wherein each first pixel control line is connected to the pixel circuits of a single pixel row; first row driver circuits, wherein each first row driver circuit is configured to output a first digital voltage level to a single first pixel control line in a first time period and to have a high output impedance in a second time period; and first source follower amplifiers, wherein each first source follower amplifier is configured to control a voltage on one of the first pixel control lines depending on a signal applied to a gate of the first source follower amplifier in the second time period.