WO2025201264A1 - Power supply short-circuit detection circuit and detection method - Google Patents

Abstract

A power supply short-circuit detection circuit and detection method. The circuit comprises a processing chip, a charging circuit module, an output loop module and a comparison circuit, wherein the output loop module is connected between the charging circuit module and the comparison circuit, and the output loop module is further connected to the processing chip; the output loop module comprises N control loops, each of which comprises a signal input end, a switching transistor and a connection end; the processing chip is used for activating any one of the N control loops as a target control loop to perform power supply short-circuit detection; the comparison circuit is used for receiving an output voltage of the target control loop and comparing same with a reference voltage, and outputting a high-level or low-level comparison result to the processing chip; and the processing chip is used for receiving the comparison result outputted from the comparison circuit and determining, on the basis of the comparison result, whether the target control loop has a power supply short-circuit fault. The detection circuit implements remote short-circuit detection for a power supply loop, thereby improving detection efficiency and reducing labor costs.

Description

Power supply short circuit detection circuit and detection method

CROSS-REFERENCE TO RELATED APPLICATIONS

This application claims priority to the Chinese patent application filed with the Patent Office of China on March 29, 2024, with application number 202410374196.4 and application name “A Power Short Circuit Detection Circuit and Detection Method”, the entire contents of which are incorporated herein by reference.

Technical Field

The present application relates to the technical field of electronic circuits, and in particular to a power supply short circuit detection circuit and detection method.

Background Art

As the number of large data centers increases, the number of servers contained within them also increases. Consequently, the probability of server failure also increases, making server fault detection and maintenance a critical task. When a server experiences an abnormality upon startup, it could be due to a variety of reasons, one of which could be a short circuit within the server. One detection method involves on-site disassembly to check for a short circuit within the server, but this requires an engineer to be present on-site. Given the widespread distribution of data centers, where the potential for short circuits is unknown, disassembling the server on-site to check for a short circuit is inefficient and costly.

In addition, another detection method is to remotely power on the server, which may cause burning in the short-circuit area, exacerbating the short circuit and causing damage to the internal circuit of the server.

Summary of the Invention

In view of this, the present application provides a power short circuit detection circuit and detection method for remotely detecting whether a short circuit occurs in the power circuit inside the server, thereby avoiding the need for maintenance engineers to arrive at the site to disassemble the server for inspection.

In a first aspect, the present application provides a power short circuit detection circuit, the circuit comprising: a processing chip, a charging circuit module, an output loop module and a comparison circuit;

The output circuit module is connected between the charging circuit module and the comparison circuit, and the output circuit module is also connected to at least one signal output terminal of the processing chip;

The output circuit module includes N control circuits, each of which includes a signal input terminal, a switch tube, and a connection terminal. Each signal input terminal is connected to a signal output terminal of the processing chip to receive a control signal output from the processing chip. Each connection terminal is used to connect to a power circuit inside the server. The switch tube is arranged between the signal input terminal and the connection terminal to control whether the control circuit in which it is located is turned on or off. N ≥ 1 and is a positive integer.

A processing chip is used to start any one of the N control loops as a target control loop for power short circuit detection, and to control other control loops except the target control loop to be in a closed state. After the target control loop is started, power is supplied through the charging circuit module;

A comparison circuit is used to receive the output voltage of the target control loop, compare it with the reference voltage, and output a high or low level comparison result to the processing chip;

The processing chip is used to receive the comparison result output from the comparison circuit and determine whether a power short circuit fault occurs in the target control loop according to the comparison result.

The power short-circuit detection circuit provided in this aspect includes an output circuit module, which includes N control circuits and can be used to connect multiple power circuits inside a server. By processing the detection enable signal of the chip and the control signal input to any one of the N control circuits, one of the N control circuits is turned on, and short-circuit detection of the power circuit of the server connected to the control circuit is started. The output voltage collected by the comparison circuit is compared with the reference voltage to obtain a comparison result of a high-level or low-level signal, thereby realizing remote short-circuit detection of the power circuit, improving detection efficiency, and saving labor costs.

In addition, this detection circuit is used to remotely control the output circuit module to start short-circuit detection inside the server before the server is powered on or when the server cannot be powered on, so as to promptly detect whether a short circuit has occurred in the power circuit, avoiding the maintenance engineer from disassembling the server on site to detect whether a fault has occurred, and also avoiding damage to the server caused by restarting the server again after a short circuit.

In combination with the first aspect, in some possible implementations, the comparison circuit is specifically used to: output a high-level signal to the processing chip when the comparison output voltage is greater than or equal to the reference voltage; and output a low-level signal to the processing chip when the comparison output voltage is less than the reference voltage.

In conjunction with the first aspect, in some possible implementations, the processing chip is specifically configured to: determine that a power short circuit has not occurred in the target control circuit upon receiving a high-level signal from the comparison circuit; and determine that a power short circuit has occurred in the target control circuit upon receiving a low-level signal from the comparison circuit. This implementation utilizes a comparison circuit to detect a short circuit in a power circuit within the server, eliminating the need for maintenance engineers to arrive on-site for disassembly and inspection. This improves detection efficiency and saves labor costs.

In conjunction with the first aspect, in some possible implementations, the switch tube of each control loop is a MOS tube, the g pole of the MOS tube is connected to the signal input terminal, the d pole of the MOS tube is connected to the power output terminal of the charging circuit module, and the s pole of the MOS tube is connected to the connection terminal;

When the processing chip inputs low-level signals to the N signal input terminals of the N control loops, the MOS transistor of each control loop is disconnected, and each control loop is in a closed state;

When the processing chip outputs a high-level signal to one of the N signal input terminals, the MOS transistor connected to the signal input terminal is turned on, the control loop where the turned-on MOS transistor is located is started, the output loop module supplies power to the control loop, and the comparison circuit starts to collect the output voltage of the control loop.

In this embodiment, a MOS tube is provided in the control loop to implement short-circuit detection of any one of the N control loops. When all the N control loops are polled and tested, the detection operation of the internal power supply circuit of the server is completed.

In combination with the first aspect, in some possible implementations, the charging circuit module is connected to a DC power supply;

The charging circuit module includes: MOS transistor Q100, MOS transistor Q101, transistor Q102, transistor Q103, operational amplifier U1 and multiple resistors, wherein transistor Q102 and transistor Q103 form a mirror current source;

The g-pole of the MOS transistor Q100 is connected to the detection enable signal, the d-pole of the MOS transistor Q100 is connected to the non-inverting input terminal of the operational amplifier U1, and the s-pole of the MOS transistor Q100 is connected to the ground;

The non-inverting input terminal of the operational amplifier U1 is also connected to the first resistor R1 and the second resistor R2. The inverting input terminal of the operational amplifier U1 is grounded via the third resistor R3. The output terminal of the operational amplifier U1 is connected to the g-pole of the MOS transistor Q101. The d-pole of the MOS transistor Q101 outputs current to the output circuit via the mirror current source.

In conjunction with the first aspect, in some possible implementations, the detection enable signal is controlled by the processing chip to output a high level or a low level; and the charging circuit module is specifically configured to:

When the detection enable signal outputs a high level, the MOS tube Q100 is closed and outputs a low level to the non-inverting input terminal of the operational amplifier U1, and the charging circuit module stops supplying power to the output loop module;

When the detection enable signal outputs a low level, the MOS transistor Q100 is disconnected and outputs the first voltage V1 to the non-inverting input terminal of the operational amplifier U1. The output terminal of the operational amplifier U1 outputs a high level to the MOS transistor Q101. The s-pole of the MOS transistor Q101 outputs the first current I1 on the third resistor R3. The d-pole of the MOS transistor Q101 turns on the transistors Q102 and Q103 of the mirror current source. The charging circuit module outputs the second current I2 to the output loop module through the mirror current source.

In combination with the first aspect, in some possible implementations, the first voltage V1 is determined by a first relationship, which is:

Wherein, V1 is the first voltage, _Vpower is the output voltage of the DC power supply, R1 is the first resistor, and R2 is the second resistor.

Furthermore, the first current I1 is determined by a second relational expression, which is:

Wherein, I1 is the first current I1, and R3 is the third resistor.

In combination with the first aspect, in some possible implementations, the charging circuit module further includes: a fourth resistor R4 and a fifth resistor R5, wherein the fourth resistor R4 is connected between the DC power supply and the transistor Q102, and the fifth resistor R5 is connected between the DC power supply and the transistor Q103;

The DC power supply outputs a third current I3 through the fourth resistor R4 , and the DC power supply outputs a fourth current I4 through the fifth resistor R5 .

In combination with the first aspect, in some possible implementations, if R4=R5, then I3=I4; when the s-pole of the MOS transistor Q101 outputs the first current I1 on the third resistor R3 and the mirror current source outputs the second current I2 to the output loop module, I1=I3, I2=I4, and I2=I1.

In combination with the first aspect, in some possible implementations, the comparison circuit includes an operational amplifier U2, a sixth resistor R6, and a seventh resistor R7, wherein the sixth resistor R6 and the seventh resistor R7 are voltage divider resistors;

The non-inverting input terminal of the operational amplifier U2 is connected to the voltage output terminal of any control loop of the output loop module, so as to collect the output voltage of any control loop;

The inverting input terminal of the operational amplifier U2 is grounded via a seventh resistor R7;

The output end of the operational amplifier U2 is connected to the processing chip for outputting the comparison result to the processing chip.

In combination with the first aspect, in some possible implementations, the server includes N power supply circuits, each of which is equivalent to a parallel circuit consisting of a total capacitor CL and a load resistor RL;

The capacitor CL is used to charge and store energy, and the load resistor RL is used to shunt current.

In conjunction with the first aspect, in some possible implementations, the processing chip is specifically configured to:

Controlling the input high-level signals to the 1st to Nth power supply circuits one by one, and controlling the detection enable signal to take effect, and starting the charging circuit module to supply power to the xth power supply circuit, 1≤x≤N;

Calculate the time T(x) taken for the voltage of the x-th power circuit to rise to the set detection threshold based on the current value output by the charging circuit module and the total capacitance value of the x-th power circuit;

When the time T(x) reaches the preset duration, if a high-level signal output by the comparison circuit is received, it is determined that no power short circuit fault occurs in the xth power supply circuit; if a low-level signal is received, it is determined that a short circuit fault occurs in the xth power supply circuit.

In combination with the first aspect, in some possible implementations, the comparison circuit is further used to, when the charging circuit module is started to power the xth power supply circuit, collect the output voltage corresponding to the xth power supply circuit after a delay of T2, where T2>2·T1, and T1 is the charging time for the capacitor CL of the xth power supply circuit.

In combination with the first aspect, in some possible implementations, when the charging circuit module is started to supply power to the xth power supply loop, the charging voltage of the power supply is greater than the reference voltage.

In some embodiments of the present application, the processing chip is a complex programmable logic chip CPLD.

In a second aspect, the present application further provides a power short circuit detection method, which is applied to the power short circuit detection circuit of the first aspect, and the method includes:

When the output circuit module in the power short-circuit detection circuit is connected to N power circuits inside the server, the processing chip controls the input of high-level signals to the first to Nth power circuits one by one, and controls the detection enable signal in the charging circuit module to take effect, thereby starting the charging circuit module to supply power to the xth power circuit, where 1≤x≤N;

Calculate the time required for the voltage of the xth power circuit to rise to a set detection threshold based on the current value output by the charging circuit module and the total capacitance value of the xth power circuit;

When the time reaches the preset time length, if the processing chip receives the high level signal output by the comparison circuit, it is determined that no power short circuit fault occurs in the xth power supply loop.

Furthermore, the method further includes: if the processing chip receives a low-level signal output by the comparison circuit, determining that a short circuit fault occurs in the xth power supply loop.

The method provided by this aspect is that the processing chip controls the conduction of any one of N control loops, starts short-circuit detection of the power circuit of the server connected to the control loop, and compares the output voltage collected by the comparison circuit with the reference voltage to achieve remote short-circuit detection of the power circuit. Therefore, before the server is powered on or when the server cannot be powered on, remote control and detection of whether the power circuit has a short circuit are possible. This avoids the maintenance engineer from disassembling the server on site to detect whether a fault has occurred, and also avoids damage to the server caused by restarting the server again after a short circuit.

In a third aspect, the present application provides a computer device comprising: a memory and a processor, the memory and the processor being communicatively connected to each other, computer instructions being stored in the memory, and the processor executing the power short circuit detection method of the above-mentioned second aspect or any corresponding embodiment thereof by executing the computer instructions.

In addition, the present application provides a non-volatile readable storage medium having computer instructions stored thereon, the computer instructions being used to enable a computer to execute the power short circuit detection method of the above-mentioned second aspect or any corresponding embodiment thereof.

BRIEF DESCRIPTION OF THE DRAWINGS

In order to more clearly illustrate the specific implementation methods of the present application or the technical solutions in the prior art, the following is a brief introduction to the drawings required for use in the specific implementation methods or the description of the prior art. Obviously, the drawings described below are some implementation methods of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

FIG1 is a circuit diagram of a power short circuit detection circuit provided in an embodiment of the present application;

FIG2 is a schematic diagram of a power short circuit detection circuit provided in an embodiment of the present application;

FIG3 is a circuit diagram of another power short circuit detection circuit provided in an embodiment of the present application;

FIG4 is a partial circuit diagram of an output circuit provided in an embodiment of the present application;

FIG5 is an equivalent circuit diagram of a power supply circuit provided in an embodiment of the present application;

FIG6 is a flow chart of a power short circuit detection method provided by an embodiment of the present application;

FIG7 is a flow chart of a short circuit detection method provided by an embodiment of the present application;

FIG8 is a schematic diagram of the hardware structure of a computer device provided in an embodiment of the present application.

DETAILED DESCRIPTION

To make the purpose, technical solutions, and advantages of the embodiments of the present application more clear, the technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without making creative efforts shall fall within the scope of protection of this application.

The technical solution of the present application can be applied to the field of electronic circuit technology, and mainly involves detecting whether a short circuit occurs in the internal power supply circuit of a server or other network device.

Specifically, if a server experiences an abnormal startup, there's a chance that a short circuit has occurred within the server. This can be caused by components, components, cable or component detachment, or aging of the printed circuit board (PCB). When these short circuits occur, the server may not be able to access the relevant error logs, making it impossible for maintenance engineers to remotely obtain information about the server's abnormality.

When the server fails to power on for the first time, the maintenance engineer will first check the server log to see if there is any relevant error information. If there is any relevant error information, the maintenance engineer will perform repairs according to the error information prompts.

If no relevant error message is displayed, the maintenance engineer will generally attempt to power on the server again. If the server still cannot power on normally after the second attempt, the maintenance engineer will conduct an on-site inspection to see if there is any abnormality. The inspection sequence is generally to first check the server's appearance for any abnormalities, then open the chassis and check the server for any abnormalities such as loose cables, obvious damage to components or parts, etc.

During remote testing, repowering the server can cause burns in the short-circuited area, exacerbating the damage caused by the short-circuit issue. If a maintenance engineer arrives on-site to conduct a fault inspection, they must unpack the server to gain access to the server's interior and individually check each power circuit for short circuits. This requires a high level of experience and requires analysis of each circuit individually, resulting in low detection efficiency and high costs.

Based on the above analysis, an embodiment of the present application provides a power short circuit detection circuit for remotely detecting whether a short circuit occurs inside a server, and can also specifically determine which power circuit has a short circuit, thereby improving detection efficiency and reducing labor costs.

The power short circuit detection circuit provided in this embodiment is described in detail below.

Referring to FIG1 , a power short circuit detection circuit is provided in an embodiment of the present application. The circuit includes: a processing chip, a charging circuit module, an output loop module, and a comparison circuit.

The output circuit module is connected between the charging circuit module and the comparison circuit, and is also connected to at least one signal output terminal of the processing chip. Each signal output terminal is connected to a signal input terminal of the output circuit module.

The output loop module includes N control loops, each control loop includes a signal input terminal, a switch tube and a connection terminal, wherein each signal input terminal is connected to a signal output terminal of the processing chip, and is used to receive a control signal output from the processing chip. Each connection terminal is used to connect to a power supply circuit inside the server. The switch tube is arranged between the signal input terminal and the connection terminal, and is used to control the conduction or disconnection of the control loop in which it is located. N ≥ 1 and is a positive integer.

The processing chip is used to start any one of the N control loops as the target control loop for power short circuit detection, and to control other control loops except the target control loop to be in a closed state. After the target control loop is started, power is supplied through the charging circuit module.

The comparison circuit is used to receive the output voltage of the target control loop, compare it with the reference voltage, and output a high level or low level comparison result to the processing chip.

Specifically, the comparison circuit is used to output a high-level signal to the processing chip when the comparison output voltage is greater than or equal to the reference voltage; and output a low-level signal to the processing chip when the comparison output voltage is less than the reference voltage.

The processing chip is used to receive the comparison result output from the comparison circuit and determine whether a power short circuit fault occurs in the target control loop according to the comparison result.

Furthermore, the processing chip is specifically used to determine that a power short circuit fault does not occur in the target control loop when receiving a high-level signal output by the comparison circuit; and to determine that a power short circuit fault occurs in the target control loop when receiving a low-level signal output by the comparison circuit.

In some embodiments of the present application, the processing chip is a complex programmable logic device (CPLD).

In this embodiment, CPLD control is adopted to design a charging circuit module, an output loop module, and a comparison circuit. The CPLD controls the output loop module to select any output loop and controls the charging circuit module to charge the selected output loop. The comparison module detects the relevant voltage and compares the result, such as outputting a high-level or low-level signal to the CPLD. Finally, the CPLD determines whether a short circuit fault occurs based on the comparison result, and the CPLD records the abnormality log and reports it to the system.

Furthermore, as shown in Figure 2, the functions and effects of each module are as follows:

Processing chip, such as CPLD: It is responsible for controlling the operation of the charging circuit module and controlling the output circuit module to select a specified circuit. Other unselected circuits remain in a closed state. At the same time, the comparison result of the comparison circuit is recorded. The comparison result is used to determine whether a short circuit fault occurs in the power circuit where the current specified circuit is located.

Charging circuit module: designed as a controllable current source, connected to the processing chip. When the processing chip control enable signal is valid, the charging circuit module starts working to charge the output loop module with a small current. At this time, the charging circuit module is equivalent to a constant current source.

Output circuit module: All power circuits that need to be tested inside the server or on the board are connected through output circuits 1 to n. Each circuit can be controlled by a MOS switch (an electronic switch). The CPLD can control that only one output power circuit is connected to the main circuit of the detection circuit at the same time, and the other output power circuits are in the off state.

The comparator circuit, also known as the short-circuit comparator circuit, collects the output voltage of the output circuit and compares it with a reference voltage. When the detected output voltage is higher than the reference voltage, it outputs a high-level signal to the CPLD, indicating that the circuit is normal and there is no short circuit. When a low-level signal is output to the CPLD, it indicates that a short circuit has occurred. The detection voltage remains low and cannot rise above the reference voltage. The short-circuit detection result remains low, indicating that a short circuit has occurred in the current power circuit and is fed back to the CPLD for recording.

The processing chip also records information. When a high-level or low-level signal from a comparison circuit indicates a short circuit in a power circuit connected to an output circuit, the processing chip records the x-value of the current detection circuit and generates a short-circuit log. This log is then reported to the system for easy review by maintenance engineers. If a server fails to boot, maintenance engineers can remotely control the processing chip and send instructions to execute the relevant short-circuit detection process, thereby detecting faults in all power circuits within the server.

In one possible implementation, as shown in Figures 3 and 4 , in the detection circuit, the output circuit module includes 1 to N control circuits, corresponding to 1 to n power circuits. Specifically, the switch transistor in each control circuit is a MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor). For example, N control circuits include N MOSFETs, namely Q1, Q2, ..., Qn. These MOSFETs are all N-channel MOSFETs.

Furthermore, the g-pole (gate) of each MOS tube is connected to the signal input end for receiving the control signal output from the processing chip, the d-pole (drain) of each MOS tube is connected to the power output end of the charging circuit module, and the s-pole (source) of each MOS tube is connected to the connection end.

As shown in Figure 4, the g-pole of MOS transistor Q1 is connected to control signal 1, the d-pole is connected to node 106 corresponding to the power output, and the s-pole is connected to loop 1. The pin of loop 1 serves as the connection point for the first control loop, used to connect to power loop 1 within the server. The first control loop consists of "control signal input terminal 1 - MOS transistor Q1 - connection terminal (loop 1)." Similarly, "control signal input terminal 2 - MOS transistor Q2 - connection terminal (loop 2)" forms the second control loop, and finally "control signal input terminal n - MOS transistor Qn - connection terminal (loop n)" forms the Nth control loop.

When the processing chip inputs low-level signals to the N signal input terminals of the N control loops, the MOS transistor of each control loop is disconnected, and each control loop is in a closed state;

When the processing chip outputs a high-level signal to one of the N signal input terminals, the MOS transistor connected to the signal input terminal is turned on, the control loop where the turned-on MOS transistor is located is started, the output loop module supplies power to the control loop, and the comparison circuit starts to collect the output voltage of the control loop.

Specifically, during the design of the detection circuit provided in this embodiment, N power circuits to be detected are selected on the motherboard. Each power circuit is connected to the detection circuit via a MOS transistor in series. For example, MOS transistor Q1 is connected to node 106 in power circuit 1. The g-pole of the MOS transistor is controlled by "control signal 1" output by the CPLD. When the CPLD outputs a high level to control signal 1, MOS transistor Q1 turns on, connecting circuit 1 to node 106, and MOS transistor Q1 acts as a switch. The second, third, ..., nth circuits are connected to the detection circuit node 106 in the same manner. The CPLD outputs only a high-level signal to one of control signals 1-n at a time according to the set sequence, while the other control signals are pulled low to ensure low output levels. This ensures that only one of MOS transistors Q1, Q2, ..., Qn is turned on at a time, while the other MOS transistors are turned off.

In the on state, the MOS tube is turned on, the control loop where the MOS tube is located is connected to the detection loop, and the comparison circuit collects and compares the output voltage on the control loop.

In this embodiment, an output circuit module is provided, including N control circuits. The CPLD processes the control signal of each circuit to select a power circuit inside the server for short circuit detection. The MOS tubes connected in series are connected to the main circuit, so that the CPLD can connect a certain circuit to the detection main circuit according to the rules, thereby realizing remote detection of the power circuit inside the server.

In some embodiments, the charging circuit module is further connected to a DC power supply.

As shown in FIG3 , the charging circuit module includes: MOS transistor Q100 , MOS transistor Q101 , transistor Q102 , transistor Q103 , operational amplifier U1 , and multiple resistors, wherein transistor Q102 and transistor Q103 form a mirror current source.

The g-pole of the MOS transistor Q100 is connected to the detection enable signal, the d-pole of the MOS transistor Q100 is connected to the non-inverting input of the operational amplifier U1, and the s-pole of the MOS transistor Q100 is grounded. The non-inverting input of the operational amplifier U1 is also connected to the first resistor R1 and the second resistor R2. The inverting input of the operational amplifier U1 is grounded via the third resistor R3. The output of the operational amplifier U1 is connected to the g-pole of the MOS transistor Q101. The d-pole of the MOS transistor Q101 outputs current to the output circuit via a mirror current source.

Furthermore, the detection enable signal is controlled by the processing chip to output a high level or a low level; the charging circuit module is specifically used to close the MOS tube Q100 when the detection enable signal outputs a high level, output a low level to the non-inverting input terminal of the operational amplifier U1, and the charging circuit module stops supplying power to the output loop module.

When the detection enable signal outputs a low level, the MOS transistor Q100 is disconnected and outputs the first voltage V1 to the non-inverting input terminal of the operational amplifier U1. The output terminal of the operational amplifier U1 outputs a high level to the MOS transistor Q101. The s-pole of the MOS transistor Q101 outputs the first current I1 on the third resistor R3. The d-pole of the MOS transistor Q101 turns on the transistors Q102 and Q103 of the mirror current source. The charging circuit module outputs the second current I2 to the output loop module through the mirror current source.

Specifically, as shown in Figure 3, node 200 is the input power supply for the mainboard, typically a 12V DC power supply. Node 101 is the input control terminal for the modular component. When Detect Enable_N is low, the module activates. The Detect Enable output high/low level is controlled by the CPLD. When node 101 is high, Q100 turns on, and node 102 is pulled low, disabling power to the charging circuit module.

When the detection enable_N is low, that is, the node 101 is low, Q100 is turned off, and the voltage of the node 102 is obtained by the voltage division of R1 and R2. The node voltage _V102 (i.e., the first voltage V1) can be calculated by the relationship (1). The first relationship is:

Wherein, V1 is the first voltage, _Vpower is the output voltage of the DC power supply, R1 is the first resistor, and R2 is the second resistor.

At this time, the resistance of node 103 to ground is R3, and the constant current output of the charging circuit module is a first current I1. The first current I1 is determined by the voltage of node 102 and the resistance value of R3. Furthermore, the first current I1 is determined by a second relationship, which is:

Wherein, I1 is the first current I1, and R3 is the third resistor.

In this embodiment, the values of R1, R3 and R4 can be adjusted according to the requirements of the load resistance to determine the magnitude of the first current I1. Setting the first current I1 can affect subsequent detection parameters such as the detection current and detection time.

The charging circuit module further includes a fourth resistor R4 and a fifth resistor R5, wherein the fourth resistor R4 is connected between the DC power supply and the transistor Q102, and the fifth resistor R5 is connected between the DC power supply and the transistor Q103. The DC power supply outputs a third current I3 through the fourth resistor R4, and the DC power supply outputs a fourth current I4 through the fifth resistor R5.

If R4=R5, then I3=I4; when the S-pole of the MOS tube Q101 outputs the first current I1 on the third resistor R3 and the mirror current source outputs the second current I2 to the output loop module, I1=I3, I2=I4, and I2=I1.

Specifically, when the charging circuit module is operating, node 104, i.e., the output terminal of operational amplifier U1, outputs a high level. MOS transistor Q101 operates in the variable resistance range, and Q102 and Q103 are turned on. Q102 and Q103 form a mirrored current source. The resistance values of R4 and R5 are generally set. When R4 = R5, currents I3 and I4 are equal, and I3 = I1. Since the current I2 at node 106 is equal to I4, the final current outputted to node 106 is also I2. At this point, the second current I2 is equal to the first current I1.

In this embodiment, a constant current output charging circuit module is added, which can control the switch through a signal, and uses key components such as an operational amplifier U1, a MOS tube and two transistors to achieve constant current output. The output current size can be set as needed.

In some other embodiments, the comparison circuit includes an operational amplifier U2, a sixth resistor R6, and a seventh resistor R7, wherein the sixth resistor R6 and the seventh resistor R7 are voltage divider resistors.

The non-inverting input of operational amplifier U2 is connected to the voltage output of any control loop of the output loop module, for collecting the output voltage of any control loop. The inverting input of operational amplifier U2 is grounded via a seventh resistor R7. The output of U2 is connected to the processing chip, for outputting the comparison result to the processing chip.

Specifically, as shown in FIG3 , node 107 is a reference voltage Vref obtained by dividing the voltage of node 200 by the sixth resistor R6 and the seventh resistor R7. When the voltage of node 106 is higher than the voltage of node 107, that is, an output voltage of the control loop is greater than or equal to the reference voltage Vref, the node 108 output by the operational amplifier U2 is a high level, indicating that there is no short circuit in the connected loop at this time. Node 108 is monitored by the CPLD, and the high-level signal output by node 108 is transmitted to the CPLD.

When the voltage at the node 106 is always lower than the voltage at the node 107 , that is, the output voltage is lower than the reference voltage Vref, it indicates that a short circuit has occurred in the loop.

When one of the control signals is pulled high and node 101 outputs a low level, a delay is required to determine whether the level of node 108 is high or low. The delay T needs to take into account the charging current I, the total output capacitance C of the loop, and the reference voltage Vref set at node 107. According to equation (3), the calculated time T is greater than the CPLD delay time T, and then short-circuit detection is performed.

Relationship (3) is:

Its equivalent circuit is shown in Figure 5. The server includes N power circuits inside. Each power circuit is equivalent to a parallel circuit consisting of a total capacitor CL and a load resistor RL. The capacitor CL is used for charging and energy storage, and the load resistor RL is used for current diversion.

Furthermore, the equivalent load capacitance of loop 1 is CL1. When loop 1 is connected to node 106 of the detection circuit, the charging circuit module outputs a second current I2 to charge capacitor CL1. Charging time T1 = CL1·Vreference/I2. Since resistor RL1 acts as a shunt, the delayed reading time is more than twice T1, ensuring that T>2·T1. Furthermore, when setting T, the conditions of all loops are taken into consideration, ensuring that T is greater than twice the maximum value among T1, T2, ..., Tn.

In addition, when setting the reference voltage Vref, the condition of RL needs to be considered. Taking loop 1 in FIG5 as an example, after the second current I2 fully charges loop 1, the final charging voltage V at node 106 can be calculated by the following formula: V1 = I2·RL1.

The reference voltage Vref must be set to be less than V1, that is, Vref<V1, in order to effectively complete the detection. Therefore, when setting the reference voltage Vref in this embodiment, the different RL values of all n power supply circuits (V1, V2...Vn) must be considered, and Vref must be less than all voltage values.

In this embodiment, a short-circuit comparison circuit is provided to compare the delayed loop output voltage with a set reference voltage Vref to detect whether a short circuit occurs in the currently connected loop.

Optionally, in other embodiments, the processing chip is specifically used to control the input of high-level signals to the 1st to Nth power supply circuits one by one, and to control the detection enable signal to take effect, and to start the charging circuit module to supply power to the xth power supply circuit, where 1≤x≤N and N is a positive integer.

Based on the current value output by the charging circuit module and the total capacitance value of the x-th power supply circuit, the time T(x) taken for the voltage of the x-th power supply circuit to climb to the set detection threshold is calculated. When the time T(x) reaches the preset duration, if a high-level signal is received from the comparison circuit, it is determined that no power short circuit fault has occurred in the x-th power supply circuit; if a low-level signal is received from the comparison circuit, it is determined that a short circuit fault has occurred in the x-th power supply circuit.

Furthermore, the comparison circuit is further configured to collect the output voltage corresponding to the xth power circuit after a delay of T2 when the charging circuit module is started to supply power to the xth power circuit, where T2>2·T1, and T1 is the charging time for the capacitor CL of the xth power circuit.

The detection circuit provided in the above embodiment includes a controllable charging circuit module, which can output a controllable charging current according to the total capacitance of the server loop capacitor to power the power supply circuit in the subsequent output loop module.

In addition, N MOS tubes are connected in series with N control loops. Each control loop contains a MOS tube, which is used to control any specified loop to access the short-circuit detection circuit and perform short-circuit detection in sequence, so as to traverse and detect all power circuits on the server and conduct a comprehensive detection to see if a short-circuit fault occurs inside the server.

In the detection circuit of this embodiment, a comparator circuit compares the delayed detection circuit output voltage with a set reference voltage Vref to detect whether a short circuit has occurred in the currently connected circuit. This enables remote short-circuit detection of the power circuit, improves detection efficiency, and saves labor costs.

In addition, before the server is powered on or when the server cannot be powered on, a remote command is sent to start internal short-circuit detection to detect possible power short-circuit problems, avoiding maintenance engineers from disassembling the server on site and avoiding damage caused by trying to power it on again.

It should be noted that this technical solution can also be used in other systems that require remote short circuit detection, or to perform health checks on circuits to be detected before powering on each power supply system.

This embodiment further provides a power short circuit detection method, which can be used in the power short circuit detection circuit of the above embodiment. FIG6 is a flow chart of a power short circuit detection method according to an embodiment of the present application. As shown in FIG6 , the method includes:

Step S101: When the output circuit module in the power short circuit detection circuit is connected to N power circuits inside the server, the processing chip controls the input high-level signals to the 1st to Nth power circuits one by one, and controls the detection enable signal in the charging circuit module to take effect, and starts the charging circuit module to supply power to the xth power circuit, 1≤x≤N, where N is a positive integer.

Step S102: Calculating the time taken for the voltage of the xth power circuit to rise to a set detection threshold based on the current value output by the charging circuit module and the total capacitance value of the xth power circuit;

Step S103: When the time reaches the preset duration, the processing chip determines whether it receives the high level signal output by the comparison circuit.

Step S104: If yes, that is, the processing chip receives the high-level signal output by the comparison circuit, it is determined that no power short circuit fault occurs in the xth power supply loop.

Step S105: If not, that is, the processing chip receives the low-level signal output by the comparison circuit, it is determined that a short circuit fault occurs in the xth power supply loop.

In a specific embodiment, as shown in FIG7 , the above method specifically includes:

Step 1: After the detection starts, the CPLD sets the control signal x to 0.

Step 2: CPLD polling enables control signal x=x+1. Therefore, the initial value of x is 1, so x starts from 1, indicating that detection starts from the first power supply circuit, corresponding to circuit 1 of control signal 1.

Step 3: CPLD pulls up the control signal x and outputs a high-level signal. At this time, the x power supply circuit is connected to the inspection main circuit.

Step 4: The CPLD controls the detection enable signal in the charging circuit module to take effect. At this time, the charging circuit module starts to charge the xth power supply circuit connected to the inspection circuit and outputs the second current I2.

Step 5: Based on the current value I2 output by the charging circuit module and the total capacitance value CL of the x-th loop, calculate the time T(x) required for the loop voltage to climb to the set detection threshold Vth. After the timing reaches time T(x), the comparison circuit outputs a high-level or low-level signal.

If the comparison circuit outputs a high level to the CPLD, it indicates that no short circuit occurs; if the comparison circuit output still maintains a low level to the CPLD, it is determined that a short circuit fault occurs in the current x loop.

Step 6: The CPLD compares the value of x to see if it is equal to n, where n is the total number of power loops.

If x<n, it means that the polling traversal is not completed. At this time, return to "Step 2" and execute x=x+1 to perform short-circuit detection on the 2nd, 3rd, ... power supply circuits, and continue to cycle the above method flow from Step 3 to Step 5.

If x = n, then all n circuits have been inspected. The inspection and testing are complete. The inspection results are recorded, and a log is generated and reported for review by maintenance engineers.

The method provided by this aspect is that the processing chip controls the conduction of any one of N control loops, starts short-circuit detection of the power circuit of the server connected to the control loop, and compares the output voltage collected by the comparison circuit with the reference voltage to achieve remote short-circuit detection of the power circuit. Therefore, before the server is powered on or when the server cannot be powered on, remote control and detection of whether the power circuit has a short circuit are possible. This avoids the maintenance engineer from disassembling the server on site to detect whether a fault has occurred, and also avoids damage to the server caused by restarting the server again after a short circuit.

The further functional description of the above method steps is the same as that of the embodiment of the above circuit structure, and can be found in the embodiments shown in Figures 1 to 5 above, which will not be repeated here.

An embodiment of the present application further provides a computer device having the detection circuit shown in FIG. 1 to FIG. 5 .

Please refer to Figure 8, which is a structural diagram of a computer device provided by an optional embodiment of the present application. As shown in Figure 8, the computer device includes: one or more processors 10, a memory 20, and interfaces for connecting various components, including high-speed interfaces and low-speed interfaces. The various components are connected to each other using different buses and can be installed on a common motherboard or installed in other ways as needed. The processor can process instructions executed within the computer device, including instructions stored in or on the memory to display graphical information of the GUI on an external input/output device (such as a display device coupled to the interface). In some optional embodiments, if necessary, multiple processors and/or multiple buses can be used together with multiple memories and multiple memories. Similarly, multiple computer devices can be connected, and each device provides some necessary operations (for example, as a server array, a group of blade servers, or a multi-processor system). Figure 8 takes a processor 10 as an example.

The processor 10 may be a central processing unit, a network processor, or a combination thereof. The processor 10 may further include a hardware chip. The hardware chip may be an application-specific integrated circuit, a programmable logic device, or a combination thereof. The programmable logic device may be a complex programmable logic device, a field programmable gate array, a general purpose array logic, or any combination thereof.

The memory 20 stores instructions that can be executed by at least one processor 10, so as to enable at least one processor 10 to implement the power short circuit detection method shown in the above embodiment.

The memory 20 may include a program storage area and a data storage area, wherein the program storage area may store an operating system, an application required for at least one function; the data storage area may store data created based on the use of a computer device for displaying a small program landing page, etc. In addition, the memory 20 may include a high-speed random access memory, and may also include a non-transient memory, such as at least one disk storage device, a flash memory device, or other non-transient solid-state storage device. In some optional embodiments, the memory 20 may optionally include a memory remotely located relative to the processor 10, and these remote memories may be connected to the computer device via a network. Examples of the above-mentioned network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and a combination thereof.

The memory 20 may include a volatile memory, such as a random access memory; the memory may also include a non-volatile memory, such as a flash memory, a hard disk or a solid-state drive; the memory 20 may also include a combination of the above types of memory.

The computer device further includes an input device 30 and an output device 40. The processor 10, the memory 20, the input device 30 and the output device 40 may be connected via a bus or other means, and FIG8 takes the bus connection as an example.

The input device 30 can receive input digital or character information and generate key signal input related to user settings and function control of the computer device, such as a touch screen, a keypad, a mouse, a trackpad, a touch pad, an indicator stick, one or more mouse buttons, a trackball, a joystick, etc. The output device 40 can include a display device, an auxiliary lighting device (e.g., an LED), and a tactile feedback device (e.g., a vibration motor). The above-mentioned display device includes but is not limited to a liquid crystal display, a light emitting diode, a display, and a plasma display. In some optional embodiments, the display device can be a touch screen.

The computer device further includes a communication interface for the computer device to communicate with other devices or a communication network.

The embodiment of the present application also provides a non-volatile readable storage medium. The above-mentioned method according to the embodiment of the present application can be implemented in hardware, firmware, or implemented as a computer code that can be recorded in a storage medium, or implemented as a computer code that is originally stored in a remote storage medium or a non-temporary machine-readable storage medium and downloaded through a network and will be stored in a local storage medium, so that the method described herein can be stored in such software processing on a storage medium using a general-purpose computer, a dedicated processor, or programmable or dedicated hardware. Among them, the storage medium can be a magnetic disk, an optical disk, a read-only storage memory, a random access memory, a flash memory, a hard disk or a solid-state drive, etc.; further, the storage medium can also include a combination of the above-mentioned types of memory. It can be understood that the computer, processor, microprocessor controller or programmable hardware includes a storage component that can store or receive software or computer code. When the software or computer code is accessed and executed by the computer, processor or hardware, the power short circuit detection method shown in the above embodiment is implemented.

Although the embodiments of the present application have been described with reference to the accompanying drawings, those skilled in the art may make various modifications and variations without departing from the spirit and scope of the present application, and such modifications and variations shall fall within the scope defined by the appended claims.

Claims (20)

A power short circuit detection circuit, characterized in that the circuit comprises: a processing chip, a charging circuit module, an output loop module and a comparison circuit, wherein: The output circuit module is connected between the charging circuit module and the comparison circuit, and the output circuit module is also connected to at least one signal output terminal of the processing chip; The output circuit module includes N control circuits, each of which includes a signal input terminal, a switch tube, and a connection terminal. Each of the signal input terminals is connected to a signal output terminal of the processing chip and is configured to receive a control signal output from the processing chip. Each of the connection terminals is configured to connect to a power supply circuit inside the server. The switch tube is arranged between the signal input terminal and the connection terminal and is configured to control the control circuit in which it is located to be turned on or off. N is ≥ 1 and is a positive integer. The processing chip is configured to activate any one of the N control loops as a target control loop for power short circuit detection, and to control other control loops except the target control loop to be in a closed state, wherein the target control loop is powered by the charging circuit module after activation; The comparison circuit is configured to receive the output voltage of the target control loop, compare it with a reference voltage, and output a high level or low level comparison result to the processing chip; The processing chip is configured to receive a comparison result output from the comparison circuit, and determine whether a power short circuit fault occurs in the target control loop according to the comparison result. The circuit according to claim 1, wherein the comparison circuit is specifically configured to: When the output voltage is greater than or equal to the reference voltage, a high level signal is output to the processing chip; When the output voltage is smaller than the reference voltage, a low level signal is output to the processing chip. The circuit according to claim 2, wherein the processing chip is specifically configured to: When receiving the high level signal output by the comparison circuit, determining that no power short circuit fault occurs in the target control loop; When a low level signal output by the comparison circuit is received, it is determined that a power short circuit fault occurs in the target control loop. The circuit according to claim 1, wherein the switch tube of each control loop is a MOS tube, the g-pole of the MOS tube is connected to the signal input terminal, the d-pole of the MOS tube is connected to the power output terminal of the charging circuit module, and the s-pole of the MOS tube is connected to the connection terminal; When the processing chip inputs low-level signals to the N signal input terminals of the N control loops, the MOS transistor of each control loop is disconnected, and each control loop is in a closed state; When the processing chip outputs a high-level signal to one of the N signal input terminals, the MOS transistor connected to the signal input terminal is turned on, the control loop where the turned-on MOS transistor is located is started, the output loop module supplies power to the control loop, and the comparison circuit starts to collect the output voltage of the control loop. The circuit according to claim 4, wherein the charging circuit module is connected to a DC power supply; The charging circuit module includes: MOS transistor Q100, MOS transistor Q101, transistor Q102, transistor Q103, operational amplifier U1 and multiple resistors, wherein the transistor Q102 and the transistor Q103 form a mirror current source; The g-pole of the MOS transistor Q100 is connected to the detection enable signal, the d-pole of the MOS transistor Q100 is connected to the non-inverting input terminal of the operational amplifier U1, and the s-pole of the MOS transistor Q100 is connected to the ground; The non-inverting input terminal of the operational amplifier U1 is further connected to the first resistor R1 and the second resistor R2. The inverting input terminal of the operational amplifier U1 is grounded via the third resistor R3. The output terminal of the operational amplifier U1 is connected to the g-pole of the MOS transistor Q101. The d-pole of the MOS transistor Q101 outputs current to the output loop via the mirror current source. The circuit according to claim 5, wherein the detection enable signal is controlled by the processing chip to output a high level or a low level; and the charging circuit module is specifically configured as follows: When the detection enable signal outputs a high level, the MOS transistor Q100 is closed, outputting a low level to the non-inverting input terminal of the operational amplifier U1, and the charging circuit module stops supplying power to the output loop module; When the detection enable signal outputs a low level, the MOS transistor Q100 is disconnected and outputs the first voltage V1 to the non-inverting input terminal of the operational amplifier U1. The output terminal of the operational amplifier U1 outputs a high level to the MOS transistor Q101. The s-pole of the MOS transistor Q101 outputs the first current I1 on the third resistor R3. The d-pole of the MOS transistor Q101 turns on the transistors Q102 and Q103 of the mirror current source. The charging circuit module outputs the second current I2 to the output loop module through the mirror current source. The circuit according to claim 6, wherein the first voltage V1 is determined by a first relationship, wherein the first relationship is:
Wherein, V1 is the first voltage, _Vpower is the output voltage of the DC power supply, R1 is the first resistor, and R2 is the second resistor. The circuit according to claim 7, wherein the first current I1 is determined by a second relationship, wherein the second relationship is:
Wherein, I1 is the first current, and R3 is the third resistor. The circuit according to claim 8, characterized in that the charging circuit module further comprises: a fourth resistor R4 and a fifth resistor R5, wherein the fourth resistor R4 is connected between the DC power supply and the transistor Q102, and the fifth resistor R5 is connected between the DC power supply and the transistor Q103; The DC power supply outputs a third current I3 through the fourth resistor R4 , and the DC power supply outputs a fourth current I4 through the fifth resistor R5 . The circuit according to claim 9, wherein if R4=R5, then I3=I4; When the S-pole of the MOS transistor Q101 outputs the first current I1 on the third resistor R3 and the mirror current source outputs the second current I2 to the output loop module, I1 = I3, I2 = I4, and I2 = I1. The circuit according to any one of claims 1 to 10, characterized in that the comparison circuit comprises an operational amplifier U2, a sixth resistor R6, and a seventh resistor R7, wherein the sixth resistor R6 and the seventh resistor R7 are voltage divider resistors, The non-inverting input terminal of the operational amplifier U2 is connected to the voltage output terminal of any control loop of the output loop module, and is configured to collect the output voltage of any control loop; The inverting input terminal of the operational amplifier U2 is grounded through the seventh resistor R7; The output end of the operational amplifier U2 is connected to the processing chip and is configured to output a comparison result to the processing chip. The circuit according to claim 5, wherein the server comprises N power supply circuits, each of which is equivalent to a parallel circuit consisting of a total capacitor CL and a load resistor RL; The capacitor CL is configured to charge and store energy, and the load resistor RL is configured to shunt current. The circuit according to claim 12, wherein the processing chip is specifically configured to: Controlling the input of high-level signals to the first to Nth power supply circuits one by one, and controlling the detection enable signal to take effect, and starting the charging circuit module to supply power to the xth power supply circuit, 1≤x≤N; Calculate the time T(x) taken for the voltage of the xth power supply circuit to climb to a set detection threshold based on the current value output by the charging circuit module and the total capacitance value of the xth power supply circuit; When the time T(x) reaches the preset duration, if a high-level signal is received from the comparison circuit, it is determined that no power short circuit fault occurs in the x-th power supply circuit; if a low-level signal is received, it is determined that a short circuit fault occurs in the x-th power supply circuit. The circuit according to claim 13 is characterized in that the comparison circuit is further configured to, when the charging circuit module is started to power the xth power circuit, collect the output voltage corresponding to the xth power circuit after a delay of T2, wherein T2>2·T1, and T1 is the charging time of the capacitor CL of the xth power circuit. The circuit according to claim 14, wherein when the charging circuit module is started to supply power to the xth power supply circuit, the charging voltage of the power supply is greater than the reference voltage. The circuit according to any one of claims 1 to 10, characterized in that the processing chip is a complex programmable logic chip CPLD. A power short circuit detection method, characterized in that the method is applied to the power short circuit detection circuit according to any one of claims 1 to 16, and the method comprises: When the output circuit module in the power short circuit detection circuit is connected to N power circuits inside the server, the processing chip controls the input of high-level signals to the first to Nth power circuits one by one, and controls the detection enable signal in the charging circuit module to take effect, thereby starting the charging circuit module to supply power to the xth power circuit, where 1≤x≤N, and N is a positive integer; Calculating the time required for the voltage of the xth power supply circuit to climb to a set detection threshold based on the current value output by the charging circuit module and the total capacitance value of the xth power supply circuit; When the time reaches the preset time length, if the processing chip receives a high level signal output by the comparison circuit, it is determined that no power short circuit fault occurs in the xth power supply loop. The method according to claim 17, further comprising: If the processing chip receives the low level signal output by the comparison circuit, it is determined that a short circuit fault occurs in the xth power supply loop. The method according to claim 17, wherein when the output circuit module in the power short circuit detection circuit is connected to N power circuits inside the server, the processing chip controls the first to Nth power circuits one by one to input high-level signals, comprising: After the detection starts, the processing chip sets the control signal x to 0; The processing chip polls and enables the control signal x=x+1, and starts detecting from the first power supply circuit; The processing chip pulls up the control signal and outputs a high-level signal; The xth power supply circuit is connected to the inspection main circuit. The method according to claim 19, further comprising: The processing chip compares whether the value of x is equal to N, where N is the total number of power circuits; If the value of x is equal to N, the power short circuit detection result is statistically recorded; Generate a detection log based on the power short circuit detection result and report it.