WO2025201010A1

WO2025201010A1 - Methods for enhanced synchronization block design in wireless communications

Info

Publication number: WO2025201010A1
Application number: PCT/CN2025/081533
Authority: WO
Inventors: Chenmeng LI; Wen Tang; Tao Chen
Original assignee: MediaTek Singapore Pte Ltd
Current assignee: MediaTek Singapore Pte Ltd
Priority date: 2024-03-25
Filing date: 2025-03-10
Publication date: 2025-10-02
Anticipated expiration: 2026-09-25
Also published as: WO2025199680A1

Abstract

Various solutions for enhanced synchronization block design in wireless communications are described. An apparatus may receive a synchronization block (SyncBlock) from a network node. The SyncBlock may include one or a plurality of at least one of a primary synchronization signal (PSS), a secondary synchronization signal (SSS), and a physical broadcast channel (PBCH). The apparatus may accumulate the one or the plurality of the at least one of the PSS, the SSS, and the PBCH within the SyncBlock. Then, the apparatus may perform a synchronization with the network node based on the accumulation.

Description

METHODS FOR ENHANCED SYNCHRONIZATION BLOCK DESIGN IN WIRELESS COMMUNICATIONS

CROSS REFERENCE TO RELATED PATENT APPLICATION (S)

The present disclosure is part of a non-provisional application claiming the priority benefit of PCT Application No. PCT/CN2024/083571, filed 25 March 2024, the content of which herein being incorporated by reference in its entirety.

TECHNICAL FIELD

The present disclosure is generally related to wireless communications and, more particularly, to enhanced synchronization block design in wireless communications.

BACKGROUND

Unless otherwise indicated herein, approaches described in this section are not prior art to the claims listed below and are not admitted as prior art by inclusion in this section.

The wireless communications technologies have grown exponentially over the years. A long-term evolution (LTE) system offers high peak data rates, low latency, improved system capacity, and low operating cost resulting from simplified network architecture. LTE system, also known as the 4^th generation (4G) system, also provides seamless integration to older wireless network, such as GSM, CDMA and universal mobile telecommunication system (UMTS) . In LTE system, an evolved universal terrestrial radio access network (E-UTRAN) includes a plurality of evolved Node-Bs (eNodeBs or eNBs) communicating with a plurality of mobile stations, referred to as user equipments (UEs) . The 3^rd generation partner project (3GPP) network normally includes a hybrid of 2G/3G/4G systems. The next generation mobile network (NGMN) board, has decided to focus the future NGMN activities on defining the end-to-end requirements for 5^th generation (5G) new radio (NR) systems and 6G systems.

In wireless communication, low signal-to-noise (SNR) ratio received at the receiver (e.g., UE) often occurs due to poor background environment or long-distance communications. For example, in non-terrestrial network (NTN) system, the distance between the UE and the satellite is quite long and the radio condition of the communications therebetween may vary rapidly due to satellite and UE movements. Consequently, low SNR ratio will lead to low success rates in signal detection, demodulation, and/or decoding at the receiver.

Therefore, there is a need to provide proper schemes to address this issue.

SUMMARY

The following summary is illustrative only and is not intended to be limiting in any way. That is, the following summary is provided to introduce concepts, highlights, benefits and advantages of the novel and non-obvious techniques described herein. Select implementations are further described below in the detailed description. Thus, the following summary is not intended to identify essential features of the claimed subject matter, nor is it intended for use in determining the scope of the claimed subject matter.

One objective of the present disclosure is proposing schemes, concepts, designs, systems, methods and apparatus pertaining to enhanced synchronization block design in wireless communications. It is believed that the above-described issue would be avoided or otherwise alleviated by implementing one or more of the proposed schemes described herein.

In one aspect, a method may involve an apparatus receiving a synchronization block (SyncBlock) from a network node, wherein the SyncBlock comprises one or a plurality of at least one of a primary synchronization signal (PSS) , a secondary synchronization signal (SSS) , and a physical broadcast channel (PBCH) . The method may also involve the apparatus accumulating the one or the plurality of the at least one of the PSS, the SSS, and the PBCH within the SyncBlock. The method may further involve the apparatus performing a synchronization with the network node based on the accumulation.

In one aspect, a method may involve a network node generating a SyncBlock comprising one or a plurality of at least one of a PSS, an SSS, and a PBCH. The method may also involve the network node transmitting the SyncBlock to an apparatus.

It is noteworthy that, although description provided herein may be in the context of certain radio access technologies, networks and network topologies such as Long-Term Evolution (LTE) , LTE-Advanced, LTE-Advanced Pro, 5th Generation (5G) , New Radio (NR) , Internet-of-Things (IoT) and Narrow Band Internet of Things (NB-IoT) , Industrial Internet of Things (IIoT) , beyond 5G (B5G) , and 6th Generation (6G) , the proposed concepts, schemes and any variation (s) /derivative (s) thereof may be implemented in, for and by other types of radio access technologies, networks and network topologies. Thus, the scope of the present disclosure is not limited to the examples described herein.

BRIEF DESCRIPTION OF THE DRAWINGS

The accompanying drawings are included to provide a further understanding of the disclosure and are incorporated in and constitute a part of the present disclosure. The drawings illustrate implementations of the disclosure and, together with the description, serve to explain the principles of the disclosure. It is appreciable that the drawings are not necessarily in scale as some components may be shown to be out of proportion than the size in actual implementation in order to clearly illustrate the concept of the present disclosure.

FIG. 1 is a diagram depicting an example scenario of the time-frequency structure of a synchronization signal block (SSB) in 5G NR.

FIG. 2 is a diagram depicting an example scenario of a communication environment in which various solutions and schemes in accordance with the present disclosure may be implemented.

FIG. 3 is a diagram depicting an example scenario of SyncBlock burst pattern in time domain in accordance with an implementation of the present disclosure.

FIG. 4 is a diagram depicting an example scenario of PSS/SSS/PBCH shot pattern within a SyncBlock in accordance with an implementation of the present disclosure.

FIG. 5 is a diagram depicting another example scenario of PSS/SSS/PBCH shot pattern within a SyncBlock in accordance with an implementation of the present disclosure.

FIG. 6 is a diagram depicting an example scenario of PSS shot pattern design for detection performance enhancement in accordance with an implementation of the present disclosure.

FIG. 7 is a block diagram of an example communication system in accordance with an implementation of the present disclosure.

FIG. 8 is a flowchart of an example process in accordance with an implementation of the present disclosure.

FIG. 9 is a flowchart of another example process in accordance with an implementation of the present disclosure.
DETAILED DESCRIPTION OF PREFERRED IMPLEMENTATIONS

Detailed embodiments and implementations of the claimed subject matters are disclosed herein. However, it shall be understood that the disclosed embodiments and implementations are merely illustrative of the claimed subject matters which may be embodied in various forms. The present disclosure may, however, be embodied in many different forms and should not be construed as limited to the exemplary embodiments and implementations set forth herein. Rather, these exemplary embodiments and implementations are provided so that description of the present disclosure is thorough and complete and will fully convey the scope of the present disclosure to those skilled in the art. In the description below, details of well-known features and techniques may be omitted to avoid unnecessarily obscuring the presented embodiments and implementations.
Overview

Implementations in accordance with the present disclosure relate to various techniques, methods, schemes and/or solutions pertaining to enhanced synchronization block design in wireless communications. According to the present disclosure, a number of possible solutions may be implemented separately or jointly. That is, although these possible solutions may be described below separately, two or more of these possible solutions may be implemented in one combination or another.

In the present disclosure, NTN refers to a network that uses radio frequency (RF) and information processing resources carried on high, medium and low orbit satellites or other high-altitude communication platforms to provide communication services for UEs. According to the load capacity on the satellite, there are two typical scenarios, namely: transparent payload and regenerative payload. In transparent payload mode, the satellite does not process the signal and waveform in the communication service but, rather, only functions as an RF amplifier to forward data. In regenerative payload mode, the satellite, other than RF amplification, also has the processing capabilities of modulation/demodulation, coding/decoding, switching, routing and so on.

As previously mentioned, low SNR ratio will lead to low success rates in signal detection, demodulation, and/or decoding at the receiver side. In 5G NR, SSB is the key signal for UEs to synchronize with network. FIG. 1 illustrates an example scenario 100 of the time-frequency structure of an SSB in 5G NR. As shown in FIG. 1, an SSB may consist of primary and secondary synchronization signals (PSS, SSS) , each occupying 1 symbol and 127 subcarriers, and a PBCH spanning across 3 orthogonal frequency-division multiplexing (OFDM) symbols and 240 subcarriers. To address the issue of low SNR ratio leading to low success rates in signal detection, demodulation, and/or decoding at the receiver, some time or frequency domain signal accumulation techniques may be employed. Specifically, the transmitter (e.g., base station (BS) ) may repeat the transmission of the same signal (e.g., SSB) , while the receiver (e.g., UE) may accumulate all the repeated signals for detection, demodulation, and/or decoding, or accumulate the detection or demodulation results of each repeated signal as the final result. However, in the scenario of time-domain signal repetition at the transmitter, the repetition of signals at different time intervals by the transmitter may impact the success rate of signal detection, demodulating, and/or decoding at the receiver, which influence the DL synchronization procedure.

In view of the above, the present disclosure proposes a number of schemes pertaining to enhanced synchronization block design in wireless communications. According to the schemes of the present disclosure, a SyncBlock may include one or a plurality of at least one of a PSS, an SSS, and a PBCH, such that the receiver (e.g., UE) may accumulate the one or the plurality of the PSS, the SSS, and/or the PBCH within one SyncBlock to perform the synchronization with the transmitter (e.g., BS) . In other words, the SyncBlock may include a plurality of items selected from the group consisting of PSS, SSS, and PBCH. Accordingly, by applying the schemes of the present disclosure, the success rate of signal detection, demodulating, and/or decoding at the receiver may be enhanced.

FIG. 2 illustrates an example scenario 200 of a communication environment in which various solutions and schemes in accordance with the present disclosure may be implemented. Scenario 200 involves a UE 210 in wireless communication with a network 220 (e.g., a wireless network including an NTN and a TN) via a terrestrial network node 222 (e.g., a BS such as an evolved Node-B (eNB) , a Next Generation Node-B (gNB) , a transmission/reception point (TRP) , or a gateway) and/or a non-terrestrial network node 224 (e.g., a satellite) . For example, the terrestrial network node 222 and the non-terrestrial network node 224 may form an NTN serving cell for wireless communication with the UE 210. In such communication environment, the UE 210, the network 220, and the terrestrial network node 222 and/or the non-terrestrial network node 224 may implement various schemes pertaining to enhanced synchronization block design in wireless communications in accordance with the present disclosure, as described below. It is noteworthy that, while the various proposed schemes may be individually or separately described below, in actual implementations some or all of the proposed schemes may be utilized or otherwise implemented jointly. Of course, each of the proposed schemes may be utilized or otherwise implemented individually or separately.

Under the first scheme of the present disclosure, the framework of the SyncBlock is proposed, including the SyncBlock’s content, periodicity, location in time domain, size in time domain, and time/frequency resources.

In some implementations, the content of the SyncBlock may include at least one of PSS (s) , SSS(s) , and PBCH (s) (e.g., including the demodulation reference signals (DMRS) within PBCH (s) ) .

In some implementations, aside from the PSS (s) , SSS (s) and/or PBCH (s) symbols, there may be one or multiple symbols within the SyncBlock, that are empty or used for other transmitting contents (e.g., signals other than PSS and SSS, channels other than PBCH, etc. ) . From the SyncBlock perspective, the empty symbols may be used to transmit data other than PSS/SSS/PBCH, but the data itself does not belong to the SyncBlock.

In some implementations, the (pre-) defined content of a SyncBlock may be different for different sub-carrier spacing (SCS) , different bandwidth part (BWP) , and/or different frequency band.

In some implementations, the SyncBlock periodicity may be (pre-) defined, e.g., in 3GPP technical specification (s) .

In some implementations, the start symbol of the SyncBlock periodicity may be the SyncBlock location reference point in time domain.

In some implementations, the start symbol of the SyncBlock periodicity may be described/indicated by an offset value to a reference symbol, slot, frame, half-frame, and/or system frame number (SFN) , etc.

In some implementations, the location of a SyncBlock within the SyncBlock periodicity in time domain may be described/indicated by an offset value to the start symbol of the SyncBlock periodicity, (i.e., SyncBlock location reference point) .

In some implementations, the size of a SyncBlock may be either one or multiple symbols or slots.

In some implementations, the first and last symbols of a SyncBlock may be either a PSS, SSS, PBCH symbol, an empty symbol, or a symbol for other transmission purpose.

In some implementations, a SyncBlock may occupy different (pre-) defined frequency bandwidth for different SCS, BWP, and/or frequency band. Additionally, or optionally, a SyncBlock’s frequency center location in frequency domain may be different for different SCS, BWP, and/or frequency band.

In some implementations, the (pre-) defined time resource (e.g., the SyncBlock periodicity, and/or size, location within the periodicity, etc. ) of a SyncBlock may be different for different SCS, BWP, and/or frequency band.

In some implementations, there may be one or multiple SyncBlocks within a SyncBlock periodicity.

In some implementations, the SyncBlock (s) within the same SyncBlock periodicity may be transmitted by the transmitter via the same beam or different beams.

In some implementations, the SyncBlock (s) within the same SyncBlock periodicity may have the same time-frequency structure and/or shot pattern, and have different time domain locations.

FIG. 3 illustrates an example scenario 300 of SyncBlock burst pattern in time domain in accordance with an implementation of the present disclosure. As shown in FIG. 3, the SyncBlock location reference point is the start symbol of the SyncBlock periodicity, which is represented as t=0. The time-domain location of the first SyncBlock (denoted as SyncBlock #1) within the SyncBlock periodicity is represented as t=offset 1, and the time-domain location of the second SyncBlock (denoted as SyncBlock #2) within the SyncBlock periodicity is represented as t=offset 2. In addition, both SyncBlock #1 and SyncBlock #2 occurs periodically according to the SyncBlock periodicity.

Under the second scheme of the present disclosure, the PSS/SSS/PBCH shot pattern design within a SyncBlock is proposed, including the shot definition, shot size, shot location in time domain, and shot content.

In some implementations, a PSS/SSS/PBCH shot represents for a PSS signal, SSS signal, or PBCH (as well as the embedded reference signal) , respectively.

In some implementations, the size/length of a shot may be (pre-) defined, and may be one or multiple symbols.

In some implementations, the lengths of PSS, SSS, and PBCH shots are independent with each other, i.e., the lengths of the PSS, SSS, and PBCH shots within the same SyncBlock are either the same or different.

In some implementations, the location of the first symbol of a shot in time domain within a SyncBlock may be described/indicated by an offset value to the start symbol of the SyncBlock (i.e., shot location reference point) .

In some implementations, the locations of all the PSS, SSS, or PBCH shots in time domain within a SyncBlock may be called the PSS, SSS, or PBCH shot pattern.

In some implementations, the locations of the PSS, SSS, and PBCH shots within the same SyncBlock may be independent with each other. In one example, the locations of the PSS shots within a SyncBlock may be different from the SSS and PBCH shots within the same SyncBlock. In another example, the locations of the SSS and PBCH shots within the same SyncBlock may be either the same or different (or partially overlapped in time domain and not overlapped in frequency domain) .

In some implementations, the locations of the PSS shots, SSS shots and PBCH shots within the same SyncBlock may not overlap with each other. In one example, the locations of the PSS shots within a SyncBlock may not overlapped with the SSS and PBCH shots within the same SyncBlock. In another example, the locations of the SSS and PBCH shots within the same SyncBlock may be either overlapped, partially overlapped, or not overlapped in time domain. Additionally, or optionally, the PSS shots, SSS shots and PBCH shots may not be overlapped in frequency domain.

In some implementations, the shot content of each PSS, SSS, or PBCH shot within the same SyncBlock may be the same or different. For example, the payloads of the first and second PBCH shots within the same SyncBlock may be the same or different.

In some implementations, the shot pattern design in the second scheme of the present disclosure may be applied for all of PSS, SSS, and PBCH.

In some implementations, the PSS/SSS/PBCH shot pattern within different SyncBlocks in the same SyncBlock periodicity may be the same.

In some implementations, at least one of the PSS shot (s) , SSS shot (s) , and PBCH shot (s) occur within a SyncBlock.

In some implementations, the PSS shot (s) , SSS shot (s) , and PBCH shot (s) occur within the same SyncBlock may be transmitted via the same beam of the transmitter.

FIG. 4 illustrates an example scenario 400 of the PSS/SSS/PBCH shot pattern within a SyncBlock in accordance with an implementation of the present disclosure. As shown in FIG. 4, there are 3 PSS shots, 4 PBCH shots, and 3 SSS shots within the SyncBlock. Specifically, the shot pattern starts with one PBCH shot followed by two PSS shots, then another PBCH shot followed by one PSS shot and two SSS shots, and then one more PBCH shot followed by one SSS shot, and ends with another PBCH shot.

FIG. 5 illustrates an example scenario 500 of the PSS/SSS/PBCH shot pattern within a SyncBlock in accordance with an implementation of the present disclosure. As shown in FIG. 5, there are 4 PSS shots and 4 PBCH shots within the SyncBlock. The shot location reference point is the start symbol of the SyncBlock periodicity, which is represented as t=0. The location of the first PSS shot in time domain is represented as t=offset 1, the location of the second PSS shot in time domain is represented as t=offset 2, the location of the third PSS shot in time domain is represented as t=offset 3, and the location of the fourth PSS shot in time domain is represented as t=offset 4. Similarly, the locations of the first, second, third, and fourth PBCH shots in time domain are represented as t=offset a, t=offset b, t=offset c, and t=offset d, respectively.

Under the third scheme of the present disclosure, the PSS shot pattern design for detection performance enhancement is proposed, which aims to render the time-domain gap (s) (e.g., in symbols) between PSS shots within the SyncBlock (s) be different from each other. The goal may be simplified as to find a (bit) sequence made of 0’s and 1’s , that has the best correlation property with its time delayed version (e.g., different lags) . The length of the sequence is the same as the SyncBlock size in time domain. The first symbol of each PSS shot within the SyncBlock may be represented as the non-zero element position of the sequence, i.e., the position of each non-zero element of the sequence corresponds to the first symbol of each PSS shot within the SyncBlock.

The positions of the non-zero elements within the sequence S may be represented as: Idx={a1, a2, …, aN} , where the length of Idx is N, equal to the number of the PSS shots within the SyncBlock. The sequence S may be represented as: where M is the sequence length. The sequence S should aim at obtaining a C, and maximizing the distance between the max value of C and the second max value of C: Alternatively, or additionally, the sequence S should aim at obtaining a C2, and maximizing the distance between the max value of C2 and the second max value of C2: where S_q (m) represents the cyclic shift version of S, and q represents the cyclic shift length.

FIG. 6 illustrates an example scenario 600 of the PSS shot pattern design for detection performance enhancement in accordance with an implementation of the present disclosure. As shown in FIG. 6, there are 4 PSS shots within the SyncBlock. The sequence may be determined as: S={1 1 0 1 0 0 0 1} , Idx= {0 1 3 7} , C= {1 1 0 1 1 1 1 4 1 1 1 1 0 1 1} . The position of the first symbol of each PSS shot may be represented as: {0 1 3 7} +offset 1, where the offset 1 represents the offset value of the first symbol of PSS shot 1 to the start symbol of the SyncBlock.

In addition, some examples of the possible sequence S and PSS pattern within a SyncBlock are listed in the following table.

Illustrative Implementations

FIG. 7 illustrates an example communication system 700 having an example communication apparatus 710 and an example network apparatus 720 in accordance with an implementation of the present disclosure. Each of communication apparatus 710 and network apparatus 720 may perform various functions to implement schemes, techniques, processes and methods described herein pertaining to enhanced synchronization block design in wireless communications, including scenarios/schemes described above as well as processes 800 and 900 described below.

Communication apparatus 710 may be a part of an electronic apparatus, which may be a UE such as a portable or mobile apparatus, a wearable apparatus, a wireless communication apparatus or a computing apparatus. For instance, communication apparatus 710 may be implemented in a smartphone, a smartwatch, a personal digital assistant, an electronic control unit (ECU) in a vehicle, a digital camera, or a computing equipment such as a tablet computer, a laptop computer or a notebook computer. Communication apparatus 710 may also be a part of a machine type apparatus, which may be an IoT, NB-IoT, or IIoT UE such as an immobile or a stationary apparatus, a home apparatus, a roadside unit (RSU) , a wire communication apparatus or a computing apparatus. For instance, communication apparatus 710 may be implemented in a smart thermostat, a smart fridge, a smart door lock, a wireless speaker or a home control center. Alternatively, communication apparatus 710 may be implemented in the form of one or more integrated-circuit (IC) chips such as, for example and without limitation, one or more single-core processors, one or more multi-core processors, one or more reduced-instruction set computing (RISC) processors, or one or more complex-instruction-set-computing (CISC) processors. Communication apparatus 710 may include at least some of those components shown in FIG. 7 such as a processor 712, for example. Communication apparatus 710 may further include one or more other components not pertinent to the proposed scheme of the present disclosure (e.g., internal power supply, display device and/or user interface device) , and, thus, such component (s) of communication apparatus 710 are neither shown in FIG. 7 nor described below in the interest of simplicity and brevity.

Network apparatus 720 may be a part of an electronic apparatus, which may be a network node such as a satellite, a BS, a cell, a router or a gateway of a 4G/5G/B5G/6G, NR, IoT, NB-IoT, IIoT, or NTN network. For instance, network apparatus 720 may be implemented in a satellite or an eNB/gNB/TRP in a 4G/5G, NR, IoT, NB-IoT, IIoT, or NTN network. Alternatively, network apparatus 720 may be implemented in the form of one or more IC chips such as, for example and without limitation, one or more single-core processors, one or more multi-core processors, or one or more RISC or CISC processors. Network apparatus 720 may include at least some of those components shown in FIG. 7 such as a processor 722, for example. Network apparatus 720 may further include one or more other components not pertinent to the proposed scheme of the present disclosure (e.g., internal power supply, display device and/or user interface device) , and, thus, such component (s) of network apparatus 720 are neither shown in FIG. 7 nor described below in the interest of simplicity and brevity.

In one aspect, each of processor 712 and processor 722 may be implemented in the form of one or more single-core processors, one or more multi-core processors, or one or more CISC processors. That is, even though a singular term “a processor” is used herein to refer to processor 712 and processor 722, each of processor 712 and processor 722 may include multiple processors in some implementations and a single processor in other implementations in accordance with the present disclosure. In another aspect, each of processor 712 and processor 722 may be implemented in the form of hardware (and, optionally, firmware) with electronic components including, for example and without limitation, one or more transistors, one or more diodes, one or more capacitors, one or more resistors, one or more inductors, one or more memristors and/or one or more varactors that are configured and arranged to achieve specific purposes in accordance with the present disclosure. In other words, in at least some implementations, each of processor 712 and processor 722 is a special-purpose machine specifically designed, arranged and configured to perform specific tasks, including synchronization block design, in a device (e.g., as represented by communication apparatus 710) and a network node (e.g., as represented by network apparatus 720) in accordance with various implementations of the present disclosure.

In some implementations, communication apparatus 710 may also include a transceiver 716 coupled to processor 712 and capable of wirelessly transmitting and receiving data. In some implementations, transceiver 716 may be capable of wirelessly communicating with different types of UEs and/or wireless networks of different radio access technologies (RATs) . In some implementations, transceiver 716 may be equipped with a plurality of antenna ports (not shown) such as, for example, four antenna ports. That is, transceiver 716 may be equipped with multiple transmit antennas and multiple receive antennas for beamforming and multiple-input multiple-output (MIMO) wireless communications. In some implementations, network apparatus 720 may also include a transceiver 726 coupled to processor 722. Transceiver 726 may include a transceiver capable of wirelessly transmitting and receiving data. In some implementations, transceiver 726 may be capable of wirelessly communicating with different types of UEs of different RATs. In some implementations, transceiver 726 may be equipped with a plurality of antenna ports (not shown) such as, for example, four antenna ports. That is, transceiver 726 may be equipped with multiple transmit antennas and multiple receive antennas for beamforming and MIMO wireless communications.

In some implementations, communication apparatus 710 may further include a memory 714 coupled to processor 712 and capable of being accessed by processor 712 and storing data therein. In some implementations, network apparatus 720 may further include a memory 724 coupled to processor 722 and capable of being accessed by processor 722 and storing data therein. Each of memory 714 and memory 724 may include a type of random-access memory (RAM) such as dynamic RAM (DRAM) , static RAM (SRAM) , thyristor RAM (T-RAM) and/or zero-capacitor RAM (Z-RAM) . Alternatively, or additionally, each of memory 714 and memory 724 may include a type of read-only memory (ROM) such as mask ROM, programmable ROM (PROM) , erasable programmable ROM (EPROM) and/or electrically erasable programmable ROM (EEPROM) . Alternatively, or additionally, each of memory 714 and memory 724 may include a type of non-volatile random-access memory (NVRAM) such as flash memory, solid-state memory, ferroelectric RAM (FeRAM) , magnetoresistive RAM (MRAM) and/or phase-change memory.

Each of communication apparatus 710 and network apparatus 720 may be a communication entity capable of communicating with each other using various proposed schemes in accordance with the present disclosure. For illustrative purposes and without limitation, a description of capabilities of communication apparatus 710, as a UE, and network apparatus 720, as a network node, is provided below with processes 800 and 900.
Illustrative Processes

FIG. 8 illustrates an example process 800 in accordance with an implementation of the present disclosure. Process 800 may be an example implementation of above scenarios/schemes, whether partially or completely, with respect to enhanced synchronization block design in wireless communications. Process 800 may represent an aspect of implementation of features of communication apparatus 710. Process 800 may include one or more operations, actions, or functions as illustrated by one or more of blocks 810 to 830. Although illustrated as discrete blocks, various blocks of process 800 may be divided into additional blocks, combined into fewer blocks, or eliminated, depending on the desired implementation. Moreover, the blocks of process 800 may be executed in the order shown in FIG. 8 or, alternatively, in a different order. Process 800 may be implemented by or in communication apparatus 710 or any suitable UE or machine type devices. Solely for illustrative purposes and without limitation, process 800 is described below in the context of communication apparatus 710, as a UE, and network apparatus 720, as a network node. Process 800 may begin at block 810.

At block 810, process 800 may involve processor 712 of communication apparatus 710 receiving, via transceiver 716, a SyncBlock from network apparatus 720, wherein the SyncBlock comprises one or a plurality of at least one of a PSS, an SSS, and a PBCH. Process 800 may proceed from block 810 to block 820.

At block 820, process 800 may involve processor 712 accumulating the one or the plurality of the at least one of the PSS, the SSS, and the PBCH within the SyncBlock. Process 800 may proceed from block 820 to block 830.

At block 830, process 800 may involve processor 712 performing a synchronization with network apparatus 720 based on the accumulation.

In some implementations, the SyncBlock may include at least one of the following: (i) one or more PSSs; (ii) one or more SSSs; (iii) one or more PBCHs; and (iv) one or more symbols that are empty or include contents other than the PSSs, the SSSs, and the PBCHs.

In some implementations, the SyncBlock may be received within a (SyncBlock) periodicity in time domain, and the periodicity starts from a start symbol at a location reference point in time domain or at a first offset to a reference symbol, slot, frame, half-frame, or SFN.

In some implementations, the SyncBlock may start at a second offset to the start symbol of the periodicity.

In some implementations, one or more SyncBlocks may be transmitted within the periodicity by network apparatus 720 via a same beam or different beams.

In some implementations, the one or more SyncBlocks within the periodicity may have a same time-frequency structure or a same shot pattern which indicates a pattern of shots each representing the PSS, the SSS, or the PBCH.

In some implementations, lengths of the PSS, the SSS, and the PBCH may be independent with each other.

In some implementations, each of the PSS, the SSS, and the PBCH may start at an offset to a start symbol of the SyncBlock; or locations of the PSS, the SSS, and the PBCH in time domain may be independent with each other; or locations of the PSS, the SSS, and the PBCH in time domain may not overlap with each other; or locations of the SSS and the PBCH in time domain may overlap with each other.

In some implementations, the plurality of the PSS, the SSS, or the PBCH may include a same payload or different payloads.

In some implementations, gaps between the plurality of the PSS in time domain may be different from each other.

FIG. 9 illustrates an example process 900 in accordance with an implementation of the present disclosure. Process 900 may be an example implementation of above scenarios/schemes, whether partially or completely, with respect to enhanced synchronization block design in wireless communications. Process 900 may represent an aspect of implementation of features of network apparatus 720. Process 900 may include one or more operations, actions, or functions as illustrated by one or more of blocks 910 to 920. Although illustrated as discrete blocks, various blocks of process 900 may be divided into additional blocks, combined into fewer blocks, or eliminated, depending on the desired implementation. Moreover, the blocks of process 900 may be executed in the order shown in FIG. 9 or, alternatively, in a different order. Process 900 may be implemented by or in network apparatus 720 as well as any variations thereof. Solely for illustrative purposes and without limitation, process 900 is described below in the context of communication apparatus 710, as a UE, and network apparatus 720, as a network node. Process 900 may begin at block 910.

At block 910, process 900 may involve processor 722 of network apparatus 720 generating a SyncBlock comprising one or a plurality of at least one of a PSS, an SSS, and a PBCH. Process 900 may proceed from block 910 to block 920.

At block 920, process 900 may involve processor 722 transmitting, via transceiver 726, the SyncBlock to communication apparatus 710.

In some implementations, the SyncBlock may be transmitted within a (SyncBlock) periodicity in time domain, and the periodicity starts from a start symbol at a location reference point in time domain or at a first offset to a reference symbol, slot, frame, half-frame, or SFN.

In some implementations, lengths of the PSS, the SSS, and the PBCH may be independent with each other; or each of the PSS, the SSS, and the PBCH may start at an offset to a start symbol of the SyncBlock; or locations of the PSS, the SSS, and the PBCH in time domain may be independent with each other; or locations of the PSS, the SSS, and the PBCH in time domain may not overlap with each other; or locations of the SSS and the PBCH in time domain overlap with each other.

In some implementations, the generating of the SyncBlock may include: determining a bit sequence representing a PSS shot pattern of the SyncBlock, wherein each position of non-zero elements of the bit sequence corresponds to a first symbol of one PSS shot within the SyncBlock, and the bit sequence has a best correlation property with time delayed versions and/or or cyclic shift versions of the bit sequence; and generating the SyncBlock based on the bit sequence.
Additional Notes

The herein-described subject matter sometimes illustrates different components contained within, or connected with, different other components. It is to be understood that such depicted architectures are merely examples, and that in fact many other architectures can be implemented which achieve the same functionality. In a conceptual sense, any arrangement of components to achieve the same functionality is effectively "associated" such that the desired functionality is achieved. Hence, any two components herein combined to achieve a particular functionality can be seen as "associated with" each other such that the desired functionality is achieved, irrespective of architectures or intermedial components. Likewise, any two components so associated can also be viewed as being "operably connected" , or "operably coupled" , to each other to achieve the desired functionality, and any two components capable of being so associated can also be viewed as being "operably couplable" , to each other to achieve the desired functionality. Specific examples of operably couplable include but are not limited to physically mateable and/or physically interacting components and/or wirelessly interactable and/or wirelessly interacting components and/or logically interacting and/or logically interactable components.

Further, with respect to the use of substantially any plural and/or singular terms herein, those having skill in the art can translate from the plural to the singular and/or from the singular to the plural as is appropriate to the context and/or application. The various singular/plural permutations may be expressly set forth herein for sake of clarity.

Moreover, it will be understood by those skilled in the art that, in general, terms used herein, and especially in the appended claims, e.g., bodies of the appended claims, are generally intended as “open” terms, e.g., the term “including” should be interpreted as “including but not limited to, ” the term “having” should be interpreted as “having at least, ” the term “includes” should be interpreted as “includes but is not limited to, ” etc. It will be further understood by those within the art that if a specific number of an introduced claim recitation is intended, such an intent will be explicitly recited in the claim, and in the absence of such recitation no such intent is present. For example, as an aid to understanding, the following appended claims may contain usage of the introductory phrases "at least one" and "one or more" to introduce claim recitations. However, the use of such phrases should not be construed to imply that the introduction of a claim recitation by the indefinite articles "a" or "an" limits any particular claim containing such introduced claim recitation to implementations containing only one such recitation, even when the same claim includes the introductory phrases "one or more" or "at least one" and indefinite articles such as "a" or "an, " e.g., “a” and/or “an” should be interpreted to mean “at least one” or “one or more; ” the same holds true for the use of definite articles used to introduce claim recitations. In addition, even if a specific number of an introduced claim recitation is explicitly recited, those skilled in the art will recognize that such recitation should be interpreted to mean at least the recited number, e.g., the bare recitation of "two recitations, " without other modifiers, means at least two recitations, or two or more recitations. Furthermore, in those instances where a convention analogous to “at least one of A, B, and C, etc. ” is used, in general such a construction is intended in the sense one having skill in the art would understand the convention, e.g., “a system having at least one of A, B, and C” would include but not be limited to systems that have A alone, B alone, C alone, A and B together, A and C together, B and C together, and/or A, B, and C together, etc. In those instances where a convention analogous to “at least one of A, B, or C, etc. ” is used, in general such a construction is intended in the sense one having skill in the art would understand the convention, e.g., “a system having at least one of A, B, or C” would include but not be limited to systems that have A alone, B alone, C alone, A and B together, A and C together, B and C together, and/or A, B, and C together, etc. It will be further understood by those within the art that virtually any disjunctive word and/or phrase presenting two or more alternative terms, whether in the description, claims, or drawings, should be understood to contemplate the possibilities of including one of the terms, either of the terms, or both terms. For example, the phrase “A or B” will be understood to include the possibilities of “A” or “B” or “A and B. ”

From the foregoing, it will be appreciated that various implementations of the present disclosure have been described herein for purposes of illustration, and that various modifications may be made without departing from the scope and spirit of the present disclosure. Accordingly, the various implementations disclosed herein are not intended to be limiting, with the true scope and spirit being indicated by the following claims.

Claims

A method, comprising:

receiving, by a processor of an apparatus, a synchronization block (SyncBlock) from a network node, wherein the SyncBlock comprises one or a plurality of at least one of a primary synchronization signal (PSS) , a secondary synchronization signal (SSS) , and a physical broadcast channel (PBCH) ;

accumulating, by the processor, the one or the plurality of the at least one of the PSS, the SSS, and the PBCH within the SyncBlock; and

performing, by the processor, a synchronization with the network node based on the accumulation.
The method of Claim 1, wherein the SyncBlock comprises at least one of the following:

one or more PSSs;

one or more SSSs;

one or more PBCHs; and

one or more symbols that are empty or comprise contents other than the PSSs, the SSSs, and the PBCHs.
The method of Claim 1, wherein the SyncBlock is received within a periodicity in time domain, and the periodicity starts from a start symbol at a location reference point in time domain or at a first offset to a reference symbol, slot, frame, half-frame, or system frame number (SFN) .
The method of Claim 3, wherein the SyncBlock starts at a second offset to the start symbol of the periodicity.
The method of Claim 3, wherein one or more SyncBlocks are transmitted within the periodicity by the network node via a same beam or different beams.
The method of Claim 5, wherein the one or more SyncBlocks within the periodicity have a same time-frequency structure or a same shot pattern which indicates a pattern of shots each representing the PSS, the SSS, or the PBCH.
The method of Claim 1, wherein lengths of the PSS, the SSS, and the PBCH are independent with each other.
The method of Claim 1, wherein:

each of the PSS, the SSS, and the PBCH starts at an offset to a start symbol of the SyncBlock;

locations of the PSS, the SSS, and the PBCH in time domain are independent with each other;

locations of the PSS, the SSS, and the PBCH in time domain do not overlap with each other; or

locations of the SSS and the PBCH in time domain overlap with each other.
The method of Claim 1, wherein the plurality of the PSS, the SSS, or the PBCH comprise a same payload or different payloads.
The method of Claim 1, wherein gaps between the plurality of the PSS in time domain are different from each other.
A method, comprising:

generating, by a processor of a network node, a synchronization block (SyncBlock) comprising one or a plurality of at least one of a primary synchronization signal (PSS) , a secondary synchronization signal (SSS) , and a physical broadcast channel (PBCH) ; and

transmitting, by the processor, the SyncBlock to an apparatus.
The method of Claim 11, wherein the SyncBlock comprises at least one of the following:

one or more PSSs;

one or more SSSs;

one or more PBCHs; and

one or more symbols that are empty or comprise contents other than the PSSs, the SSSs, and the PBCHs.
The method of Claim 11, wherein the SyncBlock is transmitted within a periodicity in time domain, and the periodicity starts from a start symbol at a location reference point in time domain or at a first offset to a reference symbol, slot, frame, half-frame, or system frame number (SFN) .
The method of Claim 13, wherein the SyncBlock starts at a second offset to the start symbol of the periodicity.
The method of Claim 13, wherein one or more SyncBlocks are transmitted within the periodicity by the network node via a same beam or different beams.
The method of Claim 15, wherein the one or more SyncBlocks within the periodicity have a same time-frequency structure or a same shot pattern which indicates a pattern of shots each representing the PSS, the SSS, or the PBCH.
The method of Claim 11, wherein:

lengths of the PSS, the SSS, and the PBCH are independent with each other;

each of the PSS, the SSS, and the PBCH starts at an offset to a start symbol of the SyncBlock;

locations of the PSS, the SSS, and the PBCH in time domain are independent with each other;

locations of the PSS, the SSS, and the PBCH in time domain do not overlap with each other; or

locations of the SSS and the PBCH in time domain overlap with each other.
The method of Claim 11, wherein the plurality of the PSS, the SSS, or the PBCH comprise a same payload or different payloads.
The method of Claim 11, wherein gaps between the plurality of the PSS in time domain are different from each other.
The method of Claim 19, wherein the generating of the SyncBlock comprises:

determining a bit sequence representing a PSS shot pattern of the SyncBlock, wherein each position of non-zero elements of the bit sequence corresponds to a first symbol of one PSS shot within the SyncBlock, and the bit sequence has a best correlation property with time delayed versions or cyclic shift versions of the bit sequence; and

generating the SyncBlock based on the bit sequence.