WO2025200087A1 - 基于预测执行的带状态可编程数据平面结构及芯片 - Google Patents

基于预测执行的带状态可编程数据平面结构及芯片

Info

Publication number
WO2025200087A1
WO2025200087A1 PCT/CN2024/091773 CN2024091773W WO2025200087A1 WO 2025200087 A1 WO2025200087 A1 WO 2025200087A1 CN 2024091773 W CN2024091773 W CN 2024091773W WO 2025200087 A1 WO2025200087 A1 WO 2025200087A1
Authority
WO
WIPO (PCT)
Prior art keywords
read
processor
write
data packet
stateful
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
PCT/CN2024/091773
Other languages
English (en)
French (fr)
Inventor
刘斌
陈智康
冯勇
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Tsinghua University
Original Assignee
Tsinghua University
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tsinghua University filed Critical Tsinghua University
Publication of WO2025200087A1 publication Critical patent/WO2025200087A1/zh
Pending legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F8/00—Arrangements for software engineering
    • G06F8/30—Creation or generation of source code

Definitions

  • the stateful data plane functionality can be summarized as an EFSM (extended finite state machine).
  • EFSM extended finite state machine
  • the packet state is read from the flow state table; an action is performed based on the current state and input. This action may result in a state update, which is written back to the flow state table.
  • the inconsistency between writing back to the flow state table and the forward processing flow of the pipeline makes existing pipeline technology unable to support more complex stateful operations.
  • the present application provides a stateful programmable data plane structure and chip based on speculative execution to solve the problems that the pipeline technology in the related art cannot support more complex stateful operations and has high development costs.
  • the first aspect of the present application provides a stateful programmable data plane structure based on predictive execution, including: multiple stage processors, wherein the multiple stage processors form a data processing pipeline, and each stage processor processes a pipeline stage; a side ring, wherein the side ring includes multiple ring nodes, and the multiple ring nodes are connected to each stage processor in a one-to-one correspondence; any stage processor in the multiple stage processors is configured as a read processor or a write processor, the read processor reads the state required to be read by at least one stateful data packet, and predicts that the state of the stateful data packet remains unchanged; the write processor writes the state required to be written by the stateful data packet, identifies the data packet whose state is modified and needs to be resubmitted, uploads the data packet that needs to be resubmitted to the ring node corresponding to the write processor, and sends it to the ring node corresponding to the read processor through the side ring, The read processor downloads the data packets that need to be re
  • the stage processor includes a configurable scheduling module, wherein the configurable scheduling module of the read processor is configured as a read scheduling module, the configurable scheduling module of the write processor is configured as a write scheduling module, and the configurable scheduling modules of other stage processors are not activated.
  • both the read scheduling module and the write scheduling module include: a dirty table stored in a content-addressable memory, wherein the keyword used to match in the dirty table is a state table index of the flow, wherein the dirty table of the write scheduling module contains a table of keywords, and the dirty table of the read scheduling module contains a table of keywords and corresponding data; the write scheduling module writes the flow corresponding to the data packet with modified state into the dirty table, and sends a write-back control signal to the read scheduling module through the side ring, and the read scheduling module writes the flow corresponding to the data packet with modified state into the dirty table according to the write-back control signal.
  • the read processor also includes: a resubmission buffer for storing resubmitted data packets;
  • the read scheduling module also includes: a data packet buffer for storing data packets that hit the dirty table, and the data packets of each flow are linked in a first linked list and a second linked list, the first linked list is used to store newly arrived data packets on the pipeline, and the second linked list is used to store data packets that need to be resubmitted; an order-preserving check module for scheduling data packets in the data packet buffer, and when the data packets in the data packet buffer are scheduled, whether the data packets that need to be resubmitted of the flow where the scheduled data packets are located have all arrived in the resubmission buffer and have all been moved to the second linked list of the data packet buffer.
  • the order-preserving checking module is further configured to: start a timer until the timer times out, and determine that all data packets that need to be resubmitted have arrived at the resubmission buffer.
  • a heartbeat address field is set on the bus of the side ring.
  • the heartbeat address field is independent of other fields on the bus, and each pipeline stage occupies one bit of the heartbeat address field, and the signal carrying the heartbeat is written into the heartbeat address field; when the timer receives the signal carrying the heartbeat sent from the corresponding write processor, the timing is advanced by one moment.
  • sequence checking module is also used to: write the serial number of each data packet into the counter table when each data packet reads the status; if the serial number of the data packet that needs to be resubmitted is equal to the serial number in the counter table, it is determined that all the data packets that need to be resubmitted have arrived at the resubmission buffer.
  • the read processor is also used to write a flush signal to the corresponding ring node when the data packet of a flow in the data packet buffer starts to be scheduled, send it to the ring node corresponding to the write processor through the side ring, and download it to the write processor; the write processor removes the corresponding flow from the dirty table according to the flush signal.
  • the read scheduling module includes first to third levels of state consistency, wherein the first level of state consistency includes: the read operation of the data packet is after the write operation of all data packets before the data packet; the second level of state consistency includes: on the stream where the target data packet is located, the read operation of K data packets after the target data packet is allowed to be before the write operation of K data packets, and starting from the K+1th data packet, the read operation of the data packet is after the write operation of all data packets before the data packet; the third level of state consistency includes: the order of the read operation and the write operation of the data packet is arbitrary.
  • a second embodiment of the present application provides a programmable switching chip, including: a stateful programmable data plane structure based on speculative execution according to any one of the above embodiments.
  • the embodiment of the present application adds a simple side ring to the pipeline, so that each pipeline stage is connected to it.
  • the data flow is opposite to the direction of the pipeline, providing a fast backward communication path.
  • the read processor reads the state required to read the data packet with state, and the write processor can write back the state across stages when writing back the data packet that needs to modify the state.
  • the whole process is very convenient and more efficient, and supports complex stateful functions, thereby reducing the development cost, deployment cost and maintenance cost of in-network computing applications as a whole.
  • the problems of pipeline technology in related technologies that cannot support more complex stateful operations and have high development costs are solved.
  • Figure 1 shows the technical architecture of Banzai in related art
  • FIG2 is a circuit diagram of an atomic operation of Banzai in the related art
  • FIG3 is a technical architecture diagram of a distributed reconfigurable matching table in related art
  • FIG4 is a block diagram of a stateful programmable data plane structure based on speculative execution according to an embodiment of the present application
  • FIG6 is a schematic diagram of a finite state machine under bounded stale consistency provided according to an embodiment of the present application.
  • the present application provides a stateful programmable data plane structure based on predictive execution, which adds a simple side ring to the pipeline so that each pipeline stage is connected to it. On the side ring, the data flow is opposite to the direction of the pipeline, providing a fast backward communication path.
  • the read processor reads the state of the data packet with state, and the write processor writes back the data packet that needs to modify the state, it can cross the stage.
  • the distributed reconfigurable matching table uses a multi-core, multi-threaded run-to-completion (RTC) processor to support stateful functions.
  • dRMT decouples the memory and processor on the switch chip, and the processor accesses the memory resources in the memory cluster through the switch network, as shown in Figure 3.
  • RTC run-to-completion
  • dRMT uses shared memory to store the state table, it needs to handle the state consistency problem through access scheduling and locking, resulting in unpredictable waiting times on some processors, thereby destroying the deterministic delay premise preset by its compilation algorithm based on integer linear programming. Such programs cannot pass compilation.
  • each processor maintains its own copy of the state table, a complex synchronization mechanism is required. system, and consumes a lot of additional memory.
  • the stage processor includes a configurable scheduling module, wherein the configurable scheduling module of the read processor is configured as a read scheduling module, the configurable scheduling module of the write processor is configured as a write scheduling module, and the configurable scheduling modules of other stage processors are not activated.
  • RAPID Ring-Augmented Pipeline Dataplane
  • the overall technical architecture of RAPID is shown in Figure 4.
  • the embodiment of the present application can add a simple side ring to the pipeline and connect each pipeline stage to it.
  • the direction of data flow and pipeline can be opposite, thereby providing a fast backward communication path.
  • the direction of data flow and pipeline can also be opposite. They can be the same, or a bidirectional data path can be used, that is, data can flow bidirectionally between adjacent nodes; those skilled in the art can select or set them specifically, and there is no specific limitation.
  • the embodiment of the present application proposes a behavioral abstraction of "local read-remote write" in RAPID.
  • RAPID For complex stateful functions, it involves a series of stage processors in the pipeline.
  • the flow state table is stored on the first processor in the series, and the data packet reads the state on the first processor. After being processed by several processors, the state is written back across stages on the last processor in the series.
  • the control signals, addresses, and data written back across stages are uploaded by the last processor to its corresponding ring node, sent to the ring node corresponding to the first processor through the side ring, and then written into the state table stored in the first processor.
  • a configurable scheduling module is installed on each stage processor of the embodiment of the present application, as shown in Figure 5.
  • the module can be reconstructed as a read scheduling module or a write scheduling module.
  • the scheduling module on the read processor is configured as a read scheduling module
  • the scheduling module on the write processor is configured as a write scheduling module
  • the scheduling module on the middle processor is not activated.
  • the scheduling module is implemented as a bypass without being inserted into the pipeline, so the activated scheduling module will not introduce additional delays for pipeline processing.
  • the scheduling module and its connected side rings are lossless to the pipeline performance.
  • the read scheduling module and the write scheduling module of the embodiment of the present application both include: a dirty table stored in a content-addressable memory, wherein the keyword used to match in the dirty table is a state table index of the flow, wherein the dirty table of the write scheduling module contains a table of keywords, and the dirty table of the read scheduling module contains a table of keywords and corresponding data; the write scheduling module writes the flow corresponding to the data packet with modified status into the dirty table, and sends a write-back control signal to the read scheduling module through the side ring, and the read scheduling module writes the flow corresponding to the data packet with modified status into the dirty table according to the write-back control signal.
  • both the read scheduling module and the write scheduling module of the embodiment of the present application are equipped with a small content addressable memory as a dirty table for registering the "dirty" flow currently undergoing stateful processing.
  • the keyword used for matching in the dirty table is the state table index of the flow (for example, the hash value of the flow ID).
  • the dirty table in the write scheduling module is a table containing only keywords, while the dirty table in the read scheduling module also contains related data.
  • the read processor of the embodiment of the present application also includes: a resubmission buffer for storing data packets that need to be resubmitted; the read scheduling module also includes: a data packet buffer for storing data packets that hit the dirty table, and the data packets of each flow are linked in a first linked list and a second linked list, the first linked list is used to store newly arrived data packets on the pipeline, and the second linked list is used to store data packets that need to be resubmitted.
  • packets of flows not in the dirty table will be processed without blocking, and packets of dirty flows that are resubmitted and blocked will only be opportunistically scheduled in idle pipeline cycles. Therefore, packets that are resubmitted and blocked require a resubmit buffer (RB). Under normal traffic conditions, the load on the switch pipeline is light, leaving There are enough idle cycles to process the buffered packets. The packets newly arrived from the pipeline and hitting the dirty table in the read scheduling module are stored in the packet buffer (PB) of the read scheduling module.
  • PB packet buffer
  • Both RB and PB are queues. Once the first packet in the RB has a chance to enter the pipeline, it moves from the RB to the PB.
  • packets for each flow are linked in two linked lists: the first linked list (NL) that stores newly arrived packets in the pipeline, and the second linked list (RL) that stores resubmitted packets. Metadata for the two linked lists is maintained in the dirty table, while the link pointer for each linked list node is stored in a dedicated register set.
  • the read scheduling module of the embodiment of the present application also includes an order-preserving check module for scheduling packets in the packet buffer and detecting whether, when the packets in the packet buffer are scheduled, all packets that need to be resubmitted for the flow to which the scheduled packets belong have arrived at the resubmission buffer and have all been moved to the second linked list (RL) of the packet buffer.
  • RL second linked list
  • the read scheduling module can schedule data packets of a flow in the PB only under the following conditions:
  • Condition (2) can only be met after condition (1) is met.
  • Condition (2) is guaranteed by the resubmitted packet counter maintained in the dirty table. Each time the RB receives a packet that needs to be resubmitted, the corresponding counter is incremented; each time a packet that needs to be resubmitted is moved from the RB to the PB, the corresponding counter is decremented. A counter value of 0 means that condition (2) is met.
  • the RL is inserted as a whole before the NL to prepare for scheduling, and the new RL is reset to an empty linked list.
  • the embodiment of the present application designs two different checking schemes for condition (1) to ensure that when a data packet of a flow in the PB is scheduled, all data packets previously read in the stale state have been resubmitted to the read processor, as follows:
  • Solution 1 A timer-based solution starts a timer until the timer times out and determines that all packets that need to be resubmitted have arrived at the resubmission buffer.
  • the timer-based solution maintains a timer field in the dirty table of the read scheduling module.
  • the read scheduling module receives a remote write signal, it writes the flow corresponding to the modified state packet to the dirty table and starts the timer.
  • the timer is a countdown that continuously decreases over time. When the timer expires, it indicates that enough time has passed for all previously sent packets to return to the RB.
  • the time it takes for a packet to be read locally and written remotely in the pipeline is only related to the pipeline parameters and the number of stages between them, which is a constant that can be determined by the compiler (in The timer is initialized to the sum of these two values at startup. Therefore, if there is no congestion on the side ring, the timer advances by one tick per cycle, ensuring that all previously sent packets reach the RB.
  • the timer-based solution ensures that the timer value will only decrease in an unblocked period by designing the communication protocol on the side ring, so that even if the side ring is blocked, it can still ensure that all previously sent data packets arrive at the RB when the timer times out.
  • the side ring can transmit three signals: cross-stage status writeback, data packets that need to be resubmitted, and clearing signals.
  • the bus on the side ring of the embodiment of the present application adds an additional field to represent the heartbeat address.
  • the heartbeat address is a bitmap, with each bit corresponding to a stage on the chip.
  • the write scheduler continuously sends heartbeats to the read scheduler. Because each pipeline stage's heartbeat occupies only one bit in the heartbeat address field, and the heartbeat address field is independent of other fields in the bus, any signal (considered an idle signal when the bus is idle) can simultaneously carry any number of heartbeats.
  • signals from the side ring compete with signals from the current stage being uploaded to the ring node. Except for the idle signal, which is directly discarded, other signals are stored in queue buffers in both directions, and bus arbitration is performed by the scheduler.
  • the read scheduler will not receive the heartbeat for a period of time.
  • the read scheduler's timer advances by one time if and only if a heartbeat is received, thus achieving accurate timing. Whether idle cycles are blocked does not affect timing accuracy; the heartbeat carried by the idle signal can be directly transferred to another signal when it is discarded.
  • Solution 2 A counter-based solution.
  • the sequence checking module of the embodiment of the present application is also used to write the serial number of each data packet into the counter table when each data packet is in the read state; if the serial number of the data packet that needs to be resubmitted is equal to the serial number in the counter table, it is determined that all the data packets that need to be resubmitted have arrived at the read processor.
  • the counter-based solution adds a small amount of memory to each pipeline stage. These memories are used to store counter tables on the read processor.
  • the read scheduling module receives the remote write signal sent back, it writes the flow corresponding to the modified state data packet into the dirty table.
  • the counter table maintains a sequence number for each flow.
  • a metadata field is used to store the sequence number of each data packet. It is written and incremented when the data packet enters the pipeline, and the sequence number maintained by the counter table is the maximum sequence number of the stateful data packet that has passed.
  • the sequence number of the data packet that needs to be resubmitted is compared with the sequence number in the local counter table. If the two are equal, it means that all the data packets sent before have returned to the RB.
  • the timer-based solution only requires adding additional fields to the dirty table, offering advantages in terms of chip area and power consumption.
  • the counter-based solution is simpler to implement and doesn't rely on precise time counting, offering better scalability.
  • the read processor is further configured to start queuing a data packet of a flow in the data packet buffer.
  • the cleaning signal is written into the corresponding ring node, sent to the ring node corresponding to the write processor through the side ring, and downloaded to the write processor; the write processor removes the corresponding flow from the dirty table according to the cleaning signal.
  • the write scheduling module detects that a packet will cause a change in its flow state (i.e., a remote write is triggered)
  • the flow is registered in the write scheduling module's dirty table.
  • the write-back control signal reaches the target processor from the side ring, it simultaneously notifies the read scheduling module on that processor to register the flow in its own dirty table. If a subsequent packet in the write scheduling module hits the dirty table, it indicates a prediction error.
  • the packet is uploaded to the side ring and resent to the read processor, re-entering the local read-remote write stateful processing flow.
  • the flow registered in the read scheduling module's dirty table serves as a safeguard, preventing newly arriving packets of that flow from entering stateful processing.
  • the read scheduling module sends a flush signal to notify the write scheduling module to remove the flow from its dirty table. Once all backlogged packets have been sent, the flow is removed from the read scheduling module's local dirty table.
  • hash collisions are possible.
  • a flow that is not actually dirty may be found in the dirty table, causing it to be incorrectly blocked and resubmitted, resulting in a certain degree of performance loss.
  • the probability of hash collisions is very low, so the impact of hash collisions on overall packet processing performance is almost negligible.
  • the read scheduling module includes first to third levels of state consistency, wherein the first level of state consistency includes: the read operation of a data packet is after the write operation of all data packets before the data packet; the second level of state consistency includes: on the stream where the target data packet is located, the read operation of K data packets after the target data packet is allowed to be before the write operation of K data packets, and starting from the K+1th data packet, the read operation of the data packet is after the write operation of all data packets before the data packet; the third level of state consistency includes: the order of the read operation and the write operation of the data packet is arbitrary.
  • the first level of state consistency can be strong consistency
  • the third level of state consistency can be weak consistency
  • the second level of state consistency can be bounded staleness consistency
  • the target data packet can be any data packet
  • the state of the flow where the target data packet is located obeys the bounded staleness consistency requirements.
  • the preset number can be specified according to actual conditions, such as setting it to K.
  • embodiments of the present application can use predictive execution technology to process data packets.
  • the read processor always predicts that a stateful data packet will not modify its state.
  • a data packet does not modify its state, it does not cause state consistency issues, so there is no need to block the processing of subsequent data packets, thereby not affecting the packet processing performance of the switching chip.
  • a data packet needs to modify its state, it indicates that the previous prediction was wrong. At this time, not only does it need to write back the state data across stages, but it also needs to trigger the state consistency guarantee mechanism.
  • every packet that hits the dirty table in the write scheduling module should be resubmitted.
  • For weak consistency when a packet causes a state change, only the new state is written back without registering the flow in the dirty table, thus preventing the resubmission of subsequent packets. This is suitable for scenarios where the state can eventually converge even if some packets read stale state (for example, a rate limiter).
  • a finite state machine For bounded staleness consistency, a finite state machine (FSM) is used to guide the behavior of the write scheduling module under bounded staleness consistency, as shown in Figure 6.
  • FSM finite state machine
  • a flow is not in the dirty table of the write scheduling module and can pass normally without resubmission.
  • the FSM transitions to the "expiring" state, and a decrementing counter is initialized to K. In this state, up to K packets of the flow can pass without resubmission.
  • the counter reaches 0, the FSM transitions to the "expired" state, and the flow is registered in the dirty table, starting a round of strict state synchronization. Only the flush signal from the read scheduling module can remove the flow from the dirty table of the write scheduling module and restore the state of the flow to the "normal" state.
  • the embodiment of the present application can be based on the P4_16 language and enhance it by introducing a new abstract structure - the mutable table (muTable), which is equivalent to the table in P4.
  • the muTable can be modified by the data plane, so it can be used to implement the flow state table.
  • User-written programs can apply read and write primitives to the muTable object to customize the processing logic of the stateful function.
  • the compiler decides whether it can be implemented in a single stage or multiple stages based on the complexity of the stateful function.
  • Simple stateful functions that can be implemented by atomic operations will be compiled into a single stage, and the cross-stage data write-back function will not be enabled; complex stateful functions that cannot be implemented by atomic operations will be compiled into multiple stages and implemented using cross-stage data write-back.
  • stateful processing involves modifying some data (for example, reducing the TTL field in the IPv4 protocol), packet resubmission may cause the data to be modified multiple times, resulting in a read-after-write conflict and incorrect results.
  • the compiler uses a "field renaming" technique to solve this problem. For fields that are modified between the local read and the remote write, the compiler creates a copy of the field in the metadata. When reading the field between the local read and the remote write, it is read only from the location of the copy, not from the location of the field itself, which may have been modified once.
  • this application implements a low-cost, high-performance data plane structure to support complex stateful functions, which can offload more in-network computing applications from servers or middleboxes to programmable switches, thereby reducing the communication delay of in-network computing, reducing the use of network bandwidth, reducing the network system's demand for servers or middlebox devices, and simplifying in-network computing.
  • a programming method for computing applications thereby reducing the overall development cost, deployment cost and maintenance cost of computing applications in the network.
  • Load balancers are an essential feature in cloud networks.
  • LBs Load balancers
  • client packets are sent to a virtual destination IP address, and the LB assigns a physical IP address to each packet. If an input packet finds an existing mapping from its flow to a physical IP address in the state table, it is forwarded using that address. Otherwise, a policy or algorithm is applied to select a physical IP address for the packet, and the new mapping from the packet flow to the physical IP address is written back to the state table.
  • Determining the physical server for a newly arrived flow can require complex logic.
  • the conventional approach is to have the controller software on the server make the decision and then write the result back to the flow state table. Multiple forwarding and communication delays can put pressure on the packet buffer on the switch, reducing throughput.
  • the present embodiment offloads the logic for determining a new physical IP address for stateful LB to the data plane through cross-stage writeback, effectively improving LB performance.
  • DDoS attacks such as DNS floods, TCP SYN floods, and amplification attacks, have always been a significant challenge for networks.
  • Traditional server- or middlebox-based solutions are costly and have limited throughput.
  • the cross-stage data writeback feature proposed in this application provides a high-performance DDoS detection solution that can be implemented on the switch data plane:
  • incoming packets are classified using access lists (e.g., blacklists, whitelists, and graylists for attack flows, normal flows, and suspicious flows, respectively).
  • the detection/analysis module then analyzes them based on the list search results. This module can be a sketch or a series of header field checks. If a packet on the whitelist is deemed suspicious, the decision module updates the list and moves the corresponding flow from the whitelist to the graylist. Other inter-list movements are similar.
  • Traffic shaping and policy control are critical in enforcing Quality of Service (QoS) policies and ensuring optimal bandwidth allocation.
  • QoS Quality of Service
  • packets are first classified based on user-defined header fields and then evaluated by some rate control or scheduling algorithm based on the current queue or link state.
  • the packet is queued or dropped, and the queue state is updated (i.e., written back to the evaluation module).
  • the writeback is from the egress pipeline to the ingress pipeline. Since the pioneering work of PIFO, many efforts have been made to make packet scheduling programmable. However, most of them cannot avoid cross-stage data writeback. On today's pipeline-based chips, these schemes have to use packet recycling or approximation methods, which affects scheduling performance or accuracy.
  • a simple side ring is added to the pipeline so that each pipeline stage is connected to it.
  • the data flow is opposite to the direction of the pipeline, providing a fast backward communication path.
  • the read processor reads the state required to read the state of the data packet with state, and the write processor can write back the state across stages when writing back the data packet that needs to modify the state.
  • the whole process is very convenient and more efficient, and supports complex stateful functions, thereby reducing the development cost, deployment cost and maintenance cost of in-network computing applications as a whole.
  • the problems that the pipeline technology in the related art cannot support more complex stateful operations and has high development costs are solved.
  • an embodiment of the present application further provides a programmable switching chip, including the stateful programmable data plane structure based on speculative execution of the above embodiment.
  • first and second are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the technical features indicated.
  • N means at least two, such as two, three, etc., unless otherwise clearly defined.

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)

Abstract

本申请涉及可编程数据平面技术领域，特别涉及一种基于预测执行的带状态可编程数据平面结构及芯片，其中，数据平面结构包括：多个阶段处理器，多个阶段处理器组成数据处理的流水线，每个阶段处理器处理一个流水线阶段；侧环，侧环上包括多个环节点，每个环节点和每个阶段处理器一一对应连接；读处理器读取带状态的数据包所需要读取的状态；写处理器写入带状态的数据包所需要写入的状态，识别被修改状态的需要重新提交的数据包，将重新提交的数据包上传至对应的环节点，通过侧环发送至读处理器对应的环节点，读处理器从对应环节点下载需要重新提交的数据包。由此，解决了相关技术中的流水线技术无法支持较为复杂的带状态操作及开发成本高等问题。

Description

基于预测执行的带状态可编程数据平面结构及芯片
相关申请的交叉引用
本申请基于申请号为202410360790.8，申请日为2024年03月27日申请的中国专利申请提出，并要求该中国专利申请的优先权，该中国专利申请的全部内容在此引入本申请作为参考。
技术领域
本申请涉及可编程数据平面技术领域，特别涉及一种基于预测执行的带状态可编程数据平面结构及芯片。
背景技术
可编程交换机包括可编程数据平面和控制平面，数据平面负责协议解析与逆解析、数据包处理，控制平面负责下发解析规则及流表匹配规则。从定制的协议转发到支持网内计算应用，高性能的可编程交换芯片进一步发掘了数据平面设备的潜力。高吞吐量的需求使得硬件流水线成为交换芯片架构的主要选择。尽管流水线具有无与伦比的吞吐量，但它假设了一个正向处理流程，这阻碍了对许多有价值应用至关重要的带状态功能的有效支持。
带状态的数据平面功能可以概括为EFSM(extended finite state machine，扩展有限状态机)。数据包的状态从流状态表中读取；根据当前状态和输入执行相应的操作；该操作可能会导致状态更新，该更新将被写回流状态表。写回流状态表的操作和流水线的正向处理流程之间的矛盾，使得现有的流水线技术无法支持较为复杂的带状态操作。
发明内容
本申请提供一种基于预测执行的带状态可编程数据平面结构及芯片，以解决相关技术中的流水线技术无法支持较为复杂的带状态操作，且存在开发成本高等问题。
本申请第一方面实施例提供一种基于预测执行的带状态可编程数据平面结构，包括：多个阶段处理器，其中，多个阶段处理器组成数据处理的流水线，每个阶段处理器处理一个流水线阶段；侧环，其中，侧环上包括多个环节点，多个环节点和每个阶段处理器一一对应连接；多个阶段处理器中任意阶段处理器被配置为读处理器或写处理器，读处理器读取至少一个带状态的数据包所需要读取的状态，并预测带状态的数据包状态不变；写处理器写入带状态的数据包所需要写入的状态，识别被修改状态的需要重新提交的数据包，将需要重新提交的数据包上传至写处理器对应环节点，通过侧环发送至读处理器对应环节点， 读处理器从对应环节点下载需要重新提交的数据包。
可选地，阶段处理器包括可配置调度模块，其中，读处理器的可配置调度模块被配置为读调度模块，写处理器的可配置调度模块被配置为写调度模块，其他阶段处理器的可配置调度模块不激活。
可选地，读调度模块与写调度模块均包括：存储在内容可寻址存储器中的脏表，用于在脏表中匹配的关键字是流的状态表索引，其中，写调度模块的脏表包含关键字的表，读调度模块的脏表包含关键字的表和对应数据；写调度模块将修改状态的数据包对应的流写入脏表，并通过侧环发送写回控制信号给读调度模块，读调度模块根据写回控制信号将修改状态的数据包对应的流写入脏表。
可选地，读处理器还包括：重新提交缓冲区，用于保存重新提交的数据包；读调度模块还包括：数据包缓冲区，用于保存命中脏表的数据包，且每个流的数据包被链接在第一链表和第二链表中，第一链表用于存储流水线上新到来的数据包，第二链表用于存储需要重新提交的数据包；保序检查模块，用于调度数据包缓冲区的数据包，在数据包缓冲区的数据包被调度时，需要被调度数据包所在流的需要重新提交的数据包是否已经全部到达重新提交缓冲区，并已经全部移动到数据包缓冲区的第二链表。
可选地，保序检查模块还用于：启动计时器，直到计时器超时，确定需要重新提交的数据包已经全部到达重新提交缓冲区。
可选地，侧环的总线上设置有心跳地址字段，心跳地址字段与总线上其他字段独立，且每个流水线阶段占用心跳地址字段的一个位，将携带有心跳的信号写入心跳地址字段；计时器收到发自对应写处理器的携带有心跳的信号时计时前进1个时刻。
可选地，保序检查模块还用于：在每个数据包读状态时将每个数据包的序列号写入计数器表；若需要重新提交的数据包的序列号与计数器表中的序列号相等，确定需要重新提交的数据包已经全部到达重新提交缓冲区。
可选地，读处理器还用于在数据包缓冲区内的一个流的数据包开始被调度时，将清扫信号写入对应环节点，通过侧环发送至写处理器对应的环节点，并下载至写处理器；写处理器根据清扫信号将对应的流从脏表移除。
可选地，读调度模块包括第一至第三等级的状态一致性，其中，第一等级的状态一致性包括：数据包的读操作在数据包之前的所有数据包的写操作之后；第二等级的状态一致性包括：在目标数据包所在流上，允许目标数据包之后的K个数据包的读操作在K个数据包的写操作之前，从第K+1个数据包开始，数据包的读操作在数据包之前的所有数据包的写操作之后；第三等级的状态一致性包括：数据包的读操作与写操作次序任意。
本申请第二方面实施例提供一种可编程交换芯片，包括：上述实施例任意一项实施例的基于预测执行的带状态可编程数据平面结构。
由此，本申请包括如下有益效果：
本申请实施例通过在流水线增加了一个简单的侧环，使每个流水线阶段都与其连接。在侧环上，数据流与流水线的方向相反，提供了一条快速的后向通信路径。读处理器读取带有状态的数据包所需要读取的状态，写处理器写回需要修改状态的数据包时可以跨阶段地写回状态，整个过程非常方便且更高效，且支持复杂的带状态功能，从而在整体上降低网内计算应用的开发成本、部署成本和维护成本。由此，解决了相关技术中的流水线技术无法支持较为复杂的带状态操作，且存在开发成本高等问题。
本申请附加的方面和优点将在下面的描述中部分给出，部分将从下面的描述中变得明显，或通过本申请的实践了解到。
附图说明
本申请上述的和/或附加的方面和优点从下面结合附图对实施例的描述中将变得明显和容易理解，其中：
图1为相关技术中Banzai的技术架构；
图2为相关技术中Banzai的原子操作电路图；
图3为相关技术中分布式可重配置匹配表的技术架构图；
图4为根据本申请实施例提供的基于预测执行的带状态可编程数据平面结构的方框图；
图5为根据本申请实施例提供的调度模块结构图；
图6为根据本申请实施例提供的有界陈旧一致性下的有限状态机示意图。
具体实施方式
下面详细描述本申请的实施例，实施例的示例在附图中示出，其中自始至终相同或类似的标号表示相同或类似的元件或具有相同或类似功能的元件。下面通过参考附图描述的实施例是示例性的，旨在用于解释本申请，而不能理解为对本申请的限制。
下面参考附图描述本申请实施例的基于预测执行的带状态可编程数据平面结构及芯片。针对上述背景技术中提到的问题，本申请提供了一种基于预测执行的带状态可编程数据平面结构，通过在流水线增加了一个简单的侧环，使每个流水线阶段都与其连接。在侧环上，数据流与流水线的方向相反，提供了一条快速的后向通信路径。读处理器读取带有状态的数据包所需要读取的状态，写处理器写回需要修改状态的数据包时，可以跨阶段地 写回状态，整个过程非常方便且更高效，且支持复杂的带状态功能，从而在整体上降低网内计算应用的开发成本、部署成本和维护成本。由此，解决了相关技术中的流水线技术无法支持较为复杂的带状态操作，且存在开发成本高等问题。
在介绍本申请的具体内容之前，对涉及到本申请的相关技术进项详细说明，包括以下几个：
1、相关技术一
如图1所示，Banzai是Intel推出的可编程交换机Tofino的技术原型，用户通过编写协议无关语言对Tofino搭载的协议和功能进行编程，并通过Intel提供的运行时软件对芯片上的流表和状态表进行操作。如图1所示，Banzai在数据包进入时通过可编程解析器解析出数据包的头部字段，并通过入口和出口的两个流水线对头部进行处理。这两条结构相同的流水线构成了Banzai的可编程数据包处理逻辑，每条流水线由一系列阶段，即匹配-操作表(MAT)组成，MAT是该原型的基本可编程单元。用户通过协议无关语言程序对MAT进行两方面的编程：在该阶段数据包需要查询什么流表，查询得到结果之后应执行怎样的处理逻辑。
在Banzai中每个阶段的处理逻辑使用一组并行的原子操作进行。原子操作使用的电路如图2所示，它可以执行一个“读取-加/减-写回”的功能。原子操作的操作对象可以是数据包头部的一个字段，或者状态表中的一个寄存器。但由于原子操作的简单性，只有简单的带状态功能(例如，计数器)可以经由原子操作实现。对于较为复杂的功能，确定下一个状态的逻辑可能一系列操作和表访问，无法通过原子操作实现。为了避免流水线出现瓶颈，该技术方案无法通过简单地扩展原子操作电路、增强原子操作功能来支持这些带状态功能。由于流水线的单向性，没有有效的机制将状态数据写回到早期阶段。唯一的办法是重新循环(即将数据包重新发送到流水线头部再次处理)，但该方法可能会导致同一个流的数据包在流水线中的次序被破坏，发生无法避免的读后写(WAR)冲突，造成状态一致性问题(即读取到过时状态)。
2、相关技术二
分布式可重配置匹配表(dRMT)采用多核多线程的运行至完成(RTC)处理器支持带状态功能。dRMT将交换芯片上的存储器和处理器解耦，处理器通过交换网络访问内存簇中的存储器资源，如图3所示。如果dRMT使用共享内存来存储状态表，则需要通过访问调度和加锁来处理状态一致性问题，导致一些处理器上出现无法预测的等待时间，从而破坏其基于整数线性规划的编译算法所预设的确定性延迟前提，这样的程序无法通过编译。如果每个处理器维护自己的状态表副本，则需要复杂的同步机 制，且消耗大量的额外内存。
3、相关技术三
FlowBlaze使用队列和调度机制以保证状态一致性。在FlowBlaze的每个阶段中，数据包会在一个独立的流上下文表中查询其所属的流是否正在当前阶段被处理；一旦一个数据包进入到带状态功能的处理流程中(在ESFM表上匹配并执行操作)，FlowBlaze就会阻塞后续同流的数据包，从而保证状态一致性。FlowBlaze的做法事实上假设了进入带状态功能的所有数据包都可能更改状态，这可能会造成流水线停顿从而会产生性能瓶颈。实际上，带状态功能可能仅应用于流的一个子集；在带状态处理下的不同流可能访问不同的状态；同一流的数据包可能不会更改状态。这使得连续的数据包不太可能读取和更新相同的状态。此外，额外的流上下文表和调度模块会使FlowBlaze占用较大的芯片面积；对于无法通过单个EFSM表完成的更复杂的带状态功能FlowBlaze也无法提供支持。
具体而言，图4为本申请实施例所提供的一种基于预测执行的带状态可编程数据平面结构的方框示意图。
如图4所示，该基于预测执行的带状态可编程数据平面结构包括：多个阶段处理器、侧环、多个环节点等。
其中，多个阶段处理器组成数据处理的流水线，每个阶段处理器处理一个流水线阶段；侧环上包括多个环节点，多个环节点和每个阶段处理器一一对应连接；多个阶段处理器中任意阶段处理器被配置为读处理器或写处理器，读处理器读取至少一个带状态的数据包所需要读取的状态，并预测带状态的数据包状态不变；写处理器写入带状态的数据包所需要写入的状态，识别被修改状态的需要重新提交的数据包，将需要重新提交的数据包上传至写处理器对应环节点，通过侧环发送至读处理器对应环节点，读处理器从对应环节点下载需要重新提交的数据包。
在本申请一个实施例中，阶段处理器包括可配置调度模块，其中，读处理器的可配置调度模块被配置为读调度模块，写处理器的可配置调度模块被配置为写调度模块，其他阶段处理器的可配置调度模块不激活。
可以理解的是，本申请实施例的提出支持跨阶段数据写回的低成本、高性能的数据平面体系结构：RAPID(Ring-Augmented Pipeline Dataplane，带环流水线数据平面)。RAPID的总体技术架构如图4所示。在RAPID中，本申请实施例可以在流水线增加了一个简单的侧环，并使每个流水线阶段都与其连接。作为一个具体的示例，在侧环上，数据流与流水线的方向可以相反由此提供了一条快速的后向通信路径，另外，数据流与流水线的方向也 可以相同，或者，采用双向的数据通路，即相邻节点之间数据可以双向流动；本领域技术人员可以具体选择或设置，不作具体限定。
其次，本申请实施例在RAPID中提出了“本地读-远程写”的行为抽象。对于复杂的带状态功能，其涉及流水线中的一系列阶段处理器。系列中的第一个处理器上存储流状态表，数据包在第一个处理器上读取状态，经过若干个处理器的处理后，在系列中的最后一个处理器上跨阶段地写回状态。跨阶段写回的控制信号、地址和数据被最后一个处理器上传到其对应的环节点中，通过侧环发送到第一个处理器对应的环节点，随后写入到第一个处理器存储的状态表里。
为了保证状态一致性，本申请实施例的每个阶段处理器上安装了一个可配置的调度模块，如图5所示。根据用户程序该模块可以被重构为读调度模块或写调度模块。在一个“本地读-远程写”的系列处理器中，读处理器上的调度模块被配置为读调度模块，写处理器上的调度模块被配置为写调度模块，中间的处理器上的调度模块则不激活。借助数据预取技术，调度模块被实现为旁路而不插入到流水线中，因此激活的调度模块也不会为流水线处理引入额外的延迟。当用户程序不需要跨阶段数据写回时，调度模块及其相连的侧环对流水线性能是无损的。
进一步地，本申请实施例的读调度模块与写调度模块均包括：存储在内容可寻址存储器中的脏表，用于在脏表中匹配的关键字是流的状态表索引，其中，写调度模块的脏表包含关键字的表，读调度模块的脏表包含关键字的表和对应数据；写调度模块将修改状态的数据包对应的流写入脏表，并通过侧环发送写回控制信号给读调度模块，读调度模块根据写回控制信号将修改状态的数据包对应的流写入脏表。
可以理解的是，本申请实施例的读调度模块与写调度模块都安装有一个小的内容可寻址存储器作为脏表，用于注册当前正在进行带状态处理的“脏”流。用于在脏表中匹配的关键字是流的状态表索引(例如，流ID的哈希值)。写调度模块中的脏表是一个仅包含关键字的表，而读调度模块中的脏表还包含相关数据。
进一步地，本申请实施例的读处理器还包括：重新提交缓冲区，用于保存需要重新提交的数据包；读调度模块还包括：数据包缓冲区，用于保存命中脏表的数据包，且每个流的数据包被链接在第一链表和第二链表中，第一链表用于存储流水线上新到来的数据包，第二链表用于存储需要重新提交的数据包。
在本申请实施例中，不在脏表中的流的数据包将被无阻塞地处理，被重新提交并阻塞的脏流的数据包仅在空闲的流水线周期中被机会性地调度。因此，被重新提交并阻塞的数据包需要一个重新提交缓冲区(RB)。在正常流量条件下，交换机流水线的负载较轻，留 有足够的空闲周期来处理缓冲的数据包。而从流水线新到达并在读调度模块中命中脏表的数据包被保存在读调度模块的数据包缓冲区(PB)中。
其中，RB和PB都是队列，一旦RB中的第一个数据包有机会进入流水线，它就会从RB移动到PB。在PB中每个流的数据包被链接在两个链表中，分别是存储流水线上新到来的数据包的第一链表(NL)和存储重新提交数据包的第二链表(RL)。两个链表的元数据在脏表里维护，而每个链表节点的链接指针由一个专用的寄存器组存储。
其次，为了保证状态一致性，一个流的数据包被带状态功能处理的次序应当和其到达交换机的次序相同。为了保持数据包次序，本申请实施例的读调度模块还包括保序检查模块，用于调度数据包缓冲区的数据包，并检测数据包缓冲区的数据包被调度时，需要被调度数据包所在流的需要重新提交的数据包是否已经全部到达重新提交缓冲区，并已经全部移动到数据包缓冲区的第二链表(RL)。
而读调度模块只有在以下条件下才能调度PB中的一个流的数据包：
条件(1)该流在本地读到远程写之间的流水线上没有数据包，即已经全部被重新发送到RB；
条件(2)该流在RB中的所有需要重新提交的数据包都已被移动到PB。
条件(2)只有在满足条件(1)后才能满足。条件(2)由在脏表中维护的重新提交数据包计数器保证。每次RB接收到一个需要重新提交的数据包时，相应的计数器就会增加；每次将一个需要重新提交的数据包从RB移动到PB时，相应的计数器就会减少。计数器值为0意味着满足条件(2)。当一个流同时满足(1)和(2)时，RL会被整体插入到NL之前以准备被调度，而新的RL重置为空链表。
进一步地，本申请实施例为条件(1)设计了两种不同的检查方案，以保证PB中的一个流的数据包被调度时，此前读取到陈旧状态的数据包都已经被重新提交给读处理器，具体如下：
方案1：基于计时器的解决方案，启动计时器，直到计时器超时，确定需要重新提交的数据包已经全部到达重新提交缓冲区。
具体而言，基于计时器的解决方案在读调度模块的脏表上维护一个计时器字段。当读调度模块接收到发回的远程写信号时，将修改状态的数据包对应的流写入到脏表，同时启动计时器。计时器是一个会随时间持续递减的倒计时，当计时器超时，说明已经过了足够长的时间让此前被发送出去的数据包全部回到RB。
因为数据平面的流水线是不阻塞的，所以一个数据包在流水线上从本地读到远程写之间的时间仅和流水线参数及二者之间的阶段数量相关，是一个编译器可以确定的常数(以 主时钟周期数为单位)。同时，一个数据包在没有被阻塞的情况下，从写处理器经由侧环重新提交到读处理器的时间，也是可以被编译器预先确定的。计时器启动时被初始化为这两个数值之和，因此如果侧环上没有发生阻塞，则每个周期计时器的值前进1个时刻，恰好可以保证此前发出的所有数据包都到达RB。
由此可见，基于计时器的解决方案通过设计侧环上的通信协议来保证只有在无阻塞的周期下计时器的值才会减少，从而让侧环发生阻塞的情况下，依然能够保证计时器超时时，此前发出的所有数据包都到达RB。而侧环可以传递三种信号：跨阶段状态写回、需要重新提交的数据包和清扫信号。在这三种信号所需要的控制标签、地址和数据总线之外，本申请实施例侧环上的总线额外加入了一个字段表示心跳地址。
其中，心跳地址是一个位图，每个位对应芯片上的一个阶段。写调度模块会持续向读调度模块发送心跳，因为每个流水线阶段的心跳只占用心跳地址字段的一个位，且心跳地址字段独立于总线中的其他字段，所以任何信号(总线闲置时视为一个空信号)都可以同时携带任意数量的心跳。在侧环上的每个环节点，来自侧环的信号会和当前阶段向环节点上传的信号发生竞争。除空信号会被直接丢弃外，其他信号被分别存储在两个方向上的队列缓冲区里，通过调度器进行总线仲裁。当携带心跳的信号在某个环节点被阻塞时，都会导致一个周期内读调度模块无法接收到心跳。读调度模块的计时器当且仅当接收到心跳时值前进1个时刻，由此达成准确的计时。而空闲的周期是否阻塞不影响计时准确性，空信号携带的心跳可以在其被丢弃时直接移交给另一个信号。
方案2：基于计数器的解决方案，本申请实施例的保序检查模块还用于在每个数据包读状态时将每个数据包的序列号写入计数器表；若需要重新提交的数据包的序列号与计数器表中的序列号相等，确定需要重新提交的数据包已经全部到达读处理器。
具体而言，基于计数器的解决方案在每个流水线阶段增加了少量的存储器。在读处理器上这些存储器用于存放计数器表，当读调度模块接收到发回的远程写信号时，将修改状态的数据包对应的流写入到脏表，计数器表为每个流维护一个序列号。使用一个元数据字段来存放每个数据包的序列号，在数据包进入流水线时写入并自增，而计数器表维护的序列号是通过的带状态数据包的最大序列号。被需要重新提交的数据包的序列号和本地计数器表中的序列号进行比较，如果二者相等，就说明此前发出的所有数据包都已经回到RB。
需要说明的是，以上两种方案的选择案对应两种不同的使用场景。基于计时器的解决方案只需要在脏表中增加额外的字段，芯片面积和功耗上有所优势；基于计数器的解决方案实现较为简单，并且不依赖对时间的精确计数，具有更好的可扩展性。
在本申请一个实施例中，读处理器还用于数据包缓冲区内的一个流的数据包开始被调 度，将清扫信号写入对应环节点，通过侧环发送至写处理器对应的环节点，并下载到写处理器；写处理器根据清扫信号将对应的流从脏表移除。
可以理解的是，当写调度模块发现某个数据包会导致其流状态发生变化(即远程写被触发)，该流就会在写调度模块的脏表中注册。当写回控制信号从侧环上到达目标处理器时，同时通知该处理器上的读调度模块在自己的脏表中注册该流。后续数据包在写调度模块命中脏表时说明预测错误，数据包会被上传到侧环上，重新发送给读处理器，并重新进入本地读-远程写的带状态处理流程。在读处理器这一侧，读调度模块的脏表中注册的流充当保护措施，防止新到达的该流的数据包进入有状态处理。在其驻留期间，该流的任何已经允许通过的数据包都会经历预测失败并被重新提交给读处理器的过程。当一个流的所有预测失败的数据包都已经被重新提交后，读调度模块发送一个清扫信号通知写调度模块从其脏表中移除该流。当所有积压的数据包都被发送后，该流将从读调度模块的本地脏表中移除。
因为脏表记录的是哈希值而不是流ID本身，所以存在哈希碰撞的可能。在哈希碰撞的情况下，一个实际上状态非脏的流可能被脏表命中，从而错误地阻塞和重新提交，造成一定程度的性能损失。在通常的流量和哈希函数下，哈希碰撞的概率非常低，因此哈希碰撞对总体数据包处理性能的影响几乎可以忽略不计。
在本申请一个实施例中，读调度模块包括第一至第三等级的状态一致性，其中，第一等级的状态一致性包括：数据包的读操作在数据包之前的所有数据包的写操作之后；第二等级的状态一致性包括：在目标数据包所在流上，允许目标数据包之后的K个数据包的读操作在K个数据包的写操作之前，从第K+1个数据包开始，数据包的读操作在数据包之前的所有数据包的写操作之后；第三等级的状态一致性包括：数据包的读操作与写操作次序任意。
其中，第一等级的状态一致性可以为强一致性，第三等级的状态一致性可以为弱一致性，第二等级的状态一致性可以为有界陈旧一致性，目标数据包可以为任意数据包，目标数据包所在流的状态服从有界陈旧一致性要求，预设数量可以根据实际情况进行指定，比如设置为K个。
具体而言，对所有应用程序实施强一致性可能不值得付出性能损失的代价，因此本申请实施例可以允许用户自行指定每个应用的状态一致性级别。强一致性是指：总是不允许数据包读取陈旧状态，即一个数据包的读操作必须后于此前所有数据包的写操作；弱一致性是指：允许数据包读取陈旧状态，即数据包的读写操作次序可以是任意的；有界陈旧一致性是指：允许最多K个数据包忽略陈旧状态的读取，当达到K个时必须同步到新的状态，其中，K为用户指定的常数。
可以理解的是，本申请实施例可以采用预测执行技术处理数据包。在默认的情况下，读处理器总是预测一个带状态的数据包不会修改它的状态。当一个数据包不修改状态时，它不会引起状态一致性问题，因此不需要阻塞后续数据包的处理，从而不会影响交换芯片的数据包处理性能。但当一个数据包需要修改状态时，说明之前的预测错误，此时不但需要跨阶段写回状态数据，还需要触发状态一致性的保证机制。
具体而言，对于强一致性，每个在写调度模块中命中脏表的数据包都应该被重新提交。对于弱一致性，当一个数据包导致状态改变时，只有新状态被写回，而不在脏表中注册该流，从而防止后续数据包的重新提交，适用于即使某些数据包读取了陈旧状态，状态最终也能收敛的场景(例如，一个流速限制器)。
对于有界陈旧一致性，使用一个有限状态机(FSM)来指导有界陈旧一致性下写调度模块的行为，如图6所示。在“正常”状态下，一个流不在写调度模块的脏表中，可以正常通过而不需要重新提交。当一个数据包导致状态改变时，FSM过渡到“即将过期”状态，并且一个递减计数器被初始化为K。在这个状态下，该流的最多K个数据包可以通过而无需重新提交。当计数器达到0时，FSM过渡到“已过期”状态，并且该流在脏表中注册，开始一轮严格的状态同步。只有来自读调度模块的清扫信号才能从写调度模块的脏表中移除该流，并将该流的状态恢复为“正常”状态。
在实际的实现过程中，本申请实施例可以以P4_16语言为基础，对其进行增强，通过引入了一个新的抽象结构——可变表(muTable)，它与P4中的table相当。与table相比，muTable可以由数据平面进行修改，因此它可以用来实现流状态表。用户编写的程序可以对muTable对象应用读和写原语，以定制带状态功能的处理逻辑。在编译应用程序时，编译器根据带状态功能的复杂性来决定它是否可以在单个阶段或多个阶段中实现。可以原子操作实现的简单带状态功能会被编译到单个阶段中，不启用跨阶段数据写回功能；原子操作不能实现的复杂带状态功能会被编译到多个阶段中，使用跨阶段数据写回实现。
如果有状态处理涉及修改某些数据(例如，减少IPv4协议中的TTL字段)，则数据包重新提交可能会导致数据被多次修改，发生写后读冲突，从而导致结果不正确。编译器使用“字段重命名”技术来解决这个问题。对于在本地读和远程写之间被修改的字段，编译器会在元数据中为该字段创建一个副本。在本地读和远程写之间读取该字段时，只从副本的位置读取，而不从可能被修改过一次的字段本身位置读取。
综上，本申请实现了一种低成本、高性能的数据平面结构，以支持复杂的带状态功能，可以将更多网内计算应用从服务器或中间盒卸载到可编程交换机上，从而降低网内计算的通信延迟，减少网络带宽的使用，减少网络系统对服务器或中间盒设备的需求，简化网内 计算应用的编程方法，从而在整体上降低网内计算应用的开发成本、部署成本和维护成本。
下面结合几个具体应用场景对本申请实施例的基于预测执行的带状态可编程数据平面结构进行详细说明：
1)应用场景1：
负载均衡器(LB)是云网络中不可或缺的功能。目前，越来越多的数据中心使用带状态LB来替代无状态LB。在带状态LB中，客户端数据包被发送到虚拟目标IP地址，LB为每个数据包分配一个物理IP地址。如果输入数据包在状态表中找到从其所在流到物理IP地址的现有映射，则使用该地址进行转发；否则，将应用某种策略或算法为数据包选择一个物理IP地址，并将从数据包流到物理IP地址的新映射写回到状态表。
为新到来的流确定物理服务器可能需要复杂的逻辑。相关技术中的做法是让搭载在服务器上的控制器软件做出决策，再将结果写回流状态表。多次转发和通信延迟会对交换机上的数据包缓冲区造成压力，从而使吞吐量降低。本申请实施例可以通过跨阶段写回，将带状态LB新确定物理IP的逻辑卸载到数据平面上，从而有效提高LB性能。
2)应用场景2：
DDoS攻击(如DNS泛洪、TCP SYN泛洪和放大攻击)一直是网络面临的重大挑战。传统的基于服务器或中间盒的解决方案成本高昂且吞吐量有限。本申请提供的跨阶段数据写回功能提供了一种高性能的DDoS检测方案，可以在交换机数据平面上实现：
首先，通过访问列表(例如，分别用于攻击流、正常流和可疑流的黑名单、白名单和灰名单)对传入数据包进行分类，然后由检测/分析模块根据列表搜索结果进行分析。该模块可以是一个草图(sketch)或一系列报头字段检查。如果白名单上的数据包被视为可疑，则决策模块会通过更新列表将相应的流从白名单移动到灰名单。其他的名单间移动与此类似。
3)应用场景3：
流量整形和策略控制在执行服务质量(QoS)策略并确保最佳带宽分配方面至关重要。在此过程中，数据包首先根据用户定义的报头字段进行分类，然后根据当前队列或链路状态，通过一些速率控制或调度算法进行评估。接下来，数据包被排队或丢弃，并更新队列状态(即，写回到评估模块)。在这种情况下，写回将从出口流水线到入口流水线。自PIFO的开创性工作以来，已经做出了许多努力来使数据包调度可编程化。然而，它们中的大多数都无法避免跨阶段数据写回。在当今基于流水线的芯片上，这些方案不得不使用数据包再循环或近似方法，这会影响调度性能或准确性。
4)应用场景4：
带状态防火墙可以使用有限状态机跟踪和监视活动的网络连接，并根据流上下文检测恶意流量。与无状态防火墙相比，它提供了更高的安全性和更强的攻击缓解能力。在带状态防火墙中，首先检查状态表以确定数据包是否属于现有连接。如果是，则更新连接状态和相关的超时值；否则，根据预定义的防火墙规则评估数据包，以确定是否应允许或拒绝连接，并应用匹配的规则。如果允许新连接，状态表将使用连接的信息(例如，流ID和连接状态)进行更新。由于不同模块之间复杂的状态转换和消息传递，如果要在纯数据平面流水线上实行该方案，同样需要本申请提供的跨阶段数据写回支持。
5)应用场景5：
Top-K大流检测可用于流量感知路由、流量工程和实时网络监控。由于Top-K大流检测使用的哈希表超出了单个流水线阶段的存储空间，所以为了在数据平面中使用Top-K检测，需要将表分布在阶段。数据包首先需要经过每个阶段以获取适当的位置，然后将数据写回到选定的阶段。在当前的流水线设备中，此类操作必须求助控制器或数据包再循环。本申请提供的跨阶段数据写回可以使该过程变得非常方便且更高效。
根据本申请实施例提出的基于预测执行的带状态可编程数据平面结构，通过在流水线增加了一个简单的侧环，使每个流水线阶段都与其连接。在侧环上，数据流与流水线的方向相反，提供了一条快速的后向通信路径。读处理器读取带有状态的数据包所需要读取的状态，写处理器写回需要修改状态的数据包时可以跨阶段地写回状态，整个过程非常方便且更高效，且支持复杂的带状态功能，从而在整体上降低网内计算应用的开发成本、部署成本和维护成本。由此，解决了相关技术中的流水线技术无法支持较为复杂的带状态操作，且存在开发成本高等问题。
此外，本申请实施例还提供一种可编程交换芯片，包括上述实施例的基于预测执行的带状态可编程数据平面结构。
在本说明书的描述中，参考术语“一个实施例”、“一些实施例”、“示例”、“具体示例”、或“一些示例”等的描述意指结合该实施例或示例描述的具体特征、结构、材料或者特点包含于本申请的至少一个实施例或示例中。在本说明书中，对上述术语的示意性表述不是必须针对的是相同的实施例或示例。而且，描述的具体特征、结构、材料或者特点可以在任一个或N个实施例或示例中以合适的方式结合。此外，在不相互矛盾的情况下，本领域的技术人员可以将本说明书中描述的不同实施例或示例以及不同实施例或示例的特征进行结合和组合。
此外，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以 明示或者隐含地包括至少一个该特征。在本申请的描述中，“N个”的含义是至少两个，例如两个，三个等，除非另有明确具体的限定。
尽管上面已经示出和描述了本申请的实施例，可以理解的是，上述实施例是示例性的，不能理解为对本申请的限制，本领域的普通技术人员在本申请的范围内可以对上述实施例进行变化、修改、替换和变型。

Claims (10)

  1. 一种基于预测执行的带状态可编程数据平面结构，其特征在于，包括：
    多个阶段处理器，其中，所述多个阶段处理器组成数据处理的流水线，每个阶段处理器处理一个流水线阶段，且所述每个阶段处理器允许被配置为读处理器或写处理器；
    侧环，其中，所述侧环上包括多个环节点，所述多个环节点和所述每个阶段处理器一一对应连接；
    所述多个阶段处理器中任意阶段处理器被配置为读处理器或写处理器，所述读处理器读取至少一个带状态的数据包所需要读取的状态，并预测带状态的数据包状态不变；所述写处理器写入带状态的数据包所需要写入的状态，识别被修改状态的需要重新提交的数据包，将所述需要重新提交的数据包上传至所述写处理器对应环节点，通过所述侧环发送至所述读处理器对应环节点，所述读处理器从对应环节点下载所述需要重新提交的数据包。
  2. 根据权利要求1所述的基于预测执行的带状态可编程数据平面结构，其特征在于，所述阶段处理器包括可配置调度模块，其中，所述读处理器的可配置调度模块被配置为读调度模块，所述写处理器的可配置调度模块被配置为写调度模块，其他阶段处理器的可配置调度模块不激活。
  3. 根据权利要求2所述的基于预测执行的带状态可编程数据平面结构，其特征在于，所述读调度模块与所述写调度模块均包括：
    存储在内容可寻址存储器中的脏表，在所述脏表中匹配的关键字是流的状态表索引，其中，所述写调度模块的脏表包含关键字的表，所述读调度模块的脏表包含关键字的表和对应数据；所述写调度模块将修改状态的数据包对应的流写入脏表，并通过所述侧环发送写回控制信号给所述读调度模块，所述读调度模块根据所述写回控制信号将所述修改状态的数据包对应的流写入脏表。
  4. 根据权利要求3所述的基于预测执行的带状态可编程数据平面结构，其特征在于，所述读处理器还包括：重新提交缓冲区，用于保存重新提交的数据包；所述读调度模块还包括：
    数据包缓冲区，用于保存命中所述脏表的数据包，且每个流的数据包被链接在第一链表和第二链表中，所述第一链表用于存储流水线上新到来的数据包，所述第二链表用于存储所述需要重新提交的数据包；
    保序检查模块，用于调度所述数据包缓冲区的数据包，并检测所述数据包缓冲区的数据包被调度时，需要被调度数据包所在流的需要重新提交的数据包是否已经全部到达所述 重新提交缓冲区，并已经全部移动到所述数据包缓冲区的第二链表。
  5. 根据权利要求4所述的基于预测执行的带状态可编程数据平面结构，其特征在于，所述保序检查模块还用于：
    启动计时器，直到所述计时器超时，确定所述需要重新提交的数据包已经全部到达所述重新提交缓冲区。
  6. 根据权利要求5所述的基于预测执行的带状态可编程数据平面结构，其特征在于，所述侧环的总线上设置有心跳地址字段，所述心跳地址字段与所述总线上其他字段独立，且每个流水线阶段占用所述心跳地址字段的一个位，将携带有心跳的信号写入所述心跳地址字段；
    所述计时器收到发自对应写处理器的所述携带有心跳的信号时计时前进1个时刻。
  7. 根据权利要求4所述的基于预测执行的带状态可编程数据平面结构，其特征在于，所述保序检查模块还用于：
    在每个数据包读状态时将所述每个数据包的序列号写入计数器表；
    若所述需要重新提交的数据包的序列号与所述计数器表中的序列号相等，确定所述需要重新提交的数据包已经全部到达所述重新提交缓冲区。
  8. 根据权利要求4所述的基于预测执行的带状态可编程数据平面结构，其特征在于，所述读处理器还用于在数据包缓冲区内的一个流的数据包开始被调度时，将清扫信号写入对应环节点，通过所述侧环发送至所述写处理器对应的环节点，并下载至所述写处理器；
    所述写处理器根据所述清扫信号将对应的流从所述脏表移除。
  9. 根据权利要求4所述的基于预测执行的带状态可编程数据平面结构，其特征在于，所述读调度模块包括第一至第三等级的状态一致性，其中，
    第一等级的状态一致性包括：数据包的读操作在所述数据包之前的所有数据包的写操作之后；
    第二等级的状态一致性包括：在目标数据包所在流上，允许所述目标数据包之后的K个数据包的读操作在所述K个数据包的写操作之前，从第K+1个数据包开始，数据包的读操作在所述数据包之前的所有数据包的写操作之后；
    第三等级的状态一致性包括：数据包的读操作与写操作次序任意。
  10. 一种可编程交换芯片，其特征在于，包括如权利要求1-9任意一项所述的基于预测执行的带状态可编程数据平面结构。
PCT/CN2024/091773 2024-03-27 2024-05-08 基于预测执行的带状态可编程数据平面结构及芯片 Pending WO2025200087A1 (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN202410360790.8 2024-03-27
CN202410360790.8A CN118259887B (zh) 2024-03-27 2024-03-27 基于预测执行的带状态可编程数据平面系统及芯片

Publications (1)

Publication Number Publication Date
WO2025200087A1 true WO2025200087A1 (zh) 2025-10-02

Family

ID=91604628

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2024/091773 Pending WO2025200087A1 (zh) 2024-03-27 2024-05-08 基于预测执行的带状态可编程数据平面结构及芯片

Country Status (2)

Country Link
CN (1) CN118259887B (zh)
WO (1) WO2025200087A1 (zh)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN119071255B (zh) * 2024-07-11 2025-06-24 清华大学 处理器可重构的可编程交换系统及可编程数据平面芯片
US12425356B1 (en) 2024-07-11 2025-09-23 Tsinghua University Reconfigurable processor-based programmable switching fabric and programmable data plane chip
CN119149202B (zh) * 2024-09-13 2025-05-13 宜安芯微电子(江苏)有限公司 一种asic芯片中多种hash算法并行运算控制优化方法

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5185878A (en) * 1988-01-20 1993-02-09 Advanced Micro Device, Inc. Programmable cache memory as well as system incorporating same and method of operating programmable cache memory
CN112230901A (zh) * 2020-10-29 2021-01-15 厦门市易联众易惠科技有限公司 一种基于异步io模型的网络编程框架系统及方法
CN114416150A (zh) * 2022-01-18 2022-04-29 清华大学 可编程数据平面在运行时的更新方法及装置

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3311181A1 (de) * 1982-03-29 1983-09-29 Racal-Data Communication, Inc., 33166 Miami, Fla. Daten-modem
US7546399B2 (en) * 2002-03-25 2009-06-09 Intel Corporation Store and forward device utilizing cache to store status information for active queues
US7809009B2 (en) * 2006-02-21 2010-10-05 Cisco Technology, Inc. Pipelined packet switching and queuing architecture
US8341280B2 (en) * 2008-12-30 2012-12-25 Ebay Inc. Request and response decoupling via pluggable transports in a service oriented pipeline architecture for a request response message exchange pattern
WO2023220483A2 (en) * 2023-09-15 2023-11-16 Futurwei Technologies, Inc. An architecture and algorithm for a programmable pipeline to support stateful packet processing

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5185878A (en) * 1988-01-20 1993-02-09 Advanced Micro Device, Inc. Programmable cache memory as well as system incorporating same and method of operating programmable cache memory
CN112230901A (zh) * 2020-10-29 2021-01-15 厦门市易联众易惠科技有限公司 一种基于异步io模型的网络编程框架系统及方法
CN114416150A (zh) * 2022-01-18 2022-04-29 清华大学 可编程数据平面在运行时的更新方法及装置

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
FENG YONG, CHEN ZHIKANG, ZHANG YINCHAO, ZHOU HANYI, SUN RUOYU, DONG WENKUO, LU PENG, LIU SHUXIN, ZHANG CHUWEN, SONG HAOYU, XU YANG: "Empower Programmable Pipeline for Advanced Stateful Packet Processing", PROCEEDINGS OF THE 21ST USENIX SYMPOSIUM ON NETWORKED SYSTEMS DESIGN AND IMPLEMENTATION, 16 April 2024 (2024-04-16) - 2024-04-18, XP093360273 *

Also Published As

Publication number Publication date
CN118259887A (zh) 2024-06-28
CN118259887B (zh) 2026-01-02

Similar Documents

Publication Publication Date Title
CN118259887B (zh) 基于预测执行的带状态可编程数据平面系统及芯片
JP4068166B2 (ja) 高性能多層スイッチ要素用探索エンジン・アーキテクチャ
US8515965B2 (en) Concurrent linked-list traversal for real-time hash processing in multi-core, multi-thread network processors
US7468979B2 (en) Layer-1 packet filtering
US9444737B2 (en) Packet data processor in a communications processor architecture
US8023528B2 (en) Method for resolving mutex contention in a network system
US20040246980A1 (en) Packet processing system
US8869156B2 (en) Speculative task reading in a traffic manager of a network processor
Bollapragada et al. Inside cisco ios software architecture
US7889734B1 (en) Method and apparatus for arbitrarily mapping functions to preassigned processing entities in a network system
US7443878B2 (en) System for scaling by parallelizing network workload
Caiazzi et al. Millions of low-latency state insertions on ASIC switches
Chen et al. Optimusprime: Unleash dataplane programmability through a transformable architecture
Pan et al. Nb-cache: Non-blocking in-network caching for high-performance content routers
US20230208776A1 (en) On chip router
Marts et al. MPI tag matching performance on ConnectX and ARM
Ma et al. Leveraging parallelism for multi-dimensional packetclassification on software routers
US11588747B2 (en) Systems and methods for providing lockless bimodal queues for selective packet capture
US7293158B2 (en) Systems and methods for implementing counters in a network processor with cost effective memory
Ruia et al. Flowcache: A cache-based approach for improving SDN scalability
EP1631906B1 (en) Maintaining entity order with gate managers
Wang et al. Advance virtual channel reservation
Chen et al. Phantom: Virtualizing Switch Register Resources for Accurate Sketch-based Network Measurement
Yuan et al. Network Functions With Dynamic State Management on Programmable Switches
JP2013179421A (ja) エントリの登録方法及び処理装置

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 24932757

Country of ref document: EP

Kind code of ref document: A1