WO2025199447A1

WO2025199447A1 - Variable output isolation cell

Info

Publication number: WO2025199447A1
Application number: PCT/US2025/020924
Authority: WO
Inventors: Nilay Shah; Raj Shekhar KASHYAP; Anuj Kumar Srivastava; Ankit Agrawal
Original assignee: Google LLC
Current assignee: Google LLC
Priority date: 2024-03-22
Filing date: 2025-03-21
Publication date: 2025-09-25
Anticipated expiration: 2026-09-22
Also published as: TW202541430A

Abstract

Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for keeping a signal at an active value during a power down state. In one aspect, a method comprises, during a power active state, outputting through a selection circuit an output signal, where the output signal has multiple states during the power active state. In response to a transition from the power active state to the power down state, the method further comprises sampling, by the selection circuit, the output signal to obtain a sampled output signal, storing the sampled output signal in a memory to obtain a stored output signal, and outputting, through the selection circuit, the stored output signal.

Description

VARIABLE OUTPUT ISOLATION CELL

BACKGROUND

[0001] Systems-on-Chip (SoCs) include integrated circuits with one or more modules or cells for performing operations. A system can provide power to one or more of the cells, where cells are divided into power domains to allow for power efficiency. For example, the system can power gate multiple cells by providing power to a first section of cells during a power active state and shutting off power to a second section of cells during a power down state, which allows a particular section of the circuit to function while decreasing power usage. [0002] During the power down state, the system can clamp (e.g., keep) the output signal of a cell at a value (e.g., 0 or 1). Typically these cells clamp to either a 0 or a 1 during the power down state. In this way, the system can determine whether the cell is clamped to a valid value to ensure the circuit is functioning correctly. However, in some cases, the system may need to clamp the output signal to a previous active value, rather than a fixed 0 or 1, to verify the functions of the cell. Clamp cells, however, are either clamp 1 cells that clamp to a value or 1 during power down, or clamp 0 cells that clamp to a value of 0, and do not clamp to a previous active value. Thus, there is a need for a system that can clamp signals to their active values of either 1 or 0 that are present prior to a power down state.

SUMMARY

[0003] The disclosed systems and methods keep a signal at an active value during a power down state in a manner that addresses the shortcomings described above.

[0004] In general, one innovative aspect of the subject matter described in this specification can be embodied in methods that include the actions of during a power active state: outputting through a selection circuit an output signal, wherein the output signal has a plurality of states during the power active state; in response to a transition from the power active state to a power down state: sampling, by the selection circuit, the output signal to obtain a sampled output signal, storing the sampled output signal in a memory to obtain a stored output signal; and outputting, through the selection circuit, the stored output signal. Other embodiments of this aspect include corresponding systems, apparatus, and computer programs, configured to perform the actions of the methods, encoded on computer storage devices.

[0005] Another innovative aspect of the subject matter described in this specification can be embodied in an apparatus that includes a power gating module that outputs an output signal; a power control module that outputs a plurality of control signals; a selection circuit that receives the output signal and the plurality of control signals and in response: during a power active state as indicated by the control signals: outputs the output signal, wherein the output signal has a plurality of states during the power active state; in response to a transition from the power active state to a power down state as indicated by the control signals: samples the output signal to obtain a sampled output signal, stores the sampled output signal in a memory’ to obtain a stored output signal and outputs the stored output signal.

[0006] In conventional systems, a System-on-Chip (SOC) can provide power to multiple cells of an integrated circuit. The cells can be divided into power domains, such that the system can control power to separate sections of cells for power efficiency by transitioning between a power down state and a power active state. In particular, the system can provide power to a section of cells during a power active state to perform operations, and the system can refrain from providing power (e.g., shut off power) to another section of cells during a power down state. During the power down state, the system can clamp an output signal of a cell to a clamp value, depending on the cell used, i.e., a value of 1 for a clamp 1 cell or a value of 0 for a clamp 0 cell.

[0007] However, the system is unable to change the clamp value of a clamp 1 or clamp 0 cell. In some cases, the system may need to clamp the previous active value (e.g., a l or a 0) of the cell in order to ensure correct operations of the rest of the circuit. By being unable to clamp to the previous active value of a particular cell, the system cannot ensure correct operations of the rest of the circuit, which can result in errors.

[0008] To address this problem, a selection circuit allows the system to keep (e.g., clamp) an active value of a cell that is present just prior to a power down state. The system can transition from the power active state to the power down state, and. in response to the transition, the system can use the selection circuit to select an output signal as the output of the cell based on the transition. In particular, the selection circuit can select betw een outputting a received signal (e.g., an output signal) from the power gating module or a sampled output signal of the output signal as the output.

[0009] Additionally, during the power active state, the selection circuit selects a received output signal as the output signal, such that the selection circuit does not interfere with the operations of the circuit when the system provides power to the cell, such that the selection circuit does not increase latency in the system. Therefore, the system allows for a cell to output an accurate active value during the power down state without the need for special cells and without disrupting the normal operations of the circuit. [0010] The details of one or more embodiments of the subject matter of this specification are set forth in the accompanying drawings and the description below. Other features, aspects, and advantages of the subject matter will become apparent from the description, the drawings, and the claims.

BRIEF DESCRIPTION OF THE DRAWINGS

[0011] FIG. 1 is a diagram of an example isolation cell that includes a selection circuit and a power gating module.

[0012] FIG. 2 is a timing diagram used in generating control signals for the selection circuit.

[0013] FIG. 3 is a flow diagram of an example process for keeping a signal at a sampled value during a power down state.

[0014] FIG. 4 is a diagram of an example circuit for generating an enable signal for the output multiplexor.

DETAILED DESCRIPTION

[0015] This written description describes systems and methods to keep a signal at an active value during a power down state for one or more cells in a System-On-Chip (SOC). For example, a SOC may include multiple cells, and each cell can provide an output signal that was present just prior to a power down operation output by the power gating module.

[0016] During the transition between the power active state and the power down state, a selection circuit of the cell can select an output signal as the output of the cell based on the transition. In particular, the selection circuit can select between outputting a received signal (e.g., a received output signal) from the power gating module or a sampled output signal of the received output signal as the output. In this way, the cell can output an accurate active value during the power down state.

[0017] These features and additional features are described in more detail below.

[0018] FIG. 1 is a diagram of an isolation cell 100 that includes a power control module 101, a power gating module 102, and a selection circuit 104. As depicted in Fig. 1, the selection circuit 104 comprises multiplexors and a sample flop, but other hardware configurations can be used to achieve the same functionality. The flop may alternatively be referred to as a memory.

[0019] The power control module 101 controls power to the power gating module 102, and also provides control signals to the selection circuit. As will be described below, the power control module 101 requests the power gating module 102, through request and state signals, to go into the power down state. The power gating module 102 accepts the power down when it is ready to do so, and the power control module 101, in turn, generates additional control signals to control the selection circuit.

[0020] The power gating module 102 is configured provide an output signal 112 when in a power active state. The output signal 112, can, for example, be a data signal. It will be understood that the output signal 112 is described as being provided by the power gating module 102. It will be appreciated, however, that other circuit components may generate the output signal 112. For example, the power gating module 102 may control a power gating status of one or more circuit components which may drive the output signal 112.

[0021] To control the example selection circuit 104, the power control module 101 is configured to drive one or more multiplexors of the selection circuit 104. The selection circuit 104 includes an output multiplexor 106 and a sample multiplexor 108 that are each configured to select from two input signals based on a received control signal. Additionally, the selection circuit includes a sample flop 110 that is configured to store a value of a signal output by the sample multiplexor 108.

[0022] The power gating module 102 is powered off during the power down state. However, when in the power active state, the power gating module 102 provides the output signal 112 to the selection circuit 104.

|0023| In operation, based on an enable signal 118, the selection circuit 104 selects the output signal 112 or an output of a sample flop 1 10 (referred to as the stored output signal 120) as the output signal 114, where the output of the sample flop 110 is the stored active value of the output signal 112 just prior to the power down transition. The enable signal 118 causes the output multiplexor 106 to output either the output signal 112 or stored output signal 120. The system switches the enable signal 118 on or off (e.g., 0 or 1) based on whether the systems is in a power active state or a power down state.

[0024] During the pow er active state, the enable signal 118 is such that the output multiplex selects the output signal 112 and simply passes the output signal 112 as the output of the output multiplexor 106, i.e., output multiplexor signal 114. During the power down state, the enable signal 118 is such that the output multiplexor 106 selects the output of the sample flop 110 as the output multiplexor signal 114. In this way, during the powder down state, the cell can clamp (e.g., keep) the value of the output signal 112 that was present at the power down transition. This value can be either 0 or 1. [0025] The system provides the output signal 112 to the output multiplexor 106 and the sample multiplexor 108 of the selection circuit 104. The sample multiplexor 108 is configured to receive the output signal 1 12 and a stored signal 120, where the stored signal 120 indicates a most recent active value of the input signal 112 stored in the sample flop 110. The sample multiplexor 108 is also configured to select either the output signal 112 or the stored signal 120 as the input to the sample flop 110, as depicted in Fig. 1.

[0026] The sample flop 110 is configured to store a most recent active value of the output signal 112, such that the sample flop 110 ‘'follows” the output signal 112 when receiving the output signal as input by storing the most recent value based on the received signal from the sample multiplexor 108. In particular, the sample multiplexor 108, in response to the transition signal 116-A being in a first state (e.g., the power down state), selects the output signal 112 to obtain a sampled output signal, and the sample multiplexor 108 provides the sampled signal to the sample flop 110 as input. The sample flop 110 performs the function of a memory' and stores the sampled signal to obtain a stored output signal 120. The sample flop 110 provides the stored signal 120 to the output multiplexor 106.

[0027] During the power active state, the output multiplexor 106 receives the output signal 112 and the stored output signal 120, and the output multiplexor 106 selects between the output signal 112 as the output multiplexor signal. In this way, the selection circuit 104 does not affect the normal operations of the cell during the power active state, and the sample multiplexor 108 and the sample flop 110 are following the most recent active value of the input signal 1 12.

[0028] When transitioning to the power down state, the power gating module 102 will power down; the system transitions from the power active state to the power state. In particular, the system (e.g., by the power control module 101 can provide a transition signal 116-A to the selection circuit 104. The transition signal 1 16-A is a combination of control signals, as described in further detail below with reference to FIG. 2. The transition signal 116-A can indicate the transition from the power active state to the power down state.

[0001] During the transition from the power active state to the power down state, the power control module 101 drives the enable signal 118 to select the stored output signal 120 (e.g., the stored most recent active value from the sample flop 110). In particular, the system can toggle the enable signal 118 from 0 to 1 , where 1 indicates that the output multiplexor 106 selects the stored output signal 120.

[0029] In response to the enable signal 118, the output multiplexor 106, which receives the output signal 112 and the stored signal 120, selects the stored output signal 120 as the output. instead of the output signal 112. The selection circuit 104 selects the stored output signal 120 prior to (e.g.. just before) the cell enters the power down state.

[0030] During the power down state, the selection circuit 104 clamps (e.g., keeps) the stored signal 120, such that the selection circuit 104 outputs the most recent active value of the output signal 112. The transition signal 116 is driven such that the sample multiplexor 108 selects the output stored output signal 120 as output, and thus the sample flop 110 holds the last most recent active value prior to entering the power down state.

[0031] At a later time, the power gating module 102 can then transition from the power down state to the power active state. When this happens, the transition signal 116 is changed by the power control module 101 to indicate the transition to the power active state, and the enable signal 118 is deasserted. In response to deasserting the enable signal 118. the output multiplexor 106 selects the output signal 112 from the power gating module 102 as the output of the cell.

[0032] Therefore, by implementing the selection circuit 104, the system can output a most recent active value of the output signal 112 from the cell during the power down state. Additionally, during the pow er active state, the selection circuit 104 passes the value of the output signal 112 as the output of the cell.

[0033] FIG. 2 is a timing diagram of the selection circuit. For example, the selection circuit can be the selection circuit of FIG. 1, e.g., the selection circuit 104. The power gating module 102 generates the accept signal 206. while the remaining signals are generated by the power control module 101.

[0034] The timing diagram 200 depicts multiple signals corresponding to multiple clock cycles (e.g., time). The multiple signals include the output signal 112, the output signal 114, transition signals 116 (comprising transition signals 116-A and 116-B), the enable signal 118, and the stored signal 120. The transition signals are a combination of control signals from the system, where the control signals include a request signal 202, state signals 204 (ACTIVE and PG), an accept signal 206. The timing diagram 200 also includes the pow er signal 208. [0035] During clock cycles 1 and 2, the output signal 112 is output by the selection circuit 104. At clock cycle 3. the system initiates a transition from the power active state to the power down state, as indicated by the request signal 202 going high. The request signal 202 indicates a request to transition from the current state to another state, e.g., powder up to power down, or pow er down to power up. [0036] At clock cycle 4, the system sets the transition signal 116-A to high, which indicates a request to transition from the current state to another state (e.g.. the power active state to the power down state).

[0037] The state signal 204 indicates the transition state (e.g., power active state ACTIVE or power down state PG), and the accept signal 206 indicates that the power gating module has accepted the transition. That is, the accept signal 206 is responsive to a request signal 202. The system sends the request signal 202 prior to sending the accept signal 206. The system can send the transition signal 116-A at the same time as the accept signal 206 (e g., at clock cycle 3).

[0038] The transition signal 116-A and 116-B are derived from the request signal 202, the state signal 204, and the accept signal 206, i.e., transition signal 116-A = (request signal 202 & accept signal 202 & state signal = PG), and transition signal 116-B = (request signal 202 & accept signal 202 & state signal = ACTIVE). The transition signal 116-A is a transition signal to transition to the inactive state, and provided to the sample mux 108. Conversely , the transition signal 116-B is a transition signal to transition to the active state, and is used to generate the enable signal 118, as will be describe with reference to Fig. 4 below.

[0039] The transition signal 116-A going high at clock cycle 4 causes the sample multiplexor 108 to select the output signal 112 as output, w hich, in turn, stores the value of the output signal 112 (in this case, the value of 1) in the flop 110 at clock cycle 5.

|0040| Based on the transition signal 116-A, the system toggles the enable signal 118. For example, as shown in the timing diagram 200, the enable signal 1 18 is off (e.g., at 0) from clock cycle 1 to clock cycle 4, and the system toggles on the enable signal 118 at the end of clock cycle 4. Based on receiving the enable signal 118, the selection circuit 104 clamps the value of the output signal 112 at clock cycle 4 by selecting the stored output signal 120 that is stored just prior to entering the power down state at clock cycle 5. Thus, the selection circuit 104 outputs the stored output signal 120 as the output signal 114. In particular, the flop 110 provides the stored output signal 120 to the output multiplexor 106, w hich has selected the stored output signal 120 as output. The system can then transition from the power down state to the power active state.

[0041] The transition signal 116-B is a transition signal to transition to the active state provided to the output mux 106 as part of the enable signal 118, as described in further detail below⁷ with reference to FIG. 4. The transition signal 116-B is based on the combination of the request signal 202, the state signal 204, and the accept signal 206. That is, to transition to the active state the request signal 202 may again be generated at clock cycle 13, with an accept signal 206 being generated at clock cycle 14. In this case, the state signal 204 indicates the power active state at clock cycle 13. Prior to transition from the power down state to the power active state, however, the output signal 112 resumes, e.g., at clock cycle 1 1 the output signal is again generated.

[0042] Based on receiving the transition signal 116-B, the system can toggle the enable signal 118. The enable signal 118 can be generated in a variety of ways according to the logical flow of FIG. 2. as described in further detail below with reference to FIG. 4. For example, as shown in the timing diagram 200, the enable signal 118 is on from clock cycle 4 to clock cycle 14, and the system can toggle off the enable signal 118 at clock cycle 14. Based on toggling off the enable signal 118, the selection circuit refrains from clamping the value of the output signal 112 stored at clock cycle 5 (e.g., the stored signal 120), and instead outputs the output signal 1 12 as the output multiplexor signal 114.

[0043] FIG. 3 is a flow diagram of an example process 300 for keeping a signal at active value during a power down state.

[0044] In general, the process 300 can transition back and forth between a power active state and a power dow n state. Although described as a loop, the process 300 need not transition from the power down to the power up state. The selection circuit can select an output signal as the output of a cell based on the transition. The selection circuit includes an output multiplexor (e.g., multiplexor), a sampling multiplexor, and a flop.

|0045| During the pow er active state, the process 300 outputs an output signal 114 through a selection circuit (302). For example, the output signal 1 12 is output by the power gating module 102 and received by the output multiplexor 106. The output signal 112 can have multiple states (e.g., 0 and 1) during the power active state. The output signal 114 output by the selection circuit can be the received output signal 112 from the power gating module 102. [0046] The process 300 can then transition from the power active state to a power down state (304).

[0047] During the transition to the power down state, the process 300 samples the output signal 112 to obtain a sampled output signal (306). The selection circuit obtains the sampled output signal 120 by selecting the output signal 112 as the output of the sampling multiplexor 108. In particular, the selection circuit samples the output signal 112 to obtain the sampled output signal 120 before going to the pow er down state.

[0048] The process 300 stores the sampled output signal 120 in a memory to obtain a stored output signal (308). The selection circuit stores the sampled output signal 120 by selecting the output of the flop 110 as the output of the sampling multiplexor 108. [0049] The process 300 outputs the stored output signal 120 through the selection circuit during the power down state (310). In particular, the output multiplexor 106 receives the output signal 112 and the sampled output signal 120 as input. In response to transitioning from the power active state to the power down state, the selection circuit can select the stored output signal 120 as the output of the output multiplexor 108, and accordingly, during the power down state, the selection circuit can output the stored output signal 120.

[0050] The process 300 can then transition from the power down state to a power active state (312). In response to transitioning from the power down state to the power active state, the selection circuit can output the output signal 112 through the output multiplexor 108.

[0051] FIG. 4 is a diagram of an example circuit for generating an enable signal 118 for the output multiplexor 106. FIG. 4 can be part of the power control module 101, for example. [0052] The circuit 400 generates the enable signal 118 based on the signals 116-A and 1 16- B. The circuit 400 comprises a multiplexor 402, which has four selection channels and an enable flop 404. The multiplexor 402 has a first channel that is the output of the enable flop 404, a second channel with an input of 1, and a third channel with an input of 0. The fourth channel is unused, as indicated by the “x” value. This is because, according to Fig. 2, both signals 116-A and 116-B are never high at the same time. The truth table below provides the state of the signal 118.

Table 1

[0053] Recall that transition signal 116-A = (request signal 202 & accept signal 202 & state signal = PG), and transition signal 116-B = (request signal 202 & accept signal 202 & state signal = ACTIVE). Thus, to transition to the power down state, the state PG 204 and request 202 signal go high, and the PG module will, in response, cause the accept signal 206 to go high. Accordingly, signal 116-A goes high, and the output of the mux 402 is 1. Thus, the enable flop 404 output (Enable signal 118) then goes to 1. When the system completes the transitions to the power down state, both 116-A and 116-B go low, and the output 1 is stored in the enable flop 404, as indicated by the signal 118 being 1. [0054] To transition to the power active state, the state ACTIVE 204 and request 202 signal go high, and the PG module, upon power up, causes the accept signal 206 to go high. Accordingly, mux 402 outputs the value of 0. Thereafter, and transitioning to the active state, both 116- A and 116-B go low, and the output 0 is stored in the enable flop 404, as indicated by the signal 118 being 0.

[0055] This specification uses the term "‘configured” in connection with systems and computer program components. For a system of one or more computers to be configured to perform particular operations or actions means that the system has installed on it software, firmware, hardware, or a combination of them that in operation cause the system to perform the operations or actions. For one or more computer programs to be configured to perform particular operations or actions means that the one or more programs include instructions that, when executed by data processing apparatus, cause the apparatus to perform the operations or actions. The term “flop” is used in this specification to describe a device operable to store an input value, operating as a memory⁷. However, it will be appreciated that other hardware configurations can be used to achieve the same functionality.

[0056] Embodiments of the subject matter and the functional operations described in this specification can be implemented in digital electronic circuitry, in tangibly-embodied computer software or firmware, in computer hardware, including the structures disclosed in this specification and their structural equivalents, or in combinations of one or more of them. Embodiments of the subject matter described in this specification can be implemented as one or more computer programs, i.e., one or more modules of computer program instructions encoded on a tangible storage medium, which may be non-transitory. for execution by, or to control the operation of, data processing apparatus. The computer storage medium can be a machine-readable storage device, a machine-readable storage substrate, a random or serial access memory⁷ device, or a combination of one or more of them. Alternatively or in addition, the program instructions can be encoded on an artificially-generated propagated signal, e.g., a machine-generated electrical, optical, or electromagnetic signal, that is generated to encode information for transmission to suitable receiver apparatus for execution by a data processing apparatus.

[0057] The term “data processing apparatus” refers to data processing hardware and encompasses all kinds of apparatus, devices, and machines for processing data, including by way of example a programmable processor, a computer, or multiple processors or computers. The apparatus can also be. or further include, special purpose logic circuitry, e.g., an FPGA (field programmable gate array) or an ASIC (application-specific integrated circuit). The apparatus can optionally include, in addition to hardware, code that creates an execution environment for computer programs, e.g., code that constitutes processor firmware, a protocol stack, a database management system, an operating system, or a combination of one or more of them.

[0058] A computer program, which may also be referred to or described as a program, software, a software application, an app. a module, a software module, a script, or code, can be written in any form of programming language, including compiled or interpreted languages, or declarative or procedural languages; and it can be deployed in any form, including as a stand-alone program or as a module, component, subroutine, or other unit suitable for use in a computing environment. A program may, but need not, correspond to a file in a file system. A program can be stored in a portion of a file that holds other programs or data, e.g., one or more scripts stored in a markup language document, in a single file dedicated to the program in question, or in multiple coordinated files, e.g., files that store one or more modules, sub-programs, or portions of code. A computer program can be deployed to be executed on one computer or on multiple computers that are located at one site or distributed across multiple sites and interconnected by a data communication network.

[0059] The processes and logic flows described in this specification can be performed by one or more programmable computers executing one or more computer programs to perform functions by operating on input data and generating output. The processes and logic flows can also be performed by special purpose logic circuitry, e.g.. an FPGA or an ASIC, or by a combination of special purpose logic circuitry and one or more programmed computers.

[0060] Computer-readable media suitable for storing computer program instructions and data include all forms of non-volatile memory', media and memory devices, including by way of example semiconductor memory devices, e.g., EPROM, EEPROM, and flash memory devices; magnetic disks, e.g., internal hard disks or removable disks; magneto-optical disks; and CD-ROM and DVD-ROM disks.

[0061] Embodiments of the subject matter described in this specification can be implemented in a computing system that includes a back-end component, e.g., as a data server, or that includes a middleware component, e.g.. an application server, or that includes a front-end component, e.g., a client computer having a graphical user interface, a web browser, or an app through which a user can interact with an implementation of the subject matter described in this specification, or any combination of one or more such back-end, middleware, or front-end components. The components of the system can be interconnected by any form or medium of digital data communication, e.g., a communication network. Examples of communication networks include a local area network (LAN) and a wide area netw ork (WAN), e.g.. the Internet.

[0062] The computing system can include clients and servers. A client and server are generally remote from each other and typically interact through a communication netw ork. The relationship of client and server arises by virtue of computer programs running on the respective computers and having a client-server relationship to each other. In some embodiments, a server transmits data, e.g., an HTML page, to a user device, e.g.. for purposes of displaying data to and receiving user input from a user interacting with the device, which acts as a client. Data generated at the user device, e.g., a result of the user interaction, can be received at the server from the device.

[0063] While this specification contains many specific implementation details, these should not be construed as limitations on the scope of any invention or on the scope of what may be claimed, but rather as descriptions of features that may be specific to particular embodiments of particular inventions. Certain features that are described in this specification in the context of separate embodiments can also be implemented in combination in a single embodiment. Conversely, vanous features that are described in the context of a single embodiment can also be implemented in multiple embodiments separately or in any suitable subcombination. Moreover, although features may be described above as acting in certain combinations and even initially be claimed as such, one or more features from a claimed combination can in some cases be excised from the combination, and the claimed combination may be directed to a subcombination or variation of a subcombination.

[0064] Similarly, while operations are depicted in the drawings and recited in the claims in a particular order, this should not be understood as requiring that such operations be performed in the particular order shown or in sequential order, or that all illustrated operations be performed, to achieve desirable results. In certain circumstances, multitasking and parallel processing may be advantageous. Moreover, the separation of various system modules and components in the embodiments described above should not be understood as requiring such separation in all embodiments, and it should be understood that the described program components and systems can generally be integrated together in a single software product or packaged into multiple software products.

[0065] Particular embodiments of the subject matter have been described. Other embodiments are within the scope of the following claims. For example, the actions recited in the claims can be performed in a different order and still achieve desirable results. As one example, the processes depicted in the accompanying figures do not necessarily require the particular order shown, or sequential order, to achieve desirable results. In some cases, multitasking and parallel processing may be advantageous.

[0066] What is claimed is:

Claims

1. A computer-implemented method comprising: during a power active state: outputting through a selection circuit an output signal, wherein the output signal has a plurality of states during the power active state; in response to a transition from the power active state to a power down state: sampling, by the selection circuit, the output signal to obtain a sampled output signal; storing the sampled output signal in a memory to obtain a stored output signal; and outputting, through the selection circuit, the stored output signal.

2. The computer-implemented method of claim 1, wherein the selection circuit comprises an output multiplexor that receives, as input, the output signal and the sampled output signal, and wherein: outputting through the selection circuit the output signal during the power active state comprises selecting the output signal as an output of the output multiplexor; and outputting, through the selection circuit, the stored output signal in response to transition from the power active state to a power down state comprises selecting the stored output signal as the output of the output multiplexor.

3. The computer-implemented method of claim 2, wherein the selection circuit further comprises an sampling multiplexor and a flop, wherein the sampling multiplexor receives, as input, the output signal and an output of the flop, and the flop receives as input the output of the sampling multiplexor, and wherein: sampling, by the selection circuit, the output signal to obtain a sampled output signal comprises selecting, as output of the sampling multiplexor, the output signal; and storing the sampled output signal in the memory to obtain a stored output signal comprises selecting, as output of the sampling multiplexor, the output of the flop.

4. The computer-implemented method of claim 3. wherein sampling, by the selection circuit, the output signal to obtain a sampled output signal comprises sampling, by the selection circuit, the output signal to obtain the sampled output signal before going to the power down state.

5. The computer-implemented method of claim 2, further comprising: during the power down state, outputting, through the output multiplexor, the stored output signal; in response to a transition from the power down state to the power active state, outputting, through the output multiplexor, the output signal.

6. The computer-implemented method of claim 5, wherein the selection circuit further comprises a sampling multiplexor and a flop, wherein the sampling multiplexor receives, as input, the output signal and an output of the flop, and the flop receives as input the output of the sampling multiplexor, and wherein: sampling, by the selection circuit, the output signal to obtain a sampled output signal comprises selecting, as output of the sampling multiplexor, the output signal; and storing the sampled output signal in the memory to obtain a stored output signal comprises selecting, as output of the sampling multiplexor, the output of the flop.

7. The computer-implemented method of claim 6, wherein sampling, by the selection circuit, the output signal to obtain a sampled output signal comprises sampling, by the selection circuit, the output signal to obtain the sampled output signal before going to the power active state.

8. An apparatus, comprising: a power gating module that outputs an output signal; a power control module that outputs a plurality of control signals; a selection circuit that receives the output signal and the plurality of control signals and in response: during a power active state as indicated by the control signals: outputs the output signal, w herein the output signal has a plurality of states during the power active state; in response to a transition from the power active state to a pow er down state as indicated by the control signals: samples the output signal to obtain a sampled output signal; stores the sampled output signal in a memory' to obtain a stored output signal; and outputs the stored output signal.

9. The apparatus of claim 8, wherein the selection circuit comprises an output multiplexor that receives, as input, the output signal and the sampled output signal, and wherein: during the power active state the output multiplexor outputs the output signal: and in response to transition from the power active state to a power down state, the output multiplexor outputs the stored output signal.

10. The apparatus of claim 9, wherein the selection circuit further comprises an sampling multiplexor and a flop, wherein the sampling multiplexor receives, as input, the output signal and an output of the flop, and the flop receives as input the output of the sampling multiplexor, and wherein: samples the output signal to obtain a sampled output signal comprises selecting, as output of the sampling multiplexor, the output signal; and storing the sampled output signal in the memory' to obtain a stored output signal comprises selecting, as output of the sampling multiplexor, the output of the flop.

1 1 . The apparatus of claim 10, wherein selecting, as output of the sampling multiplexor, the output signal occurs before going to the power down state.

12. The apparatus of claim 8, wherein the selection circuit, further in response to the plurality of control signals: during the power down state, outputs, through the output multiplexor, the stored output signal; in response to a transition from the power down state to the power active state, outputs, through the output multiplexor, the output signal.

13. The apparatus of claim 12, wherein the selection circuit comprises an output multiplexor that receives, as input, the output signal and the sampled output signal, and wherein: during the power active state the output multiplexor outputs the output signal: and in response to transition from the power active state to a power down state, the output multiplexor outputs the stored output signal.

14. The apparatus of claim 13, wherein the selection circuit further comprises an sampling multiplexor and a flop, wherein the sampling multiplexor receives, as input, the output signal and an output of the flop, and the flop receives as input the output of the sampling multiplexor, and wherein: samples the output signal to obtain a sampled output signal comprises selecting, as output of the sampling multiplexor, the output signal; and storing the sampled output signal in the memory to obtain a stored output signal comprises selecting, as output of the sampling multiplexor, the output of the flop.

15. The apparatus of claim 14, wherein selecting, as output of the sampling multiplexor, the output signal occurs before going to the power active state.