WO2025196833A1

WO2025196833A1 - High-resolution analog computing

Info

Publication number: WO2025196833A1
Application number: PCT/IN2025/050404
Authority: WO
Inventors: Deepak Sharma; Navakanta Bhat; Sreebrata GOSWAMI; Sreetosh GOSWAMI
Original assignee: Indian Institute of Science IISC
Current assignee: Indian Institute of Science IISC
Priority date: 2024-03-21
Filing date: 2025-03-20
Publication date: 2025-09-25
Anticipated expiration: 2026-09-21

Abstract

HIGH-RESOLUTION ANALOG COMPUTING Approaches for analog computing are disclosed. In one example, there is described an analog computing system. The analog computing 5 system comprises a crossbar array and a processor. The crossbar array comprises a bottom electrode and a top electrode, with an active material interposed between them. In one example, active material is selected from a group of compounds that comprises, but is not limited to, Ru-complex of azo-aromatic ligands, coordinated azo-aromatic ligands, un-coordinated 10 azo-aromatic ligands, or combinations thereof. The bottom electrode, the top electrode, and the active material are interposed between the top electrode and the bottom electrode in such a way that each junction acts as a memristor. Each memristor in the array is formed at the intersection (junction) of a word line and a bit line, creating a grid-like structure that 15 allows for precise control and addressing of individual memristors.

Description

HIGH-RESOLUTION ANALOG COMPUTING

FIELD OF INVENTION

[0001] The present disclosure generally relates to analog computing, and in particular, to implementation of molecular memristors for high- accuracy analog computing.

BACKGROUND

[0002] An analog computing system is a computing architecture that processes data by manipulating continuous electrical signals, as opposed to discrete binary data used in a digital computing system. Analog computing systems are designed to handle tasks involving continuous information, perform calculations and data processing operations using physical phenomena that vary continuously, potentially offering advantages in speed, energy efficiency, and parallel processing for certain types of computations. In recent decades, analog computing systems have gained renewed interest due to their potential for efficient processing of continuous data, particularly in applications like artificial intelligence (Al) and signal processing.

[0003] In the modern era, analog computing systems are being integrated with Al in several ways, for example, by way of neuromorphic computing, analog machine learning accelerators, analog Al chips, and more. Neuromorphic computing aims to mimic a neural architecture of the brain using analog circuits to represent neurons and synapses. On the other hand, analog machine learning accelerators are used to accelerate machine learning algorithms by performing operations like matrix multiplications and convolutions more efficiently. Such an integration of Al in analog computing systems is particularly beneficial in edge Al, robotics, and healthcare, where real-time processing and low power consumption is critical.

BRIEF DESCRIPTION OF FIGURES [0004] Systems and/or methods, in accordance with examples of the present subject matter are now described and with reference to the accompanying figures, in which:

[0005] FIG. 1 illustrates a schematic of an analog computing system for high resolution analog computing, as per examples of the present subject matter;

[0006] FIG. 2 illustrates a plurality of word lines and bit lines of a crossbar array of an analog computing system, as per examples of the present subject matter;

[0007] FIG. 3A illustrates a graph of the conductance changes in a memristor, spanning from lowest to highest conductance values, as a function of the number of writing pulses applied, as per examples of the present subject matter;

[0008] FIG. 3B illustrates a graph depicting the conductance measurements of a memristor between two pairs of successive states, labeled as level-2, level-3 and level 10k2, level 10k3, at various levels of data points and counts, as per examples of the present subject matter;

[0009] FIG. 3C illustrates a graph showing the probability distribution of conductance states in a memristor, as per examples of the present subject matter;

[0010] FIG. 3D illustrates a graph of the statistical distribution of conductance levels in a memristor, as per examples of the present subject matter;

[0011] FIG. 3E illustrates a graph showing the relationship between written conductance levels and the corresponding read conductance values in a memristor, as per examples of the present subject matter;

[0012] FIG. 4A illustrates a graph depicting the endurance of a memristor, over a range of reading and writing cycles, as per examples of the present subject matter;

[0013] FIG. 4B illustrates a graph showing the conductance levels of a memristor, over time, as per examples of the present subject matter; [0014] FIG. 4C illustrates a graph depicting programming of conductance levels in a memristor, using two different methods, as per examples of the present subject matter;

[0015] FIG. 4D illustrates a three-dimensional graph demonstrating the relationship between pulse voltage amplitude, pulse width, and the resulting conductance difference in a memristor, as per examples of the present subject matter;

[0016] FIG. 4E illustrates a graph showing relationship between the transition time between different subsequent pairs of conductance levels in a memristor, and the inverse of the thermal energy, as per examples of the present subject matter;

[0017] FIG. 4F illustrates a graphical representation of conductance patterns in a memristor, as per examples of the present subject matter;

[0018] FIG. 5A illustrates a graph showing the Fourier transform (FT) coefficients obtained from a memristor-based hardware implementation (memsistor), compared to a calculated FT, as per examples of the present subject matter;

[0019] FIG. 5B illustrates a graph that compares the performance of matrix-matrix multiplication across different matrix types using a memristor- based computing system (analog computing system), as per examples of the present subject matter;

[0020] FIG. 5C illustrates a graph of the conductance characteristics of a memristor as a function of the number of electrical pulses applied, as per examples of the present subject matter;

[0021] FIG. 6 illustrates two graphs representing the conductance characteristics of a memristor as a function of the number of electrical pulses applied for 9,000 weight update characteristics from 900 cross points, as per examples of the present subject matter;

[0022] FIG. 7 presents a set of four heat map graphs comparing the DFT matrix writing accuracy immediately after writing and after a period of seven months, as per examples of the present subject matter; [0023] FIG. 8 illustrates a graphical representation showing reconstructing an original waveform via an Inverse Discrete Fourier Transform (IDFT) process using the analog computing system, as per examples of the present subject matter; and

[0024] FIG. 9 depicts a series of subfigures, each consisting of a pair of graphs, as per examples of the present subject matter.

[0025] It may be noted that throughout the drawings, identical reference numbers designate similar, but not necessarily identical, elements. The figures are not necessarily to scale, and the size of some parts may be exaggerated to more clearly illustrate the example shown. Moreover, the drawings provide examples and/or implementations consistent with the description; however, the description is not limited to the examples and/or implementations provided in the drawings.

DETAILED DESCRIPTION

[0026] Generally, analog computing systems are integrated with memristors, a non-volatile electrical component that limits or regulates the flow of an electrical current in a circuit. Memristors have emerged as a promising component for analog computing systems due to an ability to retain information even without power. The integration of memristors into analog computing systems enhances performance and efficiency, paving the way for advancements in neuromorphic computing and other innovative applications.

[0027] Further, analog computing systems are well-suited for processing continuous data, which is essential in Al applications, such as neural networks and signal processing. Processing continuous data in Al applications provides a detailed and a nuanced representation of real-world data as compared to discrete data utilized in digital computing systems.

[0028] The analog computing systems leverage continuous data to perform various computations. One of the key operations in such analog computing systems is vector-matrix multiplication. Vector matrix multiplication (VMM) is a fundamental operation in many computing algorithms, especially in Al and machine learning algorithms. By using analog signals, such analog computing systems perform VMM with lower power consumption and higher speed compared to digital computing systems.

[0029] However, analog computing systems are highly susceptible to noise and variability, which may lead to inaccuracies in computations, such as VMM. Errors in VMM operations may propagate and amplify, causing significant issues in large-scale computations. Additionally, device imperfections, such as those found in memristors or resistive randomaccess memory (RRAM), may introduce additional errors due to manufacturing variations or operational wear. Analog computing systems exhibit limited flexibility compared to digital systems, thereby making reconfiguration for different computations challenging. Moreover, as the physical size and power requirements of analog components may limit ability of a computing system to handle larger datasets or more complex tasks, analog components make the computing system less scalable.

[0030] Conventionally, dot-product engines (DPEs) are configured to perform VMM in a single time-step by leveraging parallel nature of analog computation, significantly reducing computation time. DPEs consume less power compared to digital computing systems, as they are designed to perform operations directly on stored data without repeated read/write cycles. This parallel processing capability (implying that multiple operations may be carried out simultaneously, rather than sequentially as in traditional digital systems) further enhance efficiency of the analog computing systems. DPEs are particularly beneficial in Al and machine learning for tasks such as neural network inference and real-time data processing, enabling faster and more efficient computations.

[0031] Despite these advancements, the adoption of DPEs and other analog computing elements in mainstream computing has been limited due to challenges related to precision, noise, and device variability. For example, memristors, which are central to DPEs, often exhibit variability in their electrical properties, leading to inconsistent performance. Integrating DPEs with existing digital technologies is complex, requiring advanced fabrication techniques. Additionally, the cost of manufacturing and integrating memristors may be higher than traditional digital components, limiting their widespread adoption.

[0032] Example approaches for improving performance and reliability of DPEs in analog computing are disclosed. In one example, there is described an analog computing system. The analog computing system (hereinafter referred to as the “system”) comprises a crossbar array and a processor. The crossbar array comprises a bottom electrode and a top electrode, with an active material interposed between them. In one example, active material is selected from a group of compounds that comprises, but is not limited to, Ru-complex of azo-aromatic ligands, coordinated azo-aromatic ligands, un-coordinated azo-aromatic ligands, or combinations thereof. The bottom electrode, the top electrode, and the active material are interposed between the top electrode and the bottom electrode in such a way that each junction acts as a memristor.

[0033] In one example, the crossbar array is structured with a plurality of word lines and bit lines. Each memristor in the array is formed at the intersection (junction) of a word line and a bit line, creating a grid-like structure that allows for precise control and addressing of individual memristors. To facilitate operation of the array, the word lines are electrically coupled to a positive terminal, while the bit lines are coupled to a negative terminal. This configuration may enable the application of voltage differentials across specific memristors within the array.

[0034] During operation, an input voltage signal may be applied to the crossbar array structure. This application of the input voltage signal may cause a molecular transformation within each memristor. Such molecular transformation pertains to a complex electronic rearrangement and an ionic reorganization within the active material. The molecular transformations induced by the applied input voltage signal results in formation of a plurality of distinct analog levels within each memristor. These analog levels may correspond to different conductance states, effectively allowing each memristor to store analog values of data.

[0035] In one example, the plurality of distinct analog levels pertains to at least 16,520 conductance states. These conductance states may span a wide range, from a minimum of about 200 nanosiemens (nS) to a maximum of about 5.9 millisiemens (mS). Each of these discrete states corresponds to a unique analog value that may be stored in the memristor, providing a dense and highly granular method of analog data storage.

[0036] In one example, the system may be operable in a first scenario (read operation) and a second scenario (write operation). In the first scenario, the input voltage signal may act as a read voltage pulse, while in the second scenario, the input voltage signal may act as a write voltage pulse. The read voltage pulse may be applied below a certain predefined threshold voltage that would induce molecular transformation. In one example, the read voltage pulse is less than 600 millivolts (mV). When the read voltage pulse is applied, the system receives a current signal in response, which corresponds to the current conductance state (data) of the memristor being read.

[0037] On the other hand, write operations may be performed when the write voltage pulse exceeds a predefined threshold required for molecular transformation. In one example, the write voltage pulse may be in a range of about 850 mV to 1 .3 Volts (V). The exact voltage used may be fine-tuned based on a desired change in conductance. By controlling the pulse width between 40 nanoseconds - 10 microseconds (ps) and voltage between 850 mV to 1 ,3V, any conductance change ranging the minimum to maximum conductance over the 16,520 levels may be realized using a single pulse (any input voltage signal). [0038] In one example, a method of manufacturing the crossbar array structure is also described. The method comprises fabricating a bottom electrode on a substrate, using, for example, but not limited to, standard lithography and etching techniques. A molecular film may then be spin- coated on top of the substrate. A top electrode may be deposited either through a mask or via standard lithography and etching processes. The top and bottom electrodes may be composed of a metal selected from a group comprising, but is not limited to, Gold (Au), Copper (Cu), Platinum (Pt), Cobalt (Co).

[0039] In one example, for preparing the memristor, film of [RullL2](BF4)2 (L = 2,6-bis(phenylazo)pyridine is sandwiched between top and bottom gold electrodes. The film thickness may vary from 5-100 nm and the electrode thickness may be in a range of about 10-80 nm.

[0040] It may be noted that the molecular transformation (electronic reorganization and ionic rearrangement) in the memristor is facilitated based on conducting in-situ Raman spectroscopy at different analog states to measure molecular electronic states in the memristors. In one example, spectroscopic data (associated with in-situ Raman spectroscopy) revealed that transition from a lowest to a highest conductance level is governed by supramolecular charge transfer, shifting from a charge-disproportionate (CD) electronic state to a symmetric state. In the broken symmetry (CD) state, neighboring molecules hold three and one electrons in antibonding orbitals, whereas in the valence-symmetric state, all molecules contain two electrons in antibonding orbitals. The counterion positions differ between these states, making ion displacement an integral part of the transition. Individual 80 ns pulses induce selective molecular and counterion rearrangements, facilitating the transition between the CD and symmetric states.

[0041] The present approaches provide numerous technical advantages. For example, the present approaches work as a dot-product engine, wherein input values may be applied as voltages to the word lines of the crossbar array, while matrix values are stored as the conductance states of the memristors. The result of the computation may then be read as currents from the bit lines of the array. This allows for highly efficient parallel processing of certain types of mathematical operations, particularly those common in neural network and machine learning applications.

[0042] Further, present approaches facilitate a unidirectional flow of current within the read voltage regime, which simplifies the reading process and reduces potential errors. Furthermore, the memristors are designed to operate without the need for additional selector devices, which are often required in other memristive systems to prevent unwanted current flow in large arrays. This simplification contributes to an overall efficiency and scalability of the system.

[0043] Also, the physical dimensions of the components (in the analog computing system) are also carefully controlled to optimize performance. The active material layer typically has a thickness ranging from 5 nanometers (nm) to 100 nanometers (nm), while both the top and bottom electrodes have thicknesses ranging from 20 nanometers (nm) to 80 nanometers (nm). Such precise dimension may contribute to an overall performance and reliability of the memristors.

[0044] Furthermore, the present approaches provide linear changes in conductance without the need for iterative verification. The processor may apply a series of voltage pulses to a memristor, resulting in predictable and linear changes in conductance. This eliminates the need for complex write- verify schemes that are common in many other memristive systems, thereby improving the speed and efficiency of write operations. A standout feature of the memristor discussed in the present subject matter, is its linear and symmetric weight update with 900mV pulses. This means that if a specific change in conductance is required, it may be achieved in an open-loop manner by applying the appropriate number of pulses. In contrast, existing analog memristors exhibit nonlinear weight updates, necessitating costly write-and-verify loops to achieve the desired conductance changes. The ability to perform direct, predictable weight updates eliminates the need for such iterative corrections, significantly reducing the computational overhead of the writing process.

[0045] In one example, the system enables in-memory analog computation, where matrices are stored as crossbar conductance states and vectors are applied as input voltage signals, enabling one-step vectormatrix multiplication in analog domain, substantially reducing computational complexity from N² steps to a single step. The system is optimized for high- bandwidth artificial intelligence (Al) and scientific computing workloads, offering a power-efficient, scalable alternative to conventional digital memory and processing architectures.

[0046] Additionally, in the present approaches, computations leverage the physical properties of memristors within a crossbar architecture, known as a dot product engine. For instance, in vector-matrix multiplication, input values are applied as voltages to the top electrodes of the crossbar (word lines), while matrix values are stored as memristor conductance. The output is generated in a single step, with results read as currents at the bottom electrodes (bit lines). Unlike digital platforms, where the computational complexity for an nxn matrix is O(n²), the dot product engine reduces this complexity to 0(1 ), enabling highly efficient analog processing.

[0047] The above-mentioned implementations are further described herein with reference to the accompanying figures. It should be noted that the description and figures relate to exemplary implementations and should not be construed as a limitation to the present subject matter. It is also to be understood that various arrangements may be devised that, although not explicitly described or shown herein, embody the principles of the present subject matter. Moreover, all statements herein reciting principles, aspects, and embodiments of the present subject matter, as well as specific examples, are intended to encompass equivalents thereof.

[0048] FIG. 1 illustrates a schematic 100 of an analog computing system 102 for high resolution analog computing, as per examples of the present subject matter. The analog computing system 102 (hereinafter referred to as the system 102) comprises a processor 104 and a crossbar array 106.

[0049] The system 102 may be implemented as a combination of hardware and programming, for example, programmable instructions to implement a variety of functionalities. In examples described herein, such combinations of hardware and programming may be implemented in several different ways. The programmable instructions may be stored on a non- transitory machine-readable storage medium which may be coupled either directly with the system 102 or indirectly (for example, through networked means). In an example, the processor 104, for example, may be either a single processor or a combination of multiple processors, to execute such instructions. In the present examples, the non-transitory machine-readable storage medium may store instructions that when executed by the processing resource, implement the system 102. In other examples, the system 102 may be implemented as electronic circuitry.

[0050] In one example, the crossbar array 106 comprises a bottom electrode and a top electrode, with an active material interposed between them. In one example, the active material may be selected from a group of compounds that comprises, but are not limited to, Ru-complex of azoaromatic ligands, coordinated azo-aromatic ligands, un-coordinated azoaromatic ligands, or combinations thereof. The bottom electrode, the top electrode, and the active material are interposed between the top electrode and the bottom electrode in such a way that each junction acts as a memristor 108. The crossbar array 106 includes a grid-like structure where horizontal and vertical conductive lines intersect at junctions, forming a network of connections. Details pertaining to the crossbar array 106 are explained in conjunction with FIG. 2.

[0051] Thus, the system 102 leverages unique properties of the crossbar 106 to implement high-resolution analog computing for performing complex operations in a single time-step, offering significant advantages over traditional digital computing systems for certain types of computations, such as vector matrix multiplication.

[0052] FIG. 2 illustrates schematic of a crossbar array 200 for being implemented in an analog computing system (not shown), as per examples of the present subject matter. The crossbar array 200 may be similar to the crossbar array 106.

[0053] As depicted in FIG. 2, the crossbar array 200 may be a grid-like structure with a plurality of word lines 202 and a plurality of bit lines 204 intersecting each other. As discussed previously, the crossbar array 200 comprises a bottom electrode and a top electrode, with an active material interposed between them. The bottom electrode, the top electrode, and the active material are interposed between the top electrode and the bottom electrode in such a way (grid-like structure) that each junction acts as a memristor 210. In one example, each junction defined by the intersection of the word line 202 and the bit line 204 in the grid-like structure, forms the memristor 210.

[0054] The memristor 210 allows for precise control and addressing of individual memristors. To facilitate operation of the crossbar array 200, the plurality of word lines 202 is electrically coupled to a positive terminal, while the plurality of bit lines 204 is coupled to a negative terminal. This configuration may enable the application of voltage differentials across specific memristors within the array.

[0055] During operation, an input voltage signal 206 may be applied to the crossbar array 200. This application of the input voltage signal may cause a molecular transformation within each memristor 210. Such molecular transformation pertains to a complex electronic rearrangement and an ionic reorganization within the active material.

[0056] The molecular transformations induced by the applied input voltage signal 206 may result in the formation of a plurality of distinct analog levels within each memristor 210. These analog levels correspond to different conductance states, effectively allowing each memristor 210 to store analog values of data. A conductance state may refer to the electrical conductance in the active material at a given time. In one example, the plurality of distinct analog levels pertains to at least 16,520 discrete conductance states. These conductance states may span a wide range, from a minimum of about 200 nanosiemens (nS) to a maximum of about 5.9 millisiemens (mS). Each of these discrete states corresponds to a unique analog value that may be stored in the memristor, providing a dense and highly granular method of analog data storage.

[0057] In one example, the system 102 may be operable in a first scenario (read operation) and a second scenario (write operation). In the first scenario, the input voltage signal 206 may act as a read voltage pulse, while in the second scenario, the input voltage signal 206 may act as a write voltage pulse. The read voltage pulse may be applied below a first predefined threshold voltage that would induce molecular transformation. In one example, the read voltage pulse is less than 600 millivolts (mV) (first predefined threshold voltage). When the read voltage pulse is applied, the system 102 receives a current signal in response, which corresponds to the current conductance state (data) of the memristor being read.

[0058] On the other hand, write operations may be performed when the write voltage pulse exceeds a second predefined threshold required for molecular transformation. In one example, the write voltage pulse may be in a range of about 850 mV to 1.3 Volts (V) (second pre-defined voltage). The exact voltage used may be fine-tuned based on a desired change in conductance. By controlling the pulse width between 40 ns - 10 ps and voltage between 850 mV to 1.3V, any conductance change ranging the minimum to maximum conductance over the 16,520 levels may be realized using a single pulse (any input voltage signal).

[0059] In one example, the system 102 enables in-memory analog computation, where matrices are stored as crossbar conductance states and vectors are applied as input voltage signals, enabling one-step vectormatrix multiplication in analog domain, substantially reducing computational complexity from N² steps to a single step. The system 102 is optimized for high-bandwidth Al and scientific computing workloads, offering a powerefficient, scalable alternative to conventional digital memory and processing architectures.

EXPERIMENTAL DATA

[0060] FIG. 3A illustrates a graph 302 depicting change in conductance in a memristor 210, spanning from lowest to highest conductance values, as a function of the number of writing pulses applied, as per examples of the present subject matter. The conductance scale factor 10’³ is indicated at the top left, suggesting that the conductance values on the y-axis are multiplied by 10’³. The graph 302 starts with an initial conductance reference 1 at the origin, where the starting pulse count 0 marks the beginning of the potentiation process. As the number of pulses increases, the conductance rises sharply. The inset shows an a zoomed in section capturing conductance range spanning 3341.5 and 3342 mS, represented by the green line, for the pulse numbers 9316 and 9318, respectively. The midpoint pulse counts 16500 and the endpoint pulse count 33000 are marked along the x-axis to delineate the extent of the potentiation and depression phases, respectively. From 0 to 16520, it captures the potentiation process while for number of pulses between 16521 to 33040, it triggers depression. Notably, the slopes of the potentiation and depression processes are equal and opposite.

[0061] In some cases, the memristor 210 enables voltage-driven ionic rearrangement, facilitating 16,520 distinct analog levels. This feature allows the system 102 to achieve a wide range of conductance states, providing a high degree of flexibility and control in the computing process. In other aspects, the memristor 210 uses 16,520 square pulses of 900 mV amplitude and 80 ns duration for positive weight updates, and an equal number of -750 mV pulses of 65 ns for negative weight update. This approach allows for precise control over the conductance changes in the device, enabling the linear and symmetric updating or writing of the analog levels individually in one time-step.

[0062] FIG. 3B illustrates a graph 304 depicting the conductance measurements of a memristor 210 between two pairs of successive states, labeled as level-2, level-3 and level 10k2, level 10k3, at various levels of data points and counts, as per examples of the present subject matter.

[0063] In the Level-10k2, Mean Conductance G°iok2 is depicted along with its Standard Deviation o k2. In level-10k3 section, Mean Conductance Level-10k3 G°iok3 is shown with its corresponding Standard Deviation o k3. AG k3 indicates the difference between the conductance levels G°iok3 and G°iok2. The memristor 210 allows for linear and symmetric updating or writing of the analog levels individually in one time-step. This feature enables precise control over the conductance changes in the device, providing a high degree of flexibility and control in the computing process.

[0064] Similarly, in the Level-2, the mean conductance is G°2, Standard deviation is 02. Level-3 shows a mean conductance of G°3, standard deviation of 03, while AG3 represents the difference between G°2 and G°3. This provides a detailed view of the conductance characteristics and statistical variations at this measurement level, highlighting the precision and resolution of the memristor 210's conductance states. It was ensured that the difference between any two subsequent conductance levels is at least six times greater than the standard deviation at the individual levels.

[0065] FIG. 3C illustrates a graph 306 showing the probability distribution of conductance states in a memristor 210, as per examples of the present subject matter. The graph 306 illustrates the probability distribution of each conductance level around it’s mean value. Different conductance levels are denoted as Gn and their respective mean values are G°n where n varies from 1 to 16520.

[0066] In some cases, the color gradient from blue to yellow represents the progression of conductance states from the initial state (n = 1 ) to the final state (n = 16520). This suggests that all the different memristive states have noise floor less than 70nS.

[0067] In other aspects, the graph may be used to analyze the precision and repeatability of the memristor's conductance states. The distribution of conductance states may provide insights into the device's performance under different operating conditions, such as the number of pulses applied or the amplitude of the pulses. This detailed view of the conductance characteristics and statistical variations at different measurement levels may enable the memristor 210 to achieve a wide range of conductance states, providing a high degree of flexibility and control in the computing process.

[0068] FIG. 3D illustrates a graph 308 of the statistical distribution of conductance levels in a memristor 210, as per examples of the present subject matter. The x-axis represents the conductance of the levels, scaled by 10^A-3 Siemens (S), while the y-axis shows two different quantities: the change in conductance AGn(S) between two successive levels and the standard deviation of each level o_n(S), both scaled by 10^A-7 Siemens (S). The green area represents the conductance difference AGn(S) between any two successive levels within the range of 1 to 16520. The red area below represents the standard deviation o_n(S) for each level. It shows that the difference in conductance between any two levels is at least 6 times their standard deviation.

[0069] The graph demonstrates the accuracy with which each conductance level may be distinguished within the memristor 210, highlighting the device's high resolution and analog accuracy.

[0070] In other aspects, the system 102 may achieve a signal-to-noise ratio of greater than 73 dB, while consuming substantially less energy than traditional digital computers. This energy efficiency, combined with the high computing resolution offered by the system, may address some of the challenges associated with the adoption of analog computing elements in mainstream computing, such as precision, noise, and device variability. [0071] FIG. 3E illustrates a graph 310 showing the relationship between written conductance levels and the corresponding read conductance values in a memristor 210, as per examples of the present subject matter. The x-axis represents the written conductance levels, while the y-axis shows the read conductance values, both axes being scaled by 10^A-3 Siemens (S). The graph features two distinct curves: one read with a -0.5 V reading and another for a +0.5 V reading.

[0072] For negative reading voltage, shown in red, demonstrates a low read conductance value across all written conductance levels. This feature may be particularly useful in blocking the negative current through the device enabling a selector less crossbar.

[0073] In contrast, the +0.5 V reading curve, depicted in green, shows a linear increase in read conductance values corresponding to the written conductance levels. This suggests that positive voltage readings accurately reflect the written conductance states.

[0074] An inset graph plots the conductance in log-scale further emphasizing the linearity for positive readout voltage and blocking in negative voltages.

[0075] In other aspects, the memristor 210, may be read using less than 600 mV pulses of any duration without disturbing the resistance state. This feature may allow for efficient and non-destructive reading of the memristor's conductance states, potentially enhancing the overall performance and reliability of the computing system.

[0076] FIG. 4A illustrates a graph 402 depicting endurance of a memristor 210, over a range of reading and writing cycles, as per examples of the present subject matter. The x-axis represents the endurance cycles, marked by specific cycle counts including thousand cycles mark 10^A3, hundred thousand cycles mark 10^A5, ten million cycles mark 10^A7, and billion cycles mark 10^A9. The y-axis indicates the conductance of the memristor, scaled by 10^A-3 Siemens (S). [0077] The graph 402 shows a series of peaks and troughs corresponding to the conductance changes during the potentiation and depression phases of the memristor's operation. The potentiation phase refers to the process where the conductance of the memristor increases, while the depression phase refers to the process where the conductance decreases. In some cases, these phases may be controlled by applying a series of electrical pulses to the memristor, with the number and amplitude of the pulses determining the conductance level.

[0078] The pattern of conductance changes repeats consistently across the range of endurance cycles, demonstrating the device's ability to maintain stable conductance levels through numerous cycles, from a single cycle up to a billion cycles. This feature may be particularly beneficial in applications where long-term stability and repeatability of conductance states are desired, such as in non-volatile memory applications or in systems where precise control over analog states is paramount.

[0079] In other aspects, the memristor 210 may exhibit a high endurance, capable of withstanding a large number of cycles without degradation in performance. This high endurance may contribute to the overall reliability and longevity of the computing system, potentially enhancing its suitability for various computing applications.

[0080] FIG. 4B illustrates a graph 404 showing the conductance levels of a memristor 210, over time, as per examples of the present subject matter. The graph is divided into several horizontal bands, each representing a different conductance level as the device is subjected to a DC voltage of 500mV at 85°C. The darkest blue conductance band at the bottom indicates the 8^th conductance level while counting the lowest conductance level counted as level-1 and the conductance increases as the count goes up. The yellow conductance level represents the 6005^th conductance level. In between, there are additional bands indicating intermediate conductance states: dark blue conductance level 9, blue conductance level 10, light blue conductance level 1003, green conductance level 1004, light green conductance level 1005, orange conductance level 6003, and dark yellow conductance level 6004. Each level is labeled with its respective conductance level, and the data points within each band show the read-out noise of the conductance at that level over the time period represented on the x-axis. Notably, no drift is observed in any of these conductance levels.

[0081] In other aspects, the data points within each band may show the stability and consistency of the conductance at that level over the time period represented on the x-axis. This may provide a visual representation of the memristor 210's ability to maintain stable conductance levels over time, potentially highlighting the device's reliability and repeatability in analog state representation. This detailed view of the conductance characteristics over time may enable the memristor 210 to achieve a wide range of conductance states, providing a high degree of flexibility and control in the computing process.

[0082] FIG. 4C illustrates a graph 406 depicting programming of conductance levels in a memristor 210, using two different methods, as per examples of the present subject matter. The graph shows conductance difference on the y-axis, on a scale of 0 (~200nS) to 6 mS, and the programming methods on the x-axis. A pulse train, characterized by a pulse train duration of 80ns and an amplitude of +900mV may be used to write different conductance states where the number of pulse count determines the written states.

[0083] In some cases, the graph also demonstrates one pulse programming, where a single pulse of the same amplitude Vp1 or Vp2 is applied, directly achieving the desired conductance change level skipping the intermediate steps. This indicates a more efficient programming method, as it allows for direct access to any conductance level in a single time-step, thereby simplifying the weight update procedure and enhancing the computational efficiency of the memristor 210. [0084] The maximum conductance difference indicated on the graph is 6 mS, showcasing the range of conductance levels that may be achieved through these programming methods. This wide range of conductance levels may enable the memristor 210 to represent a multitude of distinct analog states, providing a high degree of flexibility and control in the computing process. This feature may be particularly beneficial in applications where high-resolution analog computing is desired, such as in signal processing, neural network training, and natural language processing.

[0085] FIG. 4D illustrates a three-dimensional graph 408 demonstrating the relationship between pulse voltage amplitude, pulse width, and the resulting conductance difference in a memristor 210, as per examples of the present subject matter. The graph 408 shows pulse voltage amplitude (0.6-1.5V) on the x-axis, pulse width ranging 80ns - 3.5 microseconds (x10^-6 s) on the y-axis, and the log of conductance difference facilitated by the applied pulse on the z-axis.

[0086] The color gradient in the graph represents the conductance difference magnitude, with the scale ranging from 10^A-9 S to 5x10^A-3 S. This color gradient may provide a visual representation of the conductance difference magnitude, allowing for easy identification of the conductance levels associated with different pulse widths and amplitudes.

[0087] The inset on the left side of the graph illustrates the root mean square error (RMSE) associated with the conductance difference. This inset may provide a detailed view of the accuracy of the memristor's conductance changes in response to different pulse widths and voltage amplitudes, highlighting the precision and repeatability of the memristor's conductance states.

[0088] In other aspects, the graph may be used to analyze the performance of the memristor 210 under different operating conditions, such as varying pulse widths and voltage amplitudes. This detailed view of the conductance characteristics as a function of pulse width and voltage amplitude may enable the memristor 210 to achieve a wide range of conductance states, providing a high degree of flexibility and control in the computing process.

[0089] FIG. 4E illustrates a graph 410 showing relationship between the transition time between different subsequent pairs of conductance levels in a memristor 210, and the inverse of the thermal energy, as per examples of the present subject matter. The x-axis represents the inverse of the Boltzmann constant times temperature (1/ksT) in electron-volts inverse (eV^A-1 ), while the y-axis shows the natural logarithm of the inverse transition time (ln(1 /transition time)) in seconds inverse (s^A-1 ). The graph features a linear fit line indicating the activation energy (Ea) for the transition between seven pairs of conductance levels, viz. level- 1 to 2, level- 501 to 502, level- 2001 to 2002, level- 5001 to 5002, level- 10001 to 10002, level- 15001 to 15002, level- 16501 to 16502. The constant transition rate and activation energies for all these different transitions suggests that this is a zeroth order transition explaining the observed linearity.

[0090] FIG. 4F illustrates a graphical representation 412 of conductance patterns in a memristor 210, as per examples of the present subject matter. The figure presents two identical images side by side representing the real and imaginary DFT matrix. Half of the crossbar (64x32) captured the [real (DFT matrix)]64x32 while the other half captured the [imaginary (DFT matrix)] 64x32. Due to the structural symmetries in DFT, half of the columns are adequate to capture all frequency components at the output.

[0091] The color gradient across the loops corresponds to the increasing conductance values, with darker colors representing lower conductance and brighter colors representing higher conductance. This color-coded representation may provide a visual indication of the conductance states of the memristor 210, potentially facilitating the interpretation and analysis of the device's conductance properties. [0092] The minimum conductance value is 0 while the maximum conductance value 5.9 mS is labeled at the bottom right corner of the figure. This value signifies the maximum conductance state achieved by the memristor 210, corresponding to the brightest color in the color gradient. The maximum conductance value 5.9 mS may be associated with a specific conductance level, which may be the maximum conductance level achievable by the memristor 210 under the given operating conditions.

[0093] The conductance scale in millisiemens (mS) is provided at the bottom of the figure to quantify the conductance levels depicted in the patterns. The conductance scale may range from 0 mS, corresponding to the starting pulse count 0, to 5.9 mS, corresponding to the maximum conductance value 5.9.

[0094] FIG. 5A illustrates a graph 502 showing the Fourier transform (FT) coefficients obtained from a memristor-based hardware implementation (memristor 210), compared to a calculated FT, as per examples of the present subject matter. The top graph shows an input waveform with voltage (V) on the y-axis and word line number on the x-axis, ranging from 1 to 64. This waveform may represent an input signal that is processed by the memristor 210. The waveform may be a time-domain signal, such as a sound wave or an electrical signal, that is converted into a frequency-domain representation through the Fourier transform process.

[0095] The bottom graph displays the corresponding FT from the hardware and the calculated FT, with column current (mA) on the y-axis and bit line number on the x-axis, also ranging from 1 to 64. The bit line markers 16, 32, 48, and 64 are labeled, corresponding to specific points along the x- axis.

[0096] The two overlaid graphs demonstrate the accuracy of the memristor hardware in replicating the software generated Fourier transform of the input signal. This feature may be particularly beneficial in applications where high-resolution signal processing is desired, such as in neural network training, natural language processing, and other core computing tasks. The ability of the memristor 210 to accurately perform the Fourier transform process may contribute to its high computing resolution, potentially enhancing the overall performance and efficiency of the computing system.

[0097] In other aspects, the memristor 210 may be capable of performing core computing tasks of signal processing, neural network training, and natural language processing with high computing resolution. This capability may be facilitated by the device's ability to achieve a wide range of distinct analog levels, as well as its ability to accurately replicate the Fourier transform of input signals. The high computing resolution of the memristor 210 may contribute to its suitability for various computing applications, potentially driving advancements in the field of analog computing.

[0098] FIG. 5B illustrates a graph 504 that compares the performance of matrix-matrix multiplication across different matrix types using a memristor-based computing system (analog computing system 102), as per examples of the present subject matter. The x-axis categorizes matrices into various types, including triangular, Hermitian, non-symmetric, symmetric, stochastic, and bi-stochastic. Each category may represent a specific type of matrix that may be processed by the memristor 210, with each type having its own characteristics and computational requirements.

[0099] The y-axis of the graph is divided into two metrics. The top half measures the root mean square error (RMSE) in nanoamperes (nA), while the bottom half measures the signal-to-noise ratio (SNR) in decibels (dB). These metrics may provide a quantitative assessment of the performance of the memristor 210 in handling matrix-matrix multiplication tasks. The RMSE may indicate the accuracy of the computations, with lower values representing higher accuracy. The SNR may measure the quality of the signal output by the memristor 210, with higher values indicating better signal quality. [0100] Violin plots are presented above the x-axis, representing the distribution of RMSE values for each matrix type. The real (Re) and imaginary (Im) components are indicated for complex matrices. These plots may provide a visual representation of the distribution of RMSE values, highlighting the variability in accuracy across different matrix types. The real and imaginary components may represent the two parts of a complex number, which may be used in computations involving complex matrices.

[0101] Colored circles are depicted below the x-axis, indicating the SNR for each matrix type. The scale for these circles ranges from 12 bits to 13.3 bits of precision. This scale may represent the precision of the signal output by the memristor 210, with higher bit values indicating higher precision. The colored circles may provide a visual representation of the SNR for each matrix type, highlighting the noise performance of the memristor 210 when handling various types of matrices.

[0102] The memristor-based computing system may be capable of performing matrix-matrix multiplication tasks with high accuracy and low noise across a wide range of matrix types. This offers the best SNR in any neuromorphic crossbar attained so far. This capability may enhance the versatility and applicability of the system in various computing applications, potentially driving advancements in the field of analog computing.

[0103] FIG. 5C illustrates a graph 506 of the conductance characteristics of a memristor 210 as a function of the number of electrical pulses applied, as per examples of the present subject matter. The x-axis of the graph may represent the number of pulses, scaled by 10⁴, while the y-axis may show the conductance in Siemens (S), scaled by 10’³. The graph may feature a series of lines that increase in conductance with the number of pulses, peaking at different conductance levels before returning to the baseline, forming a triangular pattern.

[0104] The color gradient from blue to yellow in the graph may indicate the progression of conductance levels as the number of pulses increases. The blue color may represent lower conductance levels, while the yellow color may represent higher levels. This color-coded representation may provide a visual indication of the conductance states of the memristor 210, potentially facilitating the interpretation and analysis of the device's conductance properties.

[0105] In other aspects, the graph may demonstrate the memristor's ability to achieve and maintain distinct conductance states over a wide range of pulse counts. This feature may highlight the device's precision and repeatability in analog state programming. By varying the number of pulses applied to the device, it may be possible to control the conductance levels, thereby enabling the device to represent a multitude of distinct analog states with high precision. This detailed view of the conductance characteristics as a function of pulse count may enable the memristor 210 to achieve a wide range of distinct analog levels, providing a high degree of flexibility and control in the computing process.

[0106] FIG. 6 illustrates two graphs 600 (6(a) and 6(b)), each representing the conductance characteristics of a memristor 210 as a function of the number of electrical pulses applied for 9,000 weight update characteristics from 900 cross points, as per examples of the present subject matter. Both graphs share the same x-axis, which represents the number of pulses scaled by 10⁴. The conductance characteristics are represented differently on the y-axis for each graph. The left graph shows the conductance in Siemens (S) on the y-axis, while the right graph displays the logarithm of conductance (logio(Conductance)) on the y-axis.

[0107] In some cases, the left graph 6(a) illustrates a linear and symmetric pattern of conductance change. This pattern may be observed as the conductance increases during the potentiation phase and then decreases during the depression phase. The potentiation phase refers to the process where the conductance of the memristor increases, while the depression phase refers to the process where the conductance decreases. These phases may be controlled by applying a series of electrical pulses to the memristor, with the number and amplitude of the pulses determining the conductance level.

[0108] In other aspects, the right graph 6(b) presents a similar pattern on a logarithmic scale. This scale may emphasize the precision and dynamic range of the memristor's response to electrical pulsing. The logarithmic scale may provide a more detailed view of the conductance changes, particularly for small changes that may not be easily discernible on a linear scale. This detailed view may enhance the understanding of the memristor's conductance properties and its response to electrical pulsing.

[0109] Furthermore, individual data points of 9,000 weight update characteristics, obtained from 900 cross points are overlaid on the curves to demonstrate the consistency of the memristor's behavior. These data points may represent individual measurements of the memristor's conductance at different points in time or under different operating conditions. The consistency of these data points may indicate the reliability and repeatability of the memristor's conductance states, potentially enhancing the performance and reliability of the memristor 210 in analog computing applications.

[0110] FIG. 7 presents a set of four heat map graphs 700 (7(a) - 7(d)) comparing the DFT matrix writing accuracy immediately after writing and after a period of seven months, as per examples of the present subject matter. In some aspects, the computing system may include a mechanism for writing a discrete Fourier transform (DFT) matrix with high accuracy, as depicted in FIG. 7. The x-axes of the graphs represent the column index, and the y-axes represent the row index, both ranging from 0 to 60. The color scale on the right of each graph indicates the conductance levels, scaled by 10^A-3 Siemens (S), with blue representing lower conductance and yellow representing higher conductance.

[0111] In some cases, the first graph, labeled as FIG. 7(a) Real - written, shows the real part of the DFT matrix immediately after writing. This graph may provide a visual representation of the conductance levels in the real part of the DFT matrix, with the color intensity indicating the magnitude of the conductance. The second graph, labeled as FIG. 7(b) Imag - written, shows the imaginary part of the DFT matrix at the same time. Similar to the first graph, this graph may provide a visual representation of the conductance levels in-the imaginary part of the DFT matrix.

[0112] In other aspects, the third graph, labeled as FIG. 7(c) Real - after 7 months, illustrates the real part of the DFT matrix after seven months. This graph may demonstrate the stability and retention of the conductance levels in the real part of the DFT matrix over an extended period of time. The fourth graph, labeled as FIG. 7(d) Imag - after 7 months, depicts the imaginary part of the DFT matrix after the same period. Similar to the third graph, this graph may demonstrate the stability and retention of the conductance levels in the imaginary part of the DFT matrix over time.

[0113] The consistency between the 'written' and 'after 7 months' graphs for both the real and imaginary parts may demonstrate the stability and retention of the DFT matrix over time. This feature may enhance the reliability and repeatability of the computing system, potentially driving advancements in the field of analog computing.

[0114] FIG. 8 illustrates a graphical representation 800 showing reconstructing an original waveform via an Inverse Discrete Fourier Transform (IDFT) process using the analog computing system 102, as per examples of the present subject matter. The figure illustrates a graph where the x-axis represents the row number, which may indicate discrete positions or time intervals. The y-axis on the left side of the graph may show the voltage (V) of the raw signal, while the y-axis on the right side may show the intensity of the reconstructed signal via vector matrix multiplication (VMM). [0115] The graph compares two curves: a blue curve that may represent the raw signal, and an orange curve that may represent the reconstructed signal. Both curves closely follow each other, demonstrating the accuracy of the IDFT process in reconstructing the original waveform from its frequency components. The close alignment of the two curves across all row numbers may indicate the effectiveness of the memristor- based computing system in performing IDFT operations.

[0116] In some cases, the memristor-based computing system may be capable of accurately performing a IDFT on a wide range of waveforms. The system may be able to handle waveforms of varying complexity and duration, potentially enhancing its versatility and applicability in various computing applications.

[0117] In other aspects, the memristor-based computing system may utilize different methods or algorithms for waveform reconstruction, not just DFT or IDFT. These methods may include, for example, cosine transforms, wavelet transforms, or other suitable signal processing techniques. The choice of reconstruction method may depend on the specific requirements of the computing process, such as the desired speed of computation, the precision of the waveform reconstruction, or the energy efficiency of the system.

[0118] FIG. 9 presents a series of subfigures 900, each consisting of a pair of graphs. In some aspects, the computing system may be capable of performing a discrete Fourier transform (DFT) on different representative waveforms, as depicted in FIG. 9. The top graph in each pair may show a time-domain signal waveform, with the intensity of the signal represented on the y-axis and the row number represented on the x-axis. This graph may provide a visual representation of the input signal in the time domain, potentially facilitating the interpretation and analysis of the signal's temporal characteristics.

[0119] The bottom graph in each pair may display the corresponding DFT results, with the real and imaginary components of the DFT represented on the y-axis and the column number represented on the x- axis. The real component graphs may be labeled "Real," and the imaginary component graphs may be labeled "Imaginary," providing a clear distinction between the two components of the DFT. The DFT results computed by the crossbar-based vector-matrix multiplication (VMM) system may be depicted in orange, while the DFT results computed by a software-based FFT function may be depicted in blue. This color-coded representation may provide a visual indication of the accuracy of the crossbar VMM system in capturing the frequency domain representation of the input signal, potentially facilitating the interpretation and analysis of the signal's spectral characteristics.

[0120] In some cases, the crossbar VMM system may be capable of accurately computing the DFT of various time-domain signals, highlighting the system's capability to perform complex signal processing tasks. The accuracy of the crossbar VMM system may be demonstrated by the close alignment of the orange and blue lines in the bottom graphs, indicating a high degree of correlation between the DFT results computed by the crossbar VMM system and the software based FFT function. This feature may enhance the reliability and repeatability of the crossbar VMM system in performing DFT computations, potentially driving advancements in the field of analog computing.

[0121] A number of implementations have been described. Nevertheless, it will be understood that various modifications may be made without departing from the spirit and scope of the disclosure. Accordingly, other implementations are within the scope of the following claims.

Claims

I/We Claim

1 . An analog computing system comprising: a crossbar array comprising a bottom electrode, a top electrode, and an active material interposed between the top electrode and the bottom electrode, such that each junction of the crossbar array acts as a memristor, wherein the active material is selected from a group comprising one of a Ru-complex of azoaromatic ligands, a coordinated azo-aromatic ligand, an uncoordinated azo-aromatic ligand, and combinations thereof; a processor, operably coupled to the crossbar array, to: apply an input voltage signal to the crossbar array to induce molecular transformation in each memristor, the molecular transformation is indicative of an electronic rearrangement and an ionic reorganization of the active material, the molecular transformation forms a plurality of distinct analog levels, comprising a plurality of conductance states, to store analog values of data.

2. The analog computing system as claimed in claim 1 , wherein the crossbar array comprises a plurality of word lines and a plurality of bit lines, wherein each memristor formed at each junction of the crossbar array is located at an intersection of a word line and a bit line.

3. The analog computing system as claimed in claim 2, wherein the plurality of word lines is electrically coupled to a positive terminal and the plurality of bit lines is electrically coupled to a negative terminal.

4. The analog computing system as claimed in claim 1 , wherein the plurality of distinct analog levels comprises at least 16,520 conductance states, and wherein each memristor is set to any one of the 16,520 conductance states.

5. The analog computing system as claimed in claim 4, wherein the conductance states span a range from a minimum conductance of about 200 nano siemens (nS) to a maximum conductance of about 5.9 milli siemens (mS), wherein each conductance state corresponds to a unique analog value storable in the memristor.

6. The analog computing system as claimed in claim 1 , wherein the input voltage signal comprises a read voltage pulse and a write voltage pulse.

7. The analog computing system as claimed in claim 6, wherein the processor is to: apply the read voltage pulse having a value lower than a threshold voltage required for the molecular transformation to the crossbar array; and receive a current signal from the crossbar array in response to the read voltage pulse, wherein the current signal corresponds to a conductance state of a memristor.

8. The analog computing system as claimed in claim 7, wherein the read voltage pulse is less than 600 millivolts (mV).

9. The analog computing system as claimed in claim 6, wherein the processor is to: apply the write voltage pulse having a value higher than a threshold voltage required for the molecular transformation to the crossbar array to update a conductance state of a memristor.

10. The analog computing system as claimed in claim 9, wherein the write voltage pulse is between a range of about 850 millivolts (mV) to 1 .3 Volts (V).

1 1. The analog computing system as claimed in claim 9, wherein the processor is to cause control of the pulse width of the write voltage pulse between a range of about 40 nanoseconds (ns) to 10 microseconds (ps) to achieve a predefined change in conductance.

12. The analog computing system as claimed in claim 1 , wherein one or more matrices are stored as crossbar conductance states to enable inmemory analog computing.

13. The analog computing system as claimed in claim 1 , wherein one or more vectors are applied as the input voltage signal to the crossbar array.

14. The analog computing system as claimed in claim 1 , wherein the analog computing system enables one-step vector multiplication in analog domain to reduce computational complexity from N² steps to a single step.

15. The analog computing system as claimed in claim 1 , wherein the analog computing system is optimized for providing high-bandwidth artificial intelligence (Al) and scientific computing workloads, and wherein the optimization is to provide power-efficient and a scalable architecture.