WO2025174684A1

WO2025174684A1 - Spin planarization of gapfill materials

Info

Publication number: WO2025174684A1
Application number: PCT/US2025/015201
Authority: WO
Inventors: Thomas Wellar MOUNTSIER; Yang Pan; Patrick A Van Cleemput; Samantha SiamHwa Tan
Original assignee: Lam Research Corp
Current assignee: Lam Research Corp
Priority date: 2024-02-14
Filing date: 2025-02-10
Publication date: 2025-08-21
Anticipated expiration: 2026-08-14
Also published as: TW202548890A

Abstract

Aspects of the present disclosure relate to forming planarized films on substrates. Embodiments include filling gaps with insulating material, including silicon-containing films. Vapor deposition of a flowable film on a substrate is followed by non-contact planarization of the flowable film. Non-contact planarization may include one or more techniques such as subjecting the substrate and deposited film to inertial forces (e.g., by spinning), vibration, or sonic energy.

Description

SPIN PLANARIZATION OF GAPFILL MATERIALS

INCORPORATION BY REFERENCE

[0001] A PCT Request Form is filed concurrently with this specification as part of the present application. Each application that the present application claims benefit of or priority to as identified in the concurrently filed PCT Request Form is incorporated by reference herein in its entirety and for all purposes

BACKGROUND

[0002] Filling high aspect ratio gaps with insulating material in an important process for semiconductor device structures, including shallow trench isolation (STI), inter-metal dielectric (IMD) layers, inter-layer dielectric (ILD) layers, pre-metal dielectric (PMD) layers, and passivation layers. As device geometries shrink and thermal budgets are reduced, void-free filling of narrow width, high aspect ratio (AR) features (e.g., AR>6:1) becomes increasingly difficult due to limitations of existing deposition processes.

SUMMARY

[0003] One aspect of the disclosure relates to a method of forming a planarized dielectric film, including: introducing one or more vapor phase reactants to a chamber housing a substrate having a non-planar topography including field regions and gaps between field regions; from the one or more vapor phase reactants, forming a flowable film on the substrate to fill the gaps and form a flowable overburden film on the field regions; and applying a non-contact force to planarize the flowable overburden film.

[0004] In some embodiments, applying a non-contact force includes spinning the substrate. In some embodiments, the flowable film is a silicon-containing film. In some embodiments, the method further includes removing the planarized overburden film. In some such embodiments, filling the gaps, planarizing the overburden film, and removing the planarized overburden film is performed without performing chemical-mechanical planarization (CMP).

[0005] In some embodiments, forming a flowable film on the substrate to fill the gaps and form a flowable overburden film on the field regions includes a first stage and a second stage, wherein i at least one of a vapor phase reactant partial pressure, a substrate temperature, a vapor phase reactant flow rate differs from the first stage to the second stage.

[0006] In some embodiments, forming a flowable film on the substrate to fill the gaps and form a flowable overburden film on the field regions includes selectively depositing the flowable film in at least some of the gaps by capillary condensation.

[0007] In some such embodiments, the method further includes after depositing the flowable film in at least some of the gaps by capillary condensation, changing one or more process conditions to deposit the flowable film in the remainder of the gaps.

[0008] In some such embodiments, the method further includes, after depositing the flowable film in at least some of the gaps by capillary condensation, changing one or more process conditions to deposit the flowable overburden film. In some embodiments, the method further includes inhibiting deposition on the field regions prior to forming a flowable film to fill the gaps. In some embodiments, the method further includes solidifying the flowable overburden film. In some embodiments, the flowable overburden film is at least partially solidified during planarization. In some embodiments, the flowable film and flowable overburden film are solvent- free as deposited. In some embodiments, applying a non-contact force includes vibrating the substrate. In some embodiments, applying a non-contact force includes exposing the substrate to sonic energy.

[0009] These and other aspects of the disclosure are described further below.

BRIEF DESCRIPTION OF DRAWINGS

[0010] Figure 1 is a flow diagram illustrating an example of a process for forming a planarized film.

[0011] Figures 2A-2C show examples of schematic cross-sectional illustrations of substrates including gaps that may be filled with a flowable dielectric film.

[0012] Figures 3A-3C show schematic illustrations of an example of a gap fill process on a substrate.

[0013] Figure 4 shows examples of a processing chamber during operations of a gap fill process on wafer. [0014] Figure 5 shows a representation of the wafer during or after each operation in Figure 4.

[0015] Figure 6 is a schematic illustration of a graph showing an example of a critical dimension-partial pressure deposition curve.

[0016] Figure 7 is a flow diagram illustrating an example of a multi-stage process for filling gaps on a substrate with a flowable film.

[0017] Figures 8 and 9 are examples of apparatus that may be used to implement the processes described herein.

DETAILED DESCRIPTION OF THE INVENTION

[0018] Aspects of the present disclosure relate to forming planarized films on substrates. Embodiments include filling gaps with insulating material, including silicon-containing films. Examples of silicon-containing films include films that are primarily silicon oxides, with silicon (Si) and oxygen (O) bonds (Si-0 bonds) and oxygen and hydrogen bonds (O-H bonds), films that are primarily silicon nitride, with silicon and nitrogen bonds (Si-N) and N-H bonds, and films that are primarily silicon carbides with silicon and carbon bonds (Si-C bonds) and C-H bonds. Silicon oxynitrides, silicon oxycarbides, silicon carbontrides, and silicon oxycarbonitrides may also be formed.

[0019] According to various embodiments, the methods disclosed herein involve vapor deposition of a flowable film on a substrate and non-contact planarization of the flowable film. Non-contact planarization may include one or more techniques such as subjecting the substrate and deposited film to inertial forces (e.g., by spinning), vibration, or ultrasonic waves. In some embodiments, the non-contact planarization obviates the need for contact planarization techniques such as chemical-mechanical planarization (CMP). The planarization may be performed after and/or during the deposition. After and/or during planarization, the flowable film may solidify. A dry etch may then be performed in some embodiments, for example, to remove overburden deposition.

[0020] In some embodiments, the flowable film is solvent-free as deposited.

[0021] The methods may be used for deposition and planarization of any material that can be vapor deposited to form a flowable film on a substrate, including silicon-containing films. [0022] Filling high aspect ratio gaps with insulating material is performed for integration schemes involving shallow trench isolation (STI), inter-metal dielectric (IMD) layers, inter-layer dielectric (ILD) layers, pre-metal dielectric (PMD) layers, passivation layers, etc. As device geometries shrink and thermal budgets are reduced, void-free filling of narrow width, high aspect ratio (AR) features becomes increasingly difficult due to limitations of existing deposition processes. In certain embodiments, the methods pertain to filling high aspect (AR) ratio (typically at least 6: 1, for example 7: 1 or higher), narrow width (e.g., sub-50 nm) gaps. In certain embodiments, the methods pertain to filling low AR gaps (e.g., wide trenches). Also in certain embodiments, gaps of varying AR may be on the substrate, with the embodiments directed at filling low and high AR gaps.

[0023] In a particular example, a PMD layer is provided between the device level and the first layer of metal in the interconnect level of a partially fabricated integrated circuit. The methods described herein include dielectric deposition in which gaps, (e.g., the gaps between gate conductor stacks) are filled with dielectric material. In another example, the methods are used for shallow trench isolation processes in which trenches are formed in semiconductor substrates to isolate devices. The methods described herein include dielectric deposition in these trenches. The methods can also be used for back end of line (BEOL) applications, in addition to front end of line (FEOL) applications. These can include filling gaps at an interconnect level.

[0024] The methods described herein can be used for any type of flowable dielectric process including undoped silica glass (USG), low-k, and ultra-low k ULK materials.

[0025] The term “semiconductor device” as used herein refers to any device formed on a semiconductor substrate or any device possessing a semiconductor material. In many cases, a semiconductor device participates in electronic logic or memory, or in energy conversion. The term “semiconductor device” subsumes partially fabricated devices (such as partially fabricated integrated circuits) as well as completed devices available for sale or installed in particular apparatus. In short, a semiconductor device may exist at any state of manufacture that employs a method of the subject matter disclosed herein or possesses a structure of this subject matter disclosed herein.

[0026] Vapor-phase reactants are introduced to a deposition chamber to deposit the flowable dielectric films. As-deposited, the flowable dielectric films generally have flow characteristics that can provide consistent fill of a gap. [0027] Figure 1 is a process flow diagram illustrating one example of a process for fill gaps on a substrate. The process can be used in the fabrication of semiconductor devices, displays, LEDs, photovoltaic panels and the like. As noted above, in semiconductor device fabrication, the process can be used for BEOL applications and FEOL applications. In some embodiments, the processes may be used for applications in which high aspect ratio gaps are filled with insulating material. Examples include shallow trench isolation (STI), formation of inter-metal dielectric (IMD) layers, inter-layer dielectric (ILD) layers, pre-metal dielectric (PMD) layers, and passivation layers, and filling gaps at the interconnect level. Further examples include formation of sacrificial layers for air gap formation or lift-off layers.

[0028] A substrate including a gap is provided to a deposition chamber in an operation 101. Examples of substrates include semiconductor substrates, such as silicon, silicon-on-insulator (SOI), gallium arsenide and the like, as well as glass and plastic substrates. The substrate includes at least one and typically more than one gap to be filled, with the one or more gaps being trenches, holes, vias, or other unfilled features on the substrate.

[0029] Figures 2A-2D show examples of schematic cross-sectional illustrations of substrates 201 including gaps 203. Turning first to Figure 2A, a gap 203 can be defined by sidewalls 205 and a bottom 207. It may be formed by various techniques, depending on the particular integration process, including patterning and etching blanket (i.e., planar) layers on a substrate or by building structures having gaps there-between on a substrate. In certain embodiments a top of the gap 203 can be defined as the level of field region 209, which may be a nominally planar surface. Specific examples of gaps are provided in Figures 2B and 2C. In Figure 2B, a gap 203 is shown between two gate structures 202 on a substrate 201. The substrate 201 may be a semiconductor substrate and may contain n-doped and p-doped regions (not shown). The gate structures 202 include gates 204 and silicon nitride or silicon oxy-nitride layer 211. In certain embodiments, the gap 203 is reentrant, i.e., the sidewalls taper inwardly as they extend up from the bottom 207 of the gap; gap 203 in Figure 2B is an example of a re-entrant gap.

[0030] Figure 2C shows another example of gap to be filled. In this example, gap 203 is a trench formed in silicon substrate 201. The sidewalls and bottom of the gap are defined by liner layer 216, e.g., a silicon nitride or silicon oxynitride layer. The structure also includes pad silicon oxide layer 215 and pad silicon nitride layer 213. Figure 2C is an example of a gap that may be filled during a STI process. In certain cases, liner layer 216 is not present. In certain embodiments, the sidewalls of silicon substrate 201 are oxidized. [0031] Figures 2B and 2C provide examples of gaps that may be filled with dielectric material in a semiconductor fabrication process. The processes described herein may be used to fill any gap that requires dielectric fill. In certain embodiments, the gap critical dimension is the order of about 1 -50 nm, in some cases between about 2-30 nm or 4-20 nm, e.g. 13 nm. Critical dimension refers to the width of the gap opening at its narrowest point. In certain embodiments, the aspect ratio of the gap is between 3 : 1 and 60: 1. According to various embodiments, the critical dimension of the gap is 32 nm or below and/or the aspect ratio is at least about 6: 1.

[0032] As indicated above, a gap may be defined by a bottom surface and sidewalls. The term sidewall or sidewalls may be used interchangeably to refer to the sidewall or sidewalls of a gap of any shape, including a round hole, a long narrow trench, etc. In some embodiments, the processes described herein may be used to form flowable films on planar surfaces in addition to or instead of in gaps.

[0033] In the examples of Figure 2A-2C, the substrate can be characterized by a non-planar topography including field regions and one or more gaps between the field regions.

[0034] The deposition surface may be or include one or multiple materials. For example, sidewall and bottom surfaces that define a gap may be one material or include multiple materials. Referring to Figure 2C, for example, if a liner layer 216 is present, it may be the only deposition surface. However, if the liner layer 216 is not present, the deposition surface can include the silicon substrate 201, the pad silicon oxide layer 215 and the pad silicon nitride layer 213. Examples of gap surface materials, including sidewall and/or bottom materials, include silicon nitrides, silicon oxides, silicon carbides, silicon oxynitrides, silicon oxycarbides, silicides, silicon germanium, as well as bare silicon or other semiconductor material. Particular examples include SiN, SiOz, SiC, SiON, NiSi, and polysilicon. Further examples of gap surface materials used in BEOL processing include copper, tantalum, tantalum nitride, titanium, titanium nitride, ruthenium, molybdenum, aluminum, and cobalt. In certain embodiments, prior to flowable dielectric deposition, the gap is provided with a liner, barrier or other type of conformal layer formed in the gap, such that the deposition surfaces include the conformal layer. In some embodiments, the deposition surfaces of a substrate are exposed to a treatment. Examples of pre-deposition treatments are provided further below. [0035] Returning to Figure 1, deposition gases are flowed into the deposition chamber in an operation 103. A flowable film is deposited on the substrate and including in the gap in operation 105.

[0036] For forming silicon oxides, for example, the deposition gases may include a silicon- containing compound and an oxidant, and may also include a catalyst, a solvent (and/or other surfactant) and other additives. The methods disclosed herein are not limited to particular chemistries or deposition mechanisms. The process gases may be introduced into the reactor simultaneously, or one or more component gases may be introduced prior to the others. U.S. Patent No. 8,278,224, incorporated by reference herein, provides a description of reactant gas sequences that may be used in accordance with certain embodiments.

[0037] In some embodiments, a deposition process may be described in the context of a two- step hydrolysis and condensation reaction. The first step involves hydrolysis of silicon-containing precursors by the oxidant. For example, alkoxy groups (-OR) of a alkoxy silane precursor may be replaced with hydroxyl groups (-OH). The -OH groups and the residual alkoxy groups participate in condensation reactions that lead to the release of water and alcohol molecules and the formation of Si-O-Si linkages. In a hydrolyzing medium, the silicon-containing precursor forms a fluid-like film on the wafer surface that preferentially deposits in trenches due to capillary condensation and surface tension forces, resulting in a bottom-up fill process.

[0038] Further discussion and examples of deposition gas chemistries and deposition mechanisms is provided below.

[0039] Deposition continues to deposit flowable film on the field regions between the one or more gaps. In this manner, a flowable overburden layer is deposited in an operation 107. The thickness of the overburden layer can depend on the aspect ratios of the gaps being filled. Examples of thicknesses range from 1 times the height of the topography to over 5 times the height of the topography. For example, for a 500 nm deep trench, the overburden may be between 500 nm to over 2500 nm. Thinner overburden layers may be used in some embodiments.

[0040] Non-contact planarization is performed in operation 109. Because the overburden layer is flowable, a non-contact process can be used for planarization. Non-contact refers to planarization by a method that does not require contact with a solid planarization or polishing mechanism such as CMP polishing pad or with chemical or physical etch technique such as a chemical plasma, reactive ion etching, or sputter etching technique. Examples of non-contact planarization techniques include applying an inertial force (e.g., by spinning the substrate), subjecting the substrate to vibrational force, and subjecting the substrate to sonic energy (e.g., ultrasonic or megasonic waves).

[0041] According to various embodiments, the planarization may be performed after deposition is complete, or at least partially during the deposition process. If performed during the deposition process, it may be performed while deposition gases are flowing into the chamber and film is forming on the substrate and/or in deposition-planarization cycles. Maintaining flowability during planarization is described further below.

[0042] After the process of Figure 1 is performed, the planarized film may be solid and/or be solidified. At the stage, the film can be subject to an etch to remove the overburden layer. Examples of etches include but are not limited to plasmas generated from chlorine (Ch), carbon tetrafluoride (CF4), argon (Ar), oxygen (O2)

[0043] Figures 3A-3C show an example of a gap fill process on a substrate. In Figure 3A, the substrate topography includes dense lines 301 separated by dense gaps 303, a large gap 305, and a large metal pad 307. A topography as shown in Figure 3A is challenging to fill and planarize. Atomic layer deposition (ALD) can be used to fill the dense gaps 303 but will leave the large gap 305 only partially filled. Spin-on deposition of a liquid can be used to fill features, but also has challenges filling large gaps.

[0044] Figure 3B shows the substrate after self-planarizing dielectric gap fill as described above with reference to Figure 1. The dielectric material 315 fills the dense gaps 303 and large gap 305. The substrate topography is now planar. This allows a blanket dielectric etch back as shown in Figure 3C.

[0045] Figures 4 and 5 show an example process as described in Figure 1 and that may be used in the gapfill process of Figures 3 A-3D. Figure 4 shows examples of a processing chamber during operations of a gap fill process on wafer. Figure 5 shows a representation of the wafer during or after each operation.

[0046] At 410 in Figure 4, a gas is flowed (as represented by arrows) into a chamber 412 through a showerhead 414. Vapor phase condensation results in a flowable film depositing on a wafer 416 that is supported by a pedestal 418. [0047] Turning to Figure 5, at 510, a dielectric material 505 is shown after deposition on a substrate having a topography as described with reference to Figure 3A, with dense gaps and a large gap. In the example of Figure 5, a sol-gel based flowable SiO dielectric material is illustrated. It is understood that the dielectric material may be formed from any appropriate condensation reaction. At this stage, the dielectric material is not planar.

[0048] In Figure 4, at 420, the pedestal is spun at a rate sufficient to planarize the flowable dielectric film. The rotational speed is high enough for inertial forces to overcome the viscous forces in the film. Rotating the substrate to planarize the film can be performed during the liquid film formation or separately after the deposition. In Figure 5, a planarized film is shown at 520.

[0049] Returning to Figure 4, at 430, a curing operation is performed to solidify the planarized film. In the example of Figure 4, the cure may be performed by exposing the film to one or more of heat, plasma, and ultraviolet radiation. In Figure 5, the film is shown, solidified and with shrinkage at 530. Some amount of solidification and/or gelling may occur prior to the cure operation.

[0050] At 440 in Figure 4, an etch is performed to expose the metal lines and pads, providing a planar metal and dielectric surface with no CMP process performed. This is shown at 540 in Figure

5.

[0051] Whereas spin-on glass processes involve spinning on solids dissolved in a solvent, the processes described involves a gas phase and/or surface chemical reaction to produce a liquid film.

[0052] In some embodiments, the deposition may be staged to fill features using capillary condensation. Figure 7 shows certain operations in an example of a such a method. First, selective deposition by capillary condensation is performed in an operation 701. Capillary condensation refers to the preference for liquid to remain condensed in small spaces at pressures below the saturation pressure and allows for selective deposition in gaps or in a subset of gaps that are smaller than the remaining gaps. The amount of condensation is controlled by the reactants’ partial pressures relative to their saturated vapor pressures, which are constant for a given deposition temperature. The dependence of fill rate on critical dimension can be tuned by varying the partial pressures. In this manner, selectivity can be tuned, allowing deposition in gaps prior to overburden deposition and/or deposition in larger gaps. This phenomenon is illustrated qualitatively in Figure

6, which shows a partial pressure-critical dimension deposition curve. At low enough partial pressure of a precursor, there is no condensation or deposition in gaps of any size. As the partial pressure is increased, the precursor condenses in small gaps, with deposition occurring in increasingly larger gap sizes as the partial pressure is increased. So, in the example of Figure 6, to prevent deposition on field regions or larger gaps while allowing deposition in gaps having a critical dimension of less than 20 nm, the partial pressure of the dielectric precursor is maintained within the cross-hatched portion of the curve.

[0053] Process conditions are changed in an operation 702. This may be a continuous change or a one or multi-step change. In some embodiments, partial pressure of the changed. In the same or other embodiments, temperature, precursor flow, and/or precursor identity may be changed. The conditions are changed to allow deposition in larger gaps and/or overburden deposition in an operation 703. In some embodiments, deposition continuously occurs with the change in conditions. Multiple different sets of process conditions can be used in certain embodiments. For example, a first set can be used to fill small gaps, a second set to fill intermediate-size gaps, a third set to fill large gaps, and a fourth set for the overburden.

Deposition chemistries and reaction mechanisms

Silicon-containing reactants

[0054] In some embodiments, silicon-containing films such as silicon oxides are formed with a silicon-containing precursor as a reactant. A co-reactant, such as an oxidant or nitriding agent, may be used to react with the silicon-containing reactant. As discussed further below, the process gas may further include a catalyst, a solvent (and/or other surfactant) and other additives. The gases may also include one or more dopants, e.g., a carbon-, nitrogen-, fluorine-, phosphorous- and/or boron-containing gas. Sometimes, though not necessarily, an inert carrier gas is present.

[0055] In certain embodiments, the silicon-containing precursor is an alkoxysilane. Alkoxysilanes that may be used include, but are not limited to, the following:

H_x-Si-(OR)_y where x = 0-3, x+y = 4 and R is a substituted or unsubstituted alkyl group;

R’x-Si-(OR)_y where x = 0-3, x+y = 4, R is a substituted or unsubstituted alkyl group and R’ is a substituted or unsubstituted alkyl, alkoxy or alkoxyalkane group; and

Hx(RO)y-Si-Si-(OR)yH_x where x = 0-2, x+y = 3 and R is a substituted or unsubstituted alkyl group.

[0056] Examples of silicon-containing precursors include CHsSiCOCH ; 1 -(triethoxy silyl)- 2-(diethoxymethylsilyl)ethane, l,2,3,4,5,6-hexamethoxy-l,2,3,4,5,6-hexamethylcyclohexasilane; 1 ,2-dimethoxy- 1 , 1 ,2,2-tetramethyldisilane; l,4-dioxa-2,3,5,6-tetrasilacyclohexane; bis-triethoxysilylethane (BTEOSE); bis-triethoxysilylmethane (BTEOSM); butasilanes; cyclobutasilane; cycloheptasilane; cyclohexasilane; cyclooctasilane; cyclopentasilane; decabutaoxycyclopentasilane; diethoxymethylsilane (DEMS); diethoxysilane (DES); dimethoxymethylsilane; dimethoxysilane (DMOS); dimethyldiethoxysilane (DMDEOS); dimethyldimethoxysilane (DMDMOS); disilane; dodecamethoxycyclohexasilane; ethylsilane; heptasilane; hexaethoxydisilane (HEODS); hexaethoxydislazoxane (HEDS-H); hexamethoxydisilane (HMODS); hexamethoxydisilazoxane (HMDS-H); hexamethoxydisiloxane; hexasilane; hydrogen silsesquioxane; methyl hexamethoxydisilazoxane (HMDS-CH3); methyl-diethoxysilane (MDES); methyl-dimethoxysilane (MDMS); methylsilane; methyltriethoxyorthosilicate (MTEOS); methyl-triethoxysilane (MTES); methyltrimethoxysilane (MTMOS); methyl-trimethoxysilane (MTMS); nonamethoxytrisilazoxane (NMTS); octaethoxycyclobutasilane; OctaHydro POSS™ (Polyhedral Oligomeric Silsesquioxane); octamethoxycyclicsilazoxane (OMCS); octamethoxydodecasiloxane (OMODDS); octamethoxytrisiloxane (OMOTS); octamethyl- 1, 4, dioxa-2, 3, 5, 6-tetrasilacyclohexane; octamethylcyclotetrasiloxane (OMCTS); octasilanes; pentasilanes; silane (SiHzj); T8-hydridospherosiloxane; tert-butoxydisilane; tetraacetoxysilane (Si(OAc)4); tetraethoxysilane (TEOS); tetraisocyanatesilane (TICS); tetramethoxy silane; tetramethoxysiloxane (TMOS); tetramethylcyclotetrasiloxane (TMCTS); tetramethylorthosilicate (TMOS); tetramethylsilane (4MS); tetraoxymethylcyclotetrasiloxane (TOMCTS); tetravinyltetramethylcyclotetrasiloxane (TVTMCTS); triacetoxysilane (SiH(Oac)3); triethoxysilane (TES); triethoxysiloxane (TRIES); trimethoxymethylsilane (TMOMS); trimethoxy silane (TMS or TriMOS); trimethylmethoxy silane (TMMOS); trimethylsilane (3MS); triphenylethoxysilane; trisilane; and tri-t-butoxylsilanol. Further examples of silicon containing precursors include, but are not limited to, silane (SiFU), disilane, trisilane, hexasilane, cyclohexasilane, and alkylsilanes, e.g., methylsilane, and ethylsilane.

[0057] In certain embodiments, carbon-containing silicon precursors are used, either in addition to another precursor (e.g., as a dopant to provide carbon) or as the sole silicon-containing precursor. Carbon-containing precursors can include at least one Si-C bond. Carbon-doped precursors that may be used include, but are not limited to the, following:

R’x-Si-Ry where x = 0-3, x+y = 4, R is a substituted or unsubstituted alkyl group and R’ is a substituted or unsubstituted alkyl, alkoxy or alkoxyalkane group; and SiHxR’y-Rz where x = 1-3, y = 0-2, x+y+z = 4, R is a substituted or unsubstituted alkyl group and R’ is a substituted or unsubstituted alkyl, alkoxy or alkoxyalkane group.

[0058] Examples of carbon-doped precursors are given above with further examples including, but not being limited to, trimethylsilane (3MS), tetramethylsilane (4MS), diethoxymethylsilane (DEMS), dimethyldimethoxysilane (DMDMOS), methyl-triethoxysilane (MTES), methyltrimethoxysilane, methyl-diethoxysilane, methyl-dimethoxysilane, trimethoxymethylsilane, (TMOMS), dimethoxymethylsilane, and bis(trimethylsilyl)carbodiimide.

[0059] In certain embodiments aminosilane precursors are used. Aminosilane precursors include, but are not limited to, the following: H_x-Si-(NR)_y where x = 0-3, x + y = 4 and R is an organic of hydride group.

[0060] Examples of aminosilane precursors are given above, with further examples including, but not being limited to -tert-butylamino silane (BTBAS) or tris(dimethylamino)silane.

[0061] In some embodiments, described further below, a self-catalyzing silane (such as an aminosilane) is used. In some embodiments, also described further below, a photopolymerizable silicon-containing precursor is used.

[0062] Examples of self-catalyzing silanes include aminosilanes. Aminosilanes that may be used include, but are not limited to, the following generic chemical formula: H_x-Si-(NR)_y where x = 0-3, x + y = 4 and R is an organic hydride group. For example, the structure of a self-catalyzing silane may be as follows:

[0063] Examples of self-catalyzing silanes include aminosilanes such as dimethylamino trimethylsilane, dimethylaminotriethylsilane and bisdimethylaminodiethylsilane: dimethylamino trimethylsilane dimethylaminotriethylsilane bisdimethylaminodiethylsilane

[0064] Further examples of self-catalyzing silanes include, but are not limited to, 1, 1,1, 3,3,3- hexamethyldisilazane (CH3)3SiN(H)Si(CH3)3 (HDMS); bis(diethylamino)silane; bis(trimethylsilyl)carbodiimide; bis-tert-butylamino silane (BTBAS); cyclic azasilanes; hexamethyldisilazane (HMDS); methylsilatrane; silatrane; tert-butylamino silane (BTBAS); tetrakis(dimethyllamino)silane; tris(dimethylamino)silane; trisilylamine (TSA); trisdimethylamino methylsilane; trisdimethylamino silane; trismethylamino methylsilane; trismethylamino silane; bisdimethylamino dimethylsilane; bisdimethylamino ethoxy methyl silane; methylamino diethoxy methyl silane; trismethylamino vinyl silane; bismethylamino divinyl silane; bisdimethylamino ethoxy vinyl silane; acetoxy silanes; and combinations thereof.

[0065] In some embodiments, acetoxy silanes may be used as silicon-containing precursors. In some embodiments, the reaction may begin with the deposition of an acetoxy -based precursor, followed by an amine-based catalyst or aminosilane, such as any of those describe above. Example acetoxy-based precursors include, but are not limited to, tetraoxysilane and siloxane: siloxane [0066] In the structure above, Ri , R2, R3, and R4 may be same or different N-alkylamines. Some self-catalyzing silanes may have at least one N alkylamine linked or coordinated directly with the silicon with other organic functional groups forming linkages with the silicon. Different ligands can be chosen up to a total of 4 (including the alkylamine group). Some examples of the different ligands that can be chosen are: N alkyl amine; N,N dialkyl amine; alkoxy; alkyl; alkenyl; alkynyl; aromatic groups; and hydrogen.

[0067] In some embodiments, the dielectric precursor is a silicon-containing compound capable of undergoing photo-induced polymerization. Examples of such compounds include cyclic siloxanes, cyclic silazanes, and linear or cyclic silicon-containing precursors containing vinyl or other unsaturated hydrocarbon groups.

[0068] Examples of cyclic siloxanes include octamethylcyclotetrasiloxane (OMCTS), tetravinyltetramethylcyclotetrasiloxane (TVTMCTS), tetramethylcyclotetrasiloxane (TMCTS), pentamethylcyclopentasiloxane, and hexamethylcyclotrisiloxane. In some embodiments, cyclic siloxanes can be used in the methods described herein for catalyst- free deposition processes. In some embodiments, cyclic silazanes can be used in the methods described herein for catalyst-free deposition processes.

[0069] In some embodiments, dielectric precursors having relatively high boiling points are employed. For example, TMCTS has a boiling point of 135°C, TVTMCTS has a boiling point of 224°C, and OMCTS has a boiling point of 175°C. In some embodiments, dielectric precursors having boiling points of at least 100°C, at least 125°C, at least 150°C, at least 175°C, or at least 200°C are employed. Boiling points are given at atmospheric pressure.

[0070] According to various embodiments, the as-deposited film is a silicon oxide film or a silicon nitride film, including carbon-containing silicon oxide or silicon nitride films. According to various embodiments, Si-C or Si-N containing dielectric precursors may be used, either as a main dielectric precursor or a dopant precursor, to introduce carbon or nitrogen into the film. Examples of such films include carbon doped silicon oxides and silicon oxynitrides. In some embodiments, the silicon nitride film, including primarily Si-N bonds with N-H bonds.

Co-reactant

[0071] For silicon oxide deposition, an oxidant may be employed in some embodiments. In some other embodiments, oxygen may be supplied solely by a cyclic siloxane precursor, for example, such that the deposition is a single reactant deposition, with no co-reactant. However, an oxidant may be supplied depending on the oxygen content of the particular precursor employed.

[0072] If employed, examples of suitable oxidants include, but are not limited to, ozone (O3), peroxides including hydrogen peroxide (H2O2), oxygen (O2), water (H2O), alcohols such as methanol, ethanol, and isopropanol, nitric oxide (NO), nitrous dioxide (NO2) nitrous oxide (N2O), carbon monoxide (CO) and carbon dioxide (CO2). In certain embodiments, a remote plasma generator may supply activated oxidant species.

[0073] For silicon nitride deposition, a nitrogen co-reactant may be employed in some embodiments. In some other embodiments, nitrogen may be supplied solely by a cyclic silazane precursor, for example, such that the deposition is a single reactant deposition, with no co-reactant. If employed, examples of suitable nitrogen co-reactants include, but are not limited to, ammonia (NH3), hydrazine (N2H4), nitrogen (N2), NO, NO2, and N2O.

Dopant

[0074] One or more dopant precursors, e.g., a carbon-, nitrogen-, fluorine-, phosphorous- and/or boron-containing gas, may be supplied. Sometimes, though not necessarily, an inert carrier gas is present. In certain embodiments, the gases are introduced using a liquid injection system. In certain embodiments, carbon-doped silicon precursors are used, either in addition to another precursor (e.g., as a dopant) or alone. Carbon-doped precursors can include at least one Si-C bond. In certain embodiments, aminosilane precursors are used.

Catalyst

[0075] In some embodiments, the deposition may be a catalyst-free deposition that does not employ any one of the below-described catalysts. However, a catalyst may be employed in certain embodiments. In certain embodiments, a proton donor catalyst is employed. Examples of proton donor catalysts include 1) acids including nitric, hydrofluoric, phosphoric, sulfuric, hydrochloric and bromic acids; 2) carboxylic acid derivatives including R-COOH and R-C(=O)X where R is substituted or unsubstituted alkyl, aryl, acetyl or phenol and X is a halide, as well as R-COOC-R carboxylic anhydrides; 3) Si_xX_yH_z where x = 1-2, y = 1-3, z = 1-3 and X is a halide; 4) R_xSi-X_y where x = 1-3 and y = 1-3; R is alkyl, alkoxy, alkoxyalkane, aryl, acetyl or phenol; and X is a halide; and 5) ammonia and derivatives including ammonium hydroxide, hydrazine, hydroxylamine, and R-NH2 where R is substituted or unsubstituted alkyl, aryl, acetyl, or phenol. [0076] In addition to the examples of catalysts given above, halogen-containing compounds which may be used include halogenated molecules, including halogenated organic molecules, such as dichlorosilane (SiChFh), trichlorosilane (SiChH), methylchlorosilane (SiCFfeClHz), chlorotriethoxysilane, chlorotrimethoxysilane, chloromethyldiethoxysilane, chloromethyldimethoxysilane, vinyltrichlorosilane, diethoxydichlorosilane, and hexachlorodisiloxane. Acids which may be used may be mineral acids such as hydrochloric acid (HC1), sulfuric acid (H2SO4), and phosphoric acid (H3PO4); organic acids such as formic acid (HCOOH), acetic acid (CH3COOH), and trifluoroacetic acid (CF3COOH). Bases which may be used include ammonia (NH3) or ammonium hydroxide (NH4OH), phosphine (PH3); and other nitrogen- or phosphorus-containing organic compounds. Additional examples of catalysts are chloro-diethoxysilane, methanesulfonic acid (CH3SO3H), trifluoromethanesulfonic acid (“triflic”, CF3SO3H), chloro-dimethoxysilane, pyridine, acetyl chloride, chloroacetic acid (CH2CICO2H), dichloroacetic acid (CHQ2CO2H), trichloroacetic acid (CO2CO2H), oxalic acid (HO2CCO2H), benzoic acid (C6H5CO2H), and triethylamine.

[0077] Examples of other catalysts include hydrochloric acid (HC1), hydrofluoric acid (HF), acetic acid, trifluoroacetic acid, formic acid, dichlorosilane, trichlorosilane, methyltrichlorosilane, ethyltrichlorosilane, trimethoxychlorosilane, and triethoxychlorosilane.

[0078] In some implementations, halogen-free acid catalysts may be employed, with examples including 1) acids including nitric, phosphoric, sulfuric acids; and 2) carboxylic acid derivatives including R-COOH where R is substituted or unsubstituted alkyl, aryl, acetyl or phenol, as well as R-COOC-R carboxylic anhydrides.

[0079] The halogen-free organic acid catalyst may be a proton donor having a pH between about 1 and about 7, with a pKa between about 1 and about 6. A good proton donor may be a compound that can give up its proton/H+ easily, which results in a higher reaction rate. The pKa is correlated with the speed of the reaction due to the catalyzing nature of the organic acid.

[0080] Halogen-free organic acid catalysts include 1) acids including nitric, phosphoric, sulfuric acids; and 2) carboxylic acid derivatives including R-COOH where R is substituted or unsubstituted alkyl, aryl, acetyl or phenol, as well as R-COOC-R carboxylic anhydrides. These carboxylic acid derivatives may have structures such as the following generic organic structures:

Examples of halogen-free organic acid catalysts include ethylenediaminetetraacetic acid (CioHieNzOs), picric acid (C6H3N3O7), and acetic acid (CH3COOH). Further examples of organic acids that could be used as catalysts include, but are not limited to, tartaric acid (C4H6O6), citric acid (CeHgO?), formic acid (HCOOH), oxalic acid (HO2CCO2H), sulfonic acids (RS(=0)2-0H), benzoic acid (C6H5CO2H), methanesulfonic acid (CH3SO3H), any other substituted derivatives of these acids, or combinations thereof. Some other nonorganic acids could be used in some embodiments, including pyrophosphoric acid (H4P2O7), phosphoric acid (H3PO4), and sulfuric acid (H2SO4). In some embodiments, a fluorine-containing organic acid may be suitable for use, such as triflic acid (CF3SO3H), or trifluoroacetic acid (CF3CO2H), but note that fluorine anions may cause contamination and degradation in the substrate and so may be avoided in other embodiments. In various embodiments, the halogen-free organic acid is photosensitive. A photosensitive catalyst may be identified by comparison of shrinkage (or other cure characteristic) of a film in dark conditions versus under light. For example, an optical mask pattern applied to an uncured flowable oxide film can be translated to the oxide’s thickness profile. Preliminary data from deposition with acetic acid shows photosensitivity with 38% - 45% less shrinkage being observed after thermal cure for wafers kept in the dark compared to control wafers left out under cleanroom fluorescent light. No such behavior is observed for identical tests with chloride catalyzed deposited fdms. In embodiments where operation 402a is performed while the substrate is exposed to UV radiation and a photosensitive halogen-free organic acid is used, the reaction rate may be increased.

Surfactants

[0081] Surfactants may be used to relieve surface tension and increase wetting of reactants on the substrate surface. They may also increase the miscibility of the dielectric precursor with the other reactants, especially when condensed in the liquid phase. Examples of surfactants include solvents, alcohols, ethylene glycol and polyethylene glycol. Difference surfactants may be used for carbon-doped silicon precursors because the carbon-containing moiety often makes the precursor more hydrophobic. [0082] Solvents may be non-polar or polar and protic or aprotic. The solvent may be matched to the choice of dielectric precursor to improve the miscibility in the oxidant. Non-polar solvents include alkanes and alkenes; polar aprotic solvents include acetones and acetates; and polar protic solvents include alcohols and carboxylic compounds.

[0083] Examples of solvents that may be introduced include alcohols, e.g., isopropyl alcohol, ethanol and methanol, or other compounds, such as ethers, carbonyls, nitriles, miscible with the reactants. Solvents are optional and in certain embodiments may be introduced separately or with the oxidant or another process gas. Examples of solvents include, but not limited to, methanol, ethanol, isopropanol, acetone, diethylether, acetonitrile, dimethylformamide, and dimethyl sulfoxide, tetrahydrofuran (THF), dichloromethane, hexane, benzene, toluene, isoheptane and diethylether. The solvent may be introduced prior to the other reactants in certain embodiments, either by puffing or normal delivery. In some embodiments, the solvent may be introduced by puffing it into the reactor to promote hydrolysis, especially in cases where the precursor and the oxidant have low miscibility.

Carrier gases

[0084] Sometimes, though not necessarily, an inert carrier gas is present. For example, helium and/or argon, may be introduced into the chamber with one of the compounds described above.

[0085] Any of the process gases (silicon-containing precursor, oxidant or other co-reactant, solvent, catalyst, etc.) either alone or in combination with one or more other reactants, may be introduced prior to the remaining reactants. Also in certain embodiments, one or more reactants may continue to flow into the reaction chamber after the remaining reactant flows have been shut off.

Reaction Mechanisms

[0086] The deposition methods described herein are not limited to a particular reaction mechanism. For example, the reaction mechanism may involve an adsorption reaction, a hydrolysis reaction, a condensation reaction, a polymerization reaction, a vapor-phase reaction producing a vapor-phase product that condenses, condensation of one or more of the reactants prior to reaction, or a combination of these.

[0087] In some embodiments, deposition into uses a self-catalyzing silane that undergoes hydrolysis and condensation reactions. Various self catalyzing silanes may be aminosilanes. In some implementations, aminosilanes having one or more secondary amines are used. In an example of a reaction mechanism for the hydrolysis of a self-catalyzing silylamine, electrons from the nitrogen in one of the amino groups bond with a hydrogen atom on a water molecule, thereby resulting in the protonation of an -NHR’ ligand and the formation of a negative -OH hydroxide group. The intermediate state has a hydrogen atom bound to the nitrogen of the -NHR’ ligand, thereby forming a slightly positive -NH2R’ amino group. In the next step, a concerted nucleophilic SN 1 attack by a -OH hydroxide group occurs on the silicon center of the compound, along with the cleaving of the NH2R amino leaving group. The last step shows a released R’NH2 amino compound and SiR(NHR’)20H. The steps may be repeated for each of the -NHR’ groups on the silane to form Si(OH)3R. In some embodiments, one or more ligands on the self-catalyzing silane may not react. The significance of the self-catalyzing silane is that the compound has the catalyzing groups already attached to the silane, such that the aminosilane can undergo hydrolysis with water or a proton donor to form the desired intermediate prior to condensation.

[0088] Amines are 19ydrolysable in water, creating a silanol-rich product in a basic medium (e.g., pH > 7) leading to a rapidly catalyzed condensation to give the desired oxide network. The proliferating Si-OH groups proceed to poly condense and form an -Si-O-Si- network with an H2O molecule given off as a co-product with each condensation reaction. By selecting the appropriate self-catalyzing silane, no nitrogen remains in the resulting film as the ammonia or alkyl amine is removed as a by-product.

[0089] The resulting silanol-rich product may undergo a condensation mechanism to form an - Si-O-Si- network. The condensation mechanism may be the condensation mechanism. In some embodiments, some organic ligands on the silanol compound may remain bonded to the silane throughout condensation to yield a carbon-doped silicon oxide compound. Condensation mechanisms may include alcoxolation, oxolation, olation, or any combination of these.

[0090] In some embodiments, a photo-polymerization reaction may occur, with the UV radiation during and/or after film condensation on the substrate. In some embodiments, a reaction may proceed by a radical-chain mechanism. The radical initiation mechanism is possibly (but not limited to) an adsorbate-based radical which adds across oxidizable neighbors such as unsaturated hydrocarbon bonds (such as terminal vinyl, hydrides, or halides) on a siloxane ring that constitute the condensed precursor. Radical propagation progresses to generate a polymer film out of the condensed liquid and release H radicals that recombine to release H2 gas or terminal hydride on reactor surfaces. The final product is a dense low-k oxide film devoid of unsaturated hydrocarbons. [0091] In some embodiments, ring opening and polymerization may include photo dissociation of small amounts of water:

H2O + UV (wavelength less than 242.5) -> H⁺ + OH"

[0092] The ring opening and polymerization reactions may proceed with a hydroxyl anion generated by the photodissociation attacks a silicon atom of a siloxane ring, which results in the ring opening. Polymerization may then proceed by a SiO" attack on another siloxane ring, resulting in opening that ring and polymerizing.

[0093] The above-described photo-mediated mechanisms are distinct from sol gel deposition reactions where a precursor and an oxidizer are introduced and condensed onto a substrate where they are allowed to react via hydrolysis and polycondensation to form an oxide film with water and alcohol as byproducts. Advantages to certain described embodiments include reduced or eliminated reliance on post deposition film processing such as thermal or UV cure for film densification and removal of reaction byproducts, excess reactants and adsorbed residual hydroxyl groups to attain the desired physical and electrical properties. As noted above, in some embodiments, the described methods allow flowable dielectric deposition without a catalyst and with a halide-free chemistry.

[0094] By contrast, hydrolysis and polycondensation depositions may include use of catalysts that could oxidize metallic components of integrated structures. A radical chain reaction mechanism also has a significantly more rapid rate of deposition that a hydrolysispolycondensation reaction.

Reaction conditions

[0095] Reactions conditions can be such that the dielectric precursor, or a vapor phase product of a reaction thereof, condenses on the substrate surface to form a flowable film. Chamber pressure may be between about 1 and 200 Torr, in certain embodiments, it is between 10 and 75 Torr. In a particular embodiment, chamber pressure is about 10 Torr.

[0096] Substrate temperature is between about -20°C and 100°C in certain embodiments. In certain embodiments, temperature is between about -20°C and 30°C, e.g., between -10°C and 10°C. Pressure and temperature may be varied to adjust deposition time; high pressure and low temperature are generally favorable for quick deposition. High temperature and low pressure will result in slower deposition time. Thus, increasing temperature may involve increasing pressure. In one embodiment, the temperature is about 5°C and the pressure about 10 Torr. Exposure time depends on reaction conditions as well as pore or other gap size. Deposition rates are from about 100 angstroms/min to 1 micrometer/min according to various embodiments. The substrate is exposed to the reactants under these conditions for a period long enough to deposit a flowable film in the pores or other gaps. In certain embodiments, deposition time is 0.1-5 seconds.

[0097] The amount of condensation may be controlled by the reactants’ partial pressures relative to their saturated vapor pressures (which are constant for a given deposition temperature).

Pre- treatment

[0098] According to various embodiments, a pretreatment operation involves exposure to a plasma containing oxygen, nitrogen, helium or some combination of these. The plasma may be downstream or in-situ, generated by a remote plasma generator, such as an Astron® remote plasma source, an inductively-coupled plasma generator or a capacitively-coupled plasma generator. Examples of pre-treatment gases include O2, O3, H2O, NO, NO2, N2O, H2, N2, He, Ar, and combinations thereof, either alone or in combination with other compounds. Examples of chemistries include O2, O2/N2, 02/He, 02/Ar, O2/H2 and H2/He. The particular process conditions may vary depending on the implementation. In alternate embodiments, the pretreatment operation involves exposing the substrate to O2, O2/N2, 02/He, 02/Ar or other pretreatment chemistries, in a non-plasma environment. The particular process conditions may vary depending on the implementation. In these embodiments, the substrate may be exposed to the pretreatment chemistry in the presence energy from another energy source, including a thermal energy source, a ultra-violet source, a microwave source, etc. In certain embodiments, in addition to or instead of the pretreatment operations described above, a substrate is pretreated with exposure to a catalyst, surfactant, or adhesion-promoting chemical. The pre-treatment operation, if performed, may occur in the deposition chamber or may occur in another chamber prior to transfer of the substrate to the deposition chamber. Once in the deposition chamber, and after the optional pre-treatment operation, process gases are introduced.

[0099] Surface treatments to create hydrophilic surfaces that can be wet and nucleate evenly during deposition are described in U.S. Patent Application No. 14/519,400, titled “Treatment For Flowable Dielectric Deposition On Substrate Surfaces,” incorporated by reference herein. As described therein, the surface treatments may involve exposure to a remote plasma. [0100] In the same or other environments, a pre-treatment may be performed to inhibit deposition on the field regions and/or at the tops of gaps. In some embodiments, an inhibition plasma is used to creates a passivated surface and increase a nucleation barrier of the deposited liquid film. In some such embodiments, the inhibition plasma is generated from an inhibition gas generated from one of a fluorine-containing compound (such as nitrogen trifluoride (NF3), molecular nitrogen (N2), argon (Ar), helium (He), molecular hydrogen (H2), ammonia (NH3), an amine, a diol, an aminoalcohol, a thiol, or a combination thereof.

Planarization

[0101] As described above, the planarization is a non-contact planarization. In some embodiments, it is performed in the same chamber as the deposition. In some embodiments, the substrate is spun to planarize the vapor-deposited material. In some embodiments, the vapor- deposited material is subject to sonic energy (e.g., acoustic vibration at any appropriate frequency). In some embodiments, the vapor-material is subject to ultrasonic or megasonic waves. One or more of these techniques may be used to planarize the material.

[0102] In some embodiments, the vapor-deposited material is maintained at a temperature (e.g., below 100°C, below 50°C, or below 0°C) during the planarization to help maintain its flowable state prior to solidication.

Solidification

[0103] The film may be cured by purely thermal anneal, exposure to a downstream or direct plasma, exposure to ultraviolet or microwave radiation or exposure to another energy source. Thermal anneal temperatures may be 300°C or greater (depending on the allowable thermal budget). The treatment may be performed in an inert environment (Ar, He, etc.) or in a potentially reactive environment. Oxidizing environments (using O2, N2O, O3, H2O, H2O2, NO, NO2, CO, CO2 etc.) may be used, though in certain situation nitrogen-containing compounds will be avoided to prevent incorporation of nitrogen in the film. In other embodiments, nitridizing environments (using N2, N2O, NH3, NO, NO2 etc.) can be used and can incorporate a certain amount of nitrogen in the film. In some embodiments, a mix of oxidizing and nitridizing environments are used. Carbon -containing chemistries may he used to incorporate some amount of carbon into the deposited film. According to various embodiments, the composition of the densified film depends on the as-deposited film composition and the treatment chemistry. For example, in certain embodiments, an Si(OH)_x as-deposited gel is converted to a SiO network using an oxidizing plasma cure. In other embodiments, an Si(OH)x as-deposited gel is converted to a SiON network. In other embodiments, an Si(NH)x as-deposited gel is converted to an SiON network.

[0104] In certain embodiments, the film is cured by exposure to a plasma, either remote or direct (inductive or capacitive). This may result in a top-down conversion of the flowable film to a densified solid film. The plasma may be inert or reactive. Helium and argon plasma are examples of inert plasmas; oxygen and steam plasmas are examples of oxidizing plasmas (used for example, to remove carbon as desired). Hydrogen-containing plasmas may also be used. An example of a hydrogen-containing plasma is a plasma generated from a mix of hydrogen gas (H2) and a diluent such as inert gas. Temperatures during plasma exposure are typically about 25°C or higher. In certain embodiments, an oxygen or oxygen-containing plasma is used to remove carbon. In some embodiments, temperature during plasma exposure can be lower, e.g., -15°C to 25^oC.

[0105] Temperatures during cures may range from 0-600°C, with the upper end of the temperature range determined by the thermal budget at the particular processing stage. In certain embodiments, the temperatures range from about 200°C-^55o°^c. Pressures may be from 0. 1-10 Torr, with high oxidant pressures used for removing carbon.

[0106] Other annealing processes, including rapid thermal processing (RTP) may also be used to solidify and shrink the film. If using an ex situ process, higher temperatures and other sources of energy may be employed. Ex situ treatments include high temperature anneals (700-1000°C) in an environment such as N2, O2, H2O, Ar and He. In certain embodiments, an ex situ treatment involves exposing the film to ultraviolet radiation, e.g., in an ultraviolet thermal processing (UVTP) process. For example, temperatures of 100°C, or above, e.g., 100°C-400°C, in conjunction with UV exposure may be used to cure the film. Other flash curing processes, including RTP or laser anneal, may be used as well.

[0107] Substrate temperature throughout the deposition and simultaneous or subsequent UV or plasma exposure may be maintained at a level below the boiling point of the dielectric precursors and reaction products thereof. Pressure throughout the deposition and simultaneous or subsequent plasma or UV exposure may be sub-atmospheric. Example UV intensities include 50 W to 500 W of 253.7 nm UV from a broadband (190 nm to 290 nm) source. Apparatus

[0108] Figure 8 shows an example of a deposition chamber for flowable dielectric deposition. A deposition chamber 800 (also referred to as a reactor, or reactor chamber) includes chamber housing 802, top plate 804, skirt 806, showerhead 808, pedestal column 824, and seal 826 provide a sealed volume for flowable dielectric deposition. Wafer 810 is supported by chuck 812 and insulating ring 814. Chuck 812 includes RF electrode 816 andresistiveheater element 818. Chuck 812 and insulating ring 814 are supported by pedestal 820, which includes platen 822 and pedestal column 824. Pedestal column 824 passes through seal 826 to interface with a pedestal drive (not shown). Pedestal column 824 includes platen coolant line 828 and pedestal purge line 830. Showerhead 808 includes co-reactant-plenum 832 and precursor-plenum 834, which are fed by co-reactant-gas line 836 and precursor-gas line 838, respectively. Co-reactant-gas line 836 and precursor-gas line 838 may be heated prior to reaching showerhead 808 in zone 840. While a dualflow plenum is described herein, a single-flow plenum may be used to direct gas into the chamber. For example, reactants may be supplied to the showerhead and may mix within a single plenum before introduction into the reactor. 820' and 820 refer to the pedestal, but in a lowered (820) and raised (820') position.

[0109] The chamber is equipped with, or connected to, gas delivery system for delivering reactants to reactor chamber 800. A gas delivery system may supply chamber 810 with one or more co-reactants, such as oxidants, including water, oxygen, ozone, peroxides, alcohols, etc. which may be supplied alone or mixed with an inert carrier gas. The gas delivery system may also supply chamber with one or more dielectric precursors, for example triethoxy silane (TES), which may be supplied alone or mixed with an inert carrier gas. The gas delivery system is also configured to deliver one or more treatment reagents, for plasma treatment as described herein reactor cleaning. For example, for plasma processing, hydrogen, argon, nitrogen, oxygen or other gas may be delivered.

[0110] Deposition chamber 800 serves as a sealed environment within which flowable dielectric deposition may occur. In many embodiments, deposition chamber 800 features a radially symmetric interior. Reducing or eliminating departures from a radially symmetric interior helps ensure that flow of the reactants occurs in a radially balanced manner over wafer 810. Disturbances to the reactant flows caused by radial asymmetries may cause more or less deposition on some areas of wafer 810 than on other areas, which may produce unwanted variations in wafer uniformity. [0111] Deposition chamber 800 includes several main components. Structurally, deposition chamber 800 may include a chamber housing 802 and a top plate 804. Top plate 804 is configured to attach to chamber housing 802 and provide a seal interface between chamber housing 802 and a gas distribution manifold/showerhead, electrode, or other module equipment. Different top plates 804 may be used with the same chamber housing 802 depending on the particular equipment needs of a process.

[01 12] Chamber housing 802 and top plate 804 may be machined from an aluminum, such as 6061-T6, although other materials may also be used, including other grades of aluminum, aluminum oxide, and other, non-aluminum materials. The use of aluminum allows for easy machining and handling and makes available the elevated heat conduction properties of aluminum.

[0113] Top plate 804 may be equipped with a resistive heating blanket to maintain top plate 804 at a desired temperature. For example, top plate 804 may be equipped with a resistive heating blanket configured to maintain top plate 804 at a temperature of between -20°C and 100°C. Alternative heating sources may be used in addition to or as an alternative to a resistive heating blanket, such as circulating heated liquid through top plate 804 or supplying top plate 804 with a resistive heater cartridge.

[0114] Chamber housing 802 may be equipped with resistive heater cartridges configured to maintain chamber housing 802 at a desired temperature. Other temperature control systems may also be used, such as circulating heated fluids through bores in the chamber walls.

[0115] The chamber interior walls may be temperature-controlled during flowable dielectric to a temperature between -20°C and 100°C. In some implementations, top plate 804 may not include heating elements and may instead rely on thermal conduction of heat from chamber resistive heater cartridges to maintain a desired temperature. Various embodiments may be configured to temperature-control the chamber interior walls and other surfaces on which deposition is undesired, such as the pedestal, skirt, and showerhead, to a temperature approximately 10°C to 40°C higher than the target deposition process temperature. In some implementations, these components may be held at temperatures above this range.

[01 16] Through actively heating and maintaining deposition chamber 800 temperature during processing, the interior reactor walls may be kept at an elevated temperature with respect to the temperature at which wafer 810 is maintained. Elevating the interior reactor wall temperature with respect to the wafer temperature may minimize condensation of the reactants on the interior walls of deposition chamber 800 during flowable film deposition. If condensation of the reactants occurs on the interior walls of deposition chamber 800, the condensate may form a deposition layer on the interior walls, which is undesirable.

[0117] In addition to, or alternatively to, heating chamber housing 802 and/or top plate 804, a hydrophobic coating may be applied to some or all of the wetted surfaces of deposition chamber 800 and other components with wetted surfaces, such as pedestal 820, insulating ring 814, or platen 822, to prevent condensation. Such a hydrophobic coating may be resistant to process chemistry and processing temperature ranges, e.g., a processing temperature range of -20°C to 100°C. Some silicone-based and fluorocarbon-based hydrophobic coatings, such as polyethylene, may not be compatible with an oxidizing, e.g., plasma, environment and may not be suitable for use. Nanotechnology based coatings with super-hydrophobic properties may be used; such coatings may be ultra-thin and may also possess oleophobic properties in addition to hydrophobic properties, which may allow such a coating to prevent condensation as well as deposition of many reactants, used in flowable film deposition. One example of a suitable super-hydrophobic coating is titanium dioxide (TiO₂).

[0118] Various thermal breaks may separate various components of the chamber 800. As used herein, a thermal break refers to a physical separation, i.e., gap, between parts which is sufficiently large enough to substantially prevent conductive heat transfer between the parts via any gases trapped within the thermal break yet which is also sufficiently small enough to prevent substantial convective heat transfer between the parts via the gases. Parts or portions of parts which are either in direct contact, or which are separated by a gap but which are still sufficiently close enough together to experience significant conductive heat transfer across the gap via any gases trapped within the gap, may be referred to as being in “thermal contact” with each other.

[0119] Deposition chamber 800 may also include one or more energy sources embedded within or mounted to the deposition chamber 800, such as UV sources for cure or sonic or vibrational energy sources for planarization. In some embodiments, the pedestal or other substrate support is configured to rotate. In certain embodiments, a controller 850 is employed to control process conditions during deposition, planarization, and solidification.

[0120] A schematic example of a chamber including a rotatable substate support and energy sources embedded in the showerhead is shown in Figure 9. Chamber 901 includes a showerhead 903; similar to showerhead 808 in the example of Figure 8, showerhead 903 has one or more plenums 905 for introducing reactant gases to form a flowable film. Further, energy sources 907 are embedded within or mounted on the showerhead 903 to provide energy to the substrate. For example, energy sources 907 may be UV sources. The showerhead 903 may be designed such that the energy sources 907 and gas openings are in a regular pattern such that gas delivery and energy exposure are fairly uniform across a substrate in the chamber. A pedestal 913 is configured to support a substrate. In some embodiments, the pedestal 913, or a support thereon, is rotatable such that a substrate can be rotated for planarization of a flowable film and/or for uniform energy exposure.

[0121] As indicated above with respect to Figure 8, in certain embodiments, a controller 850 is employed to control process conditions. Such a controller may be used to control operations in any of the apparatuses depicted in Figures 8 and 9.

[0122] The controller 850 will typically include one or more memory devices and one or more processors. The processor may include a CPU or computer, analog and/or digital input/output connections, stepper motor controller boards, etc. Typically there will be a user interface associated with controller 850. The user interface may include a display screen, graphical software displays of the apparatus and/or process conditions, and user input devices such as pointing devices, keyboards, touch screens, microphones, etc.

[0123] In certain embodiments, the controller 850 may also control all of the activities during the process, including gas flow rate, chamber pressure, generator process parameters. The controller 850 executes system control software including sets of instructions for controlling the timing, mixture of gases, chamber pressure, pedestal (and substrate) temperature, UV power, and other parameters of a particular process. The controller 850 may also control concentration of various process gases in the chamber by regulating valves, liquid delivery controllers and MFCs in the delivery system as well as flow restriction valves and the exhaust line. The controller 850 executes system control software including sets of instructions for controlling the timing, flow rates of gases and liquids, chamber pressure, substrate temperature, UV power, and other parameters of a particular process. Other computer programs stored on memory devices associated with the controller may be employed in some embodiments. In certain embodiments, the controller 850 controls the transfer of a substrate into and out of various components of the apparatuses.

[0124] The computer program code for controlling the processes in a process sequence can be written in any conventional computer readable programming language: for example, assembly language, C, C++, Pascal, Fortran or others. Compiled object code or script is executed by the processor to perform the tasks identified in the program. The system software may be designed or configured in many different ways. For example, various chamber component subroutines or control objects may be written to control operation of the chamber components necessary to carry out the described processes. Examples of programs or sections of programs for this purpose include process gas control code and pressure control code.

[0125] In some implementations, the controller 850 is part of a system, which may be part of the above-described examples. Such systems can include semiconductor processing equipment, including a processing tool or tools, chamber or chambers, a platform or platforms for processing, and/or specific processing components (a wafer pedestal, a gas flow system, etc.). These systems may be integrated with electronics for controlling their operation before, during, and after processing of a semiconductor wafer or substrate. The electronics may be referred to as the “controller,” which may control various components or subparts of the system or systems. The controller 850, depending on the processing requirements and/or the type of system, may be programmed to control any of the processes disclosed herein, including the delivery of processing gases, temperature settings (e.g., heating and/or cooling), pressure settings, vacuum settings, power settings, radio frequency (RF) generator settings, RF matching circuit settings, frequency settings, flow rate settings, fluid delivery settings, rotational speed settings, UV power and duty cycle settings, vibration settings, sonic energy source power and duty cycle, positional and operation settings, wafer transfers into and out of a tool and other transfer tools and/or load locks connected to or interfaced with a specific system.

[0126] Broadly speaking, the controller 850 may be defined as electronics having various integrated circuits, logic, memory, and/or software that receive instructions, issue instructions, control operation, enable cleaning operations, enable endpoint measurements, and the like. The integrated circuits may include chips in the form of firmware that store program instructions, digital signal processors (DSPs), chips defined as application specific integrated circuits (ASICs), and/or one or more microprocessors, or microcontrollers that execute program instructions (e.g., software). Program instructions may be instructions communicated to the controller 850 in the form of various individual settings (or program files), defining operational parameters for carrying out a particular process on or for a semiconductor wafer or to a system. The operational parameters may, in some embodiments, be part of a recipe defined by process engineers to accomplish one or more processing steps during the fabrication of one or more layers, materials, metals, oxides, silicon, silicon dioxide, surfaces, circuits, and/or dies of a wafer. [0127] The controller 850, in some implementations, may be a part of or coupled to a computer that is integrated with, coupled to the system, otherwise networked to the system, or a combination thereof. For example, the controller 850 may be in the “cloud” or all or a part of a fab host computer system, which can allow for remote access of the wafer processing. The computer may enable remote access to the system to monitor current progress of fabrication operations, examine a history of past fabrication operations, examine trends or performance metrics from a plurality of fabrication operations, to change parameters of current processing, to set processing steps to follow a current processing, or to start a new process. In some examples, a remote computer (e.g. a server) can provide process recipes to a system over a network, which may include a local network or the Internet. The remote computer may include a user interface that enables entry or programming of parameters and/or settings, which are then communicated to the system from the remote computer. In some examples, the controller 850 receives instructions in the form of data, which specify parameters for each of the processing steps to be performed during one or more operations. It should be understood that the parameters may be specific to the type of process to be performed and the type of tool that the controller 850 is configured to interface with or control. Thus as described above, the controller 850 may be distributed, such as by comprising one or more discrete controllers that are networked together and working towards a common purpose, such as the processes and controls described herein. An example of a distributed controller for such purposes would be one or more integrated circuits on a chamber in communication with one or more integrated circuits located remotely (such as at the platform level or as part of a remote computer) that combine to control a process on the chamber.

[0128] Without limitation, example systems may include a plasma etch chamber or module, a deposition chamber or module, a spin-rinse chamber or module, a metal plating chamber or module, a clean chamber or module, a bevel edge etch chamber or module, a physical vapor deposition (PVD) chamber or module, a chemical vapor deposition (CVD) chamber or module, an atomic layer deposition (ALD) chamber or module, an atomic layer etch (ALE) chamber or module, an ion implantation chamber or module, a track chamber or module, a UV exposure chamber or module, and any other semiconductor processing systems that may be associated or used in the fabrication and/or manufacturing of semiconductor wafers.

[0129] As noted above, depending on the process step or steps to be performed by the tool, the controller 850 might communicate with one or more of other tool circuits or modules, other tool components, cluster tools, other tool interfaces, adjacent tools, neighboring tools, tools located throughout a factory, a main computer, another controller, or tools used in material transport that bring containers of wafers to and from tool locations and/or load ports in a semiconductor manufacturing factory.

[0130] The controller parameters relate to process conditions such as, for example, timing of each operation, pressure inside the chamber, substrate temperature, process gas flow rates, wafer rotational speed, etc. These parameters are provided to the user in the form of a recipe, and may be entered utilizing the user interface. Signals for monitoring the process may be provided by analog and/or digital input connections of the controller 850. The signals for controlling the process are output on the analog and digital output connections of the apparatus.

[0131] The disclosed methods and apparatuses may also be implemented in systems including lithography and/or patterning hardware for semiconductor fabrication. Further, the disclosed methods may be implemented in a process with lithography and/or patterning processes preceding or following the disclosed methods. The apparatus/process described hereinabove may be used in conjunction with lithographic patterning tools or processes, for example, for the fabrication or manufacture of semiconductor devices, displays, LEDs, photovoltaic panels and the like. Typically, though not necessarily, such tools/processes will be used or includes together in a common fabrication facility. Lithographic patterning of a film typically comprises some or all of the following steps, each step enabled with a number of possible tools: (1) application of photoresist on a workpiece, i.e., substrate, using a spin-on or spray-on tool; (2) curing of photoresist using a hot plate or furnace or UV curing tool; (3) exposing the photoresist to visible or UV or x-ray light with a tool such as a wafer stepper; (4) developing the resist so as to selectively remove resist and thereby pattern it using a tool such as a wet bench; (5) transferring the resist pattern into an underlying film or workpiece by using a dry or plasma-assisted etching tool; and (6) removing the resist using a tool such as an RF or microwave plasma resist stripper.

[0132] Although the foregoing invention has been described in some detail for purposes of clarity of understanding, it will be apparent that certain changes and modifications may be practiced within the scope of the appended claims. It should be noted that there are many alternative ways of implementing the processes described herein. Accordingly, the present embodiments are to be considered as illustrative and not restrictive, and the invention is not to be limited to the details given herein.

Claims

In the Claims

1. A method comprising: introducing one or more vapor phase reactants to a chamber housing a substrate having a non-planar topography including field regions and gaps between field regions; from the one or more vapor phase reactants, forming a flowable film on the substrate to fill the gaps and form a flowable overburden film on the field regions; applying a non-contact force to planarize the flowable overburden film.

2. The method of claim 1, wherein applying a non-contact force comprises spinning the substrate.

3. The method of claim 1, wherein the flowable film is a silicon-containing film.

4. The method of claim 1 , further comprising removing the planarized overburden film.

5. The method of claim 4, wherein filling the gaps, planarizing the overburden film, and removing the planarized overburden film is performed without performing chemical-mechanical planarization (CMP).

6. The method of claim 1 , wherein forming a flowable film on the substrate to fill the gaps and form a flowable overburden film on the field regions comprises a first stage and a second stage, wherein at least one of a vapor phase reactant partial pressure, a substrate temperature, a vapor phase reactant flow rate differs from the first stage to the second stage.

7. The method of claim 1, wherein forming a flowable film on the substrate to fill the gaps and form a flowable overburden film on the field regions comprises selectively depositing the flowable film in at least some of the gaps by capillary condensation.

8. The method of claim 7, further comprising, after depositing the flowable film in at least some of the gaps by capillary condensation, changing one or more process conditions to deposit the flowable film in the remainder of the gaps.

9. The method of claim 7, further comprising, after depositing the flowable film in at least some of the gaps by capillary condensation, changing one or more process conditions to deposit the flowable overburden film.

10. The method of claim 1, further comprising inhibiting deposition on the field regions prior to forming a flowable film to fill the gaps.

11. The method of claim 1 , further comprising solidifying the flowable overburden film.

12. The method of claim 11, wherein the flowable overburden film is at least partially solidified during planarization.

13. The method of claim 1, wherein the flowable film and flowable overburden film are solvent-free as deposited.

14. The method of claim 1, wherein applying a non-contact force comprises vibrating the substrate.

15. The method of claim 1, wherein applying a non-contact force comprises exposing the substrate to sonic energy.