WO2025158697A1 - Field-effect transistor with multiple work function gate - Google Patents

Abstract

Structures, and methods for making such structures, for metal-oxide-semiconductor field-effect transistors (MOSFETs) that have gate structures having multiple work function regions. More specifically, within each MOSFET made in accordance with the present invention, the gate material above a gate oxide is differentially doped in vertically-striped regions so as to exhibit different work functions per region, resulting in a substantial improvement (over 20% in some embodiments) in the drain-to-source breakdown voltage V_BD of the device. The higher V_BD means that fewer multiple work function MOSFETs are needed in a series stack to withstand a specified voltage compared to a stack of conventional MOSFETs, allowing a reduction in IC size. Alternatively, a single multiple work function MOSFET may be designed with a shorter gate length L_G to withstand the same voltage as a single conventional MOSFET, but should exhibit a lower R_ON due to the shorter gate length L_G.

Description

FIELD-EFFECT TRANSISTOR WITH MULTIPLE WORK FUNCTION GATE

This invention relates to transistor devices, and more particularly to field effect transistors.

Virtually all modern electronic products (including laptop computers, mobile telephones, and electric cars) utilize metal-oxide-semiconductor field-effect transistors (MOSFETs) fabricated as part of integrated circuits (ICs). In many cases, MOSFET ICs are fabricated using a semiconductor-on-insulator (SOI) structure in place of conventional “bulk” silicon substrates in semiconductor manufacturing. More specifically, SOI transistors are generally fabricated in and on a crystalline semiconductor layer formed on an electrically insulating layer (often called a “buried oxide” or “BOX” layer), which in turn is formed on a bulk substrate. The BOX layer reduces certain parasitic effects typical of bulk silicon MOSFET processes, thereby improving performance, particularly for radio frequency (RF) applications. SOI substrates have many benefits over bulk silicon substrates, including higher speed, lower power consumption, improved RF performance, and improved radiation resistance.

In many IC applications, electrically-isolated pairs of N-type MOSFETs (“nFETs”) and P-type MOSFETs (“pFETs”) form complementary metal-oxide-semiconductor (CMOS) FETs. CMOS FETs are often the preferred building blocks for RF and logic circuits due to their scalability, low power, and design flexibility.

FIG. 1 is a cross-sectional stylized view of a typical prior art enhancement-mode nFET 100 (note that the dimensions of various elements are not to scale). In the illustrated example, an Active Region 102 is formed on a buried oxide (BOX) layer 104 (e.g., SiO₂) formed on top of a substrate 106. The Active Region 102 may comprise, for example, crystalline Si, Ge, or an SiGe alloy or layered mixture. The substrate 106 may comprise, for example, silicon or sapphire. The BOX layer 104 and Active Region 102 may be considered to be a substructure 107 formed on the substrate 106.

A self-aligned N-type source region 108 and self-aligned N-type drain region 110 are formed in the Active Region 102 adjacent to an overlying gate structure 112 and between isolation structures 114. The isolation structures 114 may be, for example, shallow trench isolation (STI) structures formed from, for example, SiO₂. In some embodiments, optional regions (not shown) may be fabricated within the Active Region 102 near the side edges of the gate structure 112, such as halo implants and/or lightly-doped drain (LDD) implants (for example, to control short-channel effects).

The gate structure 112 overlies a channel region (also referred to as the “body”) between the source region 108 and the drain region 110 comprising a doped semiconductor region 116 (P-type in this example, commonly referred to as a “P-well”) within the Active Region 102. The gate structure 112 generally comprises an insulator 118 (e.g., an SiO₂ layer, commonly referred to as a “gate oxide” or “GOX”) and overlaying gate material 120 (e.g., N+ or P+ polysilicon, or a replacement metal gate). Offset spacers 122 along both sides of the gate structure 112 may also be formed as part of the fabrication process for making the gate structure 112. Spacers are generally fabricated by depositing an oxide layer over an IC structure and then etching the deposited oxide; oxide deposited on the essentially vertical sidewalls of a gate structure will etch away more slowly than oxide deposited on the surrounding horizontal portions of the IC structure. A salicide (self-aligned silicide) layer (not shown) may be formed over the source region 108, drain region 110, and gate structure 112 to reduce the series resistance to those features. Enhancement mode pFETS have a similar structure, but with different doping characteristics, as do depletion mode nFETs and pFETs.

A superstructure (not shown) may be fabricated on top of the substructure 107 to complete the IC. A superstructure may include, for example, conductive vias, insulating layers (dielectrics), metallization layers, and electrical contacts (pads) for die-to-package connections. For example, FIG. 1 shows stylized electrically conductive contacts S, D, and G made to the source region 108, the drain region 110, and the gate structure 112, respectively, that would be fabricated as part of the IC superstructure. Other common IC structures are omitted for clarity. The multiple steps needed for making elements and features of the MOSFET 100 structure, such as masking, doping (via implantation, diffusion, etc.), epitaxy, cleaving, polishing, etc., are well known in the art.

Improving the performance of MOSFETs, particularly as MOSFET structures within ICs shrink to ever smaller dimensions, is of importance to the electronics industry. The present invention encompasses new and improved MOSFET structures and methods for making such structures.

The present invention encompasses structures, and methods for making such structures, for metal-oxide-semiconductor field-effect transistors (MOSFETs) that have gate structures having multiple work function regions. More specifically, within each MOSFET made in accordance with the present invention, the gate material above a gate oxide (GOX) is differentially doped in vertically-striped regions so as to exhibit different work functions per region, resulting in a substantial improvement (over 20% in some embodiments) in the drain-to-source breakdown voltage V_BD of the device. The higher V_BD means that fewer multiple work function MOSFETs are needed in a series stack to withstand a specified voltage compared to a stack of conventional MOSFETs, allowing a reduction in IC size. Alternatively, a single multiple work function MOSFET may be designed with a shorter gate length L_G to withstand the same voltage as a single conventional MOSFET, but should exhibit a lower R_ON due to the shorter gate length L_G.

One embodiment of the invention encompasses a field-effect transistor including a source region, a drain region spaced from the source region, a channel region between the source region and the drain region, and a gate structure overlying the channel region, the gate structure including an insulating layer overlying the channel region and a gate material overlying the insulating layer, wherein the gate material includes a first edge region adjacent the source region and doped to have a first work function, a second edge region adjacent the drain region and doped to have a second work function, and a central region between the first and the second edge regions and doped to have a third work function.

Another embodiment of the invention encompasses a semiconductor-on-insulator field-effect transistor including a substrate, an electrically insulating layer formed on the substrate, an active region formed on the electrically insulating layer, a source region formed in the active region, a drain region formed in the active region and spaced from the source region, a doped well between the source region and the drain region, and a gate structure overlying the doped well and between the source region and the drain region, the gate structure including an insulating layer overlying the channel region and a gate material overlying the insulating layer, wherein the gate material includes a first edge region adjacent the source region and doped to have a first work function, a second edge region adjacent the drain region and doped to have a second work function, and a central region between the first and the second edge regions and doped to have a third work function.

The details of one or more embodiments of the invention are set forth in the accompanying drawings and the description below. Other features, objects, and advantages of the invention should be apparent from the description and drawings, and from the claims.

[FIG. 1] FIG. 1 is a cross-sectional stylized view of a typical prior art enhancement-mode nFET (note that the dimensions of various elements are not to scale).
[FIG. 2] FIG. 2 is a cross-sectional stylized view of a novel enhancement-mode nFET (note that the dimensions of various elements are not to scale).
[FIGS. 3A-3L] FIGS. 3A-3L are cross-sectional stylized views of example fabrication stages for the novel nFET of FIG. 2.
[FIG. 3M] FIG. 3M is a cross-sectional stylized view of an nFET having both a stepped insulator and a gate structure having multiple work function regions N+/P+/N+.
[FIG. 4] FIG. 4 is a cross-sectional stylized view of an alternative fabrication stage for the novel nFET of FIG. 2.
[FIGS. 5A-5H] FIGS. 5A-5H are cross-sectional stylized views of example alternative fabrication stages for the novel nFET of FIG. 2 using a non-self-aligned process for forming the gate structure.
[FIGS. 6A-6C] FIGS. 6A-6C are cross-sectional stylized views of example alternative fabrication stages for the novel nFET of FIG. 2 using a self-aligned process for forming the gate structure.
[FIGS. 7A-7H] FIGS. 7A-7H are cross-sectional stylized views of example fabrication stages for an nFET including a first multiple work function gate structure fabricated using self-aligned edge gate regions.
[FIGS. 8A-8E] FIGS. 8A-8E are cross-sectional stylized views of example fabrication stages for an nFET including a second multiple work function gate structure fabricated using self-aligned edge gate regions and a stepped gate insulator.
[FIG. 9] FIG. 9 is a top plan view of a substrate that may be, for example, a printed circuit board or chip module substrate (e.g., a thin-film tile).
[FIG. 10] FIG. 10 is a process flow chart showing one method of fabricating a field-effect transistor.
[FIG. 11] FIG. 11 is a process flow chart showing one method of fabricating a semiconductor-on-insulator field-effect transistor.
[FIG. 12] FIG. 12 is a process flow chart showing one method of fabricating a semiconductor-on-insulator field-effect transistor using self-aligned edge gate regions.
Like reference numbers and designations in the various drawings indicate like elements unless the context requires otherwise.

The present invention encompasses structures, and methods for making such structures, for metal-oxide-semiconductor field-effect transistors (MOSFETs) that have gate structures having multiple work function regions. More specifically, within each MOSFET made in accordance with the present invention, the gate material above a gate oxide (GOX) is differentially doped in vertically-striped regions so as to exhibit different work functions per region. The resulting device exhibits a substantial improvement (over 20% in some embodiments) in the drain-to-source breakdown voltage V_BD of the device while attaining an excellent R_ON*C_OFF figure of merit.

An advantage of the higher breakdown voltage V_BD of MOSFETs having a multiple work function gate structure compared to conventional MOSFETs is that fewer multiple work function MOSFETs are needed in a series stack of devices to withstand a specified voltage compared to a stack of conventional MOSFETs, allowing a reduction in IC size. Alternatively, a single multiple work function MOSFET may be designed with a shorter gate length L_G to withstand the same voltage as a single conventional MOSFET, but the multiple work function MOSFET should exhibit a lower R_ON due to the shorter gate length L_G, thus consuming less power and improving performance (especially RF performance).

In some fabrication technologies, the gate length L_G of constituent MOSFETs is a significant factor in determining the layout density of an IC die. Again, multiple work function MOSFETs may be designed with a shorter gate length L_G to withstand the same voltage as conventional MOSFETs. The use of multiple work function MOSFET with a short gate length L_G in such fabrication technologies enables denser layouts and thus smaller ICs.

FIG. 2 is a cross-sectional stylized view of a novel enhancement-mode nFET 200 (note that the dimensions of various elements are not to scale). Similar in many aspects to the nFET 100 of FIG. 1, the novel nFET 200 of FIG. 2 differs by including a modified gate structure 202 having a length L_G and comprising multiple work function regions (doped gate regions 204a, 204b, 204c in this example). In the illustrated example, edge gate regions 204a and 204c are N+ doped, while central gate region 204b is P+ doped. Enhancement mode pFETS, depletion mode nFETs, and depletion mode pFETs would have a similar structure, but with different doping patterns (e.g., P+/N+/P+ for pFETs). Note that edge gate regions 204a and 204c may be doped to the same concentration to have the same work function, or may be doped to different concentrations to have different work functions. While FIG. 2 shows three gate regions 204a-204c, in some embodiments it may be useful to have more than three gate regions within a single unitary gate structure 202.

The configuration shown in FIG. 2 is particularly suitable for use with switches, in which the “drain” input may change sides during operation, thus necessitating that both edge gate regions 204a and 204c be symmetric. For applications like amplifiers where the flow of current is unidirectional (and thus have a “stationary” drain) only one edge gate regions (e.g., just 204c) may be used.

It has been found that altering the work function of the central gate region 204b by doping with a P+ dopant rather than an N+ dopant raises the threshold voltage V_TH of the nFET 200 by about 1 volt compared to a MOSFET fabricated in a similar process but with a conventional gate structure 112 (as in FIG. 1). As noted above, the breakdown voltage V_BD of the inventive device increases by over 20% in some embodiments, a substantial improvement compared to MOSFETs having a conventional gate structure 112.

The respective lengths a1, b1, a2 (in the X dimension) of gate regions 204a, 204b, 204c may depend on the manufacturing process used to fabricate the nFET 200. In general, it may be useful for b1 to be equal to or less than about 75% of a1 + a2. In one process, a1 and a2 may each be equal to or greater than about 40nm, while b1 may be equal to or greater than about 60nm. The boundaries between the gate regions 204a, 204b, 204c may be varied (within the limits of a selected manufacturing process), and the edge gate regions 204a and 204c need not have the same length (i.e., a1 need not equal a2).

Note that the different work functions may increase the ON resistance, R_ON, of the nFET 200. For example, in one modeled device in which length b1 = a1 + a2 (i.e., the length b1 of central gate region 204b is about 50% of the total gate length L_G in the X dimension), the R_ON for the device may be increased only by about 3.5-5.5%. Other device optimizations may further reduce R_ON.

FIGS. 3A-3L are cross-sectional stylized views of example fabrication stages for the novel nFET of FIG. 2.

FIG. 3A shows a portion of an Active Region 102 formed on a BOX layer 104 (e.g., SiO₂), which is in turn formed on top of a substrate 106 (e.g., Si). Additionally, isolation structures 114 and a doped semiconductor P-well 116 have been formed. In some embodiments, the Active Region 102 may be formed directly on top of a bulk Si substrate 106, thus omitting the BOX layer 104.

FIG. 3B shows that a thin sacrificial oxide layer 302 has been formed, such as by thermal oxidation of the top portion of the P-well 116 (which is Si in this example). The sacrificial oxide layer 302 helps to clean the surface of the P-well 116 and is subsequently etched away, such as by washing with hydrofluoric acid (HF) or buffered HF.

FIG. 3C shows that, after removal of the thin sacrificial oxide layer 302, an oxide layer 304 has been formed (e.g., by thermal oxidation) on the top portion of the P-well 116.

FIG. 3D shows that a layer of photoresist material 306 (e.g., a polymer) has been deposited over the surface of the structure of FIG. 3C.

FIG. 3E shows that the layer of photoresist material 306 and thicker oxide layer 304 have been patterned and etched to define the insulator 118 portion of the final gate structure 202 (see FIG. 3L) above a portion of the P-well 116.

FIG. 3F shows that the remaining photoresist material 306 from FIG. 3E has been removed and that a layer of gate material 308 (e.g., polysilicon) has been deposited on the resulting structure.

FIG. 3G shows that the gate material 308 of FIG. 3F has been patterned and etched to remove any gate material 308 not overlaying the insulator 118.

FIG. 3H shows that a layer of spacer material 310 (e.g., SiO₂) has been formed over the structure of FIG. 3G.

FIG. 3i shows that the spacer material 310 has been formed into spacers 122 on the side edges of the insulator 118 and remaining gate material 308, which together now define a gate structure 202. In subsequent steps, the gate material 308 will be differentially doped in approximately vertical stripes so as to exhibit different work functions, as shown in FIG. 2.

Some embodiments may include extra steps to fabricate regions (not shown) such as halo implants and/or lightly-doped drain (LDD) implants within the Active Region 102 near the side edges of the gate structure 202.

FIG. 3J shows that the structure of FIG. 3i has been patterned to form an implantation mask 312 over a central gate region 204b of the gate structure 202, and that an N+ dopant (e.g., arsenic or phosphorous) has been implanted in the source region 108, the drain region 110, and edge gate regions 204a, 204c adjacent to respective ones of the source and drain regions 108, 110.

FIG. 3K shows that the structure of FIG. 3J has been patterned to form an implantation mask 314 over the edge gate regions 204a, 204c of the gate structure 202 and over the source and drain regions 108, 110. FIG. 3K also shows that a P+ dopant (e.g., boron or boron difluoride) has been implanted in the central gate region 204b between the edge gate regions 204a, 204c and spaced from the source and drain regions 108, 110.

The order of the steps illustrated in FIG. 3J and FIG. 3K may be reversed if desired. That is, the P+ implantation of the central gate region 204b may be performed before the N+ implantation of the edge gate regions 204a, 204c.

FIG. 3L shows that the implantation masks have been removed, and that stylized electrically conductive contacts S, D, and G have been made to the source region 108, the drain region 110, and the gate structure 202, respectively, that would be fabricated as part of an IC superstructure (not otherwise shown). As should be clear, FIG. 3L and FIG. 2 are essentially the same.

In some embodiments, the insulator 118 portion of the gate structure 202 may comprise a stepped structure that lowers the parasitic gate-to-source capacitance C_GS and gate-to-drain capacitance C_GD. For example, FIG. 3M is a cross-sectional stylized view of an nFET having both a stepped insulator 118 and a gate structure 202 having multiple work function regions N+/P+/N+. Stepped insulator structures are taught in U.S. Provisional Patent Application No. 63/520,865, filed on August 21, 2023, entitled “Field-Effect Transistor Having Multiple Gate Oxide Thicknesses”, the contents of which are incorporated by reference.

FIG. 4 is a cross-sectional stylized view of an alternative fabrication stage for the novel nFET of FIG. 2. Focused on just the gate structure 202 after the stage shown in FIG. 3i, FIG. 4 shows that a P+ implantation has been made in the central gate region 204b (e.g., using the masking and implantation steps shown in FIG. 3K). Edge gate regions 204a and 204c have been N+ doped (e.g., by ion implantation) at an angle (e.g., θ and -θ) selected to avoid significant implantation into the central gate region 204b. Since the work function of the gate structure 202 is determined by the nature of the work function material in contact with the insulator 118, some N+ doping of the top portion of the central gate region 204b should not affect performance. After formation of the gate regions 204a-204c, processing may continue as described above.

FIGS. 5A-5G are cross-sectional stylized views of example alternative fabrication stages for the novel nFET of FIG. 2 using a non-self-aligned process for forming the gate structure 202. The stages shown in FIGS. 3A-3C would be followed, leaving a thicker oxide layer 304 formed on the top portion of the P-well 116.

FIG. 5A shows that a layer of gate material 502 (e.g., polysilicon) has been deposited on the resulting structure, followed by deposition of a layer of P+ doped material 504, such as boron-doped glass.

FIG. 5B shows that the P+ doped material 504 has been patterned and etched to form a P+ cap 506 spaced above the insulator 118 by the gate material 502.

FIG. 5C shows that a layer of material 508, such as undoped glass or phosphorous-doped glass or other suitable material, has been formed over the gate material 502 and P+ cap 506 to protect the exposed gate material 502.

FIG. 5D shows that the structure of FIG. 5C has been subjected to an annealing process which causes the P+ dopant (e.g., boron) in the P+ cap 506 to diffuse into the underlying gate material 502 and form a central P+ doped gate region 204b.

FIG. 5E shows that the layer of material 508 and the P+ cap 506 of FIG. 5D have been etched away.

FIG. 5F shows that the gate material 502 and insulator 118 have been etched to form a gate structure 202, and spacers 122 have been formed on the sides of the gate structure 202 as described above (see FIGS. 3H and 3i).

FIG. 5G shows that an N+ dopant (e.g., arsenic or phosphorous) has been implanted in the source region 108, the drain region 110, and the edge gate regions 204a, 204c adjacent to respective ones of the source and drain regions 108, 110. In some embodiments, an optional implantation shield 510 of photoresist or the like may be patterned and etched to define a protective cover over the central P+ doped gate region 204b, such as when the P+ doping concentration needs to be maintained at a high level and not diluted by the N+ implantation.

FIG. 5H shows that any implantation shields have been removed, and that stylized electrically conductive contacts S, D, and G have been made to the source region 108, the drain region 110, and the gate structure 202, respectively, that would be fabricated as part of an IC superstructure (not otherwise shown). As should be clear, FIG. 5H and FIG. 3L are essentially the same.

As an alternative to the implantation stage shown in FIG. 5G, angled implantation of N+ dopant in edge gate regions 204a and 204c may be used, as described above with respect to FIG. 4.

Of note, the process outlined in FIGS. 5A-5H does not require the extra shielding and P+ implantation steps shown in FIG. 3K.

FIGS. 6A-6C are cross-sectional stylized views of example alternative fabrication stages for the novel nFET of FIG. 2 using a self-aligned process for forming the gate structure 202. The stages shown in FIGS. 3A-3C and FIGS. 5A-5D would be followed, but preferably with a thicker layer of material 508 over the gate material 502 and P+ cap 506.

FIG. 6A shows that the layer of material 508 in FIG. 5D has been formed into spacers 512 around the sides of the P+ cap 506 of FIG. 5D.

FIG. 6B shows that the gate material 502 in FIG. 6A has been patterned and etched to conform to the sides of the spacers 512 of FIG. 6A and define edge gate regions 204a, 204c.

FIG. 6C shows that the insulator 118 has been patterned and etched to conform to the sides of the edge gate regions 204a, 204c, and that the P+ cap 506 and spacers 512 of FIG. 6B have been etched away, thus completing the gate structure 202. In addition, FIG. 6C shows that spacers 122 have been formed on the sides of the gate structure 202 as described above (see FIGS. 3H and 3i). At this point, the structure shown in FIG. 6C is equivalent to the structure shown in FIG. 5F, and the remaining steps shown in FIGS. 5G-5H may be applied.

Of note, the process outlined in FIGS. 6A-6C does not require the extra shielding and P+ implantation steps shown in FIG. 3K. Furthermore, the process outlined in FIGS. 6A-6C is self-aligned in that the spacers 512 are formed around the existing topology of the P+ cap 506 and are then used to define the etching limits for the edge gate regions 204a, 204c (see FIG. 6b) of the gate structure 202 (see FIG. 6C). Accordingly, the edge gate regions 204a, 204c are self-aligned with respect to the P+ cap 506.

FIGS. 7A-7H are cross-sectional stylized views of example fabrication stages for an nFET 700 including a first multiple work function gate structure fabricated using self-aligned edge gate regions. The substrate 106 shown in FIG. 7H is omitted from FIGS. 7A-7G to reduce clutter.

FIG. 7A shows a portion of an Active Region 102 formed on a BOX layer 104 (e.g., SiO₂), which is in turn formed on top of a substrate (see FIG. 7H). Additionally, isolation structures 114 and a doped semiconductor P-well 116 have been formed. In some embodiments, the Active Region 102 may be formed directly on top of a bulk Si substrate 106, thus omitting the BOX layer 104.

FIG. 7A also shows that a layer of gate oxide 702 has been formed over the Active Region 102. A layer of in-situ doped P+ polysilicon 704 is formed over the layer of gate oxide 702 (in-situ doping means that a material is doped when it is grown or deposited, as is known in the art). A hard mask material 706 (e.g., a metal such as amorphous silicon, polysilicon, or titanium nitride, or a dielectric such as silicon dioxide or silicon carbide) is deposited over the P+ doped polysilicon 704. The structure is then patterned and etched to form an initial gate structure 707 by removing, down to the layer of gate oxide 702, any portion of the P+ polysilicon 704 that is not protected by the hard mask material 706 defining the initial gate structure 707.

FIG. 7B shows that a layer of polysilicon 708 has been deposited (e.g., by chemical vapor deposition, CVD, or epitaxial growth) over the structure, including the initial gate structure 707. The polysilicon 708 may be in-situ doped with an N+ dopant or doped after deposition with an N+ dopant (e.g., by ion implantation). It may be useful to first clean the sidewalls of the P+ doped polysilicon 704 (e.g., with HF or buffered HF) before depositing the N+ polysilicon 708. In alternative embodiments, other N+ materials (e.g., silicon nitride) may be laid down in lieu of the N+ polysilicon.

FIG. 7C shows that the N+ polysilicon 708 not protected by the initial gate structure 707 is etched (e.g., by plasma dry etching) to remove much of the N+ polysilicon 708. In addition, the layer of gate oxide 702 not protected by the initial gate structure 707 is etched down to the Active Region 102, leaving a section of gate oxide 702a between the Active Region 102 and the initial gate structure 707. Due to the thickness (in the Z dimension) of the N+ polysilicon 708 deposited on the sidewalls of the P+ polysilicon 704, a spacer-like residual portion of the N+ polysilicon 708 remains on the sidewalls of the P+ polysilicon 704 as N+ polysilicon edge regions 708a having a uniform N+ doping. Accordingly, the initial gate structure 707 has been transformed to a first intermediate gate structure 707a.

FIG. 7D shows that the hard mask material 706 has been etched away, and that a first pair of dielectric spacers 710 (e.g., SiO₂) have been formed on the sidewalls of the N+ polysilicon edge regions 708a, thus forming a second intermediate gate structure 707b. The first pair of dielectric spacers 710 should be etched sufficiently to expose the top-most portion of the residual N+ polysilicon edge regions 708a. In some embodiments, the hard mask material 706 may be etched away at a later stage.

FIG. 7E shows that optional halo implant regions 712 and optional LDD regions 714 within the Active Region 102 may be implanted with dopants on one or both sides of the second intermediate gate structure 707b.

FIG. 7F shows that a second pair of dielectric spacers 716 (e.g., SiN) has been formed on the first pair of dielectric spacers 710, thus forming a third intermediate gate structure 707c. The second pair of dielectric spacers 716 should be etched sufficiently to expose the top-most portion of the residual N+ polysilicon edge regions 708a.

Note that since the N+ polysilicon edge regions 708a are fabricated with a spacer-like etching process, the resultant shape of the N+ polysilicon edge regions 708a is spacer-like, being thinner at the top while the base is thicker. The first pair of dielectric spacers 710 and the second pair of dielectric spacers 716 are fabricated in a similar manner, by deposition of a material (e.g., SiO₂ and/or SiN) and etching. All of the associated processing steps are self-aligned processing steps.

FIG. 7G shows an N+ implantation within the Active Region 102 has formed an N+ source region 720 and an N+ drain region 722.

FIG. 7H shows an essentially completed NFET device, with salicide layers 730 formed over the source region 720, the drain region 722, and the P+ and N+ polysilicon regions 704, 708a of the third intermediate gate structure 707c, thus forming a final gate structure 707d. Note that silicidation with NiSi generally will “consume” a portion of the underlying silicon (source and drain regions) and polysilicon (gate structure 704d) and thus the silicide will extend below the previously exposed surface of those regions/structures. In addition, NiSi will grow towards the outer edges of the N+ polysilicon edge regions 708a, providing good contact (NiSi will simultaneously grow on the N+ and P+ doped polysilicon gate regions 708a, 730 in the final gate structure 707d).

For some applications, one or more additional layers or regions may be included. For example, FIG. 7H includes an optional trap-rich silicon layer 740 between the substrate 106 and the BOX layer 104. The trap-rich Si layer 740 mitigates parasitic surface conduction and improves device performance at high RF frequencies.

A variation of the nFET 700 includes a stepped gate insulator that lowers the parasitic gate-to-source capacitance C_GS and gate-to-drain capacitance C_GD. For example, FIGS. 8A-8E are cross-sectional stylized views of example fabrication stages for an nFET including a second multiple work function gate structure fabricated using self-aligned edge gate regions and a stepped gate insulator.

FIG. 8A shows a stage of fabrication of an NFET 800 that has multiple work function regions N+/P+/N+ in a first intermediate gate structure 707a; FIG. 8A is essentially the same as FIG. 7C described above.

FIG. 8B shows the NFET 800 of FIG. 8A after being subjected to a low-temperature (e.g., in the range of about 500°C-1000°C) thermal oxidation process, which causes the gate oxide 702a to re-oxidize and grow upwards into the N+ polysilicon edge regions 708a (note that oxide grows faster in N+ polysilicon compared to P+ polysilicon). The result is formation of a “bird’s beak” oxide step 802 at the lateral edges of the gate oxide 702a and below the N+ polysilicon edge regions 708a. In FIGS. 8B and 8C, the oxide steps 802 are shown in a lighter shade than the gate oxide 702a for ease of identification; however, the materials of the two regions are the same in the illustrated example. If, for example, SiN is used in lieu of the polysilicon layer 708, then the oxide steps 802 would be of a different material than the N+ edge regions 708a.

Processing may continue with the steps shown in FIGS. 7D-7H. FIG. 8C shows an essentially completed NFET device, with salicide layers 730 formed over the source region 720, the drain region 722, and the P+ and N+ polysilicon regions 704, 708a of the third intermediate gate structure 707c, thus forming a final gate structure 707d that includes a stepped gate insulator (702a and 802).

Embodiments of the present invention encompass variations of the structure shown in FIG. 8C. While the novel embodiments described have been essentially symmetric devices, asymmetric devices may be fabricated using the same techniques. For example, FIG. 8D shows a first asymmetric nFET 820. The gate oxide 702a has an essentially uniform thickness, but the drain-side of the device lacks a halo implant region and has an enlarged 714. Compared to symmetric MOSFET devices, MOSFET devices having LDD region asymmetry provide better ON-state performance for parameters like I_dlin/I_dsat and voltage responsivity, R_V, and also improves the breakdown voltage BV_DSS.

As another example, FIG. 8E shows a second asymmetric nFET 830. The drain-side of the device lacks a halo implant region and has an enlarged LDD region 714 as in the nFET 820 of FIG. 8D. In addition, the gate oxide 702a includes an oxide step 802 at the drain-side edge of the gate oxide 702a and below the N+ polysilicon edge regions 708a, lowering the parasitic gate-to-drain capacitance C_GD.

While FIGS. 2, 3A-3M, 4, 5A-5H, 6A-6C, 7A-7H, and 8A-8E show enhancement mode nFETs, the teachings of this disclosure regarding MOSFETs having a multiple work function gate structure 202 may be applied to enhancement mode pFETs, depletion mode nFETs, and depletion mode pFETs. MOSFETs having a multiple work function gate structure may be combined on one IC with conventional MOSFETS having a single work function gate structure as may be desirable for a particular application. ICs that include MOSFETs having a multiple work function gate structure may be used in processes such as single-layer transfers and double-layer transfers in order to gain access to the backside of the IC for further processing and/or to form 3-D stackings of ICs.

Note that not all steps that may be performed during the manufacture of MOSFETs within an IC are shown in FIGS. 3A-3M, 4, 5A-5H, 6A-6C, 7A-7H, and 8A-8E. Such steps may vary between IC foundries and may include (but are not limited to) substrate thinning, planarization, special implantations, annealing, formation of ohmic contacts, and formation of additional temporary or permanent structures (e.g., drift regions, substrate contacts, passivation layers, salicide blocks, replacement metal gate (RMG)), etc. After formation of a basic MOSFET structure, back-end-of-line (BEOL) processes may be applied, such as fabrication of electrical contacts (pads), vias, insulating layers (dielectrics), metallization layers, and bonding sites for die-to-package connections.

MOSFETs having multiple work function regions N+/P+/N+ exhibit a number of significant advantages. For example: the gate length L_G may be scaled to below about 80nm (L_G < 80nm), and even below about 60nm (L_G < 60nm); some embodiments are made using a self-aligned process, simplifying fabrication; both symmetric and asymmetric MOSFETs with multiple work function gate structures may be fabricated (including both kinds on the same IC die); a thick gate oxide may be fabricated on the source-side and/or the drain-side edges of a multiple work function gate structure, lowering the parasitic gate-to-source capacitance C_GS and/or the drain-to-source capacitance C_GD; some embodiments may include an easier-to-implement (due to the preferential oxidation rate between the N+ and P+ polysilicon regions of the gate structure) thicker-thinner-thicker or thinner-thicker gate oxide combination that improves RF switch performance.

Circuits and devices in accordance with the present invention may be used alone or in combination with other components, circuits, and devices. Embodiments of the present invention may be fabricated as integrated circuits (ICs), which may be encased in IC packages and/or in modules for ease of handling, manufacture, and/or improved performance. In particular, IC embodiments of this invention are often used in modules in which one or more of such ICs are combined with other circuit components or blocks (e.g., filters, amplifiers, passive components, and possibly additional ICs) into one package. The ICs and/or modules are then typically combined with other components, often on a printed circuit board, to form part of an end-product such as a cellular telephone, laptop computer, or electronic tablet, or to form a higher-level module which may be used in a wide variety of products, such as vehicles, test equipment, medical devices, etc. Through various configurations of modules and assemblies, such ICs typically enable a mode of communication, often wireless communication.

As one example of further integration of embodiments of the present invention with other components, FIG. 9 is a top plan view of a substrate 900 that may be, for example, a printed circuit board or chip module substrate (e.g., a thin-film tile). In the illustrated example, the substrate 900 includes multiple ICs 902a-902d having terminal pads 904 which would be interconnected by conductive vias and/or traces on and/or within the substrate 900 or on the opposite (back) surface of the substrate 900 (to avoid clutter, the surface conductive traces are not shown and not all terminal pads are labelled). The ICs 902a-902d may embody, for example, signal switches, active and/or passive filters, amplifiers (including one or more LNAs), and other circuitry. For example, IC 902b may incorporate one or more instances of an IC having MOSFETs with a gate structure having multiple work function regions.

The substrate 900 may also include one or more passive devices 906 embedded in, formed on, and/or affixed to the substrate 900. While shown as generic rectangles, the passive devices 906 may be, for example, filters, capacitors, inductors, transmission lines, resistors, antennae elements, transducers (including, for example, MEMS-based transducers, such as accelerometers, gyroscopes, microphones, pressure sensors, etc.), batteries, etc., interconnected by conductive traces on or in the substrate 900 to other passive devices 906 and/or the individual ICs 902a-902d. The front or back surface of the substrate 900 may be used as a location for the formation of other structures.

Embodiments of the present invention are useful in a wide variety of larger radio frequency (RF) circuits and systems for performing a range of functions, including (but not limited to) impedance matching circuits, RF power amplifiers, RF low-noise amplifiers (LNAs), phase shifters, attenuators, antenna beam-steering systems, charge pump devices, RF switches, etc. Such functions are useful in a variety of applications, such as radar systems (including phased array and automotive radar systems), radio systems (including cellular radio systems), and test equipment.

Radio system usage includes wireless RF systems (including base stations, relay stations, and hand-held transceivers) that use various technologies and protocols, including various types of orthogonal frequency-division multiplexing (“OFDM”), quadrature amplitude modulation (“QAM”), Code-Division Multiple Access (“CDMA”), Time-Division Multiple Access (“TDMA”), Wide Band Code Division Multiple Access (“W-CDMA”), Global System for Mobile Communications (“GSM”), Long Term Evolution (“LTE”), 5G, 6G, and WiFi (e.g., 802.11a, b, g, ac, ax, be) protocols, as well as other radio communication standards and protocols.

Another aspect of the invention includes methods for fabricating MOSFETs with a gate structure having multiple work function regions. For example, FIG. 10 is a process flow chart 1000 showing one method of fabricating a field-effect transistor. The method includes: forming a gate structure over an active region of an integrated circuit, the gate structure defining a channel region and including: an insulating layer overlying the channel region; and a gate material overlying the insulating layer; a first edge region of the gate material adjacent the source region doped to have a first work function; a second edge region of the gate material adjacent the drain region doped to have a second work function; and a central region between the first and the second edge regions doped to have a third work function [Block 1002]; and forming a source region and a drain region in the active region on respective sides of the channel region [Block 1004].

As another example, FIG. 11 is a process flow chart 1100 showing one method of fabricating a semiconductor-on-insulator field-effect transistor. The method includes: forming an electrically insulating layer on a substrate [Bock 1102]; forming an active region on the electrically insulating layer [Bock 1104]; forming a doped well in the active region [Bock 1106]; forming a gate structure overlying the doped well, the gate structure defining a channel region and including: an insulating layer overlying the channel region; and a gate material overlying the insulating layer; a first edge region of the gate material adjacent the source region doped to have a first work function; a second edge region of the gate material adjacent the drain region doped to have a second work function; and a central region between the first and the second edge regions doped to have a third work function [Bock 1108]; and forming a source region and a drain region in the active region on respective sides of the channel region [Bock 1110].

As yet another example, FIG. 12 is a process flow chart showing one method of fabricating a semiconductor-on-insulator field-effect transistor using self-aligned edge gate regions. The method includes: forming an electrically insulating layer on a substrate [Bock 1202]; forming an active region on the electrically insulating layer [Bock 1204]; forming a doped well in the active region [Bock 1206]; forming a gate structure overlying the doped well, the gate structure defining a channel region, including the steps of: (1) depositing an insulating layer overlying the channel region; (2) depositing a layer of a first doped gate material over the insulating layer, the first doped gate material having a first work function; (3) depositing a layer of masking material over the layer of the first doped gate material; (4) patterning and etching the layer of masking material and the layer of the first doped gate material to define an initial gate structure; (5) depositing a layer of a second doped gate material over the insulating layer and the initial gate structure, the second doped gate material having a second work function; (6) etching the layer of the second doped gate material to define edge regions of the second doped gate material along respective sidewalls of the initial gate structure, thereby defining an intermediate gate structure; and (7) forming at least one dielectric spacer on outer edges of the intermediate gate structure, thereby defining the gate structure [Block 1208]; and forming a source region and a drain region in the active region on respective sides of the gate structure [Block 1210].

Additional aspects of the above methods may include one or more of the following: wherein the central region has a length equal to or less than about 75% of a length of the first and second edge regions; wherein the work functions of the first and second edge regions are the same; wherein the work functions of the first and second edge regions are different; wherein the central region is doped after the first and second edge regions are doped; wherein the central region is doped before the first and second edge regions are doped; wherein the first and second edge regions are implanted at an angle with a dopant; wherein the first and second edge regions are N+ doped, and the central region is P+ doped; wherein the insulating layer consists of an oxide; wherein the first doped gate material comprises polysilicon with P+ doping, and the second doped gate material comprises polysilicon with N+ doping; further including processing the insulating layer underneath the initial gate structure to form a step at each edge of the insulating layer below the second doped gate material; and/or wherein processing the insulating layer includes subjecting the insulating layer to a low-temperature thermal oxidation process.

The term “MOSFET”, as used in this disclosure, includes any field effect transistor (FET) having an insulated gate whose voltage determines the conductivity of the transistor, and encompasses insulated gates having a metal or metal-like, insulator, and/or semiconductor structure. The terms “metal” or “metal-like” include at least one electrically conductive material (such as aluminum, copper, or other metal, or highly doped polysilicon, graphene, or other electrical conductor), “insulator” includes at least one insulating material (such as silicon oxide or other dielectric material), and “semiconductor” includes at least one semiconductor material.

As used in this disclosure, the term “radio frequency” (RF) refers to a rate of oscillation in the range of about 3 kHz to about 300 GHz. This term also includes the frequencies used in wireless communication systems. An RF frequency may be the frequency of an electromagnetic wave or of an alternating voltage or current in a circuit.

With respect to the figures referenced in this disclosure, the dimensions for the various elements are not to scale; some dimensions may be greatly exaggerated vertically and/or horizontally for clarity or emphasis. In addition, references to orientations and directions (e.g., “top”, “bottom”, “above”, “below”, “lateral”, “vertical”, “horizontal”, etc.) are relative to the example drawings, and not necessarily absolute orientations or directions.

Various embodiments of the invention can be implemented to meet a wide variety of specifications. Unless otherwise noted above, selection of suitable component values is a matter of design choice. Various embodiments of the invention may be implemented in any suitable integrated circuit (IC) technology (including but not limited to MOSFET structures), or in hybrid or discrete circuit forms. Integrated circuit embodiments may be fabricated using any suitable substrates and processes, including but not limited to standard bulk silicon, high-resistivity bulk CMOS, silicon-on-insulator (SOI), and silicon-on-sapphire (SOS). Unless otherwise noted above, embodiments of the invention may be implemented in other transistor technologies, such as BiCMOS, LDMOS, BCD, FinFET, GAAFET, and SiC-based device technologies, using 2-D, 2.5-D, and 3-D structures. However, embodiments of the invention are particularly useful when fabricated using an SOI or SOS based process, or when fabricated with processes having similar characteristics. Fabrication in CMOS using SOI or SOS processes enables circuits with low power consumption, the ability to withstand high power signals during operation due to FET stacking, good linearity, and high frequency operation (i.e., radio frequencies up to and exceeding 300 GHz). Monolithic IC implementation is particularly useful since parasitic capacitances generally can be kept low (or at a minimum, kept uniform across all units, permitting them to be compensated) by careful design.

Voltage levels may be adjusted, and/or voltage and/or logic signal polarities reversed, depending on a particular specification and/or implementing technology (e.g., NMOS, PMOS, or CMOS, and enhancement mode or depletion mode transistor devices). Component voltage, current, and power handling capabilities may be adapted as needed, for example, by adjusting device sizes, serially “stacking” components (particularly FETs) to withstand greater voltages, and/or using multiple components in parallel to handle greater currents. Additional circuit components may be added to enhance the capabilities of the disclosed circuits and/or to provide additional functionality without significantly altering the functionality of the disclosed circuits.

A number of embodiments of the invention have been described. It is to be understood that various modifications may be made without departing from the spirit and scope of the invention. For example, some of the steps described above may be order independent, and thus can be performed in an order different from that described. Further, some of the steps described above may be optional. Various activities described with respect to the methods identified above can be executed in repetitive, serial, and/or parallel fashion.

It is to be understood that the foregoing description is intended to illustrate and not to limit the scope of the invention, which is defined by the scope of the following claims, and that other embodiments are within the scope of the claims. In particular, the scope of the invention includes any and all feasible combinations of one or more of the processes, machines, manufactures, or compositions of matter set forth in the claims below. (Note that the parenthetical labels for claim elements are for ease of referring to such elements, and do not in themselves indicate a particular required ordering or enumeration of elements; further, such labels may be reused in dependent claims as references to additional elements without being regarded as starting a conflicting labeling sequence).

The present application is based on and claims priority of U.S. Patent Application No. 63/624,026 filed on January 23, 2024, the entire contents of which are hereby incorporated herein by reference.

Claims (28)

1. A field-effect transistor including:
   (a) a source region;
   (b) a drain region spaced from the source region;
   (c) a channel region between the source region and the drain region; and
   (d) a gate structure overlying the channel region, the gate structure including:
   (1) an insulating layer overlying the channel region; and
   (2) a gate material overlying the insulating layer, wherein the gate material includes:
   (A) a first edge region adjacent the source region and doped to have a first work function;
   (B) a second edge region adjacent the drain region and doped to have a second work function; and
   (C) a central region between the first and the second edge regions and doped to have a third work function.
2. The field-effect transistor of claim 1, wherein the central region has a length equal to or less than about 75% of a length of the first and second edge regions.
3. The field-effect transistor of claim 1, wherein the work functions of the first and second edge regions are the same.
4. The field-effect transistor of claim 1, wherein the work functions of the first and second edge regions are different.
5. The field-effect transistor of claim 1, wherein the central region is doped after the first and second edge regions are doped.
6. The field-effect transistor of claim 1, wherein the central region is doped before the first and second edge regions are doped.
7. The field-effect transistor of claim 1, wherein the first and second edge regions are implanted at an angle with a dopant.
8. The field-effect transistor of claim 1, wherein the first and second edge regions are N+ doped, and the central region is P+ doped.
9. The field-effect transistor of claim 1, wherein the insulating layer consists of an oxide.
10. A semiconductor-on-insulator field-effect transistor including:
    (a) a substrate;
    (b) an electrically insulating layer formed on the substrate;
    (c) an active region formed on the electrically insulating layer;
    (d) a source region formed in the active region;
    (e) a drain region formed in the active region and spaced from the source region;
    (f) a doped well between the source region and the drain region; and
    (g) a gate structure overlying the doped well and between the source region and the drain region, the gate structure including:
    (1) an insulating layer overlying the channel region; and
    (2) a gate material overlying the insulating layer, wherein the gate material includes:
    (A) a first edge region adjacent the source region and doped to have a first work function;
    (B) a second edge region adjacent the drain region and doped to have a second work function; and
    (C) a central region between the first and the second edge regions and doped to have a third work function.
11. The field-effect transistor of claim 10, wherein the central region has a length equal to or less than about 75% of a length of the first and second edge regions.
12. The field-effect transistor of claim 10, wherein the work functions of the first and second edge regions are the same.
13. The field-effect transistor of claim 10, wherein the work functions of the first and second edge regions are different.
14. The field-effect transistor of claim 10, wherein the central region is doped after the first and second edge regions are doped.
15. The field-effect transistor of claim 10, wherein the central region is doped before the first and second edge regions are doped.
16. The field-effect transistor of claim 10, wherein the first and second edge regions are implanted at an angle with a dopant.
17. The field-effect transistor of claim 10, wherein the first and second edge regions are N+ doped, and the central region is P+ doped.
18. The field-effect transistor of claim 10, wherein the insulating layer consists of an oxide.
19. A method of fabricating a field-effect transistor, the method including:
    (a) forming a gate structure over an active region of an integrated circuit, the gate structure defining a channel region and including:
    (1) an insulating layer overlying the channel region;
    (2) a gate material overlying the insulating layer;
    (3) a first edge region of the gate material adjacent the source region doped to have a first work function;
    (4) a second edge region of the gate material adjacent the drain region doped to have a second work function; and
    (5) a central region between the first and the second edge regions doped to have a third work function; and
    (b) forming a source region and a drain region in the active region on respective sides of the channel region.
20. A method of fabricating a semiconductor-on-insulator field-effect transistor, the method including:
    (a) forming an electrically insulating layer on a substrate;
    (b) forming an active region on the electrically insulating layer;
    (c) forming a doped well in the active region;
    (d) forming a gate structure overlying the doped well, the gate structure defining a channel region and including:
    (1) an insulating layer overlying the channel region;
    (2) a gate material overlying the insulating layer;
    (3) a first edge region of the gate material adjacent the source region doped to have a first work function;
    (4) a second edge region of the gate material adjacent the drain region doped to have a second work function; and
    (5) a central region between the first and the second edge regions doped to have a third work function.
    (e) forming a source region and a drain region in the active region on respective sides of the channel region.
21. A method of fabricating a gate structure over an active region of an integrated circuit, the gate structure defining a channel region, including the steps of:
    (a) depositing an insulating layer overlying the channel region;
    (b) depositing a layer of a first doped gate material over the insulating layer, the first doped gate material having a first work function;
    (c) depositing a layer of masking material over the layer of the first doped gate material;
    (d) patterning and etching the layer of masking material and the layer of the first doped gate material to define an initial gate structure;
    (e) depositing a layer of a second doped gate material over the insulating layer and the initial gate structure, the second doped gate material having a second work function;
    (f) etching the layer of the second doped gate material to define edge regions of the second doped gate material along respective sidewalls of the initial gate structure, thereby defining an intermediate gate structure; and
    (g) forming at least one dielectric spacer on outer edges of the intermediate gate structure, thereby defining the gate structure.
22. The method of claim 21, wherein the first doped gate material comprises polysilicon with P+ doping, and the second doped gate material comprises polysilicon with N+ doping.
23. The method of claim 21, further including processing the insulating layer underneath the initial gate structure to form a step at each edge of the insulating layer below the second doped gate material.
24. The method of claim 23, wherein processing the insulating layer includes subjecting the insulating layer to a low-temperature thermal oxidation process.
25. A method of fabricating a semiconductor-on-insulator field-effect transistor, the method including:
    (a) forming an electrically insulating layer on a substrate;
    (b) forming an active region on the electrically insulating layer;
    (c) forming a doped well in the active region;
    (d) forming a gate structure overlying the doped well, the gate structure defining a channel region, including the steps of:
    (1) depositing an insulating layer overlying the channel region;
    (2) depositing a layer of a first doped gate material over the insulating layer, the first doped gate material having a first work function;
    (3) depositing a layer of masking material over the layer of the first doped gate material;
    (4) patterning and etching the layer of masking material and the layer of the first doped gate material to define an initial gate structure;
    (5) depositing a layer of a second doped gate material over the insulating layer and the initial gate structure, the second doped gate material having a second work function;
    (6) etching the layer of the second doped gate material to define edge regions of the second doped gate material along respective sidewalls of the initial gate structure, thereby defining an intermediate gate structure; and
    (7) forming at least one dielectric spacer on outer edges of the intermediate gate structure, thereby defining the gate structure; and
    (e) forming a source region and a drain region in the active region on respective sides of the gate structure.
26. The method of claim 25, wherein the first doped gate material comprises polysilicon with P+ doping, and the second doped gate material comprises polysilicon with N+ doping.
27. The method of claim 25, further including processing the insulating layer underneath the initial gate structure to form a step at each edge of the insulating layer below the second doped gate material.
28. The method of claim 27, wherein processing the insulating layer includes subjecting the insulating layer to a low-temperature thermal oxidation process.