WO2025155671A1 - On basemesh submesh information design in dynamic mesh coding - Google Patents

Abstract

A mechanism for processing video data is disclosed. The mechanism includes determining that an absolute difference quantization parameter (QP) value for displacement coding is coded as an unsigned integer. A conversion is performed between a visual media data and a bitstream based on the absolute difference QP value for displacement coding.

Description

On Basemesh Submesh Information Design In Dynamic Mesh Coding

CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This patent application claims the benefit of U.S. Provisional Patent Application No 63/621,844 filed on January 17, 2024, which is hereby incorporated by reference.

TECHNICAL FIELD

[0002] The present disclosure relates to generation, storage, and consumption of digital audio video media information in a file format.

BACKGROUND

[0003] Digital video accounts for the largest bandwidth used on the Internet and other digital communication networks. As the number of connected user devices capable of receiving and displaying video increases, the bandwidth demand for digital video usage is likely to continue to grow.

SUMMARY

[0004] A first aspect relates to a method for processing media data comprising: determining that an absolute difference quantization parameter (QP) value for displacement coding is coded as an unsigned integer; and performing a conversion between a visual media data and a bitstream based on the absolute difference QP value for displacement coding.

[0005] Optionally, in any of the preceding aspects, another implementation of the aspect provides that the unsigned integer compnses an unsigned integer Exponential- Golomb-coded using a variable number of bits (ue(v)). [0006] Optionally, in any of the preceding aspects, another implementation of the aspect provides that the unsigned integer comprises an unsigned integer using n bits (u(n)), where n is greater than 6.

[0007] Optionally, in any of the preceding aspects, another implementation of the aspect provides that the unsigned integer comprises an unsigned integer using n bits (u(n)), where n is 7.

[0008] Optionally, in any of the preceding aspects, another implementation of the aspect provides that the unsigned integer omprises an unsigned integer using n bits (u(n)), where n is 8.

[0009] Optionally, in any of the preceding aspects, another implementation of the aspect provides that a number of attributes of a basemesh is coded as an unsigned integer Exponential-Golomb-coded using a variable number of bits (ue(v)).

[0010] Optionally, in any of the preceding aspects, another implementation of the aspect provides that a range for the number of attributes of the basemesh is 0 to 127, inclusive.

[0011] Optionally, in any of the preceding aspects, another implementation of the aspect provides that a number of attributes of a test model of dynamic mesh coding (V -DMC) is coded as an unsigned integer Exponential- Golomb-coded using a variable number of bits (ue(v)).

[0012] Optionally, in any of the preceding aspects, another implementation of the aspect provides that a range for the number of attributes of the V-DMC is 0 to 127, inclusive.

[0013] Optionally, in any of the preceding aspects, another implementation of the aspect provides that update parameters are not included in the bitstream when an update skip flag is equal to 1. [0014] Optionally, in any of the preceding aspects, another implementation of the aspect provides that the update parameters are inferred to be 0 when the update skip flag is equal to 1.

[0015] Optionally, in any of the preceding aspects, another implementation of the aspect provides that an index of a method used to traverse vertices in static mesh coding is coded as an unsigned integer using n bits (u(n)), where n is positive integer

[0016] Optionally, in any of the preceding aspects, another implementation of the aspect provides that n is 1.

[0017] Optionally, in any of the preceding aspects, another implementation of the aspect provides that n is 2.

[0018] Optionally, in any of the preceding aspects, another implementation of the aspect provides that n is 3.

[0019] Optionally, in any of the preceding aspects, another implementation of the aspect provides that an index of a method used to traverse vertices in static mesh coding is coded as an unsigned integer Exponential- Golomb-coded using a variable number of bits (ue(v)) in a range from 0 to N, where N is a positive integer.

[0020] Optionally, in any of the preceding aspects, another implementation of the aspect provides that N is 1.

[0021] Optionally, in any of the preceding aspects, another implementation of the aspect provides that N is 3.

[0022] Optionally, in any of the preceding aspects, another implementation of the aspect provides that N is 7.

[0023] Optionally, in any of the preceding aspects, another implementation of the aspect provides that a range of displacement coordinate information is coded as an unsigned integer using 2 bits (u(2)).

[0024] Optionally, in any of the preceding aspects, another implementation of the aspect provides that a range of displacement coordinate information is coded as an unsigned integer Exponential-Golomb-coded using a variable number of bits (ue(v)) in a range from 0 to N, inclusive

[0025] Optionally, in any of the preceding aspects, another implementation of the aspect prow des that N is 1.

[0026] Optionally, in any of the preceding aspects, another implementation of the aspect provides that N is 2.

[0027] Optionally, in any of the preceding aspects, another implementation of the aspect provides that N is 3.

[0028] Optionally, in any of the preceding aspects, another implementation of the aspect provides that N is 4.

[0029] Optionally, in any of the preceding aspects, another implementation of the aspect provides that N is 5.

[0030] Optionally, in any of the preceding aspects, another implementation of the aspect provides that the conversion includes encoding the media data into the bitstream.

[0031] Optionally, in any of the preceding aspects, another implementation of the aspect provides that the conversion includes decoding the media data from the bitstream.

[0032] A second aspect relates to an apparatus for processing video or image data comprising: a processor; and a non-transitory memory with instructions thereon, wherein the instructions upon execution by the processor, cause the processor to perform the method of any of the disclosed methods.

[0033] A third aspect relates to a non-transitory computer readable medium comprising a computer program product for use by a video coding device, the computer program product comprising computer executable instructions stored on the non-transitory computer readable medium such that when executed by a processor cause the video coding device to perform the method of any of the disclosed methods.

[0034] A fourth aspect relates to a non-transitory computer-readable recording medium storing a bitstream of a video which is generated by a method performed by a video processing apparatus, wherein the method comprises: determining that an absolute difference quantization parameter (QP) value for displacement coding is coded as an unsigned integer; and performing a conversion between a visual media data and a bitstream based on the absolute difference QP value for displacement coding.

[0035] A fifth aspect relates to a method for storing a bitstream of a video, comprising: determining that an absolute difference quantization parameter (QP) value for displacement coding is coded as an unsigned integer; generating the bitstream based on the absolute difference QP value for displacement coding; and storing the bitstream in a non-transitory computer-readable recording medium.

[0036] A sixth aspect relates to a method, apparatus, or system described in the present disclosure

[0037] For the purpose of clarity, any one of the foregoing embodiments may be combined with any one or more of the other foregoing embodiments to create a new embodiment within the scope of the present disclosure

[0038] These and other features will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings and claims.

BRIEF DESCRIPTION OF THE DRAWINGS

[0039] For a more complete understanding of this disclosure, reference is now made to the following brief description, taken in connection with the accompanying drawings and detailed description, wherein like reference numerals represent like parts

[0040] FIG. 1 is a block diagram illustrating a decoder design of dynamic mesh coding.

[0041] FIG. 2 is a block diagram illustrating a structure of a dynamic mesh coding test model.

[0042] FIG. 3 is a block diagram showing an example video processing system.

[0043] FIG 4 is a block diagram of an example video processing apparatus

[0044] FIG. 5 is a flowchart for an example method of video processing.

[0045] FIG. 6 is a block diagram that illustrates an example video coding system.

[0046] FIG. 7 is a block diagram that illustrates an example encoder

[0047] FIG. 8 is a block diagram that illustrates an example decoder

[0048] FIG. 9 is a schematic diagram of an example encoder.

DETAILED DESCRIPTION

[0049] It should be understood at the outset that although an illustrative implementation of one or more embodiments are provided below, the disclosed systems and/or methods may be implemented using any number of techniques, whether currently known or yet to be developed. The disclosure should in no way be limited to the illustrative implementations, drawings, and techniques illustrated below, including the exemplary designs and implementations illustrated and described herein, but may be modified within the scope of the appended claims along with their full scope of equivalents.

1. Initial discussion

[0050] This disclosure is related to improvements to motion picture experts group immersive (MPEG-I) video-based dynamic mesh coding. Specifically, it is related to the basemesh submesh high-level syntax design. It may be also applicable to other immersive video coding standards or codecs. 2. Further discussion

[0051] In computer graphics, a three dimensional (3D)/immersive content can usually be represented by a 3D mesh and a texture map. Those mesh and texture data can be generated by a machine or can be converted from images captured by multiple cameras from different angles. Similar to two-dimensional (2D) video, when those 3D contents change with time, the mesh and texture data also change and comprises a sequence of dynamic mesh. The data volume of dynamic mesh are usually huge and make it difficult to store and transmit. To meet the requirement of applications that use dynamic mesh, Motion Picture Expert Group (MPEG) in short, issued a call for proposal [1], To efficiently use the 2D codecs that are already available, one of the key requirements is to use the current 2D video coding standard to compress most data and keep other parts simple and of low complexity Such a requirement can gurantee that the representation can take advantages of the 2D video hardware/ software systems, without many efforts to redesign a specific system just for dynamic mesh.

[0052] MPEG received 5 responses to the call for proposal Among them, a scheme [2] showed better performance compared with others So based on [2], a test model was built for the development of the planned dynamic mesh coding standard.

[0053] The latest test model of dynamic mesh coding (V-DMC) until this disclosure is drafted can be found via this link http://mpegx.int-evry.fr/software/MPEG/dmc/mpeg-vmesh-tm/-/tags/v5.0; and the latest working draft (WD) document is WD 4.0 [3],

2.1 Data representation in dynamic mesh coding

[0054] FIG. 1 is a block diagram illustrating a decoder design of dynamic mesh coding. Figure 1 shows a decoder design as described in WD 4.0 [3], It can be seen that a dynamic mesh decoder receives 4 bitstreams and performs decoding to reconstruct the dynamic mesh plus texture signals. The first bitstream is to represent the base mesh, which is a decimated version of the original mesh. The second bitstream is to represent displacement vectors between the reconstructed base mesh and the original mesh. The displacement vectors are arranged as a 2D video and compressed with an 2D video coding standard compliant codec, or the displacement can also be coded using an arithmetic codec. The third bitstream is to represent the texture (or attribute map). The attribute map is also arranged as a 2D video and compressed with an 2D video coding standard compliant codec. The design philosophy is to make the base mesh part small enough so that the module to process base mesh can be implemented simply. On the other hand, the displacement vectors and the attribute map accounts for most volume of the whole dynamic mesh data, which can be processed with the current dedicated highly efficient 2D video coding systems. Such a design can reduce the extra efforts to implement the dynamic mesh coding system and guarantee the high throughout and coding efficiency for the dynamic mesh data.

2.2 Test model of dynamic mesh coding

[0055] FIG. 2 is a block diagram illustrating a structure of a dynamic mesh coding test model. Figure 2 shows the structure of an example dynamic mesh coding model. In the model, Draco is used to compress base mesh and the HEVC test model, e.g., HM is used to compress displacement vectors and attribute map. However, it should be noted that other mesh or video coding systems can also be used in dynamic mesh coding.

[0056] The base mesh m is generated from the original mesh with a down-sampling scheme. Its quantized version m' is then coded using Draco. The reconstrused base mesh m" can be obtained by inverse quantization of m'. Displacement vectors d' arc generated by making the difference between the original mesh and the subdivided version of m" using a subdivision scheme.

2.3 Basemesh submesh information syntax and semantics

[0057] In an example V-DMC design, a basemesh submesh information is used to indicate the number of submeshes and assign identifier (ID) to each submesh. The related syntax and semantics arc shown as follows:

H.8.1.3.2.2 Basemesh submesh information

H.8.3.2.2 Basemesh submesh information

[0058] bmsi_use_single_mesh_flag equal to 1 specifies that there is only one submesh in each mesh frame referring to the BFPS. bmsi_usc_singlc_mcsh_falg equal to 0 specifics that there may be more than one submeshes in each mesh frame referring to the BFPS.

[0059] bmsi_num_submeshes_minus 1 plus 1 specifies the number of submeshes in each mesh frame referring to the BFPS. The value of bmsi_num_submcshcs_minusl shall be in the range of 0 to 63, inclusive. When not present and bmsi_use_single_mesh_flag is equal to 1 , its value is inferred to be equal to 1.

[0060] bmsi_signalled_submesh_id_flag equal to 1 specifies that the submesh ID for each mesh frame is signalled. bmsi_signalled_tile_id_flag equal to 0 specifies that submesh IDs are not signalled. [0061] bmsi_signalled_submesh_id_length_minusl plus 1 specifies the number of bits used to represent the syntax element bmsi_tile_id[ i ] when present, and the syntax element submesh_id in a submesh header. The value of bmsi_signalled_tile_id_length_minusl shall be in the range of 0 to 15, inclusive. When not present, its value is inferred to be equal to Ceil( Log2( bmsi_num_submeshes_minusl + 1 ) ) - 1.

[0062] bmsi_submesh_id[ i ] specifies the tile ID of the i-th submesh The length of the bmsi_submesh_id[ i ] syntax element is bmsi_signalled_submesh_id_length_minusl + 1 bits. When not present, the value of bmsi_submesh_id[ i ] is inferred to be equal to i, for each i in the range of 0 to bmsi_num_submeshes_minusl, inclusive. It is a requirement of bitstream conformance that bmsi_submesh_id[ i ] shall not be equal to bmsi_submesh_id[ j ] for all i !=j. The length of the bmsi_submesh_id[ i ] syntax element is bmsi_signalled_submesh_id_length_minusl + 1 bits.

[0063] The variable First SubmeshlD is computed as follows:

FirstSubmeshID= bmsi_submesh_id[0 ] for ( i = 1 ; i < bmsi_num_submeshes_minusl + 1 ; i++ )

First SubmeshlD = Min(FirstSubmeshID, bmsi_submesh_id[ i ])

3. Technical problems solved by disclosed technical solutions

[0064] An example design for dynamic mesh coding has the following problems:

[0065] First, the inferred value of bmsi_num_submeshes_minus 1 is incorrect.

[0066] Second, it is required that the value of bmsi_num_submeshes_minusl shall be in the range of 0-63 and coded as u(8). The range and the number of bits do not match. And using 8-bit to signal bmsi_num_submeshes_minus 1 may be too limited.

[0067] Third, when there is only one submesh, signalling the ID for the only submesh does not make sense.

[0068] Fourth, the number of bits to signal submesh ID is (bmsi_signalled_submesh_id_length_mmusl + 1), which is in the range of 1 to 16, which may be illegal in some cases due to the constraint that each submesh shall have a different ID value.

[0069] Fifth, in V-DMC WD 5.0, for the syntax element vltp_lod_delta_qp, the syntax and semantics are inconsistent.

[0070] Sixth, in V-DMC WD 5.0, for the syntax element vps ext bmesh data attribute count, the syntax and semantics are inconsistent.

[0071] Seventh, the update parameters in the lifting transform are signalled but not used.

[0072] Eighth, in V-DMC WD 5.0, for the syntax element mesh_vertex_traversal_method, the syntax and semantics are inconsistent.

[0073] Ninth, in V-DMC WD 5.0, for the syntax element dsps_range_log2_mmus2, the syntax and semantics are inconsistent.

4. A listing of solutions and embodiments

[0074] To solve the above problems, methods as summarized below are disclosed. The items should be considered as examples to explain the general concepts and should not be interpreted in a narrow way. Furthermore, these designs can be applied individually or combined in any manner.

1. To solve problem 1 , one of more of the following methods are specified: a. In one example, when not present, the value of bmsi_num_submeshes_minusl is inferred to be equal to 0. olve problem 2, one of more of the following methods are specified: a. In one example, the value of bmsi_num_submeshes_minusl shall be in the range of 0 to 255. b Alternatively, it is proposed to use u(6) to signal bmsi_num_submeshes_minusl etter solve problem 2, one of more of the following methods are specified: a. In one example, N-bit (N>8) may be used to signal bmsi_num_submeshes_minus 1. i. In one example, u(N) is used to signal bmsi_num_submeshes_minus 1. ii. In one example, N is equal to 12, 16, 24 or 32. olve problem 3, one of more of the following methods are specified: a. In one example, when there is only one submesh, the ID value of that submesh is not signalled. b. In one example, when there is only one submesh, the ID value of that submesh is inferred to be equal to 0. olve problem 4, one of more of the following methods are specified: a. In one example, the delta value between the number of bits to signal submesh IDs and a fixed value greater than 1 is indicated. i. In one example, the fixed value is Ceil( Log2( bmsi_num_submeshes_minusl + 1 ) ). ii. In one example, the delta value, when not present, is inferred to be equal to 0. iii. In one example, the range of the delta value is from 0 to N.

1. In one example, N is equal to 15. olve problem 5, one of more of the following methods are specified: a. In one example, the absolute difference QP value for the displacement coding is coded in ue(v) b. Alternatively, in one example, the absolute difference QP value for the displacement coding is coded in u(N), where N > 6. i In one example, N is 7 or 8 olve problem 6, one of more of the following methods are specified: a. In one example, the number of attributes of basemesh is coded in ue(v). i. Furthermore, in one example, the range is specified as 0 to 127, inclusive b. In one example, the number of attributes of V-DMC is coded in ue(v). i. Furthermore, in one example, the range is specified as 0 to 127, inclusive olve problem 7, one of more of the following methods are specified: a. In one example, update parameters are not signalled in the bitstream when update skip flag is equal to 1. i. Furthermore, in one example, update parameters are inferred to be equal to 0 when update skip flag is equal to 1. olve problem 8, one of more of the following methods are specified: a. In one example, the index of the method used to traverse the vertices in static mesh coding is coded in u(N), where N is a positive integer. i. In one example, N is 1/2/3 b. Alternatively, in one example, the index of the method used to traverse the vertices in static mesh coding is coded in ue(v) with range from 0 to N, inclusive, where N is a positive integer. i. In one example, N is M n

10. To solve problem 9, one of more of the following methods are specified: a. In one example, the range of the displacement coordinate information are coded in u(2). b Alternatively, in one example, the range of the displacement coordinate information are coded in ue(v) with the range from 0 to N, inclusive i. In one example, N is 1/2/3/4/5.

5. Embodiments

[0075] Below arc some example embodiments for the aspects summarized above in Section 4.

[0076] Most relevant parts that have been added or modified are in bold, and some of the deleted parts are in italic fonts There may be some other changes that arc editorial in nature and thus not indicated.

[0077] The following text changes are based on WD 4.0 of V-DMC [3],

5.1 Embodiment 1

[0078] This embodiment is for item 1 as summarized above in Section 4.

H.8 1.3.2.2 Basemesh submesh information

H.8 3.2.2 Basemesh submesh information bmsi_use_single_mesh_flag equal to 1 specifies that there is only one submesh in each mesh frame referring to the BFPS. bmsi_use_single_mesh_falg equal to 0 specifies that there may be more than one submeshes in each mesh frame referring to the BFPS. bmsi_num_submeshes_minusl plus 1 specifies the number of submeshes in each mesh frame referring to the BFPS The value of bmsi_num_submeshes_minusl shall be in the range of 0 to 63, inclusive When not present and bmsi_use_single_mesh_flag is equal to 1, its value is inferred to be equal to / 0.

5.2 Embodiment 2

[0079] This embodiment is for item 2. a as summarized above in Section 4.

H.8 3.2.2 Basemesh submesh information bmsi_use_single_mesh_flag equal to 1 specifies that there is only one submesh in each mesh frame referring to the BFPS. bmsi_use_single_mesh_falg equal to 0 specifies that there may be more than one submeshes in each mesh frame referring to the BFPS. bmsi_num_submeshes_minusl plus 1 specifies the number of submeshes in each mesh frame referring to the BFPS The value of bmsi_num_submeshes_minusl shall be in the range of 0 to 63 255, inclusive When not present and bmsi_use_single_mesh_flag is equal to 1, its value is inferred to be equal to 1.

5.3 Embodiment 3

[0080] This embodiment is for item 3 as summarized above in Section 4.

H.8 1.3.2.2 Basemesh submesh information

5.4 Embodiment 4

[0081] This embodiment is for item 4 as summarized above in Section 4.

H.8 1.3.2.2 Basemesh submesh information H.8 3.2.2 Basemesh submesh information bmsi_use_single_mesh_flag equal to 1 specifies that there is only one submesh in each mesh frame referring to the BFPS. bmsi_use_single_mesh_falg equal to 0 specifies that there may be more than one submeshes in each mesh frame referring to the BFPS. bmsi_num_submeshes_minusl plus 1 specifies the number of submeshes in each mesh frame referring to the BFPS. The value of bmsi_num_submeshes_minusl shall be in the range of 0 to 63, inclusive When not present and bmsi_use_single_mesh_flag is equal to 1, its value is inferred to be equal to 1 bmsi_signalled_submesh_id_flag equal to 1 specifies that the submesh ID for each mesh frame is signalled. bmsi_signalled_tile_id_flag equal to 0 specifies that submesh IDs are not signalled When not present, the value of bmsi_signalled_submesh_id_flag is inferred to be 0. bmsi signalled submesh id length minusl plus 1 specifies the number of bits used to represent the syntax element bmsi_tile_id[ i ] when present, and the syntax element submesh_id in a submesh header. The value of bmsi_signalled_tile_id_length_minusl shall be in the range of 0 to 15, inclusive. When not present, its value is inferred to be equal to Ceil( Log2( bmsi_num_submeshes_minusl + 1 ) ) - 1. bmsi_submesh_id[ i ] specifies the tile ID of the i-th submesh. The length of the bmsi_submesh_id[ i ] syntax element is bmsi_signalled_submesh_id_length_minusl + 1 bits. When not present, the value of bmsi_submesh_id[ i ] is inferred to be equal to i, for each i in the range of 0 to bmsi_num_submeshes_minusl, inclusive. It is a requirement of bitstream conformance that bmsi_submesh_id[ i ] shall not be equal to bmsi_submesh_id[ j ] for all i !=j. The length of the bmsi_submesh_id[ i ] syntax element is bmsi_signalled_submesh_id_length_minusl + 1 bits.

The variable FirstSubmeshlD is computed as follows:

FirstSubmeshID= bmsi_submesh_id[O ] for ( i = 1 ; i < bmsi_num_submeshes_minusl + 1 ; i++ )

FirstSubmeshlD = Min(FirstSubmeshID, bmsi_submesh_id[ i ])

5.5 Embodiment 5

[0082] This embodiment is for item 1 as summarized above in Section 4.

H.8 1.3.2.2 Basemesh submesh information

H.8 3.2.2 Basemesh submesh information bmsi_use_single_mesh_flag equal to 1 specifies that there is only one submesh in each mesh frame referring to the BFPS. bmsi_use_single_mesh_falg equal to 0 specifies that there may be more than one submeshes in each mesh frame referring to the BFPS. bmsi_num_submeshes_minusl plus 1 specifies the number of submeshes in each mesh frame referring to the BFPS The value of bmsi_num_submeshes_minusl shall be in the range of 0 to 63, inclusive When not present and bmsi_use_single_mesh_flag is equal to 1, its value is inferred to be equal to 1. bmsi_signalled_submesh_id_flag equal to 1 specifies that the submesh ID for each mesh frame is signalled. bmsi_signalled_tile_id_flag equal to 0 specifies that submesh IDs are not signalled. bmsi_signalled_submesh_id_delta_length minus! plus 1 Ceil( Lo«2( bmsi_num_submeshes_minusl + 1 ) ) specifies the number of bits used to represent the syntax element bmsi_tile_id[ i ] when present, and the syntax element submesh_id in a submesh header. The value of bmsi_signalled_submesh_t/fe_id_delta_length minus! shall be in the range of 0 to 15, inclusive. When not present, its value is inferred to be equal to Ceil( Log2( bmsi num submeshes minus! + 1 ) ) - 1 0. bmsi_submesh_id[ i ] specifies the tile ID of the i-th submesh. The length of the bmsi_submesh_id[ i ] syntax element is bmsi_signalled_submesh_id_length_minusl + 1 bits. When not present, the value of bmsi_submesh_id[ i ] is inferred to be equal to i, for each i in the range of 0 to bmsi_num_submeshes_minusl, inclusive. It is a requirement of bitstream conformance that bmsi_submesh_id[ i ] shall not be equal to bmsi_submesh_id[j ] for all i !=j. The length of the bmsi_submesh_id[ i ] syntax element is bmsi_signalled_submesh_id_length_minusl + 1 bits.

The variable FirstSubmeshlD is computed as follows:

FirstSubmeshID= bmsi_submesh_id[O ] for ( i = 1 ; i < bmsi_num_submeshes_minusl+ 1 ; i++ )

FirstSubmeshlD = Min(FirstSubmeshID, bmsi_submesh_id[ i ]) 5.6 Embodiment 6

[0083] This embodiment is for the invention item 6 summarized above in Section 4. The text changes are based on V-DMC WD 5 0 [5]

5.7 Embodiment 7

[0084] This embodiment is for the invention item 7 summarized above in Section 4. The text changes are based on V-DMC WD 5.0 [5],

5.8 Embodiment 8

[0085] This embodiment is for the invention item 8 summarized above in Section 4. The text changes are based on V-DMC WD 5.0 [5],

5 9 Embodiment 9

[0086] This embodiment is for the invention item 9 summarized above in Section 4. The text changes are based on V-DMC WD 5.0 [5],

5.10 Embodiment 10

[0087] This embodiment is for the invention item 10 summarized above in Section 4. The text changes are based on V-DMC WD 5.0 [5],

6. References

[1] MPEG technical requirements, “CfP for. Dynamic Mesh Coding,” ISO/IEC JTC 1 /SC 29/WG 2 doc. no. N145, in Oct 2021.

[2] K. Mammon, J. Kim, A. Tourapis and D. Podborski, “[V-CG] Apple’s Dynamic Mesh Coding CfP Response,” ISO/IEC JTC 1/SC 29/WG 7 doc no. m59281, in Apr. 2022

[3] MPEG output document, “WD 3.0 of V-DMC,” ISO/IEC JTC 1/SC 29/WG 7 doc. no. N00611, in Apr. 2023.

[4] C Huang, X. Xu, X Zhang, J. Tian and S. Liu, “Investigation of video coding of motion fields,” ISO/IEC JTC 1/SC 29/WG 7 doc. no. m61005, in Jul. 2022.

[5] MPEG output document, “WD 5.0 of V-DMC,” ISO/IEC JTC 1/SC 29/WG 7 doc. no. N00744, in Oct. 2023. [0088] FIG. 3 is a block diagram showing an example video processing system 4000 in which various techniques disclosed herein may be implemented. Various implementations may include some or all of the components of the system 4000. The system 4000 may include input 4002 for receiving video content. The video content may be received in a raw or uncompressed format, e.g., 8 or 10 bit multi-component pixel values, or may be in a compressed or encoded format. The input 4002 may represent a network interface, a peripheral bus interface, or a storage interface. Examples of network interface include wired interfaces such as Ethernet, passive optical network (PON), etc and wireless interfaces such as wireless fidelity (Wi-Fi) or cellular interfaces.

[0089] The system 4000 may include a coding component 4004 that may implement the various coding or encoding methods described in the present disclosure. The coding component 4004 may reduce the average bitrate of video from the input 4002 to the output of the coding component 4004 to produce a coded representation of the video The coding techniques are therefore sometimes called video compression or video transcoding techniques The output of the coding component 4004 may be either stored, or transmitted via a communication connected, as represented by the component 4006. The stored or communicated bitstream (or coded) representation of the video received at the input 4002 may be used by a component 4008 for generating pixel values or displayable video that is sent to a display interface 4010. The process of generating user- viewable video from the bitstream representation is sometimes called video decompression. Furthermore, while certain video processing operations are referred to as '‘coding” operations or tools, it will be appreciated that the coding tools or operations are used at an encoder and corresponding decoding tools or operations that reverse the results of the coding will be performed by a decoder.

[0090] Examples of a peripheral bus interface or a display interface may include universal serial bus (USB) or high definition multimedia interface (HDM1) or Displayport, and so on. Examples of storage interfaces include serial advanced technology attachment (SATA), peripheral component interconnect (PCI), integrated drive electronics (IDE) interface, and the like. The techniques described in the present disclosure may be embodied in various electronic devices such as mobile phones, laptops, smartphones or other devices that are capable of performing digital data processing and/or video display.

[0091] FIG. 4 is a block diagram of an example video processing apparatus 4100. The apparatus 4100 may be used to implement one or more of the methods described herein. The apparatus 4100 may be embodied in a smartphone, tablet, computer, Internet of Tilings (loT) receiver, and so on. The apparatus 4100 may include one or more processors 4102, one or more memories 4104 and video processing circuitry 4106. The processor(s) 4102 may be configured to implement one or more methods described in the present disclosure. The memory (memories) 4104 may be used for storing data and code used for implementing the methods and techniques described herein. The video processing circuitry 4106 may be used to implement, in hardware circuitry', some techniques described in the present disclosure. In some embodiments, the video processing circuitry' 4106 may be at least partly included in the processor 4102, e.g., a graphics co-processor.

[0092] FIG. 5 is a flowchart for an example method 4200 of video processing. The method 4200 determines that an absolute difference quantization parameter (QP) value for displacement coding is coded as an unsigned integer, at step 4202. In an embodiment, the unsigned integer comprises an unsigned integer Exponential-Golomb- coded using a variable number of bits (ue(v)). In an embodiment, the unsigned integer comprises an unsigned integer using n bits (u(n)), where n is greater than 6, where n is 7, or where n is 8. A conversion between a visual media data and a bitstream based on the absolute difference QP value for displacement coding is performed, at step 4204. The conversion may include encoding at an encoder, decoding at a decoder, or combinations thereof.

[0093] It should be noted that the method 4200 can be implemented in an apparatus for processing video data comprising a processor and a non-transitory memory' with instructions thereon, such as video encoder 4400, video decoder 4500, and/or encoder 4600. In such a case, the instructions upon execution by the processor, cause the processor to perform the method 4200. Further, the method 4200 can be performed by a non-transitory' computer readable medium comprising a computer program product for use by a video coding device The computer program product comprises computer executable instructions stored on the non-transitory computer readable medium such that when executed by a processor cause the video coding device to perform the method 4200

[0094] FIG. 6 is a block diagram that illustrates an example video coding system 4300 that may utilize the techniques of this disclosure The video coding system 4300 may include a source device 4310 and a destination device 4320 Source device 4310 generates encoded video data which may be referred to as a video encoding device. Destination device 4320 may decode the encoded video data generated by source device 4310 which may be referred to as a video decoding device.

[0095] Source device 4310 may include a video source 4312, a video encoder 4314, and an mput/output (I/O) interface 4316. Video source 4312 may include a source such as a video capture device, an interface to receive video data from a video content provider, and/or a computer graphics system for generating video data, or a combination of such sources. The video data may comprise one or more pictures. Video encoder 4314 encodes the video data from video source 4312 to generate a bitstream The bitstream may include a sequence of bits that form a coded representation of the video data. The bitstream may include coded pictures and associated data. The coded picture is a coded representation of a picture. The associated data may include sequence parameter sets, picture parameter sets, and other syntax structures. I/O interface 4316 may include a modulator/demodulator (modem) and/or a transmitter. The encoded video data may be transmitted directly to destination device 4320 via I/O interface 4316 througli network 4330. The encoded video data may also be stored onto a storage medium/server 4340 for access by destination device 4320.

[0096] Destination device 4320 may include an I/O interface 4326, a video decoder 4324, and a display device 4322. I/O interface 4326 may include a receiver and/or a modem. I/O interface 4326 may acquire encoded video data from the source device 4310 or the storage medium/ server 4340. Video decoder 4324 may decode the encoded video data Display device 4322 may display the decoded video data to a user. Display device 4322 may be integrated with the destination device 4320, or may be external to destination device 4320, which can be configured to interface with an external display device.

[0097] Video encoder 4314 and video decoder 4324 may operate according to a video compression standard, such as the High Efficiency Video Coding (HEVC) standard, Versatile Video Coding (VVC) standard and other current and/or further standards.

[0098] FIG. 7 is a block diagram illustrating an example of video encoder 4400, which may be video encoder 4314 in the system 4300 illustrated in FIG 6. Video encoder 4400 may be configured to perform any or all of the techniques of this disclosure. The video encoder 4400 includes a plurality of functional components. The techniques described in this disclosure may be shared among the various components of video encoder 4400. In some examples, a processor may be configured to perform any or all of the techniques described in this disclosure. [0099] The functional components of video encoder 4400 may include a partition unit 4401 , a prediction unit 4402 which may include a mode select unit 4403, a motion estimation unit 4404, a motion compensation unit 4405, an intra prediction unit 4406, a residual generation unit 4407, a transform processing unit 4408, a quantization unit 4409, an inverse quantization unit 4410, an inverse transform unit 4411, a reconstruction unit 4412, a buffer 4413, and an entropy encoding unit 4414.

[0100] In other examples, video encoder 4400 may include more, fewer, or different functional components. In an example, prediction unit 4402 may include an intra block copy (IBC) unit. The IBC unit may perform prediction in an IBC mode in which at least one reference picture is a picture where the current video block is located.

[0101] Furthermore, some components, such as motion estimation unit 4404 and motion compensation unit 4405 may be highly integrated, but are represented in the example of video encoder 4400 separately for purposes of explanation.

[0102] Partition unit 4401 may partition a picture into one or more video blocks. Video encoder 4400 and video decoder 4500 may support various video block sizes.

[0103] Mode select unit 4403 may select one of the coding modes, intra or inter, c.g., based on error results, and provide the resulting intra or inter coded block to a residual generation unit 4407 to generate residual block data and to a reconstruction unit 4412 to reconstruct the encoded block for use as a reference picture. In some examples, mode select unit 4403 may select a combination of intra and inter prediction (CIIP) mode in which the prediction is based on an inter prediction signal and an intra prediction signal. Mode select unit 4403 may also select a resolution for a motion vector (e. g. , a sub-pixel or integer pixel precision) for the block in the case of inter prediction. [0104] To perform inter prediction on a current video block, motion estimation unit 4404 may generate motion information for the current video block by comparing one or more reference frames from buffer 4413 to the current video block Motion compensation unit 4405 may determine a predicted video block for the current video block based on the motion information and decoded samples of pictures from buffer 4413 other than the picture associated with the current video block.

[0105] Motion estimation unit 4404 and motion compensation unit 4405 may perform different operations for a current video block, for example, depending on whether the current video block is in an I slice, a P slice, or a B slice.

[0106] In some examples, motion estimation unit 4404 may perform uni-directional prediction for the current video block, and motion estimation unit 4404 may search reference pictures of list 0 or list 1 for a reference video block for the current video block. Motion estimation unit 4404 may then generate a reference index that indicates the reference picture in list 0 or list 1 that contains the reference video block and a motion vector that indicates a spatial displacement between the current video block and the reference video block. Motion estimation unit 4404 may output the reference index, a prediction direction indicator, and the motion vector as the motion information of the current video block. Motion compensation unit 4405 may generate the predicted video block of the current block based on the reference video block indicated by the motion information of the current video block.

[0107] In other examples, motion estimation unit 4404 may perform bi-directional prediction for the current video block, motion estimation unit 4404 may search the reference pictures in list 0 for a reference video block for the current video block and may also search the reference pictures in list 1 for another reference video block for the current video block Motion estimation unit 4404 may then generate reference indexes that indicate the reference pictures in list 0 and list 1 containing the reference video blocks and motion vectors that indicate spatial displacements between the reference video blocks and the current video block. Motion estimation unit 4404 may output the reference indexes and the motion vectors of the current video block as the motion information of the current video block Motion compensation unit 4405 may generate the predicted video block of the current video block based on the reference video blocks indicated by the motion information of the current video block

[0108] In some examples, motion estimation unit 4404 may output a full set of motion information for decoding processing of a decoder. In some examples, motion estimation unit 4404 may not output a full set of motion information for the current video Rather, motion estimation unit 4404 may signal the motion information of the current video block with reference to the motion information of another video block. For example, motion estimation unit 4404 may determine that the motion information of the current video block is sufficiently similar to the motion information of a neighboring video block.

[0109] In one example, motion estimation unit 4404 may indicate, in a syntax structure associated with the current video block, a value that indicates to the video decoder 4500 that the current video block has the same motion information as another video block.

[0110] In another example, motion estimation unit 4404 may identify, in a syntax structure associated with the current video block, another video block and a motion vector difference (MVD). The motion vector difference indicates a difference between the motion vector of the current video block and the motion vector of the indicated video block. The video decoder 4500 may use the motion vector of the indicated video block and the motion vector difference to determine the motion vector of the current video block.

[0111] As discussed above, video encoder 4400 may predictively signal the motion vector. Two examples of predictive signaling techniques that may be implemented by video encoder 4400 include advanced motion vector prediction (AMVP) and merge mode signaling

[0112] Intra prediction unit 4406 may perform mtra prediction on the current video block. When intra prediction unit 4406 performs mtra prediction on the current video block, intra prediction unit 4406 may generate prediction data for the current video block based on decoded samples of other video blocks in the same picture. T he prediction data for the current video block may include a predicted video block and various syntax elements.

[0113] Residual generation unit 4407 may generate residual data for the current video block by subtracting the predicted video block(s) of the current video block from the current video block. The residual data of the current video block may include residual video blocks that correspond to different sample components of the samples in the current video block.

[0114] In other examples, there may be no residual data for the current video block for the current video block, for example in a skip mode, and residual generation unit 4407 may not perform the subtracting operation.

[0115] Transform processing unit 4408 may generate one or more transform coefficient video blocks for the current video block by applying one or more transforms to a residual video block associated with the current video block.

[0116] After transform processing unit 4408 generates a transform coefficient video block associated with the current video block, quantization unit 4409 may quantize the transform coefficient video block associated with the current video block based on one or more quantization parameter (QP) values associated with the current video block.

[0117] Inverse quantization unit 4410 and inverse transform unit 4411 may apply inverse quantization and inverse transforms to the transform coefficient video block, respectively, to reconstruct a residual video block from the transform coefficient video block. Reconstruction unit 4412 may add the reconstructed residual video block to corresponding samples from one or more predicted video blocks generated by the prediction unit 4402 to produce a reconstructed video block associated with the current block for storage in the buffer 4413.

[0118] After reconstruction unit 4412 reconstructs the video block, the loop filtering operation may be performed to reduce video blocking artifacts in the video block.

[0119] Entropy encoding unit 4414 may receive data from other functional components of the video encoder 4400. When entropy encoding unit 4414 receives the data, entropy encoding unit 4414 may perform one or more entropy encoding operations to generate entropy encoded data and output a bitstream that includes the entropy encoded data.

[0120] FIG. 8 is a block diagram illustrating an example of video decoder 4500 which may be video decoder 4324 in the system 4300 illustrated in FIG 6. The video decoder 4500 may be configured to perform any or all of the techniques of this disclosure. In the example shown, the video decoder 4500 includes a plurality of functional components. The techniques described in this disclosure may be shared among the various components of the video decoder 4500 In some examples, a processor may be configured to perform any or all of the techniques described in this disclosure.

[0121] In the example shown, video decoder 4500 includes an entropy decoding unit 4501, a motion compensation unit 4502, an intra prediction unit 4503, an inverse quantization unit 4504, an inverse transformation unit 4505, a reconstruction unit 4506, and a buffer 4507. Video decoder 4500 may, in some examples, perform a decoding pass generally reciprocal to the encoding pass described with respect to video encoder 4400.

[0122] Entropy decoding unit 4501 may retrieve an encoded bitstream The encoded bitstream may include entropy coded video data (e.g., encoded blocks of video data). Entropy decoding unit 4501 may decode the entropy coded video data, and from the entropy decoded video data, motion compensation unit 4502 may determine motion information including motion vectors, motion vector precision, reference picture list indexes, and other motion information. Motion compensation unit 4502 may, for example, determine such information by performing the AMVP and merge mode.

[0123] Motion compensation unit 4502 may produce motion compensated blocks, possibly performing interpolation based on interpolation filters. Identifiers for interpolation filters to be used with sub-pixel precision may be included in the syntax elements.

[0124] Motion compensation unit 4502 may use interpolation filters as used by video encoder 4400 during encoding of the video block to calculate interpolated values for sub-mteger pixels of a reference block. Motion compensation unit 4502 may determine the interpolation filters used by video encoder 4400 according to received syntax information and use the interpolation filters to produce predictive blocks.

[0125] Motion compensation unit 4502 may use some of the syntax information to determine sizes of blocks used to encode frame(s) and/or shce(s) of the encoded video sequence, partition information that describes how each macroblock of a picture of the encoded video sequence is partitioned, modes indicating how each partition is encoded, one or more reference frames (and reference frame lists) for each inter coded block, and other information to decode the encoded video sequence.

[0126] Intra prediction unit 4503 may use intra prediction modes for example received in the bitstream to form a prediction block from spatially adjacent blocks. Inverse quantization unit 4504 inverse quantizes, i.e., dequantizes, the quantized video block coefficients provided in the bitstream and decoded by entropy decoding unit 4501. Inverse transform unit 4505 applies an inverse transform.

[0127] Reconstruction unit 4506 may sum the residual blocks with the corresponding prediction blocks generated by motion compensation unit 4502 or intra prediction unit 4503 to form decoded blocks. If desired, a deblocking filter may also be applied to filter the decoded blocks in order to remove blockiness artifacts. The decoded video blocks are then stored in buffer 4507, which provides reference blocks for subsequent motion compensation/intra prediction and also produces decoded video for presentation on a display device

[0128] FIG. 9 is a schematic diagram of an example encoder 4600. The encoder 4600 is suitable for implementing the techniques of VVC The encoder 4600 includes three in-loop filters, namely a deblocking filter (DF) 4602, a sample adaptive offset (SAG) 4604, and an adaptive loop filter (ALF) 4606. Unlike the DF 4602, which uses predefined filters, the SAG 4604 and the ALF 4606 utilize the original samples of the current picture to reduce the mean square errors between the original samples and the reconstructed samples by adding an offset and by applying a finite impulse response (FIR) filter, respectively, with coded side information signaling the offsets and filter coefficients. The ALF 4606 is located at the last processing stage of each picture and can be regarded as a tool Irving to catch and fix artifacts created by the previous stages.

[0129] The encoder 4600 further includes an intra prediction component 4608 and a motion estimation/compensation (ME/MC) component 4610 configured to receive input video. The intra prediction component 4608 is configured to perform intra prediction, while the ME/MC component 4610 is configured to utilize reference pictures obtained from a reference picture buffer 4612 to perform inter prediction. Residual blocks from inter prediction or mtra prediction are fed into a transform (T) component 4614 and a quantization (Q) component 4616 to generate quantized residual transform coefficients, which are fed into an entropy coding component 4618. The entropy coding component 4618 entropy codes the prediction results and the quantized transform coefficients and transmits the same toward a video decoder (not shown). Quantization components output from the quantization component 4616 may be fed into an inverse quantization (IQ) components 4620, an inverse transform component 4622, and a reconstruction (REC) component 4624. The REC component 4624 is able to output images to the DF 4602, the SAO 4604, and the ALF 4606 for filtering prior to those images being stored in the reference picture buffer 4612.

[0130] A listing of solutions preferred by some examples is provided next.

[0131] The following solutions show examples of techniques discussed herein.

[0132] 1. A method for processing media data comprising: determining when not present, a value of bmsi_num_submeshes_minusl is inferred to be equal to 0: and performing a conversion between a visual media data and a bitstream based on the bmsi_num_submeshes_minusl .

[0133] 2. The method of solution 1, wherein the value of bmsi_num_submeshes_minus 1 shall be in the range of 0 to 255.

[0134] 3. The method of any of solutions 1 -2, wherein u(6) is used to signal bmsi_num_submeshes_minus 1. [0135] 4. The method of any of solutions 1-3, wherein N-bit is be used to signal bmsi_num_submeshes_minusl, and wherein N is greater than eight.

[0136] 5. The method of any of solutions 1-4, wherein u(N) is used to signal bmsi_num_submeshes_minus 1.

[0137] 6. The method of any of solutions 1-5, wherein N is equal to 12, 16, 24 or 32.

[0138] 7. The method of any of solutions 1 -6, wherein when there is only one submesh, the ID value of that submesh is not signalled.

[0139] 8. The method of any of solutions 1 -7, wherein when there is only one submesh, the ID value of that submesh is inferred to be equal to 0.

[0140] 9. The method of any of solutions 1-8, wherein a delta value between a number of bits to signal submesh IDs and a fixed value greater than 1 is indicated.

[0141] 10. The method of any of solutions 1-9, wherein the fixed value is Ceil( Log2( bmsi_num_submeshes_minusl + 1 ) ).

[0142] 11. The method of any of solutions 1-10, wherein the delta value, when not present, is inferred to be equal to 0.

[0143] 12. The method of any of solutions 1-11 , wherein the range of the delta value is from 0 to N

[0144] 13. The method of any of solutions 1-12, wherein N is equal to 15.

[0145] 14. An apparatus for processing video data comprising: a processor; and a non-transitory memory with instructions thereon, wherein the instructions upon execution by the processor, cause the processor to perform the method of any of solutions 1-13.

[0146] 15 A non-transitory computer readable medium comprising a computer program product for use by a video coding device, the computer program product comprising computer executable instructions stored on the non-transitory computer readable medium such that when executed by a processor cause the video coding device to perform the method of any of solutions 1-13.

[0147] 16 A non-transitory computer-readable recording medium storing a bitstream of a video which is generated by a method performed by a video processing apparatus, wherein the method comprises: determining when not present, a value of bmsi_num_submeshes_minusl is inferred to be equal to 0; and generating a bitstream based on the determining.

[0148] 17. A method for storing bitstream of a video comprising: determining when not present, a value of bmsi_num_submeshes_minusl is inferred to be equal to 0; generating a bitstream based on the determining: and storing the bitstream in a non-transitory computer -readable recording medium.

[0149] 18. A method, apparatus, or system described in the present disclosure.

[0150] In the solutions described herein, an encoder may conform to the format rule by producing a coded representation according to the format rule. In the solutions described herein, a decoder may use the format rule to parse syntax elements in the coded representation with the knowledge of presence and absence of syntax elements according to the format rule to produce decoded video.

[0151] In the present disclosure, the term “video processing” may refer to video encoding, video decoding, video compression or video decompression. For example, video compression algorithms may be applied during conversion from pixel representation of a video to a corresponding bitstream representation or vice versa. The bitstream representation of a current video block may, for example, correspond to bits that are either co-located or spread in different places within the bitstream, as is defined by the syntax For example, a macroblock may be encoded in terms of transformed and coded error residual values and also using bits in headers and other fields in the bitstream. Furthermore, during conversion, a decoder may parse a bitstream with the knowledge that some fields may be present, or absent, based on the determination, as is described in the above solutions Similarly, an encoder may determine that certain syntax fields are or are not to be included and generate the coded representation accordingly by including or excluding the syntax fields from the coded representation.

[0152] The disclosed and other solutions, examples, embodiments, modules and the functional operations described in this disclosure can be implemented in digital electronic circuitry, or in computer software, firmware, or hardware, including the structures disclosed in this disclosure and their structural equivalents, or in combinations of one or more of them. The disclosed and other embodiments can be implemented as one or more computer program products, i.e., one or more modules of computer program instructions encoded on a computer readable medium for execution by, or to control the operation of, data processing apparatus. The computer readable medium can be a machine-readable storage device, a machine -readable storage substrate, a memory device, a composition of matter effecting a machine-readable propagated signal, or a combination of one or more them. The term “data processing apparatus” encompasses all apparatus, devices, and machines for processing data, including by way of example a programmable processor, a computer, or multiple processors or computers. The apparatus can include, in addition to hardware, code that creates an execution environment for the computer program in question, e.g., code that constitutes processor firmware, a protocol stack, a database management system, an operating system, or a combination of one or more of them. A propagated signal is an artificially generated signal, e.g., a machinegenerated electrical, optical, or electromagnetic signal, that is generated to encode information for transmission to suitable receiver apparatus.

[0153] A computer program (also known as a program, softw are, software application, script, or code) can be written in any form of programming language, including compiled or interpreted languages, and it can be deployed in any fonn, including as a stand-alone program or as a module, component, subroutine, or other unit suitable for use in a computing environment. A computer program does not necessarily correspond to a file in a file system. A program can be stored in a portion of a file that holds other programs or data (e.g., one or more scripts stored in a markup language document), in a single file dedicated to the program in question, or in multiple coordinated files (e g , files that store one or more modules, sub programs, orportions of code) A computer program can be deployed to be executed on one computer or on multiple computers that are located at one site or distributed across multiple sites and interconnected by a communication network.

[0154] The processes and logic flows described in this disclosure can be performed by one or more programmable processors executing one or more computer programs to perform functions by operating on input data and generating output. The processes and logic flows can also be performed by, and apparatus can also be implemented as, special purpose logic circuitry, e.g., a field programmable gate array (FPGA) or an application specific integrated circuit (ASIC).

[0155] Processors suitable for the execution of a computer program include, by way of example, both general and special purpose microprocessors, and any one or more processors of any kind of digital computer. Generally, a processor will receive instructions and data from a read only memory or a random-access memory' or both. The essential elements of a computer are a processor for performing instructions and one or more memory' devices for storing instructions and data Generally, a computer will also include, or be operatively coupled to receive data from or transfer data to, or both, one or more mass storage devices for storing data, e.g., magnetic, magneto optical disks, or optical disks However, a computer need not have such devices. Computer readable media suitable for storing computer program instructions and data include all forms of non-volatile memory, media and memory devices, including by way of example semiconductor memory devices, e g , erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), and flash memory devices; magnetic disks, e.g , internal hard disks or removable disks; magneto optical disks; and compact disc read-only memory (CD ROM) and Digital versatile disc-read only memory' (DVD-ROM) disks. The processor and the memory can be supplemented by, or incorporated in, special purpose logic circuitry'.

[0156] While the present disclosure contains many specifics, these should not be construed as limitations on the scope of any subject matter or of what may be claimed, but rather as descriptions of features that may be specific to particular embodiments of particular techniques. Certain features that are described in the present disclosure in the context of separate embodiments can also be implemented in combination in a single embodiment. Conversely, various features that are described in the context of a single embodiment can also be implemented in multiple embodiments separately or in any suitable subcombination. Moreover, although features may be described above as acting in certain combinations and even initially claimed as such, one or more features from a claimed combination can in some cases be excised from the combination, and the claimed combination may be directed to a subcombination or variation of a subcombination.

[0157] Similarly, while operations are depicted in the drawings in a particular order, this should not be understood as requiring that such operations be performed in the particular order shown or in sequential order, or that all illustrated operations be performed, to achieve desirable results. Moreover, the separation of various system components in the embodiments described in the present disclosure should not be understood as requiring such separation in all embodiments.

[0158] Only a few implementations and examples are described and other implementations, enhancements and variations can be made based on what is described and illustrated in the present disclosure.

[0159] A first component is directly coupled to a second component when there are no intervening components, except for a line, a trace, or another medium between the first component and the second component. The first component is indirectly coupled to the second component when there are intervening components other than a line, a trace, or another medium between the first component and the second component. The term “coupled” and its variants include both directly coupled and indirectly coupled. The use of the term “about” means a range including ±10% of the subsequent number unless otherwise stated.

[0160] While several embodiments have been provided in the present disclosure, it should be understood that the disclosed systems and methods might be embodied in many other specific forms without departing from the spirit or scope of the present disclosure. The present examples are to be considered as illustrative and not restrictive, and the intention is not to be limited to the details given herein. For example, the various elements or components may be combined or integrated in another system or certain features may be omitted, or not implemented. [0161] In addition, techniques, systems, subsystems, and methods described and illustrated in the various embodiments as discrete or separate may be combined or integrated with other systems, modules, techniques, or methods without departing from the scope of the present disclosure. Other items shown or discussed as coupled may be directly connected or may be indirectly coupled or communicating through some interface, device, or intermediate component whether electrically, mechanically, or otherwise. Other examples of changes, substitutions, and alterations are ascertainable by one skilled in the art and could be made without departing from the spirit and scope disclosed herein.

Claims

CLAIMS What is claimed is:

1. A method for processing media data, comprising: determining that an absolute difference quantization parameter (QP) value for displacement coding is coded as an unsigned integer; and performing a conversion between a visual media data and a bitstream based on the absolute difference QP value for displacement coding.

2. The method of claim 1, wherein the unsigned integer comprises an unsigned integer Exponential- Golomb-coded using a variable number of bits (ue(v)).

3 The method of claim 1, wherein the unsigned integer comprises an unsigned integer using n bits (u(n)), where n is greater than 6.

4. The method of claim 1, wherein the unsigned integer comprises an unsigned integer using n bits (u(n)), where n is 7.

5. The method of claim 1, wherein the unsigned integer omprises an unsigned integer using n bits (u(n)), where n is 8.

6. The method of any of claims 1-5, wherein a number of attributes of a basemesh is coded as an unsigned integer Exponential-Golomb-coded using a variable number of bits (ue(v)).

7. The method of claim 6, wherein a range for the number of attributes of the basemesh is 0 to 127, inclusive.

8. The method of any of claims 1 -5, wherein a number of attributes of a test model of dynamic mesh coding (V-DMC) is coded as an unsigned integer Exponential-Golomb-coded using a variable number of bits (ue(v)).

9. The method of claim 8, wherein a range for the number of attributes of the V-DMC is 0 to 127, inclusive.

10. The method of any of claims 1 -9, wherein update parameters are not included in the bitstream when an update skip flag is equal to 1.

11. The method of claim 10, wherein the update parameters are inferred to be 0 when the update skip flag is equal to 1.

12. The method of any of claims 1-11, wherein an index of a method used to traverse vertices in static mesh coding is coded as an unsigned integer using n bits (u(n)), where n is positive integer.

13. The method of claim of claim 12, wherein n is 1.

14. The method of claim of claim 12, wherein n is 2.

15 The method of claim of claim 12, wherein n is 3

16. The method of any of claims 1 -11, wherein an index of a method used to traverse vertices in static mesh coding is coded as an unsigned integer Exponential-Golomb-coded using a variable number of bits (ue(v)) in a range from 0 to N, where N is a positive integer.

17. The method of claim of claim 16, wherein N is 1.

18. The method of claim of claim 16, wherein N is 3.

19. The method of claim of claim 16, w herein N is 7.

20. The method of any of claims 1-19, wherein a range of displacement coordinate information is coded as an unsigned integer using 2 bits (u(2)).

21. The method of any of claims 1-19, wherein a range of displacement coordinate information is coded as an unsigned integer Exponential-Golomb-coded using a variable number of bits (ue(v)) in a range from 0 to N, inclusive.

22 The method of claim 21 , wherein N is 1

23. The method of claim 1 , wherein N is 2.

24. The method of claim 21 , wherein N is 3.

25. The method of claim 21 , wherein N is 4.

26. The method of claim 21 , wherein N is 5.

27. The method of any of claims 1-26, wherein the conversion includes encoding the media data into the bitstream.

28. The method of any of claims 1-26, wherein the conversion includes decoding the media data from the bitstream.

29. An apparatus for processing video or image data comprising: a processor; and a non-transitory memory with instructions thereon, wherein the instructions upon execution by the processor, cause the processor to perform the method of any of claims 1-28.

30 A non-transitory computer readable medium comprising a computer program product for use by a video coding device, the computer program product comprising computer executable instructions stored on the non- transitory computer readable medium such that when executed by a processor cause the video coding device to perform the method of any of claims 1-28.

31. A non-transitory computer-readable recording medium storing a bitstream of a video which is generated by a method performed by a video processing apparatus, wherein the method comprises: determining that an absolute difference quantization parameter (QP) value for displacement coding is coded as an unsigned integer; and performing a conversion between a visual media data and a bitstream based on the absolute difference QP value for displacement coding.

32. A method for storing a bitstream of a video, comprising: determining that an absolute difference quantization parameter (QP) value for displacement coding is coded as an unsigned integer; generating the bitstream based on the absolute difference QP value for displacement coding; and storing the bitstream in a non-transitory computer-readable recording medium.

33. A method, apparatus, or system described in the present disclosure.