WO2025155358A2 - Quantum shift register codes - Google Patents

Abstract

Methods, systems, and apparatus for performing an error detection cycle of a quantum error correcting code. In one aspect, a method includes measuring a stabilizer operator, comprising: performing a respective entangling operation between a stabilizer qubit in a register of stabilizer qubits and one or more data qubits in a register of data qubits that are coupled to the stabilizer qubit; and for each of a number of repetitions, wherein the number of repetitions is dependent on a code distance of the quantum error correcting code: applying a sequence of local quantum gates for the repetition to stabilizer qubits included in the register of stabilizer qubits to logically shift the register of stabilizer qubits; and performing a respective entangling operation between the logically shifted stabilizer qubit and one or more data qubits in the register of data qubits that are coupled to the shifted stabilizer qubit.

Description

QUANTUM SHIFT REGISTER CODES

BACKGROUND

This specification relates to quantum computing.

Quantum computing provides a means to solve certain problems that cannot be solved in a reasonable period of time using conventional classical computers. These problems include factoring very large numbers into their primes and searching large, unstructured data sets. A number of physical systems are being explored for their use in quantum computing, including ions, spins in semiconductors, and superconducting circuits. However, none of these systems perform sufficiently well to serve directly as computational qubits. For example, single two-state physical systems, which can be used as physical qubits, cannot reliably encode and retain information for long enough to be useful.

Therefore, scalable quantum computers require quantum error correction. Error correction typically employs redundancy. For example, in the classical repetition code information is copied and stored multiple times. If the copies are later found to disagree, it can be determined that an error has occurred and a majority vote can be taken to recover the information. Copying quantum information is not possible due to the no-cloning theorem. Therefore, quantum error correction codes spread the logical information of one qubit onto an entangled state of multiple physical qubits. The multiple physical qubits are collectively referred to as a logical qubit. Reducing redundancy in quantum error correcting codes is an important area of research to improve the efficiency and scalability of quantum computing systems.

SUMMARY

This specification describes a new family of quantum error correcting codes referred to as quantum shift register codes.

One innovative aspect of the subject matter described in this specification can be implemented in a method for performing an error detection cycle of a quantum error correcting code using a quantum computer that comprises a register of stabilizer qubits and a register of data qubits. The method includes measuring a stabilizer operator, comprising: performing a respective entangling operation between a stabilizer qubit in the register of stabilizer qubits and one or more data qubits in the register of data qubits that are coupled to the stabilizer qubit; and for each of a number of repetitions, wherein the number of repetitions is dependent on a code distance of the quantum error correcting code: applying a sequence of local quantum gates for the repetition to stabilizer qubits included in the register of stabilizer qubits to logically shift the register of stabilizer qubits; and performing a respective entangling operation between the logically shifted stabilizer qubit and one or more data qubits in the register of data qubits that are coupled to the shifted stabilizer qubit.

Other implementations of these aspects include corresponding computer systems, apparatus, and computer programs recorded on one or more computer storage devices, each configured to perform the actions of the methods. A system of one or more classical and quantum computers can be configured to perform particular operations or actions by virtue of having software, firmware, hardware, or a combination thereof installed on the system that in operation causes or cause the system to perform the actions. One or more computer programs can be configured to perform particular operations or actions by virtue of including instructions that, when executed by data processing apparatus, cause the apparatus to perform the actions.

The foregoing and other implementations can each optionally include one or more of the following features, alone or in combination. In some implementations the quantum error correcting code comprises a wrapped hypergraph product of two classical cyclic simplex codes.

In some implementations a wrapping used to wrap the quantum error correcting code is dependent on an adjustable translational invariant symmetry parameter.

In some implementations the two classical cyclic simplex codes are the same and comprise same code parameters values.

In some implementations measuring the stabilizer operator comprises performing entangling operations between the stabilizer qubit or logically shifted stabilizer qubit and data qubits in the register of data qubits that are connected to the stabilizer qubit or logically shifted stabilizer qubit via local couplers.

In some implementations each stabilizer qubit in the register of stabilizer qubits has a weight that is larger than the number of data qubits to which the stabilizer qubit or logically shifted stabilizer qubit is physically coupled to.

In some implementations the quantum error correcting code comprises code parameters [[n, k, d]], wherein n = 46, k = 2, and d = 23.

In some implementations each stabilizer qubit in the register of stabilizer qubits is locally connected to three data qubits in the register of data qubits via local couplers and has weight 8. In some implementations the stabilizer operator comprises a product of eight Pauli matrices that act on three data qubits that are locally coupled to the stabilizer qubit and five data qubits that are non-local to the stabilizer qubit.

In some implementations the number of steps is equal to four; during a first step the sequence of local quantum gates logically shifts the register of stabilizer qubits in a first direction by three; during a second step the sequence of local quantum gates logically shifts the register of stabilizer qubits in the first direction by seven; during a third step the sequence of local quantum gates logically shifts the register of stabilizer qubits in the first direction by five; and during a fourth step the sequence of local quantum gates logically shifts the register of stabilizer qubits in the first direction by three.

In some implementations the register of stabilizer qubits and the register of data qubits comprise superconducting qubits.

In some implementations the quantum error correcting code comprises a hypergraph product of two classical cyclic simplex codes.

In some implementations each stabilizer qubit in the register of stabilizer qubits is connected to data qubits in the register of data qubits via local and non-local couplers.

In some implementations the register of stabilizer qubits and the register of data qubits comprise qubits realized by cold ions.

In some implementations the quantum error correcting code encodes two logical qubits.

In some implementations the sequence of local quantum gates for the repetition comprises SWAP gates implemented using ancilla qubits.

In some implementations the method further comprises processing the measured stabilizer operator to detect one or more errors in a quantum computation performed by the quantum computer. The method may further comprise correcting the one or more detected errors, e.g., as a post processing step in a quantum computation.

Another innovative aspect of the subject matter described in this specification can be implemented in a method performed by a quantum computer for quantum error correction of a quantum computation. The method includes performing a quantum error correction code to obtain a set of stabilizer measurements, wherein the quantum error correction code comprises a hypergraph product of two classical cyclic simplex codes; and providing the set of stabilizer measurements to a classical decoder to predict the occurrence of errors in the quantum computation. Other implementations of these aspects include corresponding computer systems, apparatus, and computer programs recorded on one or more computer storage devices, each configured to perform the actions of the methods. A system of one or more classical and quantum computers can be configured to perform particular operations or actions by virtue of having software, firmware, hardware, or a combination thereof installed on the system that in operation causes or cause the system to perform the actions. One or more computer programs can be configured to perform particular operations or actions by virtue of including instructions that, when executed by data processing apparatus, cause the apparatus to perform the actions.

The foregoing and other implementations can each optionally include one or more of the following features, alone or in combination. In some implementations the hypergraph product comprises a wrapped hypergraph product.

In some implementations the quantum error correction code encodes two logical qubits.

In some implementations performing a quantum error correction code comprises performing one or more error detection cycles.

Another innovative aspect of the subject matter described in this specification can be implemented in a quantum computing apparatus comprising: a register of data qubits, comprising a first circumferential array of data qubits and a second circumferential array of data qubits; a register of stabilizer qubits, comprising a third circumferential array of stabilizer qubits interleaved between the first and second circumferential arrays of data qubits; qubit couplers between data qubits in the first circumferential array and stabilizer qubits in the third circumferential array; qubit couplers between data qubits in the second circumferential array and stabilizer qubits in the third circumferential array; and control electronics configured to operate the register of data qubits, register of stabilizer qubits, and qubit couplers, wherein the control electronics are configured to perform operations for performing an error detection cycle of a quantum error correcting code.

The foregoing and other implementations can each optionally include one or more of the following features, alone or in combination. In some implementations the first circumferential array, second circumferential array, and third circumferential array comprise rings.

In some implementations the first circumferential array and second circumferential array are located on a first layer; the third circumferential array is located on a second layer; and the qubit couplers comprise inter-layer qubit couplers. The subject matter described in this specification can be implemented in particular ways so as to realize one or more of the following advantages.

The surface code is one of the most promising architectures for large-scale fault- tolerant quantum computing, as it has a high threshold error rate and can be implemented on a two-dimensional grid of qubits with nearest neighbor interactions. However, one of the main challenges with the surface code is its huge resource overhead. In general, a distance d surface code requires d² data physical qubits and (d — l)² ancilla physical qubits to encode one logical qubit. A fully fault-tolerant quantum computer based on the surface code and assuming realistic error rates is predicted to require millions of physical qubits. Practically, for any quantum computing hardware implementations and especially for those based on superconducting qubits, this large number of physical qubits translates into a huge number of wires that can introduce additional source of noise and dissipation and can increase the circuit complexity and fabrication difficulty'.

Reducing redundancy in the surface code is an important area of research to improve the efficiency and scalability of quantum computing systems. Some strategies attempt to reduce redundancy through higher level encoding. Traditional surface code implementations use a single level of encoding, where logical qubits are seconded into a grid of physical qubits. Higher-level encoding techniques aim to encode logical qubits into larger units, reducing the number of physical qubits needed. However, higher level encoding schemes often involve more complex encoding and decoding procedures compared to traditional surface codes. The process of converting logical qubits into the corresponding physical qubits and vice versa can be more intricate and computationally demanding. This complexity can introduce additional sources of errors and require more sophisticated control operations.

Other strategies that attempt to reduce redundancy include those based on Low Density' Parity check (LDPC) codes. However, existing LDPC codes have high weight (>4) checks, require long range connection between individual physical qubits and do not have any modularity. As a result, these codes are extremely difficult to implement in hardware.

The present disclosure describes a new family of quantum error correcting codes that substantially reduce resource overhead compared to known quantum error correcting codes, e.g., by a factor more than 10 compared to the surface code. In particular, they reduce the needed numbers of control wires by orders of magnitude. Further, the presently described quantum error correcting codes do not require more complex encoding and decoding procedures and do not require long-range connectivity between physical qubits. Further, the presently described quantum error correcting codes encode two logical qubits (unlike the surface code, which encodes one). Further, the presently described quantum error correcting codes can be efficiently implemented using different types of quantum computers, e.g., superconducting computers or using cold ions, and has a modular structure.

The details of one or more implementations of the subject matter of this specification are set forth in the accompanying drawings and the description below. Other features, aspects, and advantages of the subject matter will become apparent from the description, the drawings, and the claims.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 illustrates an example repetition code and an example cyclic simplex code.

FIG. 2 illustrates example connections between check nodes and variable nodes of an example classical cyclic simplex code.

FIG. 3 shows a graphical representation of an example quantum shift register code.

FIG. 4 shows an example superconducting physical implementation of a quantum shift register code.

FIG. 5 shows a graph that compares the logical error rate for a toric code and a quantum shift register code.

FIG. 6 depicts an example quantum computer.

DETAILED DESCRIPTION

This specification describes a new family of quantum error correcting codes referred to as quantum shift register codes. The quantum codes are obtained as a hypergraph product of two classical cyclic simplex codes with parameters [n, k, d], where n represents the codeword length, k represents the number of bits of information, and d represents the minimum Hamming distance. The translational invariant properties of the lattice generated by the hypergraph product and a wrapping technique are used to reduce resource overhead. As a result, quantum shift register codes have a smaller number of qubits compared to known quantum error correcting codes, while still maintaining the same error-correcting capability.

Classical cyclic simplex codes are particularly applicable to settings where it is important to be able to correct a large number of errors and important to be able to implement the code in hardware, since their generator polynomial can be implemented as a shift register in hardware. In cyclic simplex codes [n, k, d] the codewords are all multiples of a generator polynomial g x) of degree k — 1. The generator polynomial is a binary polynomial with coefficients in the field GF(2).

FIG. 1 illustrates an example repetition code and an example cyclic simplex code. As shown in FIG. 1, a cyclic simplex code can be represented by a graph with two types of nodes: variable nodes and check nodes. The variable nodes represent the codeword bits and the check nodes represent the parity check. Each variable node is connected to every check node that it is involved in a parity check. As an example, FIG. 1 illustrates a [15,4,8] simplex code where each check nodes checks 3 variable nodes. Check nodes are shown as hollow circles and variable nodes as filled circles. Each check node of the repetition code checks only the two neighbor variables nodes.

In contrast, in the simplex codes a check node checks nearest neighbor and distant variables nodes simultaneously (in this example at a distance a = 4).

The example of the quantum shift register code described below' is based on simplex codes Ci and C2 in which each check node checks 4 variables nodes: tw o nearest neighbor and two additional ones at distance a = 2 and b = 3, respectively. The cyclic simplex codes Ci and C2 are identical and = [23,1,23], however different simplex codes can also be used.

The hypergraph product code Ci C2 belongs to the general class of Calderbank, Shor and Steane (CSS) quantum codes and it characterized by [[1058,2,23]], where the X and Z stabilizers have weight 8 and have also long-range connections. For comparison, the X and Z stabilizers of the toric/surface code have w eight 4 and have only local connections. In this code, the hypergraph product quantum code is wrapped to reduce the resource overhead. The wrapping is determined by the translational invariant symmetry: T(x, y) = T(x + R, y — 1). For R = 5, a quantum CSS code C_q=[[46,2,23]] is obtained, where the code parameters [[46,2,23]] means that 46 is the number of data qubits, 2 is the number of logical qubits encoded and 23 is the distance of the quantum code. The distance of the quantum code C_q is the Hamming distance of the simplex code Cl and C2.

The values = 23, a = 2, b = 3, R = 3 have been chosen after optimization of the logical error rate of the quantum code C_q and are a non-limiting example only. Other values can also be used.

The quantum code C_q encodes two logical qubits. In this respect, it is similar to the toric code (that is difficult to realize in hardware because of periodic boundary conditions) but not to the surface code that encodes only one logical qubit. Because the stabilizers of the quantum code C_q are non-local and have weight 8, it could be expected that any hardware implementation of these stabilizers is extremely hard to realize (if not impossible). However, the presently described quantum shift register codes do not share the same difficulties of the hardware implementations of any powerful quantum expander codes, as described in more detail below.

To explain the advantage of the shift register, consider FIG. 2 that illustrates an example of a classical cyclic simplex code. In particular, FIG. 2 shows how each check node of the classical cyclic simplex code is connected to four variables nodes involved in the parity check matrix (each check node is connected to the variable nodes (1, 2, 4, 5)). This structure is the result of having chosen distances a = 2 and b = 3 and it translates into the fact that for this cyclic simplex code each check node that is supposed to check four variable nodes can be realized by checking two neighbor variable nodes (1,2) , shifting the variable nodes register by +3, checking again the same neighbor variable nodes that now are (4,5). The shift register nature of the classical codes provides a realization of a hardware implementation of the quantum code C_q in which each stabilizer has only 3 physical connections to realize stabilizers with weight 8, as shown in FIG. 3.

FIG. 3 shows a graphical representation of an example quantum shift register code [[46, 2, 23]]. In FIG. 3, each qubit is represented by a shaded (grey) vertex in the graph. The qubits are located in two rings: 23 qubits in the outer ring and 23 qubits in the inner ring (although a ring is a non-limiting example, other shapes or geometries could be used, generally the qubits could be arranged circumferentially). The qubits are checked by the stabilizers (Xi and Zi with i — 1, ... 23). The stabilizers Xi and Zi commute and are physically connected locally to 3 qubits. Mathematically, the stabilizers have weight 8. The measurement of the stabilizers are achieved by shifting the stabilizer register following the sequence (+3, +7, +5, +3) for the Xi stabilizer and (-3, -7, -5, -3) for the Zi stabilizer. These sequences are determined by the desired logical connections of the wrapped hypergraph product of the simplex codes.

The code encodes two logical qubits. The logical states are: i oo) = f a + .) | oo- -oo) 11 o> = A'2 I oo) with logical operators:

The logical operators overlap fully. As a result, the logical operators and T_L ² can be achieved transversally. The anti-commutation property of the logical operators are guaranteed by the odd number of qubits in the inner and outer ring.

Physically, each stabilizer connects three neighbor physical qubits. However, mathematically, the weight of the stabilizer is 8. Examples of Xi and Zi stabilizers are explicitly written in FIG. 3. The stabilizer Xi is given by the product of 8 X-Pauli matrices acting on 3 neighbor physical qubits and 5 non-local physical qubits. The non-local connections of the stabilizers are achieved by resorting to the shift register properties of the code. The shift of the stabilizer register is achieved by using only local gates. The efficiency of this quantum error correcting code depends crucially on the hardware implementation of the shift register, in particular, on the fidelity and the velocity of execution of the shift.

For a hardware implementation with superconducting qubits, the code can be fabricated on a bi-layer structure. Qubits and stabilizers can be located in two different layers. Entangling gates, e.g., CZ gates can be realized with inter-layer connections, while the shift register can be realized on the layer of the stabilizer using SWAP gates and additional ancilla qubits. FIG. 4 shows an example superconducting physical implementation of a quantum shift register code [[46,2,23]]. The qubits (shaded) are located on two rings (23+23) on one layer. The qubits are not coupled. The alternating stabilizers Xi (shaded circles) and Zi (filled circles) commute and are physically connected locally to 3 qubits. Entangling gates can be performed between the two layers. The shift of the stabilizers on the upper layer is achieved by a sequence of SWAPS with the help of 23 auxiliary ancilla qubits (hollow circles). The number of ancilla qubits required will equal the number of stabilizer qubits.

A hardware implementation with cold ions is also possible, where the movements and swaps of train of ions in linear traps have been already achieved and the quantum shift register code C_q can be realized without ancilla qubits.

FIG. 5 shows a graph that compares the logical error rate for a toric code and a quantum shift register code. The logical error rate PL is the probability that a logical operation will fail due to errors in the physical qubits. In FIG. 5, an error model where the physical qubits has a probability of flip error p is considered. As shown, for similar values of qubit overhead, the quantum shift register code Cq significantly outperforms the toric code.

The logical error rate of the toric/surface code is a function of the physical error rate and the distance d of the code. The higher the distance the lower the logical error rate:

Where p* = 0.1 is the error threshold of the surface code. FIG. 5 shows that, for a physical flip error p — 0.03, the logical error rate for the quantum shift register code Cq is P_L 4 ■ 10“⁶. In order to achieve this value of logical error rate, for physical flip error p = 0.03, a distance d = 19 surface code with n = 361 physical qubits is needed.

Another advantage of the quantum shift register code Cq is its modular structure. In fact, every pairs of logical qubits can be implemented separately.

FIG. 6 depicts an example quantum computer 600 for performing the quantum operations described in this specification. The example quantum computer 600 includes an example quantum computing device 602. The quantum computing device 602 is intended to represent various forms of quantum computing devices. The components shown here, their connections and relationships, and their functions, are exemplary only, and do not limit implementations of the inventions described and/or claimed in this document.

The example quantum computing device 602 includes a qubit assembly 652 and a control and measurement system 604. The qubit assembly 652 includes multiple physical qubits, e.g., qubit 606, that are used to perform algorithmic operations or quantum computations. While the qubits shown in FIG. 6 are arranged in a rectangular array, this is a schematic depiction and is not intended to be limiting. The qubit assembly 652 also includes adjustable coupling elements, e g., coupler 608, that allow for interactions between coupled qubits. In the schematic depiction of FIG. 6, each qubit is adjustably coupled to each of its four adjacent qubits by means of respective coupling elements. However, this is an example arrangement of qubits and couplers and other arrangements are possible, including arrangements that are non-rectangular, arrangements that allow for coupling between nonadj acent qubits, and arrangements that include adjustable coupling between more than two qubits.

Each qubit can be a physical two-level quantum system or device having levels representing logical values of 0 and 1. The specific physical realization of the multiple qubits and how they interact with one another is dependent on a variety of factors including the type of the quantum computing device 602 included in the example computer 600 or the type of quantum computations that the quantum computing device is performing. For example, in an atomic quantum computer the qubits may be realized via atomic, molecular or solid-state quantum systems, e.g., hyperfine atomic states. As another example, in a superconducting quantum computer the qubits may be realized via superconducting qubits or semi-conducting qubits, e.g., superconducting transmon states. As another example, in a NMR quantum computer the qubits may be realized via nuclear spin states.

In some implementations a quantum computation can proceed by loading qubits, e.g., from a quantum memory', and applying a sequence of unitary operators to the qubits. Applying a unitary operator to the qubits can include applying a corresponding sequence of quantum logic gates to the qubits, e.g., to implement the surface code circuits described in this specification. Example quantum logic gates include single-qubit gates, e.g., Pauli-X, Pauli-Y, Pauli-Z (also referred to as X, Y, Z), Hadamard gates, S gates, rotations, two-qubit gates, e.g., controlled-X, controlled-Y, controlled-Z (also referred to as CX, CY, CZ), controlled NOT gates (also referred to as CNOT) controlled swap gates (also referred to as CSWAP), iSWAP gates, and gates involving three or more qubits, e.g.. Toffoli gates. The quantum logic gates can be implemented by applying control signals 610 generated by the control and measurement system 604 to the qubits and to the couplers.

For example, in some implementations the qubits in the qubit assembly 652 can be frequency tunable. In these examples, each qubit can have associated operating frequencies that can be adjusted through application of voltage pulses via one or more drive-lines coupled to the qubit. Example operating frequencies include qubit idling frequencies, qubit interaction frequencies, and qubit readout frequencies. Different frequencies correspond to different operations that the qubit can perform. For example, setting the operating frequency to a corresponding idling frequency may put the qubit into a state where it does not strongly interact with other qubits, and where it may be used to perform single-qubit gates. As another example, in cases where qubits interact via couplers with fixed coupling, qubits can be configured to interact with one another by setting their respective operating frequencies at some gate-dependent frequency detuning from their common interaction frequency. In other cases, e.g., when the qubits interact via tunable couplers, qubits can be configured to interact with one another by setting the parameters of their respective couplers to enable interactions between the qubits and then by setting the qubit’s respective operating frequencies at some gate-dependent frequency detuning from their common interaction frequency. Such interactions may be performed in order to perform multi-qubit gates. The type of control signals 610 used depends on the physical realizations of the qubits. For example, the control signals may include RF or microwave pulses in an NMR or superconducting quantum computer system, or optical pulses in an atomic quantum computer system.

A quantum computation can be completed by measuring the states of the qubits, e.g., using a quantum observable such as X or Z, using respective control signals 610. The measurements cause readout signals 612 representing measurement results to be communicated back to the measurement and control system 604. The readout signals 612 may include RF, microwave, or optical signals depending on the physical scheme for the quantum computing device and/or the qubits. For convenience, the control signals 610 and readout signals 612 shown in FIG. 6 are depicted as addressing only selected elements of the qubit assembly (i.e., the top and bottom rows), but during operation the control signals 610 and readout signals 612 can address each element in the qubit assembly 652.

The control and measurement system 604 is an example of a classical computer system that can be used to perform various operations on the qubit assembly 652, as described above, as well as other classical subroutines or computations. The control and measurement system 604 includes one or more classical processors, e.g., classical processor 614, one or more memories, e.g., memory' 616, and one or more I/O units, e.g., I/O unit 618, connected by one or more data buses. The control and measurement system 604 can be programmed to send sequences of control signals 610 to the qubit assembly, e.g.. to carry out a selected series of quantum gate operations, and to receive sequences of readout signals 612 from the qubit assembly, e.g., as part of performing measurement operations.

The processor 614 is configured to process instructions for execution within the control and measurement system 604. In some implementations, the processor 614 is a single-threaded processor. In other implementations, the processor 614 is a multi -threaded processor. The processor 614 is capable of processing instructions stored in the memory⁷ 616.

The memory 616 stores information within the control and measurement system 604. In some implementations, the memory 616 includes a computer-readable medium, a volatile memory unit, and/or a non-volatile memory unit. In some cases, the memory 616 can include storage devices capable of providing mass storage for the system 604, e.g., a hard disk device, an optical disk device, a storage device that is shared over a network by multiple computing devices (e.g., a cloud storage device), and/or some other large capacity storage device. The input/output device 618 provides input/output operations for the control and measurement system 604. The input/output device 618 can include D/A converters, A/D converters, and RF/microwave/optical signal generators, transmitters, and receivers, whereby to send control signals 610 to and receive readout signals 612 from the qubit assembly, as appropriate for the physical scheme for the quantum computer. In some implementations, the input/output device 618 can also include one or more network interface devices, e.g.. an Ethernet card, a serial communication device, e.g., an RS-232 port, and/or a wireless interface device, e.g., an 802.11 card. In some implementations, the input/output device 618 can include driver devices configured to receive input data and send output data to other external devices, e.g., keyboard, printer, and display devices.

Although an example control and measurement system 604 has been depicted in FIG. 6, implementations of the subject matter and the functional operations described in this specification can be implemented in other types of digital electronic circuitry, or in computer software, firmware, or hardware, including the structures disclosed in this specification and their structural equivalents, or in combinations of one or more of them.

Implementations of the subject matter and operations described in this specification can be implemented in digital electronic circuitry, analog electronic circuitry, suitable quantum circuitry or, more generally, quantum computational systems, in tangibly -embodied software or firmware, in computer hardware, including the structures disclosed in this specification and their structural equivalents, or in combinations of one or more of them. The term “quantum computational systems” may include, but is not limited to, quantum computers, quantum information processing systems, quantum cryptography systems, or quantum simulators.

Implementations of the subject matter described in this specification can be implemented as one or more computer programs, i.e., one or more modules of computer program instructions encoded on a tangible non-transitory storage medium for execution by, or to control the operation of, data processing apparatus. The computer storage medium can be a machine-readable storage device, a machine-readable storage substrate, a random or serial access memory device, one or more qubits, or a combination of one or more of them. Alternatively, or in addition, the program instructions can be encoded on an artificially- generated propagated signal that is capable of encoding digital and/or quantum information, e.g., a machine-generated electrical, optical, or electromagnetic signal, that is generated to encode digital and/or quantum information for transmission to suitable receiver apparatus for execution by a data processing apparatus. The terms quantum information and quantum data refer to information or data that is carried by, held or stored in quantum systems, where the smallest non-trivial system is a qubit, i.e., a system that defines the unit of quantum information. It is understood that the term '‘qubit” encompasses all quantum systems that may be suitably approximated as a two- level system in the corresponding context. Such quantum systems may include multi-level systems, e.g., with two or more levels. By way of example, such systems can include atoms, electrons, photons, ions or superconducting qubits. In many implementations the computational basis states are identified with the ground and first excited states, however it is understood that other setups where the computational states are identified with higher level excited states are possible.

The term “data processing apparatus” refers to digital and/or quantum data processing hardware and encompasses all kinds of apparatus, devices, and machines for processing digital and/or quantum data, including by way of example a programmable digital processor, a programmable quantum processor, a digital computer, a quantum computer, multiple digital and quantum processors or computers, and combinations thereof. The apparatus can also be, or further include, special purpose logic circuitry, e.g., an FPGA (field programmable gate array), an ASIC (application-specific integrated circuit), or a quantum simulator, i.e , a quantum data processing apparatus that is designed to simulate or produce information about a specific quantum system. In particular, a quantum simulator is a special purpose quantum computer that does not have the capability to perform universal quantum computation. The apparatus can optionally include, in addition to hardware, code that creates an execution environment for digital and/or quantum computer programs, e.g., code that constitutes processor firmware, a protocol stack, a database management system, an operating system, or a combination of one or more of them.

A digital computer program, which may also be referred to or described as a program, software, a software application, a module, a software module, a script, or code, can be written in any form of programming language, including compiled or interpreted languages, or declarative or procedural languages, and it can be deployed in any form, including as a stand-alone program or as a module, component, subroutine, or other unit suitable for use in a digital computing environment. A quantum computer program, which may also be referred to or described as a program, software, a software application, a module, a software module, a script, or code, can be written in any form of programming language, including compiled or interpreted languages, or declarative or procedural languages, and translated into a suitable quantum programming language, or can be written in a quantum programming language, e.g., QCL or Quipper.

A computer program may, but need not, correspond to a file in a file system. A program can be stored in a portion of a file that holds other programs or data, e.g., one or more scripts stored in a markup language document, in a single file dedicated to the program in question, or in multiple coordinated files, e.g., files that store one or more modules, subprograms, or portions of code. A computer program can be deployed to be executed on one computer or on multiple computers that are located at one site or distributed across multiple sites and interconnected by a digital and/or quantum data communication network. A quantum data communication network is understood to be a network that may transmit quantum data using quantum systems, e.g. qubits. Generally, a digital data communication network cannot transmit quantum data, however a quantum data communication network may transmit both quantum data and digital data.

The processes and logic flows described in this specification can be performed by one or more programmable computers, operating with one or more processors, as appropriate, executing one or more computer programs to perform functions by operating on input data and generating output. The processes and logic flows can also be performed by, and apparatus can also be implemented as, special purpose logic circuitry', e.g., an FPGA or an ASIC, or a quantum simulator, or by a combination of special purpose logic circuitry or quantum simulators and one or more programmed digital and/or quantum computers.

For a system of one or more computers to be “configured to” perform particular operations or actions means that the system has installed on its software, firmware, hardware, or a combination of them that in operation cause the system to perform the operations or actions. For one or more computer programs to be configured to perform particular operations or actions means that the one or more programs include instructions that, when executed by data processing apparatus, cause the apparatus to perform the operations or actions. For example, a quantum computer may receive instructions from a digital computer that, when executed by the quantum computing apparatus, cause the apparatus to perform the operations or actions.

Computers suitable for the execution of a computer program can be based on general or special purpose processors, or any other kind of central processing unit. Generally, a central processing unit will receive instructions and data from a read-only memory, a random access memory, or quantum systems suitable for transmitting quantum data, e.g. photons, or combinations thereof. The elements of a computer include a central processing unit for performing or executing instructions and one or more memory devices for storing instructions and digital, analog, and/or quantum data. The central processing unit and the memory can be supplemented by, or incorporated in, special purpose logic circuitry or quantum simulators. Generally, a computer will also include, or be operatively coupled to receive data from or transfer data to, or both, one or more mass storage devices for storing data, e.g., magnetic, magneto-optical disks, optical disks, or quantum systems suitable for storing quantum information. However, a computer need not have such devices.

Quantum circuit elements (also referred to as quantum computing circuit elements) include circuit elements for performing quantum processing operations. That is, the quantum circuit elements are configured to make use of quantum-mechanical phenomena, such as superposition and entanglement, to perform operations on data in a non-deterministic manner. Certain quantum circuit elements, such as qubits, can be configured to represent and operate on information in more than one state simultaneously. Examples of superconducting quantum circuit elements include circuit elements such as quantum LC oscillators, qubits (e.g., flux qubits, phase qubits, or charge qubits), and superconducting quantum interference devices (SQUIDs) (e.g., RF-SQUID or DC-SQUID), among others.

In contrast, classical circuit elements generally process data in a deterministic manner. Classical circuit elements can be configured to collectively carry out instructions of a computer program by performing basic arithmetical, logical, and/or input/output operations on data, in which the data is represented in analog or digital form. In some implementations, classical circuit elements can be used to transmit data to and/or receive data from the quantum circuit elements through electrical or electromagnetic connections. Examples of classical circuit elements include circuit elements based on CMOS circuitry’, rapid single flux quantum (RSFQ) devices, reciprocal quantum logic (RQL) devices and ERSFQ devices, which are an energy-efficient version of RSFQ that does not use bias resistors.

In certain cases, some or all of the quantum and/or classical circuit elements may be implemented using, e.g., superconducting quantum and/or classical circuit elements. Fabrication of the superconducting circuit elements can entail the deposition of one or more materials, such as superconductors, dielectrics and/or metals. Depending on the selected material, these materials can be deposited using deposition processes such as chemical vapor deposition, phy sical vapor deposition (e.g., evaporation or sputtering), or epitaxial techniques, among other deposition processes. Processes for fabricating circuit elements described herein can entail the removal of one or more materials from a device during fabrication. Depending on the material to be removed, the removal process can include, e.g., wet etching techniques, dry etching techniques, or lift-off processes. The materials forming the circuit elements described herein can be patterned using known lithographic techniques (e.g., photolithography or e-beam lithography).

During operation of a quantum computational system that uses superconducting quantum circuit elements and/or superconducting classical circuit elements, such as the circuit elements described herein, the superconducting circuit elements are cooled down within a cryostat to temperatures that allow a superconductor material to exhibit superconducting properties. A superconductor (alternatively superconducting) material can be understood as material that exhibits superconducting properties at or below a superconducting critical temperature. Examples of superconducting material include aluminum (superconductive critical temperature of 1.2 kelvin) and niobium (superconducting critical temperature of 9.3 kelvin). Accordingly, superconducting structures, such as superconducting traces and superconducting ground planes, are formed from material that exhibits superconducting properties at or below a superconducting critical temperature.

In certain implementations, control signals for the quantum circuit elements (e.g., qubits and qubit couplers) may be provided using classical circuit elements that are electrically and/or electromagnetically coupled to the quantum circuit elements. The control signals may be provided in digital and/or analog form.

Computer-readable media suitable for storing computer program instructions and data include all forms of non-volatile digital and/or quantum memory, media and memory devices, including by way of example semiconductor memory devices, e.g., EPROM, EEPROM, and flash memory' devices; magnetic disks, e.g., internal hard disks or removable disks; magnetooptical disks; CD-ROM and DVD-ROM disks; and quantum systems, e.g., trapped atoms or electrons. It is understood that quantum memories are devices that can store quantum data for a long time with high fidel i ty and efficiency, e.g., light-matter interfaces where light is used for transmission and matter for storing and preserving the quantum features of quantum data such as superposition or quantum coherence.

Control of the various systems described in this specification, or portions of them, can be implemented in a computer program product that includes instructions that are stored on one or more non-transitory machine-readable storage media, and that are executable on one or more processing devices. The systems described in this specification, or portions of them, can each be implemented as an apparatus, method, or system that may include one or more processing devices and memory to store executable instructions to perform the operations described in this specification.

While this specification contains many specific implementation details, these should not be constmed as limitations on the scope of what may be claimed, but rather as descriptions of features that may be specific to particular implementations. Certain features that are described in this specification in the context of separate implementations can also be implemented in combination in a single implementation. Conversely, various features that are described in the context of a single implementation can also be implemented in multiple implementations separately or in any suitable sub-combination. Moreover, although features may be described above as acting in certain combinations and even initially claimed as such, one or more features from a claimed combination can in some cases be excised from the combination, and the claimed combination may be directed to a sub-combination or variation of a sub-combination.

Similarly, while operations are depicted in the drawings in a particular order, this should not be understood as requiring that such operations be performed in the particular order shown or in sequential order, or that all illustrated operations be performed, to achieve desirable results. In certain circumstances, multitasking and parallel processing may be advantageous. Moreover, the separation of various system modules and components in the implementations described above should not be understood as requiring such separation in all implementations, and it should be understood that the described program components and systems can generally be integrated together in a single software product or packaged into multiple software products.

Particular implementations of the subject matter have been described. Other implementations are within the scope of the following claims. For example, the actions recited in the claims can be performed in a different order and still achieve desirable results. As one example, the processes depicted in the accompanying figures do not necessarily require the particular order shown, or sequential order, to achieve desirable results. In some cases, multitasking and parallel processing may be advantageous.

Claims

1. A method for performing an error detection cycle of a quantum error correcting code using a quantum computer that comprises a register of stabilizer qubits and a register of data qubits, the method comprising: measuring a stabilizer operator, comprising: performing a respective entangling operation between a stabilizer qubit in the register of stabilizer qubits and one or more data qubits in the register of data qubits that are coupled to the stabilizer qubit; and for each of a number of repetitions, wherein the number of repetitions is dependent on a code distance of the quantum error correcting code: applying a sequence of local quantum gates for the repetition to stabilizer qubits included in the register of stabilizer qubits to logically shift the register of stabilizer qubits; and performing a respective entangling operation between the logically shifted stabilizer qubit and one or more data qubits in the register of data qubits that are coupled to the shifted stabilizer qubit.

2. The method of claim 1, wherein the quantum error correcting code comprises a wrapped hypergraph product of two classical cyclic simplex codes.

3. The method of claim 1, wherein a wrapping used to wrap the quantum error correcting code is dependent on an adjustable translational invariant symmetry parameter.

4. The method of claim 2 or claim 3, wherein the two classical cyclic simplex codes are the same and comprise same code parameters values.

5. The method of any one of claims 1 to 4, wherein measuring the stabilizer operator comprises performing entangling operations between the stabilizer qubit or logically shifted stabilizer qubit and data qubits in the register of data qubits that are connected to the stabilizer qubit or logically shifted stabilizer qubit via local couplers.

6. The method of claim 5, wherein each stabilizer qubit in the register of stabilizer qubits has a weight that is larger than the number of data qubits to which the stabilizer qubit or logically shifted stabilizer qubit is physically coupled to.

7. The method of any one of claims 1 to 6, wherein the quantum error correcting code comprises code parameters [[ , k, d]], wherein n = 46, k = 2, and d = 23, where n represents a codeword length, k represents a number of bits of information, and d represents a minimum Hamming distance.

8. The method of claim 7, wherein each stabilizer qubit in the register of stabilizer qubits is locally connected to three data qubits in the register of data qubits via local couplers and has weight 8.

9. The method of claim 7, wherein the stabilizer operator comprises a product of eight Pauli matrices that act on three data qubits that are locally coupled to the stabilizer qubit and five data qubits that are non-local to the stabilizer qubit.

10. The method of claim 7, wherein: the number of steps is equal to four; during a first step the sequence of local quantum gates logically shifts the register of stabilizer qubits in a first direction by three; during a second step the sequence of local quantum gates logically shifts the register of stabilizer qubits in the first direction by seven; during a third step the sequence of local quantum gates logically shifts the register of stabilizer qubits in the first direction by five; and during a fourth step the sequence of local quantum gates logically shifts the register of stabilizer qubits in the first direction by three.

1 1. The method of any one of claims 2 to 10, wherein the register of stabilizer qubits and the register of data qubits comprise superconducting qubits.

12. The method of claim 1, wherein the quantum error correcting code comprises a hypergraph product of two classical cyclic simplex codes.

13. The method of claim 12, wherein each stabilizer qubit in the register of stabilizer qubits is connected to data qubits in the register of data qubits via local and non-local couplers.

14. The method of claim 12 or claim 13, wherein the register of stabilizer qubits and the register of data qubits comprise qubits realized by cold ions.

15. The method of any one of claims 1 to 14, wherein the quantum error correcting code encodes two logical qubits.

16. The method of any one of claims 1 to 15, wherein the sequence of local quantum gates for the repetition comprises SWAP gates implemented using ancilla qubits.

17. The method of any one of claims 1 to 16, further comprising processing the measured stabilizer operator to detect errors in a quantum computation performed by the quantum computer.

18. A method performed by a quantum computer for quantum error correction of a quantum computation, the method comprising: performing a quantum error correction code to obtain a set of stabilizer measurements, wherein the quantum error correction code comprises a hypergraph product of two classical cyclic simplex codes; and providing the set of stabilizer measurements to a classical decoder to predict the occurrence of errors in the quantum computation.

19. The method of claim 18, wherein the hypergraph product comprises a wrapped hypergraph product.

20. The method of claim 18 or 19. wherein the quantum error correction code encodes two logical qubits.

21. The method of claim 18, wherein performing a quantum error correction code comprises performing one or more error detection cycles, wherein performing an error detection cycle comprises performing operations according to the method of any one of claims 1 to 17.

22. A quantum computing apparatus comprising: a plurality' of physical qubits; qubit couplers defining interactions between the plurality of qubits; and control electronics configured to operate the plurality of qubits and qubit couplers, wherein the control electronics are configured to perform operations for performing an error detection cycle of a quantum error correcting code, the operations comprising the method of any one of claims 1 to 21.

23. A quantum computing apparatus comprising: a register of data qubits, comprising a first circumferential array of data qubits and a second circumferential array of data qubits; a register of stabilizer qubits, comprising a third circumferential array of stabilizer qubits interleaved between the first and second circumferential arrays of data qubits; qubit couplers between data qubits in the first circumferential array and stabilizer qubits in the third circumferential array; qubit couplers between data qubits in the second circumferential array and stabilizer qubits in the third circumferential array; and control electronics configured to operate the register of data qubits, register of stabilizer qubits, and qubit couplers, wherein the control electronics are configured to perform operations for performing an error detection cycle of a quantum error correcting code, the operations comprising the method of any one of claims 1 to 21.

24. The quantum computing apparatus of claim 23, wherein the first circumferential array, second circumferential array, and third circumferential array comprise rings.

25. The quantum computing apparatus of claim 23 or claim 24. wherein: the first circumferential array and second circumferential array are located on a first layer; the third circumferential array is located on a second layer; and the qubit couplers comprise inter-layer qubit couplers.

26. The quantum computing apparatus of any one of claims 23 to 25, further comprising a plurality of ancilla qubits.