WO2025152189A1

WO2025152189A1 - Methods and apparatuses for downlink synchronization for ambient internet of things (iot) services

Info

Publication number: WO2025152189A1
Application number: PCT/CN2024/073379
Authority: WO
Inventors: Haipeng Lei; Xiaodong Yu; Zhennian SUN
Original assignee: Lenovo Beijing Ltd
Current assignee: Lenovo Beijing Ltd
Priority date: 2024-01-19
Filing date: 2024-01-19
Publication date: 2025-07-24
Anticipated expiration: 2026-07-19

Abstract

Embodiments of the present disclosure relate to method and apparatus for downlink synchronization for ambient IoT services. A first communication device may: detect a synchronization burst from a second communication device within a time window, wherein the synchronization burst comprises a control channel and at least one synchronization sequence; determine synchronization timing, a frame number of a first frame where the synchronization burst is detected and a slot number of a first slot where the synchronization burst is detected based on the synchronization burst; and receive data or control signaling from the second communication device or transmit data or control signaling to the second communication device according to the synchronization timing, the frame number and the slot number.

Description

METHODS AND APPARATUSES FOR DOWNLINK SYNCHRONIZATION FOR AMBIENT INTERNET OF THINGS (IOT) SERVICES

TECHNICAL FIELD

Embodiments of the present disclosure generally relate to wireless communication technology, and more particularly to Internet of Things (IoT) technology.

BACKGROUND

A wireless communication system may include one or multiple network communication devices, such as base stations, which may support wireless communication for one or multiple user communication devices, which may be otherwise known as user equipment (UE) , or other suitable terminology. The wireless communication system may support wireless communication with one or multiple user communication devices by utilizing resources of the wireless communication system (e.g., time resources (e.g., symbols, slots, subframes, frames, or the like) ) or frequency resources (e.g., subcarriers, carriers, or the like) . Additionally, the wireless communication system may support wireless communication across various radio access technologies including third generation (3G) radio access technology, fourth generation (4G) radio access technology, fifth generation (5G) (which is also known as new radio (NR) ) radio access technology, among other suitable radio access technologies beyond 5G (e.g., sixth generation (6G) ) .

SUMMARY

An article “a” before an element is unrestricted and understood to refer to “at least one” of those elements or “one or more” of those elements. The terms “a, ” “at least one, ” “one or more, ” and “at least one of one or more” may be interchangeable. As used herein, including in the claims, “or” as used in a list of items (e.g., a list of items prefaced by a phrase such as “at least one of” or “one or more of” or “one or both of” ) indicates an inclusive list such that, for example, a list of at least one of A, B, or C means A or B or C or AB or AC or BC or ABC (i.e., A and B and C) . Also, as used herein, the phrase “based on” shall not be construed as a reference to a closed set of conditions. For example, an example step that is described as “based on condition A” may be based on both a condition A and a condition B without departing from the scope of the present disclosure. In other words, as used herein, the phrase “based on” shall be construed in the same manner as the phrase “based at least in part on. ” Further, as used herein, including in the claims, a “set” may include one or more elements.

Some embodiments of the present disclosure provide a first communication device. The first communication device may include at least one transmitter; at least one receiver; and at least one processor coupled with the at least one transmitter and the at least one receiver and configured to cause the first communication device to: detect a synchronization burst from a second communication device within a time window, wherein the synchronization burst comprises a control channel and at least one synchronization sequence; determine a synchronization timing, a frame number of a first frame where the synchronization burst is detected and a slot number of a first slot where the synchronization burst is detected based on the synchronization burst; and receive data or control signaling from the second communication device or transmit data or control signaling to the second communication device according to the synchronization timing, the frame number and the slot number.

In some embodiments, the first slot includes one or more synchronization burst transmission occasions. In some embodiments, the first frame includes a single synchronization burst in a single slot of the first frame or includes a plurality of synchronization bursts in one or more slots of the first frame with each slot including one or more synchronization bursts. In some embodiments, the time window has a predetermined length and includes one or more consecutive frames with each frame including one or more synchronization bursts.

In some embodiments, the synchronization sequence has a predetermined number of bit units in a time domain and is used for transmission timing estimation in the time domain.

In some embodiments, the synchronization sequence is common to a plurality of cells, is specific to each cell, is common to different types of second communication devices in a same cell, or is specific to each type of second communication device in a same cell.

In some embodiments, the control channel indicates one or more of the following: an ID of the second communication device; the frame number of the first frame; subcarrier spacing associated with the synchronization burst; a duration of the first slot; a duration of the first frame; a half-frame indication; an indication of a position of the synchronization burst in the first frame; or a frame structure of the first frame.

In some embodiments, the synchronization burst further includes an ID of a cell associated with the second communication device or both the ID of the cell and cyclic redundancy check (CRC) bits for the ID of the cell. In some embodiments, the control channel includes an ID of a cell associated with the second communication device.

In some embodiments, the at least one synchronization sequence includes a primary synchronization sequence (PSS) and the control channel includes an ID of a secondary synchronization sequence (SSS) . In some embodiments, the at least one synchronization sequence includes an SSS and the control channel includes an ID of a PSS. In some embodiments, the at least one synchronization sequence includes a PSS and an SSS. In some embodiments, the PSS and the SSS identify a cell associated with the second communication device.

In some embodiments, the synchronization burst further includes predefined bits.

In some embodiments, the predefined bits in the synchronization burst are a prefix indicating a start position of the synchronization burst, or a postfix indicating an end position of the synchronization burst, or both the prefix and the postfix. In some embodiments, a signal in the prefix or the postfix provides radio frequency (RF) energy to the first communication device.

In some embodiments, the synchronization burst further includes a prefix including predefined bits, a postfix including predefined bits or both.

In some embodiments, the prefix indicates a start position of the synchronization burst and the postfix indicates an end position of the synchronization burst. In some embodiments, a signal in the prefix or the postfix provides RF energy to the first communication device.

In some embodiments, the synchronization burst further includes a guard period (GP) , and the GP has a predetermined number of bit units.

In some embodiments, the synchronization burst has a predetermined total number of bit units in a time domain and includes a plurality of fields, each of which has a respective predetermined number of bit units in the time domain.

In some embodiments, the first communication device is an ambient IoT device and operates in an in-band mode.

Some embodiments of the present disclosure provide a second communication device. The second communication device may include at least one transmitter; at least one receiver; and at least one processor coupled with the at least one transmitter and the at least one receiver, and configured to cause the second communication device to:transmit a synchronization burst to a first communication device within a time window, wherein the synchronization burst comprises a control channel and at least one synchronization sequence, and is transmitted in a first slot of a first frame; and transmit data or control signaling to the first communication device or receive data or control signaling from the first communication device according to a synchronization timing of the synchronization burst.

In some embodiments, the control channel indicates one or more of the following: an ID of the second communication device; the frame number of the first frame; subcarrier spacing associated with the synchronization burst; a duration of the first slot; a half-frame indication; an indication of a position of the synchronization burst in the first frame; or a frame structure of the first frame.

In some embodiments, the synchronization burst further includes an ID of a cell associated with the second communication device or both the ID of the cell and CRC bits for the ID of the cell. In some embodiments, the control channel includes an ID of a cell associated with the second communication device.

In some embodiments, the at least one synchronization sequence includes a PSS and the control channel includes an ID of an SSS. In some embodiments, the at least one synchronization sequence includes an SSS and the control channel includes an ID of a PSS. In some embodiments, the at least one synchronization sequence includes a PSS and an SSS. In some embodiments, the PSS and the SSS identify a cell associated with the second communication device.

In some embodiments, the predefined bits in the synchronization burst are a prefix indicating a start position of the synchronization burst, or a postfix indicating an end position of the synchronization burst, or both the prefix and the postfix. In some embodiments, a signal in the prefix or the postfix provides RF energy to the first communication device.

In some embodiments, the synchronization burst further includes a GP, and the GP has a predetermined number of bit units.

In some embodiments, the second communication device is a base station, a user equipment (UE) , a relay node, an integrated access and backhaul (IAB) node, a wireless access backhaul (WAB) network, a repeater, or a UE-type reader.

Some embodiments of the present disclosure provide a processor. The processor may include at least one controller coupled with at least one memory and configured to cause the processor to: detect a synchronization burst from a second communication device within a time window, wherein the synchronization burst comprises a control channel and at least one synchronization sequence; determine a synchronization timing, a frame number of a first frame where the synchronization burst is detected and a slot number of a first slot where the synchronization burst is detected based on the synchronization burst; and receive data or control signaling from the second communication device or transmit data or control signaling to the second communication device according to the synchronization timing, the frame number and the slot number.

Some embodiments of the present disclosure provide a processor. The processor may include at least one controller coupled with at least one memory and configured to cause the processor to: transmit a synchronization burst to a first communication device within a time window, wherein the synchronization burst comprises a control channel and at least one synchronization sequence, and is transmitted in a first slot of a first frame; and transmit data or control signaling to the first communication device or receive data or control signaling from the first communication device according to a synchronization timing of the synchronization burst.

Some embodiments of the present disclosure provide a method for wireless communication. The method may include: detecting a synchronization burst from a second communication device within a time window, wherein the synchronization burst comprises a control channel and at least one synchronization sequence; determining a synchronization timing, a frame number of a first frame where the synchronization burst is detected and a slot number of a first slot where the synchronization burst is detected based on the synchronization burst; and receiving data or control signaling from the second communication device or transmitting data or control signaling to the second communication device according to the synchronization timing, the frame number and the slot number.

Some embodiments of the present disclosure provide a method for wireless communication. The method may include: transmitting a synchronization burst to a first communication device within a time window, wherein the synchronization burst comprises a control channel and at least one synchronization sequence, and is transmitted in a first slot of a first frame; and transmitting data or control signaling to the first communication device or receiving data or control signaling from the first communication device according to a synchronization timing of the synchronization burst.

Some embodiments of the present disclosure provide an apparatus. According to some embodiments of the present disclosure, the apparatus may include: at least one non-transitory computer-readable medium having stored thereon computer-executable instructions; at least one receiving circuitry; at least one transmitting circuitry; and at least one processor coupled to the at least one non-transitory computer-readable medium, the at least one receiving circuitry and the at least one transmitting circuitry, wherein the at least one non-transitory computer-readable medium and the computer executable instructions may be configured to, with the at least one processor, cause the apparatus to perform a method according to some embodiments of the present disclosure.

BRIEF DESCRIPTION OF THE DRAWINGS

In order to describe the manner in which the advantages and features of the disclosure can be obtained, a description of the disclosure is rendered by reference to specific embodiments thereof, which are illustrated in the appended drawings. These drawings depict only exemplary embodiments of the disclosure and are not therefore to be considered limiting of its scope.

FIG. 1 illustrates a schematic diagram of a wireless communication system in accordance with some embodiments of the present disclosure;

FIGs. 2A-2E illustrate exemplary topologies for IoT networks and devices in accordance with some embodiments of the present disclosure;

FIGs. 3A-7G illustrate exemplary burst structures for IoT communication in accordance with some embodiments of the present disclosure;

FIGs. 8A-8E illustrate exemplary methods for transmitting synchronization bursts for IoT communication in accordance with some embodiments of the present disclosure;

FIGs. 9 and 10 illustrate flowcharts of IoT communication methods in accordance with some embodiments of the present disclosure;

FIG. 11 illustrates a block diagram of exemplary apparatus in accordance with some embodiments of the present disclosure;

FIG. 12 illustrates an example of a UE in accordance with some embodiments of the present disclosure;

FIG. 13 illustrates an example of a processor in accordance with some embodiments of the present disclosure; and

FIG. 14 illustrates an example of a network equipment (NE) in accordance with some embodiments of the present disclosure.

DETAILED DESCRIPTION

The detailed description of the appended drawings is intended as a description of the preferred embodiments of the present disclosure and is not intended to represent the only form in which the present disclosure may be practiced. It should be understood that the same or equivalent functions may be accomplished by different embodiments that are intended to be encompassed within the spirit and scope of the present disclosure.

Reference will now be made in detail to some embodiments of the present disclosure, examples of which are illustrated in the accompanying drawings. To facilitate understanding, embodiments are provided under a specific network architecture (s) and new service scenarios, such as the 3rd generation partnership project (3GPP) 5G NR or 6G, 3GPP LTE, and so on. It is contemplated that along with the developments of network architectures and new service scenarios, all embodiments in the present disclosure are also applicable to similar technical problems; and moreover, the terminologies recited in the present disclosure may change, which should not affect the principles of the present disclosure.

In recent years, IoT has attracted much attention in the wireless communication world. It is expected that further reductions of size, complexity, and power consumption of IoT devices can enable the deployment of tens or even hundreds of billions of IoT devices for various applications and provide added value across the entire value chain. However, existing technologies cannot meet all the requirements of target use cases.

As used herein, the term "ambient IoT device" or "A-IoT device" can refer to a device without batteries or with limited energy storage capabilities. For an A-IoT device, energy can be provided by harvesting radio waves, light, motion, heat, or any other suitable source. A-IoT device can also be called a zero-power terminal, a near-zero power terminal, a passive IoT device, an ambient backscatter communication (AmBC) device, tag, etc. Compared with low-power and wide-coverage services, such as narrow band (NB) IoT, enhanced machine type communication (eMTC) , A-IoT is to be designed with ultra-low complexity and ultra-low power consumption, and is orders of magnitude lower than the existing 3GPP technologies. Hence, it is suitable for more application scenarios.

The present disclosure provides various methods and apparatuses for ambient IoT communication. For example, embodiments of the present disclosure provide synchronization methods for (ambient) IoT applications. The proposed methods and apparatuses can address use cases and scenarios that cannot otherwise be fulfilled based on existing 3GPP technologies and can achieve ultra-low complexity and ultra-low power consumption for (ambient) IoT.

FIG. 1 illustrates a schematic diagram of wireless communication system 100 in accordance with some embodiments of the present disclosure.

The wireless communication system 100 may include one or more NEs 102 (e.g., one or more BSs) , one or more UEs 104, and a core network (CN) 106. The wireless communication system 100 may support various radio access technologies. In some implementations, the wireless communication system 100 may be a 4G network, such as an LTE network or an LTE-Advanced (LTE-A) network. In some other implementations, the wireless communication system 100 may be a NR network, such as a 5G network, a 5G-Advanced (5G-A) network, or a 5G ultra-wideband (5G-UWB) network. In other implementations, the wireless communication system 100 may be a combination of a 4G network and a 5G network, or other suitable radio access technology including Institute of Electrical and Electronics Engineers (IEEE) 802.11 (Wi-Fi) , IEEE 802.16 (WiMAX) , and IEEE 802.20. The wireless communication system 100 may support radio access technologies beyond 5G, for example, 6G. Additionally, the wireless communication system 100 may support technologies, such as time division multiple access (TDMA) , frequency division multiple access (FDMA) , or code division multiple access (CDMA) , etc.

The one or more NEs 102 may be dispersed throughout a geographic region to form the wireless communication system 100. One or more of the NEs 102 described herein may be or include or may be referred to as a network node, a base station, a network element, a network function, a network entity, a radio access network (RAN) , a NodeB, an eNodeB (eNB) , a next-generation NodeB (gNB) , or other suitable terminology. An NE 102 and a UE 104 may communicate via a communication link, which may be a wireless or wired connection. For example, an NE 102 and a UE 104 may perform wireless communication (e.g., receive signaling, transmit signaling) over a Uu interface.

An NE 102 may provide a geographic coverage area for which the NE 102 may support services for one or more UEs 104 within the geographic coverage area. For example, an NE 102 and a UE 104 may support wireless communication of signals related to services (e.g., voice, video, packet data, messaging, broadcast, etc. ) according to one or multiple radio access technologies. In some implementations, an NE 102 may be moveable, for example, a satellite associated with a non-terrestrial network (NTN) . In some implementations, different geographic coverage areas 112 associated with the same or different radio access technologies may overlap, but the different geographic coverage areas may be associated with a different NE 102.

The one or more UEs 104 may be dispersed throughout a geographic region of the wireless communication system 100. A UE 104 may include or may be referred to as a remote unit, a mobile device, a wireless device, a remote device, a subscriber device, a transmitter device, a receiver device, or some other suitable terminology. In some implementations, the UE 104 may be referred to as a unit, a station, a terminal, or a client, among other examples. Additionally, or alternatively, the UE 104 may be referred to as an Internet-of-Things (IoT) device, an Internet-of-Everything (IoE) device, or machine-type communication (MTC) device, among other examples.

A UE 104 may be able to support wireless communication directly with other UEs 104 over a communication link. For example, a UE 104 may support wireless communication directly with another UE 104 over a device-to-device (D2D) communication link. In some implementations, such as vehicle-to-vehicle (V2V) deployments, vehicle-to-everything (V2X) deployments, or cellular-V2X deployments, the communication link 114 may be referred to as a sidelink. For example, a UE 104 may support wireless communication directly with another UE 104 over a PC5 interface.

An NE 102 may support communication with the CN 106, or with another NE 102, or both. For example, an NE 102 may interface with another NE 102 or the CN 106 through one or more backhaul links (e.g., S1, N2, N3 or another network interface) . In some implementations, the NE 102 may communicate with each other directly. In some other implementations, the NE 102 may communicate with each other or indirectly (e.g., via the CN 106. In some implementations, one or more NEs 102 may include subcomponents, such as an access network entity, which may be an example of an access node controller (ANC) . An ANC may communicate with the one or more UEs 104 through one or more other access network transmission entities, which may be referred to as radio heads, smart radio heads, or transmission-reception points (TRPs) .

The CN 106 may support user authentication, access authorization, tracking, connectivity, and other access, routing, or mobility functions. The CN 106 may be an evolved packet core (EPC) , or a 5G core (5GC) , which may include a control plane entity that manages access and mobility (e.g., a mobility management entity (MME) , an access and mobility management (AMF) ) functions and a user plane entity that routes packets or interconnects to external networks (e.g., a serving gateway (S-GW) , a Packet Data Network (PDN) gateway (P-GW) , or a user plane function (UPF) ) . In some implementations, the control plane entity may manage non-access stratum (NAS) functions, such as mobility, authentication, and bearer management (e.g., data bearers, signal bearers, etc. ) for the one or more UEs 104 served by the one or more NEs 102 associated with the CN 106.

The CN 106 may communicate with a packet data network over one or more backhaul links (e.g., via an S1, N2, N3, or another network interface) . The packet data network may include an application server. In some implementations, one or more UEs 104 may communicate with the application server. A UE 104 may establish a session (e.g., a protocol data unit (PDU) session, or the like) with the CN 106 via an NE 102. The CN 106 may route traffic (e.g., control information, data, and the like) between the UE 104 and the application server using the established session (e.g., the established PDU session) . The PDU session may be an example of a logical connection between the UE 104 and the CN 106 (e.g., one or more network functions of the CN 106) .

In the wireless communication system 100, the NEs 102 and the UEs 104 may use resources of the wireless communication system 100 (e.g., time resources (e.g., symbols, slots, subframes, frames, or the like) or frequency resources (e.g., subcarriers, carriers) ) to perform various operations (e.g., wireless communication) . In some implementations, the NEs 102 and the UEs 104 may support different resource structures. For example, the NEs 102 and the UEs 104 may support different frame structures. In some implementations, such as in 4G, the NEs 102 and the UEs 104 may support a single frame structure. In some other implementations, such as in 5G and among other suitable radio access technologies, the NEs 102 and the UEs 104 may support various frame structures (i.e., multiple frame structures) . The NEs 102 and the UEs 104 may support various frame structures based on one or more numerologies.

In some embodiments, the NEs 102 may include one or more relay nodes, integrated access and backhaul (IAB) nodes or wireless access backhaul (WAB) nodes which can provide wireless access services for UEs 104. A relay node (or an IAB node or a WAB node) can directly connect to a BS or hop through one or more relay nodes (or one or more IAB or WAB nodes) before reaching the BS.

One or more numerologies may be supported in the wireless communication system 100, and a numerology may include a subcarrier spacing and a cyclic prefix. A first numerology (e.g., μ=0) may be associated with a first subcarrier spacing (e.g., 15 kHz) and a normal cyclic prefix. In some implementations, the first numerology (e.g., μ=0) associated with the first subcarrier spacing (e.g., 15 kHz) may utilize one slot per subframe. A second numerology (e.g., μ=1) may be associated with a second subcarrier spacing (e.g., 30 kHz) and a normal cyclic prefix. A third numerology (e.g., μ=2) may be associated with a third subcarrier spacing (e.g., 60 kHz) and a normal cyclic prefix or an extended cyclic prefix. A fourth numerology (e.g., μ=3) may be associated with a fourth subcarrier spacing (e.g., 120 kHz) and a normal cyclic prefix. A fifth numerology (e.g., μ=4) may be associated with a fifth subcarrier spacing (e.g., 240 kHz) and a normal cyclic prefix. A sixth numerology (e.g., μ =5) may be associated with a sixth subcarrier spacing (e.g., 480 kHz) and a normal cyclic prefix. A seventh numerology (e.g., μ=6) may be associated with a seventh subcarrier spacing (e.g., 960 kHz) and a normal cyclic prefix. For ambient IoT communication, additional numerologies (e.g., μ=-1 or μ =-2) may be introduced corresponding to 7.5 kHz or 3.75 kHz respectively.

A time interval of a resource (e.g., a communication resource) may be organized according to frames (also referred to as radio frames) . Each frame may have a duration, for example, a 10 millisecond (ms) duration. In some implementations, each frame may include multiple subframes. For example, each frame may include 10 subframes, and each subframe may have a duration, for example, a 1 ms duration. In some implementations, each frame may have the same duration. In some implementations, each subframe of a frame may have the same duration.

Additionally or alternatively, a time interval of a resource (e.g., a communication resource) may be organized according to slots. For example, a subframe may include a number (e.g., quantity) of slots. The number of slots in each subframe may also depend on the one or more numerologies supported in the wireless communication system 100. For instance, the first, second, third, fourth, and fifth numerologies (i.e., μ=0, μ=1, μ=2, μ=3, μ=4) associated with respective subcarrier spacings of 15 kHz, 30 kHz, 60 kHz, 120 kHz, and 240 kHz may utilize a single slot per subframe, two slots per subframe, four slots per subframe, eight slots per subframe, and 16 slots per subframe, respectively. Each slot may include a number (e.g., quantity) of symbols (e.g., orthogonal frequency-division multiplexing (OFDM) symbols) . In some implementations, the number (e.g., quantity) of slots for a subframe may depend on a numerology. For a normal cyclic prefix, a slot may include 14 symbols. For an extended cyclic prefix (e.g., applicable for 60 kHz subcarrier spacing) , a slot may include 12 symbols. The relationship between the number of symbols per slot, the number of slots per subframe, and the number of slots per frame for a normal cyclic prefix and an extended cyclic prefix may depend on a numerology. It should be understood that reference to a first numerology (e.g., μ=0) associated with a first subcarrier spacing (e.g., 15 kHz) may be used interchangeably between subframes and slots.

In the wireless communication system 100, an electromagnetic (EM) spectrum may be split, based on frequency or wavelength, into various classes, frequency bands, frequency channels, etc. By way of example, the wireless communication system 100 may support one or multiple operating frequency bands, such as frequency range designations FR1 (410 MHz –7.125 GHz) , FR2 (24.25 GHz –52.6 GHz) , FR3 (7.125 GHz –24.25 GHz) , FR4 (52.6 GHz –114.25 GHz) , FR4a or FR4-1 (52.6 GHz –71 GHz) , and FR5 (114.25 GHz –300 GHz) . In some implementations, the NEs 102 and the UEs 104 may perform wireless communication over one or more of the operating frequency bands. In some implementations, FR1 may be used by the NEs 102 and the UEs 104, among other equipment or devices for cellular communication traffic (e.g., control information, data) . In some implementations, FR2 may be used by the NEs 102 and the UEs 104, among other equipment or devices for short-range, high data rate capabilities.

FR1 may be associated with one or multiple numerologies (e.g., at least three numerologies) . For example, FR1 may be associated with a first numerology (e.g., μ =0) , which includes 15 kHz subcarrier spacing; a second numerology (e.g., μ =1) , which includes 30 kHz subcarrier spacing; and a third numerology (e.g., μ=2) , which includes 60 kHz subcarrier spacing. FR2 may be associated with one or multiple numerologies (e.g., at least 2 numerologies) . For example, FR2 may be associated with a third numerology (e.g., μ=2) , which includes 60 kHz subcarrier spacing; and a fourth numerology (e.g., μ=3) , which includes 120 kHz subcarrier spacing.

A UE 104 may include computing devices, such as desktop computers, laptop computers, personal digital assistants (PDAs) , tablet computers, smart televisions (e.g., televisions connected to the Internet) , set-top boxes, game consoles, security systems (including security cameras) , vehicle on-board computers, network devices (e.g., routers, switches, and modems) , or the like. According to some embodiments of the present disclosure, a UE 104 may include a portable wireless communication device, a smart phone, a cellular telephone, a flip phone, a device having a subscriber identity module, a personal computer, a selective call receiver, or any other device that is capable of sending and receiving communication signals on a wireless network. In some embodiments of the present disclosure, a UE 104 includes wearable devices, such as smart watches, fitness bands, optical head-mounted displays, or the like. Moreover, a UE 104 may be referred to as a subscriber unit, a mobile, a mobile station, a user, a terminal, a mobile terminal, a wireless terminal, a fixed terminal, a subscriber station, a user terminal, or a device, or described using other terminology used in the art. A UE 104 may communicate with an NE 102 (e.g., a BS) via UL (UL) communication signals. An NE 102 may communicate with a UE 104 via DL (DL) communication signals.

In some embodiments of the present disclosure, an NE 102 and a UE 104 may communicate over licensed spectrums, whereas in some other embodiments, an NE 102 and a UE 104 may communicate over unlicensed spectrums. The present disclosure is not intended to be limited to the implementation of any particular wireless communication system architecture or protocol. Persons skilled in the art should understand that as technology develops and advances, the terminologies described in the present disclosure may change, but should not affect or limit the principles and spirit of the present disclosure.

In recent years, IoT has attracted much attention in the wireless communication world. More "things" are expected to be interconnected to improve productivity efficiency and increasing comforts of life. It is expected that further reductions of size, complexity, and power consumption of IoT devices can enable the deployment of tens or even hundreds of billions of IoT devices for various applications and provide added value across the entire value chain. However, it is impossible to power all IoT devices by batteries that need to be replaced or recharged manually, which leads to high maintenance costs, serious environmental issues, and even safety hazards in some use cases (for example, wireless sensors in the electric power and petroleum industries) .

Most existing wireless communication devices are powered by batteries that need to be replaced or recharged manually. The automation and digitalization of various industries will open up numerous new markets requiring new IoT technologies supporting battery-less devices with no energy storage capability or devices with energy storage that do not need to be replaced or recharged manually. The form factors of such devices must be reasonably small to bring about the validity of target use cases. In some embodiments of the present disclosure, as will be described later, it is proposed that a capacitor may be used to support limited energy storage capability, and that the energy of such IoT devices is provided by the harvesting of radio waves, light, motion, heat, and/or any other power source (s) that may be deemed suitable.

Considering the limited size and complexity required by practical applications for battery-less devices with no energy storage capability or devices with limited energy storage that do not need to be replaced or recharged manually, the output power of an energy harvester may be typically from 1 μW to a few hundreds μW. Existing cellular devices may not work well with energy harvesting due to their peak power consumption of higher than 10 mW.

An example type of application is asset identification, which presently has to resort mainly to barcodes and RFID in most industries. The main advantage of these two technologies is their ultra-low complexity and small form factor of such tags. However, the limited reading range of a few meters usually requires handheld scanning which leads to labor intensive and time-consuming operations, or requires RFID portals/gates which leads to costly deployments. Moreover, the lack of an interference management scheme results in severe interference between RFID readers and capacity problems, especially in case of dense deployment. It is hard to support a large-scale network with seamless coverage of RFID.

Since existing technologies cannot meet all the requirements of target use cases, the present disclosure provides a new IoT technology to open up new markets within, for example, 3GPP systems, whose number of connections and/or device density can be orders of magnitude higher than existing IoT technologies. The new IoT technology can provide complexity and power consumption orders of magnitude lower than the existing 3GPP low power wide area (LPWA) technologies (e.g., Narrow-Band IoT (NB-IoT) and enhanced machine type communication (eMTC) ) , and can address use cases and scenarios that cannot otherwise be fulfilled based on existing 3GPP LPWA IoT technologies.

FIGs. 2A-2E illustrate exemplary topologies for IoT networks and devices in accordance with some embodiments of the present disclosure. In these exemplary topologies, the ambient IoT device may be provided with a carrier wave from another node (s) either inside or outside the topology. The links in each topology may be bidirectional or unidirectional.

Although elements in each topology such as the BS, UE, assisting node, or intermediate node are described in the singular, the plural is also contemplated. The mixture of indoor and outdoor placements of such nodes is regarded as a network implementation choice. Consideration would need to be taken of potential impact on device or node complexity. In the connectivity topologies, this does not imply the existence of multi-hop assisting or intermediate nodes.

In FIG. 2A, an ambient IoT device can directly and bidirectionally communicate with a BS. The communication between the BS and the ambient IoT device includes ambient IoT data and/or signaling. This topology includes the possibility that the BS transmitting to the ambient IoT device is different than the BS receiving from the ambient IoT device.

In FIG. 2B, an ambient IoT device can communicate bidirectionally with an intermediate node between the IoT device and a BS. The intermediate node can be a relay, an IAB node, a WAB node, a UE, a repeater, a UE-type reader, etc. which is capable of ambient IoT. The intermediate node may transfer ambient IoT data and/or signaling between the BS and the ambient IoT device.

In FIG. 2C, an ambient IoT device can transmit data/signaling to a BS and can receive data/signaling from an assisting node (i.e., for DL assistance) . The assisting node may receive the data/signaling from the BS. In this topology, the assisting node can be a relay, an IAB node, a WAB node, a UE, a repeater, a UE-type reader, etc. which is capable of ambient IoT.

In FIG. 2D, an ambient IoT device can receive data/signaling from a BS and can transmit data/signaling to the assisting node (i.e., for UL assistance) . The assisting node may transmit the data/signaling to the BS. In this topology, the assisting node can be a relay, an IAB node, a WAB node, a UE, a repeater, a UE-type reader, etc. which is capable of ambient IoT.

In FIG. 2E, an ambient IoT device can communicate bidirectionally with a UE. The communication between the UE and the ambient IoT device includes ambient IoT data and/or signaling.

The BS, intermediate node (e.g., an IAB node, a WAB node, a relay node, a UE, or a repeater) , assisting node (e.g., an IAB node, a WAB node, a relay node, a UE, or a repeater) , or UE-type reader which an IoT device (e.g., a tag) connects with can be referred to as a "synchronization source. " For the sake of convenience, in the context of the present disclosure, "DL" can refer to the link from a synchronization source to an IoT device (e.g., a tag) ; and "UL" can refer to the link from an IoT device (e.g., a tag) to a synchronization source.

Embodiments of the present disclosure provide various method for (ambient) IoT communication. For example, embodiments of the present disclosure provide synchronization methods for (ambient) IoT applications. The proposed solutions can support ultra-low complexity and ultra-low power consumption for IoT (e.g., ambient IoT) and can solve the aforementioned issues. More details on the embodiments of the present disclosure will be illustrated in the following text in combination with the appended drawings. For convenience, some embodiments of the present disclosure may be described with respect to ambient IoT or ambient IoT devices (e.g., an ambient IoT tag) , and it should be appreciated by persons skilled in the art that these embodiments can also be applied to other IoT devices.

For ambient IoT communication between a synchronization source (e.g., a BS, an intermediate node, an assisting node, or a UE-type reader) and an ambient IoT device (e.g., a tag) , synchronization signals may be transmitted from the synchronization source to the ambient IoT device in some embodiments. The synchronization signals can be transmitted on demand. For example, in the case that the synchronization source intends to transmit DL data or downlink command, or UL scheduling information to the ambient IoT device, or the synchronization source waits for receiving UL data from ambient IoT device, the synchronization source can transmit DL synchronization signals. The synchronization signals can be used for providing RF energy to ambient IoT devices. In some embodiments, the DL synchronization signals may be terminated in response to (e.g., after) the completion of transmitting and/or receiving from the ambient IoT device.

In some embodiments of the present disclosure, the DL synchronization signals are transmitted in a burst type in the time domain. In some embodiments, a DL synchronization burst may include consecutive time domain resources with or without a gap period at the end of the DL synchronization burst. The time domain resources can be divided into multiple time units, where each time unit can be a duration for transmitting one modulated symbol in the time domain or one bit in the time domain when, for example, the modulation order of 1 is used (e.g., when amplitude shift keying (ASK) , frequency shift keying (FSK) , Gaussian minimum shift keying (GMSK) or binary phase shift keying (BPSK) is used) . For example, such time unit can be referred to as a bit length, a bit sample, a bit unit, a symbol, a symbol length, a symbol duration or other wordings that can be conceived of by persons skilled in the art. In the context of the present disclosure, bit unit is used as an example for simplicity.

In some embodiments of the present disclosure, a DL synchronization burst has a predetermined length in the time domain, for example, a predetermined number of bit units. In the context of the present disclosure, "predetermined" means that something has been determined, established or decided before it is used. For example, a predetermined parameter or characteristic (e.g., a size, length, or duration) can mean that the parameter or characteristic is preconfigured (e.g., by radio resource control (RRC) signaling or during manufacturing) or predefined in a standard (s) (e.g., 3GPP specifications) , as long as its value is determined before it is used. For example, the number of bit units of a DL synchronization burst can be preconfigured by an RRC configuration or predefined in standards. The terms "predetermined, " "pre-known, " and "pre-defined" may be used interchangeably in this document. Such DL synchronization burst can be referred to as a DL synchronization slot, a DL synchronization sub-frame, an SS burst, an SS slot or other wordings that can be conceived of by persons skilled in the art.

In some embodiments of the present disclosure, a synchronization source has a source ID. For example, in the case that a synchronization source is a BS, the source ID can be a cell ID of the BS. In the case that a synchronization source is an intermediate node, an assisting node, or a UE-type reader, the source ID can be assigned by the network where the intermediate node, the assisting node, or the UE-type reader is located, or by the BS (e.g., a serving BS) where the intermediate node, the assisting node, or the UE-type reader is located.

Several burst structures are defined for DL synchronization and will be described in detail below. The DL synchronization burst may have a predetermined total number of bit units in the time domain. The burst may include a plurality of fields, each of which may have a respective predetermined number of bit units in the time domain. For example, a DL synchronization burst may include a control channel (e.g., a broadcast channel (BCH) ) and at least one synchronization sequence. The DL synchronization burst may also include one or more other fields.

In some embodiments of the present disclosure, a DL synchronization burst may include one or more of the following fields (or in other words, may indicate one or more of the following information) : a synchronization sequence, cell ID, CRC, a control channel (e.g., a BCH) , prefix, postfix, and GP (denoted as a "Type #A1 burst" ) .

In some embodiments, the synchronization sequence in Type #A1 burst can be a predetermined bit or symbol sequence, for example, predefined in standards. The synchronization sequence can be used as DL timing reference so that an ambient IoT device can estimate the DL timing in response to the detection of the synchronization sequence. The synchronization sequence may include a predetermined number of bit units. For example, the predetermined number can be specified in standards.

In some embodiments, the synchronization sequence can be common to a plurality of cells. For example, the same synchronization sequence can be used in a plurality of cells. In some embodiments, the synchronization sequence can be specific to each cell. For example, different synchronization sequences can be used in different cells. In some embodiments, the synchronization sequence can be common to any synchronization sequence transmitter in the same cell. For example, the same synchronization sequence is used regardless of the synchronization sequence transmitted from a BS, an intermediate node, an assisting node, or a UE-type reader in the same cell. For example, the synchronization sequence is common to different types of synchronization sources (e.g., a BS, an intermediate node, an assisting node, or a UE-type reader) in the same cell. In some embodiments, the synchronization sequence can be specific to each type of synchronization source in the same cell, thereby can be used to differentiate different types of synchronization sources in the same cell. For example, the synchronization sequence is specific to a BS, an intermediate node, an assisting node, or a UE-type reader in the same cell and thus can be used to differentiate whether the synchronization source is a BS, an intermediate node, an assisting node, or a UE-type reader.

In some embodiments, the cell ID in Type #A1 burst can be physical layer cell ID. The size of the cell ID field may be dependent on the number of physical layer cell IDs in a communication system. Taking NR system as an example, there are 1008 unique physical-layer cell identities given bywhere andWhen ambient IoT communication is deployed as an in-band mode with an NR system, for example, one frequency region of an NR system is reserved for ambient IoT transmission and reception, the same cell ID may be used for ambient IoT communication and NR communication for the same cell. The cell ID in Type #A1 burst may have 10 (or more) bits for indicating the 1008 cell IDs supported in an NR system.

The cell ID may refer to the ID of a cell associated with the synchronization source transmitting the DL synchronization burst. For example, in the case that the synchronization source is a BS, the cell ID can be a cell ID of the BS. In the case that the synchronization source is an intermediate node, an assisting node, or a UE-type reader, the cell ID can be the ID of the cell serving the intermediate node, the assisting node, or the UE-type reader.

In some embodiments, CRC bits may be generated for the cell ID. For example, 16-bit CRC or 24-bit CRC may be generated to avoid a false alarm issue and/or a lost alarm issue. In some examples, the cell ID and the generated CRC bits can be transmitted simultaneously. For example, Type #A1 burst may include both the cell ID and the generated CRC bits. In some other examples, Type #A1 burst may not include the CRC bits for the cell ID. In some examples, to improve transmission reliability of the cell ID, the cell ID, the corresponding CRC bits or both can be repeatedly transmitted within one burst.

In some embodiments, the control channel in Type #A1 burst can be used to transmit essential information bits. For example, the control channel may indicate one or more of the following: a source ID, a frame number, a subcarrier spacing (SCS) , a one-slot duration, a half-frame indication, an indication of the position of the synchronization burst in a frame (hereinafter, "position indication #A1" ) , a frame structure.

The source ID in a control channel can refer to the source ID of the transmitter (e.g., a synchronization source) transmitting the current synchronization burst. The aforementioned descriptions regarding the source ID of a synchronization source can apply here. In some embodiments, source ID may be not needed or reserved in a DL synchronization burst, for example, when the DL synchronization burst is transmitted by a BS.

The frame number in a control channel can refer to the frame where the current synchronization burst is transmitted. The size of the frame number field may be dependent on the number of frame numbers in a communication system. For example, the frame number may be the same as the frame number in an NR system. In some examples, the value of a frame number can range from 0 to 1023 and 10 bits may be required for indicating frame 0 to frame 1023. In some examples, only one or more most significant bits (MSBs) of the10 bits are indicated in the control channel and the least significant bit (s) (LSB (s) ) of the 10 bits can be indicated by other means.

The SCS in a control channel can refer the SCS of the carrier for ambient IoT transmission and reception. For example, the SCS in a control channel can refer to the SCS associated with the current synchronization burst, for example, the SCS of the carrier on which the current synchronization burst is transmitted. For example, when the ambient IoT communication is deployed as an in-band mode with an NR system, the SCS in a control channel can refer to the SCS of the NR system. The value of the SCS can be 15 kHz, 30 kHz, 60 kHz or other values (e.g., 7.5 kHz or 3.75 kHz) that can be conceived of by persons skilled in the art.

The one-slot duration in a control channel can refer the duration of the slot where the current synchronization burst is transmitted. For example, when the ambient IoT communication is deployed as an in-band mode with an NR system, the one-slot duration in a control channel can refer to the duration of a single slot of the NR system. In some embodiments, the control channel may include only one of the SCS and the one-slot duration.

The half-frame indication in a control channel can indicate the position of the current synchronization burst in the frame where the current synchronization burst is transmitted in a half-frame level. For example, it can indicate whether the current synchronization burst is located in the first half frame or the second half frame within the current frame. Position indication #A1 in a control channel can indicate the position of the current synchronization burst in the frame where the current synchronization burst is transmitted. For example, position indication #A1 can indicate whether the current synchronization burst is located in the first half frame or the second half frame within the current frame. In some examples, each half frame is 0.5 ms and each frame is 1 ms, which are similar to NR. In some embodiments, the control channel may include only one of the half-frame indication and position indication #A1.

The frame structure in a control channel can indicate the frame structure of the frame where the current synchronization burst is transmitted. For example, the frame structure in the control channel can refer to indicate the frame structure for ambient IoT transmission and reception. For example, the frame structure in the control channel can indicate a configuration for UL and DL transmissions (e.g., "tdd-UL-DL-Configuration" as specified in 3GPP specifications) . For example, this configuration may be configured by RRC signaling for the NR system. Based on this configuration, the IoT device can know a semi-static time division duplex (TDD) UL/DL configuration of the NR system and would not receive any DL signals from any slots or symbols indicated as "UL" by the configuration or transmit any UL signals in the slots or symbols indicated as "DL" by the configuration.

In some embodiments, the prefix in Type #A1 burst may include predetermined bits, for example, a number of '0' s or '1' s. For example, the number of bits of the prefix may be specified in standards. The prefix can be used to overcome a timing shift error between consecutive bursts in the time domain. In some embodiments, the signals transmitted in the prefix can provide RF energy for the IoT device (e.g., for DL reception of subsequent DL synchronization bursts) . In some embodiments, the prefix can indicate a start position of the burst. In some embodiments, the prefix can be used to indicate the type of the current DL synchronization burst structure. In some embodiments, Type #A1 burst may not include the prefix.

In some embodiments, the postfix in Type #A1 burst may include predetermined bits, for example, a number of '0' s or '1' s. For example, the number of bits of the postfix may be specified in standards. The postfix can be used to overcome a timing shift error between consecutive bursts in the time domain. In some embodiments, the signals transmitted in the postfix can provide RF energy for the IoT device (e.g., for DL reception of subsequent DL synchronization bursts) . In some embodiments, the postfix can indicate an end position of the burst. In some embodiments, the postfix can be used to indicate the type of the DL synchronization burst structure. In some embodiments, Type #A1 burst may not include the postfix.

It should be appreciated by persons skilled in the art that, in the context of the present disclosure, the term "prefix" in a burst can refer to several bits at the front of the burst, but not necessarily at the very beginning of the burst. As mentioned above, in some embodiments, the prefix in a DL synchronization burst can indicate a start position of the burst. Similarly, the term "postfix" in a burst can refers to several bits at the rear part of the burst, but not necessarily at the very end of the burst. As mentioned above, in some embodiments, the postfix in a DL synchronization burst can indicate an end position of the burst.

In some embodiments, the GP in Type #A1 burst may include predetermined bit units. The GP can avoid inter-burst interference due to a timing shift error between consecutive bursts in the time domain. The number of bit units of the GP may be predetermined, for example, specified in standards.

FIG. 3A illustrates exemplary DL synchronization burst structure 300A for Type #A1 burst in accordance with some embodiments of the present disclosure. In FIG. 3A, burst structure 300A may include a prefix field 311, a synchronization sequence field 312, a cell ID field 313, a CRC field 314, a BCH field 315, a postfix field 316 and a GP field 317.

It should be appreciated by persons skilled in the art that the arrangement of each field in exemplary burst structure 300A is only for illustrative purposes. In some embodiments, a field in Type #A1 burst can include one or more parts. For example, although in FIG. 3A, each field in burst structure 300A has one part, a field in Type #A1 burst may include more than one part. In some embodiments, the positions of the fields in Type #A1 burst can be arranged differently.

For example, FIG. 3C illustrates another exemplary DL synchronization burst structure 300C for Type #A1 burst. In FIG. 3C, burst structure 300C may include a prefix field 331, a BCH field 335, a cell ID field 333, a synchronization sequence field 332, a CRC field 334, a postfix field 336 and a GP field 337. The BCH field 335 has two parts distributed on either side of the synchronization sequence. The cell ID field 333 and the CRC field 334 are distributed on respective sides of the synchronization sequence.

For example, FIG. 3D illustrates another exemplary DL synchronization burst structure 300D for Type #A1 burst. In FIG. 3D, burst structure 300D may include a prefix field 341, a cell ID field 343, a CRC field 344, a synchronization sequence field 342, a BCH field 345, a postfix field 346 and a GP field 347. The positions of some fields in burst structure 300D are arranged differently than those in burst structure 300A. For example, the cell ID field 343 and a CRC field 344 are distributed on one side of the synchronization sequence while the BCH field 345 is distributed on another side of the synchronization sequence.

In some embodiments of the present disclosure, a DL synchronization burst may include one or more of the following fields (or in other words, may indicate one or more of the following information) : a synchronization sequence, cell ID, CRC, a control channel (e.g., a BCH) and GP (denoted as a "Type #A2 burst" ) . That is, different from Type #A1 burst, Type #A2 burst does not include a prefix and a postfix. Details described in the foregoing embodiments regarding the synchronization sequence, the cell ID, the CRC, the control channel and the GP in Type #A1 burst can apply here.

FIG. 3B illustrates exemplary DL synchronization burst structure 300B for Type #A2 burst in accordance with some embodiments of the present disclosure. In FIG. 3B, burst structure 300B may include a synchronization sequence field 322, a cell ID field 323, a CRC field 324, a BCH field 325 and a GP field 327.

It should be appreciated by persons skilled in the art that the arrangement of each field in exemplary burst structure 300B is only for illustrative purposes. In some embodiments, a field in Type #A2 burst can include one or more parts. For example, although in FIG. 3B, each field in burst structure 300B has one part, a field in Type #A2 burst may include more than one part. In some embodiments, the positions of the fields in Type #A2 burst can be arranged differently.

In some embodiments of the present disclosure, a DL synchronization burst may include one or more of the following fields (or in other words, may indicate one or more of the following information) : a synchronization sequence, a control channel (e.g., a BCH) , prefix, postfix, and GP (denoted as a "Type #B1 burst" ) .

The aforementioned descriptions regarding the synchronization sequence, prefix, postfix, and GP in Type #A1 burst can apply to Type #B1 burst.

For example, in some embodiments, the synchronization sequence in Type #B1 burst can be a predetermined bit or symbol sequence, for example, predefined in standards. The synchronization sequence can be used as DL timing reference so that an ambient IoT device can estimate the DL timing in response to the detection of the synchronization sequence. The synchronization sequence may include a predetermined number of bit units. For example, the predetermined number can be specified in standards.

For example, in some embodiments, the synchronization sequence can be common to a plurality of cells. In some embodiments, the synchronization sequence can be specific to each cell. In some embodiments, the synchronization sequence can be common to any synchronization sequence transmitter in the same cell. In some embodiments, the synchronization sequence can be specific to each type of synchronization source in the same cell, thereby can be used to differentiate different types of synchronization sources in the same cell.

For example, in some embodiments, the prefix in Type #B1 burst may include predetermined bits, for example, a number of '0' s or '1' s. For example, the number of bits of the prefix may be specified in standards. The prefix can be used to overcome a timing shift error between consecutive bursts in the time domain. In some embodiments, the signals transmitted in the prefix can provide RF energy for the IoT device (e.g., for DL reception of subsequent DL synchronization bursts) . In some embodiments, the prefix can indicate a start position of the burst. In some embodiments, the prefix can be used to indicate the type of the current DL synchronization burst structure. In some embodiments, Type #B1 burst may not include the prefix.

For example, in some embodiments, the postfix in Type #B1 burst may include predetermined bits, for example, a number of '0' s or '1' s. For example, the number of bits of the postfix may be specified in standards. The postfix can be used to overcome a timing shift error between consecutive bursts in the time domain. In some embodiments, the signals transmitted in the postfix can provide RF energy for the IoT device (e.g., for DL reception of subsequent DL synchronization bursts) . In some embodiments, the postfix can indicate an end position of the burst. In some embodiments, the postfix can be used to indicate the type of the DL synchronization burst structure. In some embodiments, Type #B1 burst may not include the postfix.

In some embodiments, the GP in Type #B1 burst may include predetermined bit units. The GP can avoid inter-burst interference due to a timing shift error between consecutive bursts in the time domain. The number of bit units of the GP may be predetermined, for example, specified in standards.

In some embodiments, the control channel in Type #B1 burst can be used to transmit essential information bits. For example, the control channel may indicate one or more of the following: cell ID, a source ID, a frame number, a subcarrier spacing, a one-slot duration, a half-frame indication, an indication of the position of the synchronization burst in a frame (hereinafter, "position indication #B1" ) , a frame structure.

The aforementioned descriptions regarding the cell ID in Type #A1 burst can apply to the cell ID in Type #B1 burst, except that the cell ID in Type #B1 burst is included in the control channel of Type #B1 burst.

For example, the cell ID in the control channel of Type #B1 burst can be physical layer cell ID. The size of the cell ID field in the control channel may be dependent on the number of physical layer cell IDs in a communication system. When ambient IoT communication is deployed as an in-band mode with an NR system, the cell ID in the control channel may have 10 (or more) bits for indicating the 1008 cell IDs supported in an NR system.

The remaining fields in the control channel of Type #B1 burst may be similarly defined as those in the control channel of Type #A1 burst.

For example, the source ID in the control channel of Type #B1 burst can refer to the source ID of the transmitter (e.g., a synchronization source) transmitting the current synchronization burst. In some embodiments, source ID may be not needed or reserved in a DL synchronization burst, for example, when the DL synchronization burst is transmitted by a BS.

For example, the frame number in the control channel of Type #B1 burst can refer to the frame where the current synchronization burst is transmitted. The size of the frame number field may be dependent on the number of frame numbers in a communication system. For example, the frame number may be the same as the frame number in an NR system. In some examples, the value of a frame number can range from 0 to 1023 and 10 bits may be required for indicating frame 0 to frame 1023. In some examples, only one or more MSBs of the10 bits are indicated in the control channel and the LSB (s) of the 10 bits can be indicated by other means.

For example, the SCS in the control channel of Type #B1 burst can refer the SCS of the carrier for ambient IoT transmission and reception. For example, the SCS in the control channel can refer to the SCS associated with the current synchronization burst, for example, the SCS of the carrier on which the current synchronization burst is transmitted. For example, when the ambient IoT communication is deployed as an in-band mode with an NR system, the SCS in a control channel can refer to the SCS of the NR system.

For example, the one-slot duration in the control channel of Type #B1 burst can refer the duration of the slot where the current synchronization burst is transmitted. For example, when the ambient IoT communication is deployed as an in-band mode with an NR system, the one-slot duration in a control channel can refer to the duration of a single slot of the NR system. In some embodiments, the control channel may include only one of the SCS and the one-slot duration.

For example, the half-frame indication in the control channel of Type #B1 burst can indicate the position of the current synchronization burst in the frame where the current synchronization burst is transmitted in a half-frame level. For example, it can indicate whether the current synchronization burst is located in the first half frame or the second half frame within the current frame. Position indication #B1 in a control channel can indicate the position of the current synchronization burst in the frame where the current synchronization burst is transmitted. For example, position indication #B1 can indicate whether the current synchronization burst is located in the first half frame or the second half frame within the current frame. In some examples, each half frame is 0.5 ms and each frame is 1 ms, which are similar to NR. In some embodiments, the control channel may include only one of the half-frame indication and position indication #B1.

For example, the frame structure in the control channel of Type #B1 burst can indicate the frame structure of the frame where the current synchronization burst is transmitted. For example, the frame structure in the control channel can refer to indicate the frame structure for ambient IoT transmission and reception. For example, the frame structure in the control channel can indicate a configuration for UL and DL transmissions (e.g., "tdd-UL-DL-Configuration" ) . For example, this configuration may be configured by RRC signaling for the NR system. Based on this configuration, the IoT device can know a semi-static TDD UL/DL configuration of the NR system and would not receive any DL signals from any slots or symbols indicated as "UL" by the configuration or transmit any UL signals in the slots or symbols indicated as "DL" by the configuration.

FIG. 4A illustrates exemplary DL synchronization burst structure 400A for Type #B1 burst in accordance with some embodiments of the present disclosure. In FIG. 4A, burst structure 400A may include a prefix field 411, a synchronization sequence field 412, a BCH field 415, a postfix field 416 and a GP field 417.

It should be appreciated by persons skilled in the art that the arrangement of each field in exemplary burst structure 400A is only for illustrative purposes. In some embodiments, a field in Type #B1 burst can include one or more parts. For example, although in FIG. 4A, each field in burst structure 400A has one part, a field in Type #B1 burst may include more than one part. In some embodiments, the positions of the fields in Type #B1 burst can be arranged differently.

For example, FIG. 4C illustrates another exemplary DL synchronization burst structure 400C for Type #B1 burst. In FIG. 4C, burst structure 400C may include a prefix field 441, a BCH field 435, a synchronization sequence field 442, a postfix field 436 and a GP field 437. The BCH field 435 has two parts distributed on either side of the synchronization sequence.

In some embodiments of the present disclosure, a DL synchronization burst may include one or more of the following fields (or in other words, may indicate one or more of the following information) : a synchronization sequence, a control channel (e.g., a BCH) and GP (denoted as a "Type #B2 burst" ) . That is, different from Type #B1 burst, Type #B2 burst does not include a prefix and a postfix. Details described in the foregoing embodiments regarding the synchronization sequence, the control channel and the GP in Type #B1 burst can apply here.

FIG. 4B illustrates exemplary DL synchronization burst structure 400B for Type #B2 burst in accordance with some embodiments of the present disclosure. In FIG. 4B, burst structure 400B may include a synchronization sequence field 422, a BCH field 425 and a GP field 427.

It should be appreciated by persons skilled in the art that the arrangement of each field in exemplary burst structure 400B is only for illustrative purposes. In some embodiments, a field in Type #B2 burst can include one or more parts. For example, although in FIG. 4B, each field in burst structure 400B has one part, a field in Type #B2 burst may include more than one part. In some embodiments, the positions of the fields in Type #B2 burst can be arranged differently.

In some embodiments of the present disclosure, a DL synchronization burst may include one or more of the following fields (or in other words, may indicate one or more of the following information) : a PSS, a control channel (e.g., a BCH) , prefix, postfix, and GP (denoted as a "Type #C1 burst" ) .

In some embodiments, the PSS in Type #C1 burst can be a predetermined bit or symbol sequence, for example, predefined in standards. The PSS can be used as for estimating the DL timing. For example, in response to detecting the PSS, an IoT device can estimate the DL timing. The PSS may be associated with the cell ID associated with the synchronization source transmitting the DL synchronization burst. For example, in an NR system, physical-layer cell identities can be determined according towhereandThere are three PSSs predefined in standards corresponding toThe PSS may include a predetermined number of bit units. For example, the predetermined number can be specified in standards. For example, a PSS can be a 127-bit length sequence. In response to detecting a PSS, an IoT device can determine the value ofFurthermore, in response to detecting an SSS ID in the control channel (which will be described later) , the IoT device can determine the value ofHence, the IoT device can determine the cell ID based on the equation

In some embodiments, the control channel in Type #C1 burst can be used to transmit essential information bits. For example, the control channel may indicate one or more of the following: an SSS ID, a source ID, a frame number, an SCS, a one-slot duration, a half-frame indication, an indication of the position of the synchronization burst in a frame (hereinafter, "position indication #C1" ) , a frame structure.

In some embodiments, the SSS ID in the control channel of Type #C1 burst is an identification of SSS. The SSS ID may be associated with the cell ID associated with the synchronization source transmitting the DL synchronization burst. The size of the SSS ID field may be dependent on the number of SSSs in a communication system. For example, in an NR system, physical-layer cell identities can be determined according towhereand There are 336 SSSs predefined in standards corresponding to The size of the SSS ID field may have 9 (or more) bits for indicating a corresponding SSS ID from the 336 SSS IDs (e.g., ) .

The remaining fields in the control channel of Type #C1 burst may be similarly defined as those in the control channel of Type #A1 burst and Type #B1 burst.

For example, the source ID in the control channel of Type #C1 burst can refer to the source ID of the transmitter (e.g., a synchronization source) transmitting the current synchronization burst. In some embodiments, source ID may be not needed or reserved in a DL synchronization burst, for example, when the DL synchronization burst is transmitted by a BS.

For example, the frame number in the control channel of Type #C1 burst can refer to the frame where the current synchronization burst is transmitted. The size of the frame number field may be dependent on the number of frame numbers in a communication system. For example, the frame number may be the same as the frame number in an NR system. In some examples, the value of a frame number can range from 0 to 1023 and 10 bits may be required for indicating frame 0 to frame 1023. In some examples, only one or more MSBs of the 10 bits are indicated in the control channel and the LSB (s) of the 10 bits can be indicated by other means.

For example, the SCS in the control channel of Type #C1 burst can refer the SCS of the carrier for ambient IoT transmission and reception. For example, the SCS in the control channel can refer to the SCS associated with the current synchronization burst, for example, the SCS of the carrier on which the current synchronization burst is transmitted. For example, when the ambient IoT communication is deployed as an in-band mode with an NR system, the SCS in a control channel can refer to the SCS of the NR system.

For example, the one-slot duration in the control channel of Type #C1 burst can refer the duration of the slot where the current synchronization burst is transmitted. For example, when the ambient IoT communication is deployed as an in-band mode with an NR system, the one-slot duration in a control channel can refer to the duration of a single slot of the NR system. In some embodiments, the control channel may include only one of the SCS and the one-slot duration.

For example, the half-frame indication in the control channel of Type #C1 burst can indicate the position of the current synchronization burst in the frame where the current synchronization burst is transmitted in a half-frame level. For example, it can indicate whether the current synchronization burst is located in the first half frame or the second half frame within the current frame. Position indication #C1 in a control channel can indicate the position of the current synchronization burst in the frame where the current synchronization burst is transmitted. For example, position indication #C1 can indicate whether the current synchronization burst is located in the first half frame or the second half frame within the current frame. In some examples, each half frame is 0.5 ms and each frame is 1 ms, which are similar to NR. In some embodiments, the control channel may include only one of the half-frame indication and position indication #C1.

For example, the frame structure in the control channel of Type #C1 burst can indicate the frame structure of the frame where the current synchronization burst is transmitted. For example, the frame structure in the control channel can refer to indicate the frame structure for ambient IoT transmission and reception. For example, the frame structure in the control channel can indicate a configuration for UL and DL transmissions (e.g., "tdd-UL-DL-Configuration" ) . For example, this configuration may be configured by RRC signaling for the NR system. Based on this configuration, the IoT device can know a semi-static TDD UL/DL configuration of the NR system and would not receive any DL signals from any slots or symbols indicated as "UL" by the configuration or transmit any UL signals in the slots or symbols indicated as "DL" by the configuration.

The aforementioned descriptions regarding the prefix, postfix, and GP in Type #A1 burst and Type #B1 burst can apply to Type #C1 burst.

In some embodiments, the prefix in Type #C1 burst may include predetermined bits, for example, a number of '0' s or '1' s. For example, the number of bits of the prefix may be specified in standards. The prefix can be used to overcome a timing shift error between consecutive bursts in the time domain. In some embodiments, the signals transmitted in the prefix can provide RF energy for the IoT device (e.g., for DL reception of subsequent DL synchronization bursts) . In some embodiments, the prefix can indicate a start position of the burst. In some embodiments, the prefix can be used to indicate the type of the current DL synchronization burst structure. In some embodiments, Type #C1 burst may not include the prefix.

In some embodiments, the postfix in Type #C1 burst may include predetermined bits, for example, a number of '0' s or '1' s. For example, the number of bits of the postfix may be specified in standards. The postfix can be used to overcome a timing shift error between consecutive bursts in the time domain. In some embodiments, the signals transmitted in the postfix can provide RF energy for the IoT device (e.g., for DL reception of subsequent DL synchronization bursts) . In some embodiments, the postfix can indicate an end position of the burst. In some embodiments, the postfix can be used to indicate the type of the DL synchronization burst structure. In some embodiments, Type #C1 burst may not include the postfix.

In some embodiments, the GP in Type #C1 burst may include predetermined bit units. The GP can avoid inter-burst interference due to a timing shift error between consecutive bursts in the time domain. The number of bit units of the GP may be predetermined, for example, specified in standards.

FIG. 5A illustrates exemplary DL synchronization burst structure 500A for Type #C1 burst in accordance with some embodiments of the present disclosure. In FIG. 5A, burst structure 500A may include a prefix field 511, a PSS field 518, a BCH field 515, a postfix field 516 and a GP field 517.

It should be appreciated by persons skilled in the art that the arrangement of each field in exemplary burst structure 500A is only for illustrative purposes. In some embodiments, a field in Type #C1 burst can include one or more parts. For example, although in FIG. 5A, each field in burst structure 500A has one part, a field in Type #C1 burst may include more than one part. In some embodiments, the positions of the fields in Type #C1 burst can be arranged differently.

In some embodiments of the present disclosure, a DL synchronization burst may include one or more of the following fields (or in other words, may indicate one or more of the following information) : a PSS, a control channel (e.g., a BCH) and GP (denoted as a "Type #C2 burst" ) . That is, different from Type #C1 burst, Type #C2 burst does not include a prefix and a postfix. Details described in the foregoing embodiments regarding the PSS, the control channel and the GP in Type #C1 burst can apply here.

FIG. 5B illustrates exemplary DL synchronization burst structure 500B for Type #C2 burst in accordance with some embodiments of the present disclosure. In FIG. 5B, burst structure 500B may include a PSS field 528, a BCH field 525 and a GP field 527.

It should be appreciated by persons skilled in the art that the arrangement of each field in exemplary burst structure 500B is only for illustrative purposes. In some embodiments, a field in Type #C2 burst can include one or more parts. For example, although in FIG. 5B, each field in burst structure 500B has one part, a field in Type #C2 burst may include more than one part. In some embodiments, the positions of the fields in Type #C2 burst can be arranged differently.

In some embodiments of the present disclosure, a DL synchronization burst may include one or more of the following fields (or in other words, may indicate one or more of the following information) : an SSS, a control channel (e.g., a BCH) , prefix, postfix, and GP (denoted as a "Type #D1 burst" ) .

In some embodiments, the SSS in Type #D1 burst can be a predetermined bit or symbol sequence, for example, predefined in standards. The SSS can be used as for estimating the DL timing. For example, in response to detecting the SSS, an IoT device can estimate the DL timing. The SSS may be associated with the cell ID associated with the synchronization source transmitting the DL synchronization burst. For example, in an NR system, physical-layer cell identities can be determined according towhereandThere are 336 SSSs predefined in standards corresponding toThe SSS may include a predetermined number of bit units. For example, the predetermined number can be specified in standards. For example, an SSS can be a 127-bit length sequence. In response to detecting an SSS, an IoT device can determine the value ofFurthermore, in response to detecting a PSS ID in the control channel (which will be described later) , the IoT device can determine the value ofHence, the IoT device can determine the cell ID based on the equation

In some embodiments, the control channel in Type #D1 burst can be used to transmit essential information bits. For example, the control channel may indicate one or more of the following: a PSS ID, a source ID, a frame number, a SCS, a one-slot duration, a half-frame indication, an indication of the position of the synchronization burst in a frame (hereinafter, "position indication #D1" ) , a frame structure.

In some embodiments, the PSS ID in the control channel of Type #D1 burst is an identification of the PSS. The PSS ID may be associated with the cell ID associated with the synchronization source transmitting the DL synchronization burst. The size of the PSS ID field may be dependent on the number of PSSs in a communication system. For example, in an NR system, physical-layer cell identities can be determined according towhereand There are 3 PSSs predefined in standards corresponding toThe size of the PSS ID field may have 2 (or more) bits for indicating a corresponding PSS ID from the 3 PSS IDs (e.g., ) .

The remaining fields in the control channel of Type #D1 burst may be similarly defined as those in the control channel of Type #A1 burst, Type #B1 burst and Type #C1 burst.

For example, the source ID in the control channel of Type #D1 burst can refer to the source ID of the transmitter (e.g., a synchronization source) transmitting the current synchronization burst. In some embodiments, source ID may be not needed or reserved in a DL synchronization burst, for example, when the DL synchronization burst is transmitted by a BS.

For example, the frame number in the control channel of Type #D1 burst can refer to the frame where the current synchronization burst is transmitted. The size of the frame number field may be dependent on the number of frame numbers in a communication system. For example, the frame number may be the same as the frame number in an NR system. In some examples, the value of a frame number can range from 0 to 1023 and 10 bits may be required for indicating frame 0 to frame 1023. In some examples, only one or more MSBs of the10 bits are indicated in the control channel and the LSB (s) of the 10 bits can be indicated by other means.

For example, the SCS in the control channel of Type #D1 burst can refer the SCS of the carrier for ambient IoT transmission and reception. For example, the SCS in the control channel can refer to the SCS associated with the current synchronization burst, for example, the SCS of the carrier on which the current synchronization burst is transmitted. For example, when the ambient IoT communication is deployed as an in-band mode with an NR system, the SCS in a control channel can refer to the SCS of the NR system.

For example, the one-slot duration in the control channel of Type #D1 burst can refer the duration of the slot where the current synchronization burst is transmitted. For example, when the ambient IoT communication is deployed as an in-band mode with an NR system, the one-slot duration in a control channel can refer to the duration of a single slot of the NR system. In some embodiments, the control channel may include only one of the SCS and the one-slot duration.

For example, the half-frame indication in the control channel of Type #D1 burst can indicate the position of the current synchronization burst in the frame where the current synchronization burst is transmitted in a half-frame level. For example, it can indicate whether the current synchronization burst is located in the first half frame or the second half frame within the current frame. Position indication #D1 in a control channel can indicate the position of the current synchronization burst in the frame where the current synchronization burst is transmitted. For example, position indication #D1 can indicate whether the current synchronization burst is located in the first half frame or the second half frame within the current frame. In some examples, each half frame is 0.5 ms and each frame is 1 ms, which are similar to NR. In some embodiments, the control channel may include only one of the half-frame indication and position indication #D1.

For example, the frame structure in the control channel of Type #D1 burst can indicate the frame structure of the frame where the current synchronization burst is transmitted. For example, the frame structure in the control channel can refer to indicate the frame structure for ambient IoT transmission and reception. For example, the frame structure in the control channel can indicate a configuration for UL and DL transmissions (e.g., "tdd-UL-DL-Configuration" ) . For example, this configuration may be configured by RRC signaling for the NR system. Based on this configuration, the IoT device can know a semi-static TDD UL/DL configuration of the NR system and would not receive any DL signals from any slots or symbols indicated as "UL" by the configuration or transmit any UL signals in the slots or symbols indicated as "DL" by the configuration.

The aforementioned descriptions regarding the prefix, postfix, and GP in Type #A1 burst, Type #B1 burst and Type #C1 burst can apply to Type #D1 burst.

For example, in some embodiments, the prefix in Type #D1 burst may include predetermined bits, for example, a number of '0' s or '1' s. For example, the number of bits of the prefix may be specified in standards. The prefix can be used to overcome a timing shift error between consecutive bursts in the time domain. In some embodiments, the signals transmitted in the prefix can provide RF energy for the IoT device (e.g., for DL reception of subsequent DL synchronization bursts) . In some embodiments, the prefix can indicate a start position of the burst. In some embodiments, the prefix can be used to indicate the type of the current DL synchronization burst structure. In some embodiments, Type #D1 burst may not include the prefix.

For example, in some embodiments, the postfix in Type #D1 burst may include predetermined bits, for example, a number of '0' s or '1' s. For example, the number of bits of the postfix may be specified in standards. The postfix can be used to overcome a timing shift error between consecutive bursts in the time domain. In some embodiments, the signals transmitted in the postfix can provide RF energy for the IoT device (e.g., for DL reception of subsequent DL synchronization bursts) . In some embodiments, the postfix can indicate an end position of the burst. In some embodiments, the postfix can be used to indicate the type of the DL synchronization burst structure. In some embodiments, Type #D1 burst may not include the postfix.

For example, in some embodiments, the GP in Type #D1 burst may include predetermined bit units. The GP can avoid inter-burst interference due to a timing shift error between consecutive bursts in the time domain. The number of bit units of the GP may be predetermined, for example, specified in standards.

FIG. 6A illustrates exemplary DL synchronization burst structure 600A for Type #D1 burst in accordance with some embodiments of the present disclosure. In FIG. 6A, burst structure 600A may include a prefix field 611, an SSS field 619, a BCH field 615, a postfix field 616 and a GP field 617.

It should be appreciated by persons skilled in the art that the arrangement of each field in exemplary burst structure 600A is only for illustrative purposes. In some embodiments, a field in Type #D1 burst can include one or more parts. For example, although in FIG. 6A, each field in burst structure 600A has one part, a field in Type #D1 burst may include more than one part. In some embodiments, the positions of the fields in Type #D1 burst can be arranged differently.

In some embodiments of the present disclosure, a DL synchronization burst may include one or more of the following fields (or in other words, may indicate one or more of the following information) : an SSS, a control channel (e.g., a BCH) and GP (denoted as a "Type #D2 burst" ) . That is, different from Type #D1 burst, Type #D2 burst does not include a prefix and a postfix. Details described in the foregoing embodiments regarding the SSS, the control channel and the GP in Type #D1 burst can apply here.

FIG. 6B illustrates exemplary DL synchronization burst structure 600B for Type #D2 burst in accordance with some embodiments of the present disclosure. In FIG. 6B, burst structure 600B may include an SSS field 629, a BCH field 625 and a GP field 627.

It should be appreciated by persons skilled in the art that the arrangement of each field in exemplary burst structure 600B is only for illustrative purposes. In some embodiments, a field in Type #D2 burst can include one or more parts. For example, although in FIG. 6B, each field in burst structure 600B has one part, a field in Type #D2 burst may include more than one part. In some embodiments, the positions of the fields in Type #D2 burst can be arranged differently.

In some embodiments of the present disclosure, a DL synchronization burst may include one or more of the following fields (or in other words, may indicate one or more of the following information) : a PSS, an SSS, a control channel (e.g., a BCH) , prefix, postfix, and GP (denoted as a "Type #E1 burst" ) .

In some embodiments, the PSS in Type #E1 burst can be a predetermined bit or symbol sequence, for example, predefined in standards. The PSS can be used as for estimating the DL timing. For example, in response to detecting the PSS, an IoT device can estimate the DL timing. The PSS may be associated with the cell ID associated with the synchronization source transmitting the DL synchronization burst. For example, in an NR system, physical-layer cell identities can be determined according towhereandThere are three PSSs predefined in standards corresponding toThe PSS may include a predetermined number of bit units. For example, the predetermined number can be specified in standards. For example, a PSS can be a 127-bit length sequence. In response to detecting a PSS, an IoT device can determine the value of

In some embodiments, the SSS in Type #E1 burst can be a predetermined bit or symbol sequence, for example, predefined in standards. The SSS can be used as a DL timing reference. For example, in response to detecting the SSS, an IoT device can estimate the DL timing. The SSS may be associated with the cell ID associated with the synchronization source transmitting the DL synchronization burst. For example, in an NR system, there are 336 SSSs predefined in standards corresponding toThe SSS may include a predetermined number of bit units. For example, the predetermined number can be specified in standards. For example, an SSS can be a 127-bit length sequence. In response to detecting an SSS, an IoT device can determine the value ofFurthermore, the IoT device can determine the cell ID based on the equation

In some embodiments, the control channel in Type #E1 burst can be used to transmit essential information bits. For example, the control channel may indicate one or more of the following: a source ID, a frame number, an SCS, a one-slot duration, a half-frame indication, an indication of the position of the synchronization burst in a frame (hereinafter, "position indication #E1" ) , a frame structure. The fields in the control channel of Type #E1 burst may be similarly defined as the corresponding ones in the control channel of the aforementioned burst types.

For example, the source ID in the control channel of Type #E1 burst can refer to the source ID of the transmitter (e.g., a synchronization source) transmitting the current synchronization burst. In some embodiments, source ID may be not needed or reserved in a DL synchronization burst, for example, when the DL synchronization burst is transmitted by a BS.

For example, the frame number in the control channel of Type #E1 burst can refer to the frame where the current synchronization burst is transmitted. The size of the frame number field may be dependent on the number of frame numbers in a communication system. For example, the frame number may be the same as the frame number in an NR system. In some examples, the value of a frame number can range from 0 to 1023 and 10 bits may be required for indicating frame 0 to frame 1023. In some examples, only one or more MSBs of the10 bits are indicated in the control channel and the LSB (s) of the 10 bits can be indicated by other means.

For example, the SCS in the control channel of Type #E1 burst can refer the SCS of the carrier for ambient IoT transmission and reception. For example, the SCS in the control channel can refer to the SCS associated with the current synchronization burst, for example, the SCS of the carrier on which the current synchronization burst is transmitted. For example, when the ambient IoT communication is deployed as an in-band mode with an NR system, the SCS in a control channel can refer to the SCS of the NR system.

For example, the one-slot duration in the control channel of Type #E1 burst can refer the duration of the slot where the current synchronization burst is transmitted. For example, when the ambient IoT communication is deployed as an in-band mode with an NR system, the one-slot duration in a control channel can refer to the duration of a single slot of the NR system. In some embodiments, the control channel may include only one of the SCS and the one-slot duration.

For example, the half-frame indication in the control channel of Type #E1 burst can indicate the position of the current synchronization burst in the frame where the current synchronization burst is transmitted in a half-frame level. For example, it can indicate whether the current synchronization burst is located in the first half frame or the second half frame within the current frame. Position indication #E1 in a control channel can indicate the position of the current synchronization burst in the frame where the current synchronization burst is transmitted. For example, position indication #E1 can indicate whether the current synchronization burst is located in the first half frame or the second half frame within the current frame. In some examples, each half frame is 0.5 ms and each frame is 1 ms, which are similar to NR. In some embodiments, the control channel may include only one of the half-frame indication and position indication #E1.

For example, the frame structure in the control channel of Type #E1 burst can indicate the frame structure of the frame where the current synchronization burst is transmitted. For example, the frame structure in the control channel can refer to indicate the frame structure for ambient IoT transmission and reception. For example, the frame structure in the control channel can indicate a configuration for UL and DL transmissions (e.g., "tdd-UL-DL-Configuration" ) . For example, this configuration may be configured by RRC signaling for the NR system. Based on this configuration, the IoT device can know a semi-static TDD UL/DL configuration of the NR system and would not receive any DL signals from any slots or symbols indicated as "UL" by the configuration or transmit any UL signals in the slots or symbols indicated as "DL" by the configuration.

The aforementioned descriptions regarding the prefix, postfix, and GP in the aforementioned burst types can apply to Type #E1 burst.

In some embodiments, the prefix in Type #E1 burst may include predetermined bits, for example, a number of '0' s or '1' s. For example, the number of bits of the prefix may be specified in standards. The prefix can be used to overcome a timing shift error between consecutive bursts in the time domain. In some embodiments, the signals transmitted in the prefix can provide RF energy for the IoT device (e.g., for DL reception of subsequent DL synchronization bursts) . In some embodiments, the prefix can indicate a start position of the burst. In some embodiments, the prefix can be used to indicate the type of the current DL synchronization burst structure. In some embodiments, Type #E1 burst may not include the prefix.

In some embodiments, the postfix in Type #E1 burst may include predetermined bits, for example, a number of '0' s or '1' s. For example, the number of bits of the postfix may be specified in standards. The postfix can be used to overcome a timing shift error between consecutive bursts in the time domain. In some embodiments, the signals transmitted in the postfix can provide RF energy for the IoT device (e.g., for DL reception of subsequent DL synchronization bursts) . In some embodiments, the postfix can indicate an end position of the burst. In some embodiments, the postfix can be used to indicate the type of the DL synchronization burst structure. In some embodiments, Type #E1 burst may not include the postfix.

In some embodiments, the GP in Type #E1 burst may include predetermined bit units. The GP can avoid inter-burst interference due to a timing shift error between consecutive bursts in the time domain. The number of bit units of the GP may be predetermined, for example, specified in standards.

FIG. 7A illustrates exemplary DL synchronization burst structure 700A for Type #E1 burst in accordance with some embodiments of the present disclosure. In FIG. 7A, burst structure 700A may include a prefix field 711, a PSS field 718, a BCH field 715, an SSS field 719, a postfix field 716 and a GP field 717.

It should be appreciated by persons skilled in the art that the arrangement of each field in exemplary burst structure 700A is only for illustrative purposes. In some embodiments, a field in Type #E1 burst can include one or more parts. For example, although in FIG. 7A, each field in burst structure 700A has one part, a field in Type #E1 burst may include more than one part. In some embodiments, the positions of the fields in Type #E1 burst can be arranged differently.

For example, FIG. 7D illustrates another exemplary DL synchronization burst structure 700D for Type #E1 burst. In FIG. 7D, burst structure 700D may include a prefix field 741, a PSS field 748, an SSS field 749, a BCH field 745, a postfix field 746 and a GP field 747. The positions of some fields in burst structure 700D are arranged differently than those in burst structure 700A.

For example, FIG. 7E illustrates another exemplary DL synchronization burst structure 700E for Type #E1 burst. In FIG. 7E, burst structure 700E may include a prefix field 751, an SSS field 759, a PSS field 758, a BCH field 755, a postfix field 756 and a GP field 757. The positions of some fields in burst structure 700E are arranged differently than those in burst structures 700A and 700D.

In some embodiments of the present disclosure, a DL synchronization burst may include one or more of the following fields (or in other words, may indicate one or more of the following information) : a PSS, an SSS, a control channel (e.g., a BCH) and GP (denoted as a "Type #E2 burst" ) . That is, different from Type #E1 burst, Type #E2 burst does not include a prefix and a postfix. Details described in the foregoing embodiments regarding the PSS, the SSS, the control channel and the GP in Type #E1 burst can apply here.

FIG. 7B illustrates exemplary DL synchronization burst structure 700B for Type #E2 burst in accordance with some embodiments of the present disclosure. In FIG. 7B, burst structure 700B may include a PSS field 728, a BCH field 725, an SSS field 729 and a GP field 727.

It should be appreciated by persons skilled in the art that the arrangement of each field in exemplary burst structure 700B is only for illustrative purposes. In some embodiments, a field in Type #E2 burst can include one or more parts. For example, although in FIG. 7B, each field in burst structure 700B has one part, a field in Type #E2 burst may include more than one part. In some embodiments, the positions of the fields in Type #E2 burst can be arranged differently.

For example, FIG. 7C illustrates another exemplary DL synchronization burst structure 700C for Type #E2 burst. In FIG. 7C, burst structure 700C may include an SSS field 739, a BCH field 735, a PSS field 738 and a GP field 737. The positions of some fields in burst structure 700C are arranged differently than those in burst structure 700B.

For example, FIG. 7F illustrates another exemplary DL synchronization burst structure 700F for Type #E2 burst. In FIG. 7F, burst structure 700F may include a PSS field 768, an SSS field 769, a BCH field 765 and a GP field 767. The positions of some fields in burst structure 700F are arranged differently than those in burst structures 700B and 700C.

For example, FIG. 7G illustrates another exemplary DL synchronization burst structure 700G for Type #E2 burst. In FIG. 7G, burst structure 700G may include an SSS field 779, a PSS field 778, a BCH field 775 and a GP field 777. The positions of some fields in burst structure 700F are arranged differently than those in burst structures 700B, 700C and 700F.

In some embodiments of the present disclosure, when a synchronization source (e.g., a BS, an intermediate node, an assisting node, or a UE-type reader) intends to transmit a DL synchronization burst, the DL synchronization burst can be transmitted from one or multiple slots of a frame. In some embodiments, the definitions of the slot and frame may be the same as those in a communication system. For example, when ambient IoT communication is deployed as an in-band mode with an NR system, the definitions of the slot and frame are the same as the NR system which the ambient IoT communication coexists with.

The one or multiple slots of a frame in which a DL synchronization burst can be transmitted can be referred to as one or more synchronization burst transmission occasions or one or more synchronization burst transmission opportunities. The transmission occasions in a frame can be predetermined, for example, predefined in standards. For example, slot 0, slot 1, slot 5, slot 6, other slot numbers, or any combination thereof can be defined as the one or more transmission occasions. In some embodiments, one transmission occasion can include one or multiple DL synchronization bursts. In some examples, the number of the bursts in one transmission occasion (e.g., a slot) may depend on the duration of a slot.

For example, a frame may include a single synchronization burst in a single slot of the frame. For example, a frame may include a plurality of synchronization bursts in one or more slots of the frame with each slot including one or more synchronization bursts.

For example, one slot (or one transmission occasion) may include only one DL synchronization burst and a frame may include only one DL synchronization burst. For example, referring to FIG. 8A, frame n only includes one transmission occasion (e.g., slot 0) which includes a single DL synchronization burst 811. In FIG. 8A-8E, it is assumed that the carrier of the burst has an SCS of 15 kHz.

For example, one slot (or one transmission occasion) may include only one DL synchronization burst and a frame may include more than one DL synchronization burst. For example, referring to FIG. 8B, frame n includes two transmission occasion (e.g., slot 0 and slot 5) each of which includes a single DL synchronization burst (i.e., synchronization burst 821 and synchronization burst 823) .

For example, one slot (or one transmission occasion) may include a plurality of DL synchronization bursts and a frame may include only one slot having DL synchronization bursts (or include only one transmission occasion) . For example, referring to FIG. 8C, frame n includes one transmission occasion (e.g., slot 0) which includes two DL synchronization bursts (i.e., synchronization burst 831 and synchronization burst 833) .

For example, one slot (or one transmission occasion) may include a plurality of DL synchronization bursts and a frame may include a plurality of slots having DL synchronization bursts (or include a plurality of transmission occasions) . For example, referring to FIG. 8D, frame n includes two transmission occasions (e.g., slot 0 and slot 5) each of which includes two DL synchronization bursts (i.e., synchronization burst 841 and synchronization burst 843 in slot 0 and synchronization burst 845 and synchronization burst 847 in slot 5) .

In response to the detection of a (e.g., one) DL synchronization burst, an IoT device can determine the slot timing within a frame (for example, based on the predetermined transmission occasion (s) , based on the predetermined transmission occasion (s) and the half-frame indication, or based on the predetermined transmission occasion (s) and the position indication) .

Same DL synchronization signals can be repeatedly transmitted within a time window. An IoT device may detect a DL synchronization burst within the time window. The time window may have a predetermined length. For example, the time window may include one or more consecutive frames with each frame including one or more synchronization bursts.

For example, referring to FIG. 8E, a time window includes two consecutive frames (i.e., frame n and frame n+1) . Each of frame n and frame n+1 has one transmission occasion (e.g., slot 0) which transmits a single DL synchronization burst 811. It should be appreciated by persons skilled in the art that the time window in FIG. 8E is only for illustrative purposes, persons skilled in the art can conceive of other exemplary time windows. For example, a time window can include one or multiple consecutive frames with each frame having one or multiple slots with each slot for transmitting one or multiple DL synchronization bursts.

FIG. 9 illustrates a flowchart of method 900 for wireless communication in accordance with some embodiments of the present disclosure. Details described in all of the foregoing embodiments of the present disclosure are applicable for the embodiments shown in FIG. 9. In some examples, method 900 may be performed by an IoT device (e.g., an ambient IoT device such as a tag) . In some embodiments, the IoT device may execute a set of instructions to control the functional elements of the IoT device to perform the described functions or operations. In some examples, a processor or controller of an IoT device may cause the IoT device to perform method 900.

At 911, a first communication device may detect a synchronization burst from a second communication device within a time window, wherein the synchronization burst includes a control channel and at least one synchronization sequence. At 913, the first communication device may determine synchronization timing, a frame number of a first frame where the synchronization burst is detected and a slot number of a first slot where the synchronization burst is detected based on the synchronization burst.

At 915, the first communication device may receive data or control signaling from the second communication device or transmit data or control signaling to the second communication device according to the synchronization timing, the frame number and the slot number.

It should be appreciated by persons skilled in the art that the sequence of the operations in exemplary method 900 may be changed and some of the operations in exemplary method 900 may be eliminated or modified, without departing from the spirit and scope of the disclosure.

FIG. 10 illustrates a flowchart of method 1000 for wireless communication in accordance with some embodiments of the present disclosure. Details described in all of the foregoing embodiments of the present disclosure are applicable for the embodiments shown in FIG. 10. In some examples, method 1000 may be performed by a synchronization source, for example, an NE (e.g., NE 102 in FIG. 1) , a BS, a relay node, an IAB node, a WAB network, a UE (e.g., UE 1010 in FIG. 1) , a repeater, or a UE-type reader. In some embodiments, the synchronization source may execute a set of instructions to control the functional elements of the synchronization source to perform the described functions or operations. In some examples, a processor or controller of the synchronization source may cause the synchronization source to perform method 1000.

At 1011, a second communication device may transmit a synchronization burst to a first communication device within a time window, wherein the synchronization burst includes a control channel and at least one synchronization sequence, and is transmitted in a first slot of a first frame. At 1013, the second communication device may transmit data or control signaling to the first communication device or receive data or control signaling from the first communication device according to a synchronization timing of the synchronization burst.

In some embodiments, the second communication device is a base station, a UE, a relay node, an IAB node, a WAB network, a repeater, or a UE-type reader.

It should be appreciated by persons skilled in the art that the sequence of the operations in exemplary method 1000 may be changed and some of the operations in exemplary method 1000 may be eliminated or modified, without departing from the spirit and scope of the disclosure.

FIG. 11 illustrates a block diagram of exemplary apparatus 1100 according to some embodiments of the present disclosure. As shown in FIG. 11, the apparatus 1100 may include at least one processor 1106 and at least one transceiver 1102 coupled to the processor 1106. The apparatus 1100 may be an IoT device (e.g., an ambient IoT tag) or a synchronization source (e.g., an NE, a BS, an IAB node, a WAB node, a relay node, a UE, a repeater or a UE-type reader) .

Although in this figure, elements such as the at least one transceiver 1102 and processor 1106 are described in the singular, the plural is contemplated unless a limitation to the singular is explicitly stated. In some embodiments of the present disclosure, the transceiver 1102 may be divided into two devices, such as a receiving circuitry and a transmitting circuitry. In some embodiments of the present disclosure, the apparatus 1100 may further include an input device, a memory, and/or other components.

In some embodiments of the present disclosure, the apparatus 1100 may be an IoT device. The transceiver 1102 and the processor 1106 may interact with each other so as to perform the operations with respect to the IoT device or the first communication device described in the foregoing embodiments such as FIGs. 9 and 10. In some embodiments of the present disclosure, the apparatus 1100 may be a synchronization source. The transceiver 1102 and the processor 1106 may interact with each other so as to perform the operations with respect to the synchronization source or the second communication device described in the foregoing embodiments such as FIGs. 9 and 10.

In some embodiments of the present disclosure, the apparatus 1100 may further include at least one non-transitory computer-readable medium.

For example, in some embodiments of the present disclosure, the non-transitory computer-readable medium may have stored thereon computer-executable instructions to cause the processor 1106 to implement the method with respect to the IoT device or the first communication device as described above. For example, the computer-executable instructions, when executed, cause the processor 1106 interacting with transceiver 1102 to perform the operations with respect to the first communication device described in FIGs. 9 and 10.

In some embodiments of the present disclosure, the non-transitory computer-readable medium may have stored thereon computer-executable instructions to cause the processor 1106 to implement the method with respect to the synchronization source or the second communication device as described above. For example, the computer-executable instructions, when executed, cause the processor 1106 interacting with transceiver 1102 to perform the operations with respect to the second communication device described in FIGs. 9 and 10.

FIG. 12 illustrates an example of a UE 1200 in accordance with aspects of the present disclosure. The UE 1200 may include a processor 1202, a memory 1204, a controller 1206, and a transceiver 1208. The processor 1202, the memory 1204, the controller 1206, or the transceiver 1208, or various combinations thereof or various components thereof may be examples of means for performing various aspects of the present disclosure as described herein. These components may be coupled (e.g., operatively, communicatively, functionally, electronically, electrically) via one or more interfaces.

The processor 1202, the memory 1204, the controller 1206, or the transceiver 1208, or various combinations or components thereof may be implemented in hardware (e.g., circuitry) . The hardware may include a processor, a digital signal processor (DSP) , an application-specific integrated circuit (ASIC) , or other programmable logic device, or any combination thereof configured as or otherwise supporting a means for performing the functions described in the present disclosure.

The processor 1202 may include an intelligent hardware device (e.g., a general-purpose processor, a DSP, a CPU, an ASIC, an FPGA, or any combination thereof) . In some implementations, the processor 1202 may be configured to operate the memory 1204. In some other implementations, the memory 1204 may be integrated into the processor 1202. The processor 1202 may be configured to execute computer-readable instructions stored in the memory 1204 to cause the UE 1200 to perform various functions of the present disclosure.

The memory 1204 may include volatile or non-volatile memory. The memory 1204 may store computer-readable, computer-executable code including instructions when executed by the processor 1202 cause the UE 1200 to perform various functions described herein. The code may be stored in a non-transitory computer-readable medium such as the memory 1204 or another type of memory. Computer-readable media includes both non-transitory computer storage media and communication media including any medium that facilitates transfer of a computer program from one place to another. A non-transitory storage medium may be any available medium that may be accessed by a general-purpose or special-purpose computer.

In some implementations, the processor 1202 and the memory 1204 coupled with the processor 1202 may be configured to cause the UE 1200 to perform one or more of the functions described herein (e.g., executing, by the processor 1202, instructions stored in the memory 1204) . For example, the processor 1202 may support wireless communication at the UE 1200 in accordance with examples as disclosed herein. For example, the UE 1200 may be configured to support means for performing the operations as described with respect to FIG. 10.

For example, the UE 1200 may be configured to support: a means for transmitting a synchronization burst to a first communication device within a time window, wherein the synchronization burst comprises a control channel and at least one synchronization sequence, and is transmitted in a first slot of a first frame; and a means for transmitting data or control signaling to the first communication device or receiving data or control signaling from the first communication device according to a synchronization timing of the synchronization burst.

The controller 1206 may manage input and output signals for the UE 1200. The controller 1206 may also manage peripherals not integrated into the UE 1200. In some implementations, the controller 1206 may utilize an operating system such as or other operating systems. In some implementations, the controller 1206 may be implemented as part of the processor 1202.

In some implementations, the UE 1200 may include at least one transceiver 1208. In some other implementations, the UE 1200 may have more than one transceiver 1208. The transceiver 1208 may represent a wireless transceiver. The transceiver 1208 may include one or more receiver chains 1210, one or more transmitter chains 1212, or a combination thereof.

A receiver chain 1210 may be configured to receive signals (e.g., control information, data, or packets) over a wireless medium. For example, the receiver chain 1210 may include one or more antennas for receive the signal over the air or wireless medium. The receiver chain 1210 may include at least one amplifier (e.g., a low-noise amplifier (LNA) ) configured to amplify the received signal. The receiver chain 1210 may include at least one demodulator configured to demodulate the receive signal and obtain the transmitted data by reversing the modulation technique applied during transmission of the signal. The receiver chain 1210 may include at least one decoder for decoding the processing the demodulated signal to receive the transmitted data.

A transmitter chain 1212 may be configured to generate and transmit signals (e.g., control information, data, or packets) . The transmitter chain 1212 may include at least one modulator for modulating data onto a carrier signal, preparing the signal for transmission over a wireless medium. The at least one modulator may be configured to support one or more techniques such as amplitude modulation (AM) , frequency modulation (FM) , or digital modulation schemes like phase-shift keying (PSK) or quadrature amplitude modulation (QAM) . The transmitter chain 1212 may also include at least one power amplifier configured to amplify the modulated signal to an appropriate power level suitable for transmission over the wireless medium. The transmitter chain 1212 may also include one or more antennas for transmitting the amplified signal into the air or wireless medium.

It should be appreciated by persons skilled in the art that the components in exemplary UE 1200 may be changed, for example, some of the components in exemplary UE 1200 may be omitted or modified or a new component (s) may be added to exemplary UE 1200, without departing from the spirit and scope of the disclosure. For example, in some embodiments, the UE 1200 may not include the controller 1206.

FIG. 13 illustrates an example of a processor 1300 in accordance with aspects of the present disclosure. The processor 1300 may be an example of a processor configured to perform various operations in accordance with examples as described herein. The processor 1300 may include a controller 1302 configured to perform various operations in accordance with examples as described herein. The processor 1300 may optionally include at least one memory 1304, which may be, for example, an L1/L2/L3 cache. Additionally, or alternatively, the processor 1300 may optionally include one or more arithmetic-logic units (ALUs) 1306. One or more of these components may be in electronic communication or otherwise coupled (e.g., operatively, communicatively, functionally, electronically, electrically) via one or more interfaces (e.g., buses) .

The processor 1300 may be a processor chipset and include a protocol stack (e.g., a software stack) executed by the processor chipset to perform various operations (e.g., receiving, obtaining, retrieving, transmitting, outputting, forwarding, storing, determining, identifying, accessing, writing, reading) in accordance with examples as described herein. The processor chipset may include one or more cores, one or more caches (e.g., memory local to or included in the processor chipset (e.g., the processor 1300) or other memory (e.g., random access memory (RAM) , read-only memory (ROM) , dynamic RAM (DRAM) , synchronous dynamic RAM (SDRAM) , static RAM (SRAM) , ferroelectric RAM (FeRAM) , magnetic RAM (MRAM) , resistive RAM (RRAM) , flash memory, phase change memory (PCM) , and others) .

The controller 1302 may be configured to manage and coordinate various operations (e.g., signaling, receiving, obtaining, retrieving, transmitting, outputting, forwarding, storing, determining, identifying, accessing, writing, reading) of the processor 1300 to cause the processor 1300 to support various operations in accordance with examples as described herein. For example, the controller 1302 may operate as a control unit of the processor 1300, generating control signals that manage the operation of various components of the processor 1300. These control signals include enabling or disabling functional units, selecting data paths, initiating memory access, and coordinating timing of operations.

The controller 1302 may be configured to fetch (e.g., obtain, retrieve, receive) instructions from the memory 1304 and determine a subsequent instruction (s) to be executed to cause the processor 1300 to support various operations in accordance with examples as described herein. The controller 1302 may be configured to track memory address of instructions associated with the memory 1304. The controller 1302 may be configured to decode instructions to determine the operation to be performed and the operands involved. For example, the controller 1302 may be configured to interpret the instruction and determine control signals to be output to other components of the processor 1300 to cause the processor 1300 to support various operations in accordance with examples as described herein. Additionally, or alternatively, the controller 1302 may be configured to manage flow of data within the processor 1300. The controller 1302 may be configured to control transfer of data between registers, ALUs, and other functional units of the processor 1300.

The memory 1304 may include one or more caches (e.g., memory local to or included in the processor 1300 or other memory, such RAM, ROM, DRAM, SDRAM, SRAM, MRAM, flash memory, etc. In some implementations, the memory 1304 may reside within or on a processor chipset (e.g., local to the processor 1300) . In some other implementations, the memory 1304 may reside external to the processor chipset (e.g., remote to the processor 1300) .

The memory 1304 may store computer-readable, computer-executable code including instructions that, when executed by the processor 1300, cause the processor 1300 to perform various functions described herein. The code may be stored in a non-transitory computer-readable medium such as system memory or another type of memory. The controller 1302 and/or the processor 1300 may be configured to execute computer-readable instructions stored in the memory 1304 to cause the processor 1300 to perform various functions. For example, the processor 1300 and/or the controller 1302 may be coupled with or to the memory 1304, the processor 1300, the controller 1302, and the memory 1304 may be configured to perform various functions described herein. In some examples, the processor 1300 may include multiple processors and the memory 1304 may include multiple memories. One or more of the multiple processors may be coupled with one or more of the multiple memories, which may, individually or collectively, be configured to perform various functions herein.

The one or more ALUs 1306 may be configured to support various operations in accordance with examples as described herein. In some implementations, the one or more ALUs 1306 may reside within or on a processor chipset (e.g., the processor 1300) . In some other implementations, the one or more ALUs 1306 may reside external to the processor chipset (e.g., the processor 1300) . One or more ALUs 1306 may perform one or more computations such as addition, subtraction, multiplication, and division on data. For example, one or more ALUs 1306 may receive input operands and an operation code, which determines an operation to be executed. One or more ALUs 1306 be configured with a variety of logical and arithmetic circuits, including adders, subtractors, shifters, and logic gates, to process and manipulate the data according to the operation. Additionally, or alternatively, the one or more ALUs 1306 may support logical operations such as AND, OR, exclusive-OR (XOR) , not-OR (NOR) , and not-AND (NAND) , enabling the one or more ALUs 1306 to handle conditional operations, comparisons, and bitwise operations.

The processor 1300 may support wireless communication in accordance with examples as disclosed herein.

For example, the processor 1300 may be configured to support means for performing the operations as described with respect to FIG. 9. For example, the processor 1300 may be configured to or operable to support: a means for detecting a synchronization burst from a second communication device within a time window, wherein the synchronization burst comprises a control channel and at least one synchronization sequence; a means for determining synchronization timing, a frame number of a first frame where the synchronization burst is detected and a slot number of a first slot where the synchronization burst is detected based on the synchronization burst; and a means for receiving data or control signaling from the second communication device or transmitting data or control signaling to the second communication device according to the synchronization timing, the frame number and the slot number.

For example, the processor 1300 may be configured to support means for performing the operations as described with respect to FIG. 10. For example, the processor 1300 may be configured to or operable to support: a means for transmitting a synchronization burst to a first communication device within a time window, wherein the synchronization burst comprises a control channel and at least one synchronization sequence, and is transmitted in a first slot of a first frame; and a means for transmitting data or control signaling to the first communication device or receiving data or control signaling from the first communication device according to a synchronization timing of the synchronization burst.

It should be appreciated by persons skilled in the art that the components in exemplary processor 1300 may be changed, for example, some of the components in exemplary processor 1300 may be omitted or modified or a new component (s) may be added to exemplary processor 1300, without departing from the spirit and scope of the disclosure. For example, in some embodiments, the processor 1300 may not include the ALUs 1306.

FIG. 14 illustrates an example of an NE 1400 in accordance with aspects of the present disclosure. The NE 1400 may include a processor 1402, a memory 1404, a controller 1406, and a transceiver 1408. The processor 1402, the memory 1404, the controller 1406, or the transceiver 1408, or various combinations thereof or various components thereof may be examples of means for performing various aspects of the present disclosure as described herein. These components may be coupled (e.g., operatively, communicatively, functionally, electronically, electrically) via one or more interfaces.

The processor 1402, the memory 1404, the controller 1406, or the transceiver 1408, or various combinations or components thereof may be implemented in hardware (e.g., circuitry) . The hardware may include a processor, a DSP, an ASIC, or other programmable logic device, or any combination thereof configured as or otherwise supporting a means for performing the functions described in the present disclosure.

The processor 1402 may include an intelligent hardware device (e.g., a general-purpose processor, a DSP, a CPU, an ASIC, an FPGA, or any combination thereof) . In some implementations, the processor 1402 may be configured to operate the memory 1404. In some other implementations, the memory 1404 may be integrated into the processor 1402. The processor 1402 may be configured to execute computer-readable instructions stored in the memory 1404 to cause the NE 1400 to perform various functions of the present disclosure.

The memory 1404 may include volatile or non-volatile memory. The memory 1404 may store computer-readable, computer-executable code including instructions when executed by the processor 1402 cause the NE 1400 to perform various functions described herein. The code may be stored in a non-transitory computer-readable medium such as the memory 1404 or another type of memory. Computer-readable media includes both non-transitory computer storage media and communication media including any medium that facilitates transfer of a computer program from one place to another. A non-transitory storage medium may be any available medium that may be accessed by a general-purpose or special-purpose computer.

In some implementations, the processor 1402 and the memory 1404 coupled with the processor 1402 may be configured to cause the NE 1400 to perform one or more of the functions described herein (e.g., executing, by the processor 1402, instructions stored in the memory 1404) . For example, the processor 1402 may support wireless communication at the NE 1400 in accordance with examples as disclosed herein. For example, the NE 1400 may be configured to support means for performing the operations as described with respect to FIG. 10.

For example, the NE 1400 may be configured to support: a means for transmitting a synchronization burst to a first communication device within a time window, wherein the synchronization burst comprises a control channel and at least one synchronization sequence, and is transmitted in a first slot of a first frame; and a means for transmitting data or control signaling to the first communication device or receiving data or control signaling from the first communication device according to a synchronization timing of the synchronization burst.

The controller 1406 may manage input and output signals for the NE 1400. The controller 1406 may also manage peripherals not integrated into the NE 1400. In some implementations, the controller 1406 may utilize an operating system such as or other operating systems. In some implementations, the controller 1406 may be implemented as part of the processor 1402.

In some implementations, the NE 1400 may include at least one transceiver 1408. In some other implementations, the NE 1400 may have more than one transceiver 1408. The transceiver 1408 may represent a wireless transceiver. The transceiver 1408 may include one or more receiver chains 1410, one or more transmitter chains 1412, or a combination thereof.

A receiver chain 1410 may be configured to receive signals (e.g., control information, data, or packets) over a wireless medium. For example, the receiver chain 1410 may include one or more antennas for receive the signal over the air or wireless medium. The receiver chain 1410 may include at least one amplifier (e.g., an LNA) configured to amplify the received signal. The receiver chain 1410 may include at least one demodulator configured to demodulate the receive signal and obtain the transmitted data by reversing the modulation technique applied during transmission of the signal. The receiver chain 1410 may include at least one decoder for decoding the processing the demodulated signal to receive the transmitted data.

A transmitter chain 1412 may be configured to generate and transmit signals (e.g., control information, data, or packets) . The transmitter chain 1412may include at least one modulator for modulating data onto a carrier signal, preparing the signal for transmission over a wireless medium. The at least one modulator may be configured to support one or more techniques such as AM, FM, or digital modulation schemes like PSK or QAM. The transmitter chain 1412 may also include at least one power amplifier configured to amplify the modulated signal to an appropriate power level suitable for transmission over the wireless medium. The transmitter chain 1412 may also include one or more antennas for transmitting the amplified signal into the air or wireless medium.

It should be appreciated by persons skilled in the art that the components in exemplary NE 1400 may be changed, for example, some of the components in exemplary NE 1400 may be omitted or modified or a new component (s) may be added to exemplary NE 1400, without departing from the spirit and scope of the disclosure. For example, in some embodiments, the NE 1400 may not include the controller 1406.

Those having ordinary skill in the art would understand that the operations or steps of the methods described in connection with the aspects disclosed herein may be embodied directly in hardware, in a software module executed by a processor, or in a combination of the two. A software module may reside in RAM memory, flash memory, ROM memory, EPROM memory, EEPROM memory, registers, a hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art. Additionally, in some aspects, the operations or steps of the methods may reside as one or any combination or set of codes and/or instructions on a non-transitory computer-readable medium, which may be incorporated into a computer program product.

While this disclosure has been described with specific embodiments thereof, it is evident that many alternatives, modifications, and variations may be apparent to those skilled in the art. The disclosure is not limited to the examples and designs described herein but is to be accorded with the broadest scope consistent with the principles and novel features disclosed herein. For example, various components of the embodiments may be interchanged, added, or substituted in other embodiments. Also, all of the elements of each figure are not necessary for the operation of the disclosed embodiments. For example, one of ordinary skill in the art of the disclosed embodiments would be enabled to make and use the teachings of the disclosure by simply employing the elements of the independent claims. Accordingly, embodiments of the disclosure as set forth herein are intended to be illustrative, not limiting. Various changes may be made without departing from the spirit and scope of the disclosure.

In this document, the terms "includes, " "including, " or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that includes a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. An element proceeded by "a, " "an, " or the like does not, without more constraints, preclude the existence of additional identical elements in the process, method, article, or apparatus that includes the element. Also, the term "another" is defined as at least a second or more. The term "having" or the like, as used herein, is defined as "including. " Expressions such as "A and/or B" or "at least one of A and B" may include any and all combinations of words enumerated along with the expression. For instance, the expression "A and/or B" or "at least one of A and B" may include A, B, or both A and B. The wording "the first, " "the second" or the like is only used to clearly illustrate the embodiments of the present disclosure, but is not used to limit the substance of the present disclosure.

Claims

A first communication device, comprising:

at least one transmitter;

at least one receiver; and

at least one processor coupled with the at least one transmitter and the at least one receiver, and configured to cause the first communication device to:

detect a synchronization burst from a second communication device within a time window, wherein the synchronization burst comprises a control channel and at least one synchronization sequence;

determine a synchronization timing, a frame number of a first frame where the synchronization burst is detected and a slot number of a first slot where the synchronization burst is detected based on the synchronization burst; and

receive data or control signaling from the second communication device or transmit data or control signaling to the second communication device according to the synchronization timing, the frame number and the slot number.
The first communication device of claim 1, wherein the first slot includes one or more synchronization burst transmission occasions;

wherein the first frame includes a single synchronization burst in a single slot of the first frame or includes a plurality of synchronization bursts in one or more slots of the first frame with each slot including one or more synchronization bursts; and

wherein the time window has a predetermined length and comprises one or more consecutive frames with each frame including one or more synchronization bursts.
The first communication device of claim 1, wherein the synchronization sequence has a predetermined number of bit units in a time domain and is used for transmission timing estimation in the time domain.
The first communication device of claim 3, wherein the synchronization sequence is common to a plurality of cells, is specific to each cell, is common to different types of second communication devices in a same cell, or is specific to each type of second communication device in a same cell.
The first communication device of claim 1, wherein the control channel indicates one or more of the following:

an ID of the second communication device;

the frame number of the first frame;

subcarrier spacing associated with the synchronization burst;

a duration of the first slot;

a duration of the first frame;

a half-frame indication;

an indication of a position of the synchronization burst in the first frame; or

a frame structure of the first frame.
The first communication device of claim 1, wherein the synchronization burst further comprises an ID of a cell associated with the second communication device or both the ID of the cell and cyclic redundancy check (CRC) bits for the ID of the cell; or

wherein the control channel comprises an ID of a cell associated with the second communication device.
The first communication device of claim 1, wherein the at least one synchronization sequence comprises a primary synchronization sequence (PSS) and the control channel comprises an ID of a secondary synchronization sequence (SSS) ,

wherein the at least one synchronization sequence comprises an SSS and the control channel comprises an ID of a PSS, or

wherein the at least one synchronization sequence comprises a PSS and an SSS; and

wherein the PSS and the SSS identify a cell associated with the second communication device.
The first communication device of claim 1, wherein the synchronization burst further comprises predefined bits.
The first communication device of claim 8, wherein the predefined bits in the synchronization burst are a prefix indicating a start position of the synchronization burst, or a postfix indicating an end position of the synchronization burst, or both the prefix and the postfix; and

wherein a signal in the prefix or the postfix provides radio frequency (RF) energy to the first communication device.
A second communication device, comprising:

at least one transmitter;

at least one receiver; and

at least one processor coupled with the at least one transmitter and the at least one receiver, and configured to cause the second communication device to:

transmit a synchronization burst to a first communication device within a time window, wherein the synchronization burst comprises a control channel and at least one synchronization sequence, and is transmitted in a first slot of a first frame; and

transmit data or control signaling to the first communication device or receive data or control signaling from the first communication device according to a synchronization timing of the synchronization burst.
The second communication device of claim 10, wherein the first slot includes one or more synchronization burst transmission occasions;

wherein the first frame includes a single synchronization burst in a single slot of the first frame or includes a plurality of synchronization bursts in one or more slots of the first frame with each slot including one or more synchronization bursts; and

wherein the time window has a predetermined length and comprises one or more consecutive frames with each frame including one or more synchronization bursts.
The second communication device of claim 10, wherein the synchronization sequence has a predetermined number of bit units in a time domain and is used for transmission timing estimation in the time domain.
The second communication device of claim 12, wherein the synchronization sequence is common to a plurality of cells, is specific to each cell, is common to different types of second communication devices in a same cell, or is specific to each type of second communication device in a same cell.
The second communication device of claim 10, wherein the control channel indicates one or more of the following:

an ID of the second communication device;

the frame number of the first frame;

subcarrier spacing associated with the synchronization burst;

a duration of the first slot;

a half-frame indication;

an indication of a position of the synchronization burst in the first frame; or

a frame structure of the first frame.
The second communication device of claim 10, wherein the synchronization burst further comprises an ID of a cell associated with the second communication device or both the ID of the cell and cyclic redundancy check (CRC) bits for the ID of the cell; or

wherein the control channel comprises an ID of a cell associated with the second communication device.
The second communication device of claim 10, wherein the at least one synchronization sequence comprises a primary synchronization sequence (PSS) and the control channel comprises an ID of a secondary synchronization sequence (SSS) ,

wherein the at least one synchronization sequence comprises an SSS and the control channel comprises an ID of a PSS, or

wherein the at least one synchronization sequence comprises a PSS and an SSS; and

wherein the PSS and the SSS identify a cell associated with the second communication device.
The second communication device of claim 10, wherein the synchronization burst further comprises predefined bits.
The second communication device of claim 17, wherein the predefined bits in the synchronization burst are a prefix indicating a start position of the synchronization burst, or a postfix indicating an end position of the synchronization burst, or both the prefix and the postfix; and

wherein a signal in the prefix or the postfix provides radio frequency (RF) energy to the first communication device.
A processor, comprising:

at least one controller coupled with at least one memory and configured to cause the processor to:

detect a synchronization burst from a second communication device within a time window, wherein the synchronization burst comprises a control channel and at least one synchronization sequence;

determine a synchronization timing, a frame number of a first frame where the synchronization burst is detected and a slot number of a first slot where the synchronization burst is detected based on the synchronization burst; and

receive data or control signaling from the second communication device or transmit data or control signaling to the second communication device according to the synchronization timing, the frame number and the slot number.
A processor, comprising:

at least one controller coupled with at least one memory and configured to cause the processor to:

transmit a synchronization burst to a first communication device within a time window, wherein the synchronization burst comprises a control channel and at least one synchronization sequence, and is transmitted in a first slot of a first frame; and

transmit data or control signaling to the first communication device or receive data or control signaling from the first communication device according to a synchronization timing of the synchronization burst.